drivers/mmc/host/sdhci-pxav2.c

   1 /*
   2  * Copyright (C) 2010 Marvell International Ltd.
   3  *              Zhangfei Gao <zhangfei.gao@marvell.com>
   4  *              Kevin Wang <dwang4@marvell.com>
   5  *              Jun Nie <njun@marvell.com>
   6  *              Qiming Wu <wuqm@marvell.com>
   7  *              Philip Rakity <prakity@marvell.com>
   8  *
   9  * This software is licensed under the terms of the GNU General Public
  10  * License version 2, as published by the Free Software Foundation, and
  11  * may be copied, distributed, and modified under those terms.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19
  20 #include <linux/err.h>
  21 #include <linux/init.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/clk.h>
  24 #include <linux/module.h>
  25 #include <linux/io.h>
  26 #include <linux/mmc/card.h>
  27 #include <linux/mmc/host.h>
  28 #include <linux/platform_data/pxa_sdhci.h>
  29 #include <linux/slab.h>
  30 #include <linux/of.h>
  31 #include <linux/of_device.h>
  32
  33 #include "sdhci.h"
  34 #include "sdhci-pltfm.h"
  35
  36 #define SD_FIFO_PARAM           0xe0
  37 #define DIS_PAD_SD_CLK_GATE     0x0400 /* Turn on/off Dynamic SD Clock Gating */
  38 #define CLK_GATE_ON             0x0200 /* Disable/enable Clock Gate */
  39 #define CLK_GATE_CTL            0x0100 /* Clock Gate Control */
  40 #define CLK_GATE_SETTING_BITS   (DIS_PAD_SD_CLK_GATE | \
  41                 CLK_GATE_ON | CLK_GATE_CTL)
  42
  43 #define SD_CLOCK_BURST_SIZE_SETUP       0xe6
  44 #define SDCLK_SEL_SHIFT         8
  45 #define SDCLK_SEL_MASK          0x3
  46 #define SDCLK_DELAY_SHIFT       10
  47 #define SDCLK_DELAY_MASK        0x3c
  48
  49 #define SD_CE_ATA_2             0xea
  50 #define MMC_CARD                0x1000
  51 #define MMC_WIDTH               0x0100
  52
  53 static void pxav2_reset(struct sdhci_host *host, u8 mask)
  54 {
  55         struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
  56         struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
  57
  58         sdhci_reset(host, mask);
  59
  60         if (mask == SDHCI_RESET_ALL) {
  61                 u16 tmp = 0;
  62
  63                 /*
  64                  * tune timing of read data/command when crc error happen
  65                  * no performance impact
  66                  */
  67                 if (pdata && pdata->clk_delay_sel == 1) {
  68                         tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
  69
  70                         tmp &= ~(SDCLK_DELAY_MASK << SDCLK_DELAY_SHIFT);
  71                         tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
  72                                 << SDCLK_DELAY_SHIFT;
  73                         tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT);
  74                         tmp |= (1 & SDCLK_SEL_MASK) << SDCLK_SEL_SHIFT;
  75
  76                         writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
  77                 }
  78
  79                 if (pdata && (pdata->flags & PXA_FLAG_ENABLE_CLOCK_GATING)) {
  80                         tmp = readw(host->ioaddr + SD_FIFO_PARAM);
  81                         tmp &= ~CLK_GATE_SETTING_BITS;
  82                         writew(tmp, host->ioaddr + SD_FIFO_PARAM);
  83                 } else {
  84                         tmp = readw(host->ioaddr + SD_FIFO_PARAM);
  85                         tmp &= ~CLK_GATE_SETTING_BITS;
  86                         tmp |= CLK_GATE_SETTING_BITS;
  87                         writew(tmp, host->ioaddr + SD_FIFO_PARAM);
  88                 }
  89         }
  90 }
  91
  92 static void pxav2_mmc_set_bus_width(struct sdhci_host *host, int width)
  93 {
  94         u8 ctrl;
  95         u16 tmp;
  96
  97         ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  98         tmp = readw(host->ioaddr + SD_CE_ATA_2);
  99         if (width == MMC_BUS_WIDTH_8) {
 100                 ctrl &= ~SDHCI_CTRL_4BITBUS;
 101                 tmp |= MMC_CARD | MMC_WIDTH;
 102         } else {
 103                 tmp &= ~(MMC_CARD | MMC_WIDTH);
 104                 if (width == MMC_BUS_WIDTH_4)
 105                         ctrl |= SDHCI_CTRL_4BITBUS;
 106                 else
 107                         ctrl &= ~SDHCI_CTRL_4BITBUS;
 108         }
 109         writew(tmp, host->ioaddr + SD_CE_ATA_2);
 110         writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
 111 }
 112
 113 static const struct sdhci_ops pxav2_sdhci_ops = {
 114         .set_clock     = sdhci_set_clock,
 115         .get_max_clock = sdhci_pltfm_clk_get_max_clock,
 116         .set_bus_width = pxav2_mmc_set_bus_width,
 117         .reset         = pxav2_reset,
 118         .set_uhs_signaling = sdhci_set_uhs_signaling,
 119 };
 120
 121 #ifdef CONFIG_OF
 122 static const struct of_device_id sdhci_pxav2_of_match[] = {
 123         {
 124                 .compatible = "mrvl,pxav2-mmc",
 125         },
 126         {},
 127 };
 128 MODULE_DEVICE_TABLE(of, sdhci_pxav2_of_match);
 129
 130 static struct sdhci_pxa_platdata *pxav2_get_mmc_pdata(struct device *dev)
 131 {
 132         struct sdhci_pxa_platdata *pdata;
 133         struct device_node *np = dev->of_node;
 134         u32 bus_width;
 135         u32 clk_delay_cycles;
 136
 137         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
 138         if (!pdata)
 139                 return NULL;
 140
 141         if (of_find_property(np, "non-removable", NULL))
 142                 pdata->flags |= PXA_FLAG_CARD_PERMANENT;
 143
 144         of_property_read_u32(np, "bus-width", &bus_width);
 145         if (bus_width == 8)
 146                 pdata->flags |= PXA_FLAG_SD_8_BIT_CAPABLE_SLOT;
 147
 148         of_property_read_u32(np, "mrvl,clk-delay-cycles", &clk_delay_cycles);
 149         if (clk_delay_cycles > 0) {
 150                 pdata->clk_delay_sel = 1;
 151                 pdata->clk_delay_cycles = clk_delay_cycles;
 152         }
 153
 154         return pdata;
 155 }
 156 #else
 157 static inline struct sdhci_pxa_platdata *pxav2_get_mmc_pdata(struct device *dev)
 158 {
 159         return NULL;
 160 }
 161 #endif
 162
 163 static int sdhci_pxav2_probe(struct platform_device *pdev)
 164 {
 165         struct sdhci_pltfm_host *pltfm_host;
 166         struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
 167         struct device *dev = &pdev->dev;
 168         struct sdhci_host *host = NULL;
 169         const struct of_device_id *match;
 170
 171         int ret;
 172         struct clk *clk;
 173
 174         host = sdhci_pltfm_init(pdev, NULL, 0);
 175         if (IS_ERR(host))
 176                 return PTR_ERR(host);
 177
 178         pltfm_host = sdhci_priv(host);
 179
 180         clk = devm_clk_get(dev, "PXA-SDHCLK");
 181         if (IS_ERR(clk)) {
 182                 dev_err(dev, "failed to get io clock\n");
 183                 ret = PTR_ERR(clk);
 184                 goto free;
 185         }
 186         pltfm_host->clk = clk;
 187         ret = clk_prepare_enable(clk);
 188         if (ret) {
 189                 dev_err(&pdev->dev, "failed to enable io clock\n");
 190                 goto free;
 191         }
 192
 193         host->quirks = SDHCI_QUIRK_BROKEN_ADMA
 194                 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
 195                 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;
 196
 197         match = of_match_device(of_match_ptr(sdhci_pxav2_of_match), &pdev->dev);
 198         if (match) {
 199                 pdata = pxav2_get_mmc_pdata(dev);
 200         }
 201         if (pdata) {
 202                 if (pdata->flags & PXA_FLAG_CARD_PERMANENT) {
 203                         /* on-chip device */
 204                         host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
 205                         host->mmc->caps |= MMC_CAP_NONREMOVABLE;
 206                 }
 207
 208                 /* If slot design supports 8 bit data, indicate this to MMC. */
 209                 if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
 210                         host->mmc->caps |= MMC_CAP_8_BIT_DATA;
 211
 212                 if (pdata->quirks)
 213                         host->quirks |= pdata->quirks;
 214                 if (pdata->host_caps)
 215                         host->mmc->caps |= pdata->host_caps;
 216                 if (pdata->pm_caps)
 217                         host->mmc->pm_caps |= pdata->pm_caps;
 218         }
 219
 220         host->ops = &pxav2_sdhci_ops;
 221
 222         ret = sdhci_add_host(host);
 223         if (ret)
 224                 goto disable_clk;
 225
 226         return 0;
 227
 228 disable_clk:
 229         clk_disable_unprepare(clk);
 230 free:
 231         sdhci_pltfm_free(pdev);
 232         return ret;
 233 }
 234
 235 static struct platform_driver sdhci_pxav2_driver = {
 236         .driver         = {
 237                 .name   = "sdhci-pxav2",
 238                 .of_match_table = of_match_ptr(sdhci_pxav2_of_match),
 239                 .pm     = &sdhci_pltfm_pmops,
 240         },
 241         .probe          = sdhci_pxav2_probe,
 242         .remove         = sdhci_pltfm_unregister,
 243 };
 244
 245 module_platform_driver(sdhci_pxav2_driver);
 246
 247 MODULE_DESCRIPTION("SDHCI driver for pxav2");
 248 MODULE_AUTHOR("Marvell International Ltd.");
 249 MODULE_LICENSE("GPL v2");
 250