1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 BayHub Technology Ltd.
5 * Authors: Peter Guo <peter.guo@bayhubtech.com>
6 * Adam Lee <adam.lee@canonical.com>
7 * Ernest Zhang <ernest.zhang@bayhubtech.com>
10 #include <linux/pci.h>
11 #include <linux/mmc/host.h>
12 #include <linux/mmc/mmc.h>
13 #include <linux/delay.h>
16 #include "sdhci-pci.h"
19 * O2Micro device registers
22 #define O2_SD_MISC_REG5 0x64
23 #define O2_SD_LD0_CTRL 0x68
24 #define O2_SD_DEV_CTRL 0x88
25 #define O2_SD_LOCK_WP 0xD3
26 #define O2_SD_TEST_REG 0xD4
27 #define O2_SD_FUNC_REG0 0xDC
28 #define O2_SD_MULTI_VCC3V 0xEE
29 #define O2_SD_CLKREQ 0xEC
30 #define O2_SD_CAPS 0xE0
31 #define O2_SD_ADMA1 0xE2
32 #define O2_SD_ADMA2 0xE7
33 #define O2_SD_INF_MOD 0xF1
34 #define O2_SD_MISC_CTRL4 0xFC
35 #define O2_SD_TUNING_CTRL 0x300
36 #define O2_SD_PLL_SETTING 0x304
37 #define O2_SD_MISC_SETTING 0x308
38 #define O2_SD_CLK_SETTING 0x328
39 #define O2_SD_CAP_REG2 0x330
40 #define O2_SD_CAP_REG0 0x334
41 #define O2_SD_UHS1_CAP_SETTING 0x33C
42 #define O2_SD_DELAY_CTRL 0x350
43 #define O2_SD_UHS2_L1_CTRL 0x35C
44 #define O2_SD_FUNC_REG3 0x3E0
45 #define O2_SD_FUNC_REG4 0x3E4
46 #define O2_SD_LED_ENABLE BIT(6)
47 #define O2_SD_FREG0_LEDOFF BIT(13)
48 #define O2_SD_FREG4_ENABLE_CLK_SET BIT(22)
50 #define O2_SD_VENDOR_SETTING 0x110
51 #define O2_SD_VENDOR_SETTING2 0x1C8
52 #define O2_SD_HW_TUNING_DISABLE BIT(4)
54 #define O2_PLL_WDT_CONTROL1 0x1CC
55 #define O2_PLL_FORCE_ACTIVE BIT(18)
56 #define O2_PLL_LOCK_STATUS BIT(14)
57 #define O2_PLL_SOFT_RESET BIT(12)
59 #define O2_SD_DETECT_SETTING 0x324
61 static void sdhci_o2_set_tuning_mode(struct sdhci_host *host)
65 /* enable hardware tuning */
66 reg = sdhci_readw(host, O2_SD_VENDOR_SETTING);
67 reg &= ~O2_SD_HW_TUNING_DISABLE;
68 sdhci_writew(host, reg, O2_SD_VENDOR_SETTING);
71 static void __sdhci_o2_execute_tuning(struct sdhci_host *host, u32 opcode)
75 sdhci_send_tuning(host, MMC_SEND_TUNING_BLOCK_HS200);
77 for (i = 0; i < 150; i++) {
78 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
80 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
81 if (ctrl & SDHCI_CTRL_TUNED_CLK) {
82 host->tuning_done = true;
85 pr_warn("%s: HW tuning failed !\n",
86 mmc_hostname(host->mmc));
93 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
94 mmc_hostname(host->mmc));
95 sdhci_reset_tuning(host);
98 static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)
100 struct sdhci_host *host = mmc_priv(mmc);
101 int current_bus_width = 0;
104 * This handler only implements the eMMC tuning that is specific to
105 * this controller. Fall back to the standard method for other TIMING.
107 if (host->timing != MMC_TIMING_MMC_HS200)
108 return sdhci_execute_tuning(mmc, opcode);
110 if (WARN_ON(opcode != MMC_SEND_TUNING_BLOCK_HS200))
114 * o2 sdhci host didn't support 8bit emmc tuning
116 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) {
117 current_bus_width = mmc->ios.bus_width;
118 mmc->ios.bus_width = MMC_BUS_WIDTH_4;
119 sdhci_set_bus_width(host, MMC_BUS_WIDTH_4);
122 sdhci_o2_set_tuning_mode(host);
124 sdhci_start_tuning(host);
126 __sdhci_o2_execute_tuning(host, opcode);
128 sdhci_end_tuning(host);
130 if (current_bus_width == MMC_BUS_WIDTH_8) {
131 mmc->ios.bus_width = MMC_BUS_WIDTH_8;
132 sdhci_set_bus_width(host, current_bus_width);
135 host->flags &= ~SDHCI_HS400_TUNING;
139 static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value)
142 pci_read_config_dword(chip->pdev,
143 O2_SD_PLL_SETTING, &scratch_32);
145 scratch_32 &= 0x0000FFFF;
148 pci_write_config_dword(chip->pdev,
149 O2_SD_PLL_SETTING, scratch_32);
152 static void o2_pci_led_enable(struct sdhci_pci_chip *chip)
157 /* Set led of SD host function enable */
158 ret = pci_read_config_dword(chip->pdev,
159 O2_SD_FUNC_REG0, &scratch_32);
163 scratch_32 &= ~O2_SD_FREG0_LEDOFF;
164 pci_write_config_dword(chip->pdev,
165 O2_SD_FUNC_REG0, scratch_32);
167 ret = pci_read_config_dword(chip->pdev,
168 O2_SD_TEST_REG, &scratch_32);
172 scratch_32 |= O2_SD_LED_ENABLE;
173 pci_write_config_dword(chip->pdev,
174 O2_SD_TEST_REG, scratch_32);
178 static void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip)
182 /* Improve write performance for SD3.0 */
183 ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32);
186 scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14));
187 pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32);
189 /* Enable Link abnormal reset generating Reset */
190 ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32);
193 scratch_32 &= ~((1 << 19) | (1 << 11));
194 scratch_32 |= (1 << 10);
195 pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32);
197 /* set card power over current protection */
198 ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32);
201 scratch_32 |= (1 << 4);
202 pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32);
204 /* adjust the output delay for SD mode */
205 pci_write_config_dword(chip->pdev, O2_SD_DELAY_CTRL, 0x00002492);
207 /* Set the output voltage setting of Aux 1.2v LDO */
208 ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32);
211 scratch_32 &= ~(3 << 12);
212 pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32);
214 /* Set Max power supply capability of SD host */
215 ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32);
218 scratch_32 &= ~(0x01FE);
219 scratch_32 |= 0x00CC;
220 pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32);
221 /* Set DLL Tuning Window */
222 ret = pci_read_config_dword(chip->pdev,
223 O2_SD_TUNING_CTRL, &scratch_32);
226 scratch_32 &= ~(0x000000FF);
227 scratch_32 |= 0x00000066;
228 pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32);
230 /* Set UHS2 T_EIDLE */
231 ret = pci_read_config_dword(chip->pdev,
232 O2_SD_UHS2_L1_CTRL, &scratch_32);
235 scratch_32 &= ~(0x000000FC);
236 scratch_32 |= 0x00000084;
237 pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32);
239 /* Set UHS2 Termination */
240 ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32);
243 scratch_32 &= ~((1 << 21) | (1 << 30));
245 pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32);
247 /* Set L1 Entrance Timer */
248 ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32);
251 scratch_32 &= ~(0xf0000000);
252 scratch_32 |= 0x30000000;
253 pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32);
255 ret = pci_read_config_dword(chip->pdev,
256 O2_SD_MISC_CTRL4, &scratch_32);
259 scratch_32 &= ~(0x000f0000);
260 scratch_32 |= 0x00080000;
261 pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32);
264 static void sdhci_pci_o2_enable_msi(struct sdhci_pci_chip *chip,
265 struct sdhci_host *host)
269 ret = pci_find_capability(chip->pdev, PCI_CAP_ID_MSI);
271 pr_info("%s: unsupport msi, use INTx irq\n",
272 mmc_hostname(host->mmc));
276 ret = pci_alloc_irq_vectors(chip->pdev, 1, 1,
277 PCI_IRQ_MSI | PCI_IRQ_MSIX);
279 pr_err("%s: enable PCI MSI failed, err=%d\n",
280 mmc_hostname(host->mmc), ret);
284 host->irq = pci_irq_vector(chip->pdev, 0);
287 static void sdhci_o2_wait_card_detect_stable(struct sdhci_host *host)
293 timeout = ktime_add_ms(ktime_get(), 50);
295 bool timedout = ktime_after(ktime_get(), timeout);
297 scratch32 = sdhci_readl(host, SDHCI_PRESENT_STATE);
298 if ((scratch32 & SDHCI_CARD_PRESENT) >> SDHCI_CARD_PRES_SHIFT
299 == (scratch32 & SDHCI_CD_LVL) >> SDHCI_CD_LVL_SHIFT)
303 pr_err("%s: Card Detect debounce never finished.\n",
304 mmc_hostname(host->mmc));
305 sdhci_dumpregs(host);
312 static void sdhci_o2_enable_internal_clock(struct sdhci_host *host)
318 /* PLL software reset */
319 scratch32 = sdhci_readl(host, O2_PLL_WDT_CONTROL1);
320 scratch32 |= O2_PLL_SOFT_RESET;
321 sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1);
323 scratch32 &= ~(O2_PLL_SOFT_RESET);
324 sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1);
326 /* PLL force active */
327 scratch32 |= O2_PLL_FORCE_ACTIVE;
328 sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1);
331 timeout = ktime_add_ms(ktime_get(), 20);
333 bool timedout = ktime_after(ktime_get(), timeout);
335 scratch = sdhci_readw(host, O2_PLL_WDT_CONTROL1);
336 if (scratch & O2_PLL_LOCK_STATUS)
339 pr_err("%s: Internal clock never stabilised.\n",
340 mmc_hostname(host->mmc));
341 sdhci_dumpregs(host);
347 /* Wait for card detect finish */
349 sdhci_o2_wait_card_detect_stable(host);
352 /* Cancel PLL force active */
353 scratch32 = sdhci_readl(host, O2_PLL_WDT_CONTROL1);
354 scratch32 &= ~O2_PLL_FORCE_ACTIVE;
355 sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1);
358 static int sdhci_o2_get_cd(struct mmc_host *mmc)
360 struct sdhci_host *host = mmc_priv(mmc);
362 sdhci_o2_enable_internal_clock(host);
364 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
367 static void sdhci_o2_enable_clk(struct sdhci_host *host, u16 clk)
369 /* Enable internal clock */
370 clk |= SDHCI_CLOCK_INT_EN;
371 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
373 if (sdhci_o2_get_cd(host->mmc)) {
374 clk |= SDHCI_CLOCK_CARD_EN;
375 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
379 void sdhci_pci_o2_set_clock(struct sdhci_host *host, unsigned int clock)
383 host->mmc->actual_clock = 0;
385 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
390 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
391 sdhci_o2_enable_clk(host, clk);
394 int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot)
396 struct sdhci_pci_chip *chip;
397 struct sdhci_host *host;
404 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
407 * mmc_select_bus_width() will test the bus to determine the actual bus
410 if (caps & SDHCI_CAN_DO_8BIT)
411 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
413 switch (chip->pdev->device) {
414 case PCI_DEVICE_ID_O2_SDS0:
415 case PCI_DEVICE_ID_O2_SEABIRD0:
416 case PCI_DEVICE_ID_O2_SEABIRD1:
417 case PCI_DEVICE_ID_O2_SDS1:
418 case PCI_DEVICE_ID_O2_FUJIN2:
419 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING);
421 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
423 sdhci_pci_o2_enable_msi(chip, host);
425 if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD0) {
426 ret = pci_read_config_dword(chip->pdev,
427 O2_SD_MISC_SETTING, ®);
430 if (reg & (1 << 4)) {
431 pr_info("%s: emmc 1.8v flag is set, force 1.8v signaling voltage\n",
432 mmc_hostname(host->mmc));
433 host->flags &= ~SDHCI_SIGNALING_330;
434 host->flags |= SDHCI_SIGNALING_180;
435 host->mmc->caps2 |= MMC_CAP2_NO_SD;
436 host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
437 pci_write_config_dword(chip->pdev,
438 O2_SD_DETECT_SETTING, 3);
441 slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd;
444 host->mmc_host_ops.execute_tuning = sdhci_o2_execute_tuning;
446 if (chip->pdev->device != PCI_DEVICE_ID_O2_FUJIN2)
448 /* set dll watch dog timer */
449 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2);
451 sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2);
461 int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip)
467 switch (chip->pdev->device) {
468 case PCI_DEVICE_ID_O2_8220:
469 case PCI_DEVICE_ID_O2_8221:
470 case PCI_DEVICE_ID_O2_8320:
471 case PCI_DEVICE_ID_O2_8321:
472 /* This extra setup is required due to broken ADMA. */
473 ret = pci_read_config_byte(chip->pdev,
474 O2_SD_LOCK_WP, &scratch);
478 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
480 /* Set Multi 3 to VCC3V# */
481 pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
483 /* Disable CLK_REQ# support after media DET */
484 ret = pci_read_config_byte(chip->pdev,
485 O2_SD_CLKREQ, &scratch);
489 pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
491 /* Choose capabilities, enable SDMA. We have to write 0x01
492 * to the capabilities register first to unlock it.
494 ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
498 pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
499 pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
501 /* Disable ADMA1/2 */
502 pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
503 pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
505 /* Disable the infinite transfer mode */
506 ret = pci_read_config_byte(chip->pdev,
507 O2_SD_INF_MOD, &scratch);
511 pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
514 ret = pci_read_config_byte(chip->pdev,
515 O2_SD_LOCK_WP, &scratch);
519 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
521 case PCI_DEVICE_ID_O2_SDS0:
522 case PCI_DEVICE_ID_O2_SDS1:
523 case PCI_DEVICE_ID_O2_FUJIN2:
525 ret = pci_read_config_byte(chip->pdev,
526 O2_SD_LOCK_WP, &scratch);
531 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
533 /* DevId=8520 subId= 0x11 or 0x12 Type Chip support */
534 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) {
535 ret = pci_read_config_dword(chip->pdev,
538 scratch_32 = ((scratch_32 & 0xFF000000) >> 24);
540 /* Check Whether subId is 0x11 or 0x12 */
541 if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) {
542 scratch_32 = 0x25100000;
544 o2_pci_set_baseclk(chip, scratch_32);
545 ret = pci_read_config_dword(chip->pdev,
549 /* Enable Base Clk setting change */
550 scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;
551 pci_write_config_dword(chip->pdev,
555 /* Set Tuning Window to 4 */
556 pci_write_config_byte(chip->pdev,
557 O2_SD_TUNING_CTRL, 0x44);
563 /* Enable 8520 led function */
564 o2_pci_led_enable(chip);
566 /* Set timeout CLK */
567 ret = pci_read_config_dword(chip->pdev,
568 O2_SD_CLK_SETTING, &scratch_32);
572 scratch_32 &= ~(0xFF00);
573 scratch_32 |= 0x07E0C800;
574 pci_write_config_dword(chip->pdev,
575 O2_SD_CLK_SETTING, scratch_32);
577 ret = pci_read_config_dword(chip->pdev,
578 O2_SD_CLKREQ, &scratch_32);
582 pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32);
584 ret = pci_read_config_dword(chip->pdev,
585 O2_SD_PLL_SETTING, &scratch_32);
589 scratch_32 &= ~(0x1F3F070E);
590 scratch_32 |= 0x18270106;
591 pci_write_config_dword(chip->pdev,
592 O2_SD_PLL_SETTING, scratch_32);
594 /* Disable UHS1 funciton */
595 ret = pci_read_config_dword(chip->pdev,
596 O2_SD_CAP_REG2, &scratch_32);
599 scratch_32 &= ~(0xE0);
600 pci_write_config_dword(chip->pdev,
601 O2_SD_CAP_REG2, scratch_32);
603 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2)
604 sdhci_pci_o2_fujin2_pci_init(chip);
607 ret = pci_read_config_byte(chip->pdev,
608 O2_SD_LOCK_WP, &scratch);
612 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
614 case PCI_DEVICE_ID_O2_SEABIRD0:
615 case PCI_DEVICE_ID_O2_SEABIRD1:
617 ret = pci_read_config_byte(chip->pdev,
618 O2_SD_LOCK_WP, &scratch);
623 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
625 ret = pci_read_config_dword(chip->pdev,
626 O2_SD_PLL_SETTING, &scratch_32);
628 if ((scratch_32 & 0xff000000) == 0x01000000) {
629 scratch_32 &= 0x0000FFFF;
630 scratch_32 |= 0x1F340000;
632 pci_write_config_dword(chip->pdev,
633 O2_SD_PLL_SETTING, scratch_32);
635 scratch_32 &= 0x0000FFFF;
636 scratch_32 |= 0x25100000;
638 pci_write_config_dword(chip->pdev,
639 O2_SD_PLL_SETTING, scratch_32);
641 ret = pci_read_config_dword(chip->pdev,
644 scratch_32 |= (1 << 22);
645 pci_write_config_dword(chip->pdev,
646 O2_SD_FUNC_REG4, scratch_32);
649 /* Set Tuning Windows to 5 */
650 pci_write_config_byte(chip->pdev,
651 O2_SD_TUNING_CTRL, 0x55);
653 ret = pci_read_config_byte(chip->pdev,
654 O2_SD_LOCK_WP, &scratch);
658 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
665 #ifdef CONFIG_PM_SLEEP
666 int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip)
668 sdhci_pci_o2_probe(chip);
669 return sdhci_pci_resume_host(chip);
673 static const struct sdhci_ops sdhci_pci_o2_ops = {
674 .set_clock = sdhci_pci_o2_set_clock,
675 .enable_dma = sdhci_pci_enable_dma,
676 .set_bus_width = sdhci_set_bus_width,
677 .reset = sdhci_reset,
678 .set_uhs_signaling = sdhci_set_uhs_signaling,
681 const struct sdhci_pci_fixes sdhci_o2 = {
682 .probe = sdhci_pci_o2_probe,
683 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
684 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD,
685 .probe_slot = sdhci_pci_o2_probe_slot,
686 #ifdef CONFIG_PM_SLEEP
687 .resume = sdhci_pci_o2_resume,
689 .ops = &sdhci_pci_o2_ops,