1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
10 * Thanks to the following companies for their support:
12 * - JMicron (hardware and technical support)
15 #include <linux/string.h>
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/device.h>
23 #include <linux/mmc/host.h>
24 #include <linux/mmc/mmc.h>
25 #include <linux/scatterlist.h>
27 #include <linux/gpio.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/mmc/slot-gpio.h>
30 #include <linux/mmc/sdhci-pci-data.h>
31 #include <linux/acpi.h>
34 #include "sdhci-pci.h"
35 #include "sdhci-pci-o2micro.h"
37 static int sdhci_pci_enable_dma(struct sdhci_host *host);
38 static void sdhci_pci_hw_reset(struct sdhci_host *host);
40 #ifdef CONFIG_PM_SLEEP
41 static int __sdhci_pci_suspend_host(struct sdhci_pci_chip *chip)
45 for (i = 0; i < chip->num_slots; i++) {
46 struct sdhci_pci_slot *slot = chip->slots[i];
47 struct sdhci_host *host;
54 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3)
55 mmc_retune_needed(host->mmc);
57 ret = sdhci_suspend_host(host);
61 if (host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ)
62 sdhci_enable_irq_wakeups(host);
69 sdhci_resume_host(chip->slots[i]->host);
73 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip)
75 mmc_pm_flag_t pm_flags = 0;
78 for (i = 0; i < chip->num_slots; i++) {
79 struct sdhci_pci_slot *slot = chip->slots[i];
82 pm_flags |= slot->host->mmc->pm_flags;
85 return device_init_wakeup(&chip->pdev->dev,
86 (pm_flags & MMC_PM_KEEP_POWER) &&
87 (pm_flags & MMC_PM_WAKE_SDIO_IRQ));
90 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip)
94 ret = __sdhci_pci_suspend_host(chip);
98 sdhci_pci_init_wakeup(chip);
103 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip)
105 struct sdhci_pci_slot *slot;
108 for (i = 0; i < chip->num_slots; i++) {
109 slot = chip->slots[i];
113 ret = sdhci_resume_host(slot->host);
123 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip)
125 struct sdhci_pci_slot *slot;
126 struct sdhci_host *host;
129 for (i = 0; i < chip->num_slots; i++) {
130 slot = chip->slots[i];
136 ret = sdhci_runtime_suspend_host(host);
138 goto err_pci_runtime_suspend;
140 if (chip->rpm_retune &&
141 host->tuning_mode != SDHCI_TUNING_MODE_3)
142 mmc_retune_needed(host->mmc);
147 err_pci_runtime_suspend:
149 sdhci_runtime_resume_host(chip->slots[i]->host);
153 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip)
155 struct sdhci_pci_slot *slot;
158 for (i = 0; i < chip->num_slots; i++) {
159 slot = chip->slots[i];
163 ret = sdhci_runtime_resume_host(slot->host);
172 /*****************************************************************************\
174 * Hardware specific quirk handling *
176 \*****************************************************************************/
178 static int ricoh_probe(struct sdhci_pci_chip *chip)
180 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
181 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
182 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
186 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
189 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
190 & SDHCI_TIMEOUT_CLK_MASK) |
192 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
193 & SDHCI_CLOCK_BASE_MASK) |
195 SDHCI_TIMEOUT_CLK_UNIT |
202 #ifdef CONFIG_PM_SLEEP
203 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
205 /* Apply a delay to allow controller to settle */
206 /* Otherwise it becomes confused if card state changed
209 return sdhci_pci_resume_host(chip);
213 static const struct sdhci_pci_fixes sdhci_ricoh = {
214 .probe = ricoh_probe,
215 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
216 SDHCI_QUIRK_FORCE_DMA |
217 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
220 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
221 .probe_slot = ricoh_mmc_probe_slot,
222 #ifdef CONFIG_PM_SLEEP
223 .resume = ricoh_mmc_resume,
225 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
226 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
227 SDHCI_QUIRK_NO_CARD_NO_RESET |
228 SDHCI_QUIRK_MISSING_CAPS
231 static const struct sdhci_pci_fixes sdhci_ene_712 = {
232 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
233 SDHCI_QUIRK_BROKEN_DMA,
236 static const struct sdhci_pci_fixes sdhci_ene_714 = {
237 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
238 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
239 SDHCI_QUIRK_BROKEN_DMA,
242 static const struct sdhci_pci_fixes sdhci_cafe = {
243 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
244 SDHCI_QUIRK_NO_BUSY_IRQ |
245 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
246 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
249 static const struct sdhci_pci_fixes sdhci_intel_qrk = {
250 .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
253 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
255 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
260 * ADMA operation is disabled for Moorestown platform due to
263 static int mrst_hc_probe(struct sdhci_pci_chip *chip)
266 * slots number is fixed here for MRST as SDIO3/5 are never used and
267 * have hardware bugs.
273 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
275 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
281 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
283 struct sdhci_pci_slot *slot = dev_id;
284 struct sdhci_host *host = slot->host;
286 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
290 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
292 int err, irq, gpio = slot->cd_gpio;
294 slot->cd_gpio = -EINVAL;
295 slot->cd_irq = -EINVAL;
297 if (!gpio_is_valid(gpio))
300 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd");
304 err = gpio_direction_input(gpio);
308 irq = gpio_to_irq(gpio);
312 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
313 IRQF_TRIGGER_FALLING, "sd_cd", slot);
317 slot->cd_gpio = gpio;
323 devm_gpio_free(&slot->chip->pdev->dev, gpio);
325 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
328 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
330 if (slot->cd_irq >= 0)
331 free_irq(slot->cd_irq, slot);
336 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
340 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
346 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
348 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
349 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC;
353 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
355 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
359 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
360 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
361 .probe_slot = mrst_hc_probe_slot,
364 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
365 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
366 .probe = mrst_hc_probe,
369 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
370 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
371 .allow_runtime_pm = true,
372 .own_cd_for_runtime_pm = true,
375 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
376 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
377 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
378 .allow_runtime_pm = true,
379 .probe_slot = mfd_sdio_probe_slot,
382 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
383 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
384 .allow_runtime_pm = true,
385 .probe_slot = mfd_emmc_probe_slot,
388 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
389 .quirks = SDHCI_QUIRK_BROKEN_ADMA,
390 .probe_slot = pch_hc_probe_slot,
395 INTEL_DSM_V18_SWITCH = 3,
396 INTEL_DSM_DRV_STRENGTH = 9,
397 INTEL_DSM_D3_RETUNE = 10,
406 static const guid_t intel_dsm_guid =
407 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F,
408 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61);
410 static int __intel_dsm(struct intel_host *intel_host, struct device *dev,
411 unsigned int fn, u32 *result)
413 union acpi_object *obj;
417 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL);
421 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) {
426 len = min_t(size_t, obj->buffer.length, 4);
429 memcpy(result, obj->buffer.pointer, len);
436 static int intel_dsm(struct intel_host *intel_host, struct device *dev,
437 unsigned int fn, u32 *result)
439 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn)))
442 return __intel_dsm(intel_host, dev, fn, result);
445 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev,
446 struct mmc_host *mmc)
451 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns);
453 pr_debug("%s: DSM not supported, error %d\n",
454 mmc_hostname(mmc), err);
458 pr_debug("%s: DSM function mask %#x\n",
459 mmc_hostname(mmc), intel_host->dsm_fns);
461 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val);
462 intel_host->drv_strength = err ? 0 : val;
464 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val);
465 intel_host->d3_retune = err ? true : !!val;
468 static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
472 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
474 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
475 /* For eMMC, minimum is 1us but give it 9us for good measure */
478 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
479 /* For eMMC, minimum is 200us but give it 300us for good measure */
480 usleep_range(300, 1000);
483 static int intel_select_drive_strength(struct mmc_card *card,
484 unsigned int max_dtr, int host_drv,
485 int card_drv, int *drv_type)
487 struct sdhci_host *host = mmc_priv(card->host);
488 struct sdhci_pci_slot *slot = sdhci_priv(host);
489 struct intel_host *intel_host = sdhci_pci_priv(slot);
491 return intel_host->drv_strength;
494 static int bxt_get_cd(struct mmc_host *mmc)
496 int gpio_cd = mmc_gpio_get_cd(mmc);
497 struct sdhci_host *host = mmc_priv(mmc);
504 spin_lock_irqsave(&host->lock, flags);
506 if (host->flags & SDHCI_DEVICE_DEAD)
509 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
511 spin_unlock_irqrestore(&host->lock, flags);
516 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20
517 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100
519 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode,
525 sdhci_set_power(host, mode, vdd);
527 if (mode == MMC_POWER_OFF)
531 * Bus power might not enable after D3 -> D0 transition due to the
532 * present state not yet having propagated. Retry for up to 2ms.
534 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) {
535 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
536 if (reg & SDHCI_POWER_ON)
538 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY);
539 reg |= SDHCI_POWER_ON;
540 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
544 #define INTEL_HS400_ES_REG 0x78
545 #define INTEL_HS400_ES_BIT BIT(0)
547 static void intel_hs400_enhanced_strobe(struct mmc_host *mmc,
550 struct sdhci_host *host = mmc_priv(mmc);
553 val = sdhci_readl(host, INTEL_HS400_ES_REG);
554 if (ios->enhanced_strobe)
555 val |= INTEL_HS400_ES_BIT;
557 val &= ~INTEL_HS400_ES_BIT;
558 sdhci_writel(host, val, INTEL_HS400_ES_REG);
561 static void sdhci_intel_voltage_switch(struct sdhci_host *host)
563 struct sdhci_pci_slot *slot = sdhci_priv(host);
564 struct intel_host *intel_host = sdhci_pci_priv(slot);
565 struct device *dev = &slot->chip->pdev->dev;
569 err = intel_dsm(intel_host, dev, INTEL_DSM_V18_SWITCH, &result);
570 pr_debug("%s: %s DSM error %d result %u\n",
571 mmc_hostname(host->mmc), __func__, err, result);
574 static const struct sdhci_ops sdhci_intel_byt_ops = {
575 .set_clock = sdhci_set_clock,
576 .set_power = sdhci_intel_set_power,
577 .enable_dma = sdhci_pci_enable_dma,
578 .set_bus_width = sdhci_set_bus_width,
579 .reset = sdhci_reset,
580 .set_uhs_signaling = sdhci_set_uhs_signaling,
581 .hw_reset = sdhci_pci_hw_reset,
582 .voltage_switch = sdhci_intel_voltage_switch,
585 static void byt_read_dsm(struct sdhci_pci_slot *slot)
587 struct intel_host *intel_host = sdhci_pci_priv(slot);
588 struct device *dev = &slot->chip->pdev->dev;
589 struct mmc_host *mmc = slot->host->mmc;
591 intel_dsm_init(intel_host, dev, mmc);
592 slot->chip->rpm_retune = intel_host->d3_retune;
595 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
598 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
599 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
600 MMC_CAP_CMD_DURING_TFR |
601 MMC_CAP_WAIT_WHILE_BUSY;
602 slot->hw_reset = sdhci_pci_int_hw_reset;
603 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
604 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
605 slot->host->mmc_host_ops.select_drive_strength =
606 intel_select_drive_strength;
610 static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot)
612 int ret = byt_emmc_probe_slot(slot);
614 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) {
615 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES,
616 slot->host->mmc_host_ops.hs400_enhanced_strobe =
617 intel_hs400_enhanced_strobe;
624 static int ni_set_max_freq(struct sdhci_pci_slot *slot)
627 unsigned long long max_freq;
629 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev),
630 "MXFQ", NULL, &max_freq);
631 if (ACPI_FAILURE(status)) {
632 dev_err(&slot->chip->pdev->dev,
633 "MXFQ not found in acpi table\n");
637 slot->host->mmc->f_max = max_freq * 1000000;
642 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot)
648 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
654 err = ni_set_max_freq(slot);
658 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
659 MMC_CAP_WAIT_WHILE_BUSY;
663 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
666 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
667 MMC_CAP_WAIT_WHILE_BUSY;
671 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
674 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY |
675 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE;
677 slot->cd_override_level = true;
678 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD ||
679 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD ||
680 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD ||
681 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD)
682 slot->host->mmc_host_ops.get_cd = bxt_get_cd;
687 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
688 .allow_runtime_pm = true,
689 .probe_slot = byt_emmc_probe_slot,
690 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
691 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
692 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
693 SDHCI_QUIRK2_STOP_WITH_TC,
694 .ops = &sdhci_intel_byt_ops,
695 .priv_size = sizeof(struct intel_host),
698 static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = {
699 .allow_runtime_pm = true,
700 .probe_slot = glk_emmc_probe_slot,
701 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
702 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
703 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
704 SDHCI_QUIRK2_STOP_WITH_TC,
705 .ops = &sdhci_intel_byt_ops,
706 .priv_size = sizeof(struct intel_host),
709 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = {
710 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
711 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
712 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
713 .allow_runtime_pm = true,
714 .probe_slot = ni_byt_sdio_probe_slot,
715 .ops = &sdhci_intel_byt_ops,
716 .priv_size = sizeof(struct intel_host),
719 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
720 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
721 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
722 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
723 .allow_runtime_pm = true,
724 .probe_slot = byt_sdio_probe_slot,
725 .ops = &sdhci_intel_byt_ops,
726 .priv_size = sizeof(struct intel_host),
729 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
730 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
731 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
732 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
733 SDHCI_QUIRK2_STOP_WITH_TC,
734 .allow_runtime_pm = true,
735 .own_cd_for_runtime_pm = true,
736 .probe_slot = byt_sd_probe_slot,
737 .ops = &sdhci_intel_byt_ops,
738 .priv_size = sizeof(struct intel_host),
741 /* Define Host controllers for Intel Merrifield platform */
742 #define INTEL_MRFLD_EMMC_0 0
743 #define INTEL_MRFLD_EMMC_1 1
744 #define INTEL_MRFLD_SD 2
745 #define INTEL_MRFLD_SDIO 3
748 static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot)
750 struct acpi_device *device, *child;
752 device = ACPI_COMPANION(&slot->chip->pdev->dev);
756 acpi_device_fix_up_power(device);
757 list_for_each_entry(child, &device->children, node)
758 if (child->status.present && child->status.enabled)
759 acpi_device_fix_up_power(child);
762 static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {}
765 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot)
767 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn);
770 case INTEL_MRFLD_EMMC_0:
771 case INTEL_MRFLD_EMMC_1:
772 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
777 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
779 case INTEL_MRFLD_SDIO:
780 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
781 MMC_CAP_POWER_OFF_CARD;
787 intel_mrfld_mmc_fix_up_power_slot(slot);
791 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = {
792 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
793 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
794 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
795 .allow_runtime_pm = true,
796 .probe_slot = intel_mrfld_mmc_probe_slot,
799 /* O2Micro extra registers */
800 #define O2_SD_LOCK_WP 0xD3
801 #define O2_SD_MULTI_VCC3V 0xEE
802 #define O2_SD_CLKREQ 0xEC
803 #define O2_SD_CAPS 0xE0
804 #define O2_SD_ADMA1 0xE2
805 #define O2_SD_ADMA2 0xE7
806 #define O2_SD_INF_MOD 0xF1
808 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
813 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
818 * Turn PMOS on [bit 0], set over current detection to 2.4 V
819 * [bit 1:2] and enable over current debouncing [bit 6].
826 return pci_write_config_byte(chip->pdev, 0xAE, scratch);
829 static int jmicron_probe(struct sdhci_pci_chip *chip)
834 if (chip->pdev->revision == 0) {
835 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
836 SDHCI_QUIRK_32BIT_DMA_SIZE |
837 SDHCI_QUIRK_32BIT_ADMA_SIZE |
838 SDHCI_QUIRK_RESET_AFTER_REQUEST |
839 SDHCI_QUIRK_BROKEN_SMALL_PIO;
843 * JMicron chips can have two interfaces to the same hardware
844 * in order to work around limitations in Microsoft's driver.
845 * We need to make sure we only bind to one of them.
847 * This code assumes two things:
849 * 1. The PCI code adds subfunctions in order.
851 * 2. The MMC interface has a lower subfunction number
852 * than the SD interface.
854 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
855 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
856 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
857 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
860 struct pci_dev *sd_dev;
863 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
864 mmcdev, sd_dev)) != NULL) {
865 if ((PCI_SLOT(chip->pdev->devfn) ==
866 PCI_SLOT(sd_dev->devfn)) &&
867 (chip->pdev->bus == sd_dev->bus))
873 dev_info(&chip->pdev->dev, "Refusing to bind to "
874 "secondary interface.\n");
880 * JMicron chips need a bit of a nudge to enable the power
883 ret = jmicron_pmos(chip, 1);
885 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
889 /* quirk for unsable RO-detection on JM388 chips */
890 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
891 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
892 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
897 static void jmicron_enable_mmc(struct sdhci_host *host, int on)
901 scratch = readb(host->ioaddr + 0xC0);
908 writeb(scratch, host->ioaddr + 0xC0);
911 static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
913 if (slot->chip->pdev->revision == 0) {
916 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
917 version = (version & SDHCI_VENDOR_VER_MASK) >>
918 SDHCI_VENDOR_VER_SHIFT;
921 * Older versions of the chip have lots of nasty glitches
922 * in the ADMA engine. It's best just to avoid it
926 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
929 /* JM388 MMC doesn't support 1.8V while SD supports it */
930 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
931 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
932 MMC_VDD_29_30 | MMC_VDD_30_31 |
933 MMC_VDD_165_195; /* allow 1.8V */
934 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
935 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
939 * The secondary interface requires a bit set to get the
942 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
943 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
944 jmicron_enable_mmc(slot->host, 1);
946 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
951 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
956 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
957 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
958 jmicron_enable_mmc(slot->host, 0);
961 #ifdef CONFIG_PM_SLEEP
962 static int jmicron_suspend(struct sdhci_pci_chip *chip)
966 ret = __sdhci_pci_suspend_host(chip);
970 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
971 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
972 for (i = 0; i < chip->num_slots; i++)
973 jmicron_enable_mmc(chip->slots[i]->host, 0);
976 sdhci_pci_init_wakeup(chip);
981 static int jmicron_resume(struct sdhci_pci_chip *chip)
985 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
986 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
987 for (i = 0; i < chip->num_slots; i++)
988 jmicron_enable_mmc(chip->slots[i]->host, 1);
991 ret = jmicron_pmos(chip, 1);
993 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
997 return sdhci_pci_resume_host(chip);
1001 static const struct sdhci_pci_fixes sdhci_o2 = {
1002 .probe = sdhci_pci_o2_probe,
1003 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1004 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD,
1005 .probe_slot = sdhci_pci_o2_probe_slot,
1006 #ifdef CONFIG_PM_SLEEP
1007 .resume = sdhci_pci_o2_resume,
1011 static const struct sdhci_pci_fixes sdhci_jmicron = {
1012 .probe = jmicron_probe,
1014 .probe_slot = jmicron_probe_slot,
1015 .remove_slot = jmicron_remove_slot,
1017 #ifdef CONFIG_PM_SLEEP
1018 .suspend = jmicron_suspend,
1019 .resume = jmicron_resume,
1023 /* SysKonnect CardBus2SDIO extra registers */
1024 #define SYSKT_CTRL 0x200
1025 #define SYSKT_RDFIFO_STAT 0x204
1026 #define SYSKT_WRFIFO_STAT 0x208
1027 #define SYSKT_POWER_DATA 0x20c
1028 #define SYSKT_POWER_330 0xef
1029 #define SYSKT_POWER_300 0xf8
1030 #define SYSKT_POWER_184 0xcc
1031 #define SYSKT_POWER_CMD 0x20d
1032 #define SYSKT_POWER_START (1 << 7)
1033 #define SYSKT_POWER_STATUS 0x20e
1034 #define SYSKT_POWER_STATUS_OK (1 << 0)
1035 #define SYSKT_BOARD_REV 0x210
1036 #define SYSKT_CHIP_REV 0x211
1037 #define SYSKT_CONF_DATA 0x212
1038 #define SYSKT_CONF_DATA_1V8 (1 << 2)
1039 #define SYSKT_CONF_DATA_2V5 (1 << 1)
1040 #define SYSKT_CONF_DATA_3V3 (1 << 0)
1042 static int syskt_probe(struct sdhci_pci_chip *chip)
1044 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1045 chip->pdev->class &= ~0x0000FF;
1046 chip->pdev->class |= PCI_SDHCI_IFDMA;
1051 static int syskt_probe_slot(struct sdhci_pci_slot *slot)
1055 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
1056 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
1057 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
1058 "board rev %d.%d, chip rev %d.%d\n",
1059 board_rev >> 4, board_rev & 0xf,
1060 chip_rev >> 4, chip_rev & 0xf);
1061 if (chip_rev >= 0x20)
1062 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
1064 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
1065 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
1067 tm = 10; /* Wait max 1 ms */
1069 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
1070 if (ps & SYSKT_POWER_STATUS_OK)
1075 dev_err(&slot->chip->pdev->dev,
1076 "power regulator never stabilized");
1077 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
1084 static const struct sdhci_pci_fixes sdhci_syskt = {
1085 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
1086 .probe = syskt_probe,
1087 .probe_slot = syskt_probe_slot,
1090 static int via_probe(struct sdhci_pci_chip *chip)
1092 if (chip->pdev->revision == 0x10)
1093 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
1098 static const struct sdhci_pci_fixes sdhci_via = {
1102 static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
1104 slot->host->mmc->caps2 |= MMC_CAP2_HS200;
1108 static const struct sdhci_pci_fixes sdhci_rtsx = {
1109 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1110 SDHCI_QUIRK2_BROKEN_64_BIT_DMA |
1111 SDHCI_QUIRK2_BROKEN_DDR50,
1112 .probe_slot = rtsx_probe_slot,
1115 /*AMD chipset generation*/
1116 enum amd_chipset_gen {
1117 AMD_CHIPSET_BEFORE_ML,
1120 AMD_CHIPSET_UNKNOWN,
1124 #define AMD_SD_AUTO_PATTERN 0xB8
1125 #define AMD_MSLEEP_DURATION 4
1126 #define AMD_SD_MISC_CONTROL 0xD0
1127 #define AMD_MAX_TUNE_VALUE 0x0B
1128 #define AMD_AUTO_TUNE_SEL 0x10800
1129 #define AMD_FIFO_PTR 0x30
1130 #define AMD_BIT_MASK 0x1F
1132 static void amd_tuning_reset(struct sdhci_host *host)
1136 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1137 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING;
1138 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1140 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1141 val &= ~SDHCI_CTRL_EXEC_TUNING;
1142 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1145 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase)
1149 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val);
1150 val &= ~AMD_BIT_MASK;
1151 val |= (AMD_AUTO_TUNE_SEL | (phase << 1));
1152 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val);
1155 static void amd_enable_manual_tuning(struct pci_dev *pdev)
1159 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val);
1160 val |= AMD_FIFO_PTR;
1161 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val);
1164 static int amd_execute_tuning(struct sdhci_host *host, u32 opcode)
1166 struct sdhci_pci_slot *slot = sdhci_priv(host);
1167 struct pci_dev *pdev = slot->chip->pdev;
1169 u8 valid_win_max = 0;
1170 u8 valid_win_end = 0;
1171 u8 ctrl, tune_around;
1173 amd_tuning_reset(host);
1175 for (tune_around = 0; tune_around < 12; tune_around++) {
1176 amd_config_tuning_phase(pdev, tune_around);
1178 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
1180 msleep(AMD_MSLEEP_DURATION);
1181 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA;
1182 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET);
1183 } else if (++valid_win > valid_win_max) {
1184 valid_win_max = valid_win;
1185 valid_win_end = tune_around;
1189 if (!valid_win_max) {
1190 dev_err(&pdev->dev, "no tuning point found\n");
1194 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2);
1196 amd_enable_manual_tuning(pdev);
1198 host->mmc->retune_period = 0;
1203 static int amd_probe(struct sdhci_pci_chip *chip)
1205 struct pci_dev *smbus_dev;
1206 enum amd_chipset_gen gen;
1208 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1209 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
1211 gen = AMD_CHIPSET_BEFORE_ML;
1213 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1214 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL);
1216 if (smbus_dev->revision < 0x51)
1217 gen = AMD_CHIPSET_CZ;
1219 gen = AMD_CHIPSET_NL;
1221 gen = AMD_CHIPSET_UNKNOWN;
1225 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ)
1226 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
1231 static const struct sdhci_ops amd_sdhci_pci_ops = {
1232 .set_clock = sdhci_set_clock,
1233 .enable_dma = sdhci_pci_enable_dma,
1234 .set_bus_width = sdhci_set_bus_width,
1235 .reset = sdhci_reset,
1236 .set_uhs_signaling = sdhci_set_uhs_signaling,
1237 .platform_execute_tuning = amd_execute_tuning,
1240 static const struct sdhci_pci_fixes sdhci_amd = {
1242 .ops = &amd_sdhci_pci_ops,
1245 static const struct pci_device_id pci_ids[] = {
1246 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh),
1247 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc),
1248 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc),
1249 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc),
1250 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712),
1251 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712),
1252 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714),
1253 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714),
1254 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe),
1255 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron),
1256 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron),
1257 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron),
1258 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron),
1259 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt),
1260 SDHCI_PCI_DEVICE(VIA, 95D0, via),
1261 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx),
1262 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk),
1263 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0),
1264 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2),
1265 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2),
1266 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd),
1267 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio),
1268 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio),
1269 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc),
1270 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc),
1271 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio),
1272 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio),
1273 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc),
1274 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio),
1275 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio),
1276 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd),
1277 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc),
1278 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc),
1279 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio),
1280 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd),
1281 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd),
1282 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio),
1283 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio),
1284 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc),
1285 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc),
1286 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc),
1287 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc),
1288 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio),
1289 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd),
1290 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc),
1291 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc),
1292 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio),
1293 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd),
1294 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc),
1295 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio),
1296 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd),
1297 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc),
1298 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio),
1299 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd),
1300 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc),
1301 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio),
1302 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd),
1303 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc),
1304 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd),
1305 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd),
1306 SDHCI_PCI_DEVICE(O2, 8120, o2),
1307 SDHCI_PCI_DEVICE(O2, 8220, o2),
1308 SDHCI_PCI_DEVICE(O2, 8221, o2),
1309 SDHCI_PCI_DEVICE(O2, 8320, o2),
1310 SDHCI_PCI_DEVICE(O2, 8321, o2),
1311 SDHCI_PCI_DEVICE(O2, FUJIN2, o2),
1312 SDHCI_PCI_DEVICE(O2, SDS0, o2),
1313 SDHCI_PCI_DEVICE(O2, SDS1, o2),
1314 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2),
1315 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2),
1316 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd),
1317 /* Generic SD host controller */
1318 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)},
1319 { /* end: all zeroes */ },
1322 MODULE_DEVICE_TABLE(pci, pci_ids);
1324 /*****************************************************************************\
1326 * SDHCI core callbacks *
1328 \*****************************************************************************/
1330 static int sdhci_pci_enable_dma(struct sdhci_host *host)
1332 struct sdhci_pci_slot *slot;
1333 struct pci_dev *pdev;
1335 slot = sdhci_priv(host);
1336 pdev = slot->chip->pdev;
1338 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1339 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1340 (host->flags & SDHCI_USE_SDMA)) {
1341 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1342 "doesn't fully claim to support it.\n");
1345 pci_set_master(pdev);
1350 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
1352 struct sdhci_pci_slot *slot = sdhci_priv(host);
1353 int rst_n_gpio = slot->rst_n_gpio;
1355 if (!gpio_is_valid(rst_n_gpio))
1357 gpio_set_value_cansleep(rst_n_gpio, 0);
1358 /* For eMMC, minimum is 1us but give it 10us for good measure */
1360 gpio_set_value_cansleep(rst_n_gpio, 1);
1361 /* For eMMC, minimum is 200us but give it 300us for good measure */
1362 usleep_range(300, 1000);
1365 static void sdhci_pci_hw_reset(struct sdhci_host *host)
1367 struct sdhci_pci_slot *slot = sdhci_priv(host);
1370 slot->hw_reset(host);
1373 static const struct sdhci_ops sdhci_pci_ops = {
1374 .set_clock = sdhci_set_clock,
1375 .enable_dma = sdhci_pci_enable_dma,
1376 .set_bus_width = sdhci_set_bus_width,
1377 .reset = sdhci_reset,
1378 .set_uhs_signaling = sdhci_set_uhs_signaling,
1379 .hw_reset = sdhci_pci_hw_reset,
1382 /*****************************************************************************\
1386 \*****************************************************************************/
1388 #ifdef CONFIG_PM_SLEEP
1389 static int sdhci_pci_suspend(struct device *dev)
1391 struct pci_dev *pdev = to_pci_dev(dev);
1392 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1397 if (chip->fixes && chip->fixes->suspend)
1398 return chip->fixes->suspend(chip);
1400 return sdhci_pci_suspend_host(chip);
1403 static int sdhci_pci_resume(struct device *dev)
1405 struct pci_dev *pdev = to_pci_dev(dev);
1406 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1411 if (chip->fixes && chip->fixes->resume)
1412 return chip->fixes->resume(chip);
1414 return sdhci_pci_resume_host(chip);
1419 static int sdhci_pci_runtime_suspend(struct device *dev)
1421 struct pci_dev *pdev = to_pci_dev(dev);
1422 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1427 if (chip->fixes && chip->fixes->runtime_suspend)
1428 return chip->fixes->runtime_suspend(chip);
1430 return sdhci_pci_runtime_suspend_host(chip);
1433 static int sdhci_pci_runtime_resume(struct device *dev)
1435 struct pci_dev *pdev = to_pci_dev(dev);
1436 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1441 if (chip->fixes && chip->fixes->runtime_resume)
1442 return chip->fixes->runtime_resume(chip);
1444 return sdhci_pci_runtime_resume_host(chip);
1448 static const struct dev_pm_ops sdhci_pci_pm_ops = {
1449 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume)
1450 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
1451 sdhci_pci_runtime_resume, NULL)
1454 /*****************************************************************************\
1456 * Device probing/removal *
1458 \*****************************************************************************/
1460 static struct sdhci_pci_slot *sdhci_pci_probe_slot(
1461 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1464 struct sdhci_pci_slot *slot;
1465 struct sdhci_host *host;
1466 int ret, bar = first_bar + slotno;
1467 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0;
1469 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1470 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1471 return ERR_PTR(-ENODEV);
1474 if (pci_resource_len(pdev, bar) < 0x100) {
1475 dev_err(&pdev->dev, "Invalid iomem size. You may "
1476 "experience problems.\n");
1479 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1480 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1481 return ERR_PTR(-ENODEV);
1484 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1485 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1486 return ERR_PTR(-ENODEV);
1489 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size);
1491 dev_err(&pdev->dev, "cannot allocate host\n");
1492 return ERR_CAST(host);
1495 slot = sdhci_priv(host);
1499 slot->rst_n_gpio = -EINVAL;
1500 slot->cd_gpio = -EINVAL;
1503 /* Retrieve platform data if there is any */
1504 if (*sdhci_pci_get_data)
1505 slot->data = sdhci_pci_get_data(pdev, slotno);
1508 if (slot->data->setup) {
1509 ret = slot->data->setup(slot->data);
1511 dev_err(&pdev->dev, "platform setup failed\n");
1515 slot->rst_n_gpio = slot->data->rst_n_gpio;
1516 slot->cd_gpio = slot->data->cd_gpio;
1519 host->hw_name = "PCI";
1520 host->ops = chip->fixes && chip->fixes->ops ?
1523 host->quirks = chip->quirks;
1524 host->quirks2 = chip->quirks2;
1526 host->irq = pdev->irq;
1528 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc));
1530 dev_err(&pdev->dev, "cannot request region\n");
1534 host->ioaddr = pcim_iomap_table(pdev)[bar];
1536 if (chip->fixes && chip->fixes->probe_slot) {
1537 ret = chip->fixes->probe_slot(slot);
1542 if (gpio_is_valid(slot->rst_n_gpio)) {
1543 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) {
1544 gpio_direction_output(slot->rst_n_gpio, 1);
1545 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
1546 slot->hw_reset = sdhci_pci_gpio_hw_reset;
1548 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1549 slot->rst_n_gpio = -EINVAL;
1553 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
1554 host->mmc->slotno = slotno;
1555 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
1557 if (slot->cd_idx >= 0) {
1558 ret = mmc_gpiod_request_cd(host->mmc, NULL, slot->cd_idx,
1559 slot->cd_override_level, 0, NULL);
1560 if (ret == -EPROBE_DEFER)
1564 dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
1569 if (chip->fixes && chip->fixes->add_host)
1570 ret = chip->fixes->add_host(slot);
1572 ret = sdhci_add_host(host);
1576 sdhci_pci_add_own_cd(slot);
1579 * Check if the chip needs a separate GPIO for card detect to wake up
1580 * from runtime suspend. If it is not there, don't allow runtime PM.
1581 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure.
1583 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
1584 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0)
1585 chip->allow_runtime_pm = false;
1590 if (chip->fixes && chip->fixes->remove_slot)
1591 chip->fixes->remove_slot(slot, 0);
1594 if (slot->data && slot->data->cleanup)
1595 slot->data->cleanup(slot->data);
1598 sdhci_free_host(host);
1600 return ERR_PTR(ret);
1603 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1608 sdhci_pci_remove_own_cd(slot);
1611 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1612 if (scratch == (u32)-1)
1615 sdhci_remove_host(slot->host, dead);
1617 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1618 slot->chip->fixes->remove_slot(slot, dead);
1620 if (slot->data && slot->data->cleanup)
1621 slot->data->cleanup(slot->data);
1623 sdhci_free_host(slot->host);
1626 static void sdhci_pci_runtime_pm_allow(struct device *dev)
1628 pm_suspend_ignore_children(dev, 1);
1629 pm_runtime_set_autosuspend_delay(dev, 50);
1630 pm_runtime_use_autosuspend(dev);
1631 pm_runtime_allow(dev);
1632 /* Stay active until mmc core scans for a card */
1633 pm_runtime_put_noidle(dev);
1636 static void sdhci_pci_runtime_pm_forbid(struct device *dev)
1638 pm_runtime_forbid(dev);
1639 pm_runtime_get_noresume(dev);
1642 static int sdhci_pci_probe(struct pci_dev *pdev,
1643 const struct pci_device_id *ent)
1645 struct sdhci_pci_chip *chip;
1646 struct sdhci_pci_slot *slot;
1648 u8 slots, first_bar;
1651 BUG_ON(pdev == NULL);
1652 BUG_ON(ent == NULL);
1654 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
1655 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
1657 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1661 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1662 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1666 BUG_ON(slots > MAX_SLOTS);
1668 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1672 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1674 if (first_bar > 5) {
1675 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1679 ret = pcim_enable_device(pdev);
1683 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
1688 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
1690 chip->quirks = chip->fixes->quirks;
1691 chip->quirks2 = chip->fixes->quirks2;
1692 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
1694 chip->num_slots = slots;
1695 chip->pm_retune = true;
1696 chip->rpm_retune = true;
1698 pci_set_drvdata(pdev, chip);
1700 if (chip->fixes && chip->fixes->probe) {
1701 ret = chip->fixes->probe(chip);
1706 slots = chip->num_slots; /* Quirk may have changed this */
1708 for (i = 0; i < slots; i++) {
1709 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
1711 for (i--; i >= 0; i--)
1712 sdhci_pci_remove_slot(chip->slots[i]);
1713 return PTR_ERR(slot);
1716 chip->slots[i] = slot;
1719 if (chip->allow_runtime_pm)
1720 sdhci_pci_runtime_pm_allow(&pdev->dev);
1725 static void sdhci_pci_remove(struct pci_dev *pdev)
1728 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1730 if (chip->allow_runtime_pm)
1731 sdhci_pci_runtime_pm_forbid(&pdev->dev);
1733 for (i = 0; i < chip->num_slots; i++)
1734 sdhci_pci_remove_slot(chip->slots[i]);
1737 static struct pci_driver sdhci_driver = {
1738 .name = "sdhci-pci",
1739 .id_table = pci_ids,
1740 .probe = sdhci_pci_probe,
1741 .remove = sdhci_pci_remove,
1743 .pm = &sdhci_pci_pm_ops
1747 module_pci_driver(sdhci_driver);
1749 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
1750 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
1751 MODULE_LICENSE("GPL");