1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 * Thanks to the following companies for their support:
8 * - JMicron (hardware and technical support)
11 #include <linux/bitfield.h>
12 #include <linux/string.h>
13 #include <linux/delay.h>
14 #include <linux/highmem.h>
15 #include <linux/module.h>
16 #include <linux/pci.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/slab.h>
19 #include <linux/device.h>
20 #include <linux/mmc/host.h>
21 #include <linux/mmc/mmc.h>
22 #include <linux/scatterlist.h>
24 #include <linux/iopoll.h>
25 #include <linux/gpio.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/pm_qos.h>
28 #include <linux/debugfs.h>
29 #include <linux/mmc/slot-gpio.h>
30 #include <linux/mmc/sdhci-pci-data.h>
31 #include <linux/acpi.h>
32 #include <linux/dmi.h>
35 #include <asm/iosf_mbi.h>
41 #include "sdhci-pci.h"
43 static void sdhci_pci_hw_reset(struct sdhci_host *host);
45 #ifdef CONFIG_PM_SLEEP
46 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip)
48 mmc_pm_flag_t pm_flags = 0;
49 bool cap_cd_wake = false;
52 for (i = 0; i < chip->num_slots; i++) {
53 struct sdhci_pci_slot *slot = chip->slots[i];
56 pm_flags |= slot->host->mmc->pm_flags;
57 if (slot->host->mmc->caps & MMC_CAP_CD_WAKE)
62 if ((pm_flags & MMC_PM_KEEP_POWER) && (pm_flags & MMC_PM_WAKE_SDIO_IRQ))
63 return device_wakeup_enable(&chip->pdev->dev);
64 else if (!cap_cd_wake)
65 return device_wakeup_disable(&chip->pdev->dev);
70 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip)
74 sdhci_pci_init_wakeup(chip);
76 for (i = 0; i < chip->num_slots; i++) {
77 struct sdhci_pci_slot *slot = chip->slots[i];
78 struct sdhci_host *host;
85 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3)
86 mmc_retune_needed(host->mmc);
88 ret = sdhci_suspend_host(host);
92 if (device_may_wakeup(&chip->pdev->dev))
93 mmc_gpio_set_cd_wake(host->mmc, true);
100 sdhci_resume_host(chip->slots[i]->host);
104 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip)
106 struct sdhci_pci_slot *slot;
109 for (i = 0; i < chip->num_slots; i++) {
110 slot = chip->slots[i];
114 ret = sdhci_resume_host(slot->host);
118 mmc_gpio_set_cd_wake(slot->host->mmc, false);
124 static int sdhci_cqhci_suspend(struct sdhci_pci_chip *chip)
128 ret = cqhci_suspend(chip->slots[0]->host->mmc);
132 return sdhci_pci_suspend_host(chip);
135 static int sdhci_cqhci_resume(struct sdhci_pci_chip *chip)
139 ret = sdhci_pci_resume_host(chip);
143 return cqhci_resume(chip->slots[0]->host->mmc);
148 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip)
150 struct sdhci_pci_slot *slot;
151 struct sdhci_host *host;
154 for (i = 0; i < chip->num_slots; i++) {
155 slot = chip->slots[i];
161 ret = sdhci_runtime_suspend_host(host);
163 goto err_pci_runtime_suspend;
165 if (chip->rpm_retune &&
166 host->tuning_mode != SDHCI_TUNING_MODE_3)
167 mmc_retune_needed(host->mmc);
172 err_pci_runtime_suspend:
174 sdhci_runtime_resume_host(chip->slots[i]->host, 0);
178 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip)
180 struct sdhci_pci_slot *slot;
183 for (i = 0; i < chip->num_slots; i++) {
184 slot = chip->slots[i];
188 ret = sdhci_runtime_resume_host(slot->host, 0);
196 static int sdhci_cqhci_runtime_suspend(struct sdhci_pci_chip *chip)
200 ret = cqhci_suspend(chip->slots[0]->host->mmc);
204 return sdhci_pci_runtime_suspend_host(chip);
207 static int sdhci_cqhci_runtime_resume(struct sdhci_pci_chip *chip)
211 ret = sdhci_pci_runtime_resume_host(chip);
215 return cqhci_resume(chip->slots[0]->host->mmc);
219 static u32 sdhci_cqhci_irq(struct sdhci_host *host, u32 intmask)
224 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
227 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
232 static void sdhci_pci_dumpregs(struct mmc_host *mmc)
234 sdhci_dumpregs(mmc_priv(mmc));
237 static void sdhci_cqhci_reset(struct sdhci_host *host, u8 mask)
239 if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL) &&
240 host->mmc->cqe_private)
241 cqhci_deactivate(host->mmc);
242 sdhci_reset(host, mask);
245 /*****************************************************************************\
247 * Hardware specific quirk handling *
249 \*****************************************************************************/
251 static int ricoh_probe(struct sdhci_pci_chip *chip)
253 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
254 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
255 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
259 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
262 FIELD_PREP(SDHCI_TIMEOUT_CLK_MASK, 0x21) |
263 FIELD_PREP(SDHCI_CLOCK_BASE_MASK, 0x21) |
264 SDHCI_TIMEOUT_CLK_UNIT |
271 #ifdef CONFIG_PM_SLEEP
272 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
274 /* Apply a delay to allow controller to settle */
275 /* Otherwise it becomes confused if card state changed
278 return sdhci_pci_resume_host(chip);
282 static const struct sdhci_pci_fixes sdhci_ricoh = {
283 .probe = ricoh_probe,
284 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
285 SDHCI_QUIRK_FORCE_DMA |
286 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
289 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
290 .probe_slot = ricoh_mmc_probe_slot,
291 #ifdef CONFIG_PM_SLEEP
292 .resume = ricoh_mmc_resume,
294 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
295 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
296 SDHCI_QUIRK_NO_CARD_NO_RESET |
297 SDHCI_QUIRK_MISSING_CAPS
300 static const struct sdhci_pci_fixes sdhci_ene_712 = {
301 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
302 SDHCI_QUIRK_BROKEN_DMA,
305 static const struct sdhci_pci_fixes sdhci_ene_714 = {
306 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
307 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
308 SDHCI_QUIRK_BROKEN_DMA,
311 static const struct sdhci_pci_fixes sdhci_cafe = {
312 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
313 SDHCI_QUIRK_NO_BUSY_IRQ |
314 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
315 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
318 static const struct sdhci_pci_fixes sdhci_intel_qrk = {
319 .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
322 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
324 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
329 * ADMA operation is disabled for Moorestown platform due to
332 static int mrst_hc_probe(struct sdhci_pci_chip *chip)
335 * slots number is fixed here for MRST as SDIO3/5 are never used and
336 * have hardware bugs.
342 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
344 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
350 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
352 struct sdhci_pci_slot *slot = dev_id;
353 struct sdhci_host *host = slot->host;
355 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
359 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
361 int err, irq, gpio = slot->cd_gpio;
363 slot->cd_gpio = -EINVAL;
364 slot->cd_irq = -EINVAL;
366 if (!gpio_is_valid(gpio))
369 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd");
373 err = gpio_direction_input(gpio);
377 irq = gpio_to_irq(gpio);
381 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
382 IRQF_TRIGGER_FALLING, "sd_cd", slot);
386 slot->cd_gpio = gpio;
392 devm_gpio_free(&slot->chip->pdev->dev, gpio);
394 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
397 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
399 if (slot->cd_irq >= 0)
400 free_irq(slot->cd_irq, slot);
405 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
409 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
415 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
417 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
418 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC;
422 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
424 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
428 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
429 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
430 .probe_slot = mrst_hc_probe_slot,
433 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
434 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
435 .probe = mrst_hc_probe,
438 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
439 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
440 .allow_runtime_pm = true,
441 .own_cd_for_runtime_pm = true,
444 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
445 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
446 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
447 .allow_runtime_pm = true,
448 .probe_slot = mfd_sdio_probe_slot,
451 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
452 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
453 .allow_runtime_pm = true,
454 .probe_slot = mfd_emmc_probe_slot,
457 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
458 .quirks = SDHCI_QUIRK_BROKEN_ADMA,
459 .probe_slot = pch_hc_probe_slot,
464 #define BYT_IOSF_SCCEP 0x63
465 #define BYT_IOSF_OCP_NETCTRL0 0x1078
466 #define BYT_IOSF_OCP_TIMEOUT_BASE GENMASK(10, 8)
468 static void byt_ocp_setting(struct pci_dev *pdev)
472 if (pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC &&
473 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SDIO &&
474 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SD &&
475 pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC2)
478 if (iosf_mbi_read(BYT_IOSF_SCCEP, MBI_CR_READ, BYT_IOSF_OCP_NETCTRL0,
480 dev_err(&pdev->dev, "%s read error\n", __func__);
484 if (!(val & BYT_IOSF_OCP_TIMEOUT_BASE))
487 val &= ~BYT_IOSF_OCP_TIMEOUT_BASE;
489 if (iosf_mbi_write(BYT_IOSF_SCCEP, MBI_CR_WRITE, BYT_IOSF_OCP_NETCTRL0,
491 dev_err(&pdev->dev, "%s write error\n", __func__);
495 dev_dbg(&pdev->dev, "%s completed\n", __func__);
500 static inline void byt_ocp_setting(struct pci_dev *pdev)
508 INTEL_DSM_V18_SWITCH = 3,
509 INTEL_DSM_V33_SWITCH = 4,
510 INTEL_DSM_DRV_STRENGTH = 9,
511 INTEL_DSM_D3_RETUNE = 10,
525 static const guid_t intel_dsm_guid =
526 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F,
527 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61);
529 static int __intel_dsm(struct intel_host *intel_host, struct device *dev,
530 unsigned int fn, u32 *result)
532 union acpi_object *obj;
536 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL);
540 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) {
545 len = min_t(size_t, obj->buffer.length, 4);
548 memcpy(result, obj->buffer.pointer, len);
555 static int intel_dsm(struct intel_host *intel_host, struct device *dev,
556 unsigned int fn, u32 *result)
558 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn)))
561 return __intel_dsm(intel_host, dev, fn, result);
564 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev,
565 struct mmc_host *mmc)
570 intel_host->d3_retune = true;
572 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns);
574 pr_debug("%s: DSM not supported, error %d\n",
575 mmc_hostname(mmc), err);
579 pr_debug("%s: DSM function mask %#x\n",
580 mmc_hostname(mmc), intel_host->dsm_fns);
582 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val);
583 intel_host->drv_strength = err ? 0 : val;
585 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val);
586 intel_host->d3_retune = err ? true : !!val;
589 static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
593 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
595 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
596 /* For eMMC, minimum is 1us but give it 9us for good measure */
599 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
600 /* For eMMC, minimum is 200us but give it 300us for good measure */
601 usleep_range(300, 1000);
604 static int intel_select_drive_strength(struct mmc_card *card,
605 unsigned int max_dtr, int host_drv,
606 int card_drv, int *drv_type)
608 struct sdhci_host *host = mmc_priv(card->host);
609 struct sdhci_pci_slot *slot = sdhci_priv(host);
610 struct intel_host *intel_host = sdhci_pci_priv(slot);
612 if (!(mmc_driver_type_mask(intel_host->drv_strength) & card_drv))
615 return intel_host->drv_strength;
618 static int bxt_get_cd(struct mmc_host *mmc)
620 int gpio_cd = mmc_gpio_get_cd(mmc);
621 struct sdhci_host *host = mmc_priv(mmc);
628 spin_lock_irqsave(&host->lock, flags);
630 if (host->flags & SDHCI_DEVICE_DEAD)
633 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
635 spin_unlock_irqrestore(&host->lock, flags);
640 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20
641 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100
643 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode,
649 sdhci_set_power(host, mode, vdd);
651 if (mode == MMC_POWER_OFF)
655 * Bus power might not enable after D3 -> D0 transition due to the
656 * present state not yet having propagated. Retry for up to 2ms.
658 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) {
659 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
660 if (reg & SDHCI_POWER_ON)
662 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY);
663 reg |= SDHCI_POWER_ON;
664 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
668 #define INTEL_HS400_ES_REG 0x78
669 #define INTEL_HS400_ES_BIT BIT(0)
671 static void intel_hs400_enhanced_strobe(struct mmc_host *mmc,
674 struct sdhci_host *host = mmc_priv(mmc);
677 val = sdhci_readl(host, INTEL_HS400_ES_REG);
678 if (ios->enhanced_strobe)
679 val |= INTEL_HS400_ES_BIT;
681 val &= ~INTEL_HS400_ES_BIT;
682 sdhci_writel(host, val, INTEL_HS400_ES_REG);
685 static int intel_start_signal_voltage_switch(struct mmc_host *mmc,
688 struct device *dev = mmc_dev(mmc);
689 struct sdhci_host *host = mmc_priv(mmc);
690 struct sdhci_pci_slot *slot = sdhci_priv(host);
691 struct intel_host *intel_host = sdhci_pci_priv(slot);
696 err = sdhci_start_signal_voltage_switch(mmc, ios);
700 switch (ios->signal_voltage) {
701 case MMC_SIGNAL_VOLTAGE_330:
702 fn = INTEL_DSM_V33_SWITCH;
704 case MMC_SIGNAL_VOLTAGE_180:
705 fn = INTEL_DSM_V18_SWITCH;
711 err = intel_dsm(intel_host, dev, fn, &result);
712 pr_debug("%s: %s DSM fn %u error %d result %u\n",
713 mmc_hostname(mmc), __func__, fn, err, result);
718 static const struct sdhci_ops sdhci_intel_byt_ops = {
719 .set_clock = sdhci_set_clock,
720 .set_power = sdhci_intel_set_power,
721 .enable_dma = sdhci_pci_enable_dma,
722 .set_bus_width = sdhci_set_bus_width,
723 .reset = sdhci_reset,
724 .set_uhs_signaling = sdhci_set_uhs_signaling,
725 .hw_reset = sdhci_pci_hw_reset,
728 static const struct sdhci_ops sdhci_intel_glk_ops = {
729 .set_clock = sdhci_set_clock,
730 .set_power = sdhci_intel_set_power,
731 .enable_dma = sdhci_pci_enable_dma,
732 .set_bus_width = sdhci_set_bus_width,
733 .reset = sdhci_cqhci_reset,
734 .set_uhs_signaling = sdhci_set_uhs_signaling,
735 .hw_reset = sdhci_pci_hw_reset,
736 .irq = sdhci_cqhci_irq,
739 static void byt_read_dsm(struct sdhci_pci_slot *slot)
741 struct intel_host *intel_host = sdhci_pci_priv(slot);
742 struct device *dev = &slot->chip->pdev->dev;
743 struct mmc_host *mmc = slot->host->mmc;
745 intel_dsm_init(intel_host, dev, mmc);
746 slot->chip->rpm_retune = intel_host->d3_retune;
749 static int intel_execute_tuning(struct mmc_host *mmc, u32 opcode)
751 int err = sdhci_execute_tuning(mmc, opcode);
752 struct sdhci_host *host = mmc_priv(mmc);
758 * Tuning can leave the IP in an active state (Buffer Read Enable bit
759 * set) which prevents the entry to low power states (i.e. S0i3). Data
760 * reset will clear it.
762 sdhci_reset(host, SDHCI_RESET_DATA);
767 #define INTEL_ACTIVELTR 0x804
768 #define INTEL_IDLELTR 0x808
770 #define INTEL_LTR_REQ BIT(15)
771 #define INTEL_LTR_SCALE_MASK GENMASK(11, 10)
772 #define INTEL_LTR_SCALE_1US (2 << 10)
773 #define INTEL_LTR_SCALE_32US (3 << 10)
774 #define INTEL_LTR_VALUE_MASK GENMASK(9, 0)
776 static void intel_cache_ltr(struct sdhci_pci_slot *slot)
778 struct intel_host *intel_host = sdhci_pci_priv(slot);
779 struct sdhci_host *host = slot->host;
781 intel_host->active_ltr = readl(host->ioaddr + INTEL_ACTIVELTR);
782 intel_host->idle_ltr = readl(host->ioaddr + INTEL_IDLELTR);
785 static void intel_ltr_set(struct device *dev, s32 val)
787 struct sdhci_pci_chip *chip = dev_get_drvdata(dev);
788 struct sdhci_pci_slot *slot = chip->slots[0];
789 struct intel_host *intel_host = sdhci_pci_priv(slot);
790 struct sdhci_host *host = slot->host;
793 pm_runtime_get_sync(dev);
796 * Program latency tolerance (LTR) accordingly what has been asked
797 * by the PM QoS layer or disable it in case we were passed
798 * negative value or PM_QOS_LATENCY_ANY.
800 ltr = readl(host->ioaddr + INTEL_ACTIVELTR);
802 if (val == PM_QOS_LATENCY_ANY || val < 0) {
803 ltr &= ~INTEL_LTR_REQ;
805 ltr |= INTEL_LTR_REQ;
806 ltr &= ~INTEL_LTR_SCALE_MASK;
807 ltr &= ~INTEL_LTR_VALUE_MASK;
809 if (val > INTEL_LTR_VALUE_MASK) {
811 if (val > INTEL_LTR_VALUE_MASK)
812 val = INTEL_LTR_VALUE_MASK;
813 ltr |= INTEL_LTR_SCALE_32US | val;
815 ltr |= INTEL_LTR_SCALE_1US | val;
819 if (ltr == intel_host->active_ltr)
822 writel(ltr, host->ioaddr + INTEL_ACTIVELTR);
823 writel(ltr, host->ioaddr + INTEL_IDLELTR);
825 /* Cache the values into lpss structure */
826 intel_cache_ltr(slot);
828 pm_runtime_put_autosuspend(dev);
831 static bool intel_use_ltr(struct sdhci_pci_chip *chip)
833 switch (chip->pdev->device) {
834 case PCI_DEVICE_ID_INTEL_BYT_EMMC:
835 case PCI_DEVICE_ID_INTEL_BYT_EMMC2:
836 case PCI_DEVICE_ID_INTEL_BYT_SDIO:
837 case PCI_DEVICE_ID_INTEL_BYT_SD:
838 case PCI_DEVICE_ID_INTEL_BSW_EMMC:
839 case PCI_DEVICE_ID_INTEL_BSW_SDIO:
840 case PCI_DEVICE_ID_INTEL_BSW_SD:
847 static void intel_ltr_expose(struct sdhci_pci_chip *chip)
849 struct device *dev = &chip->pdev->dev;
851 if (!intel_use_ltr(chip))
854 dev->power.set_latency_tolerance = intel_ltr_set;
855 dev_pm_qos_expose_latency_tolerance(dev);
858 static void intel_ltr_hide(struct sdhci_pci_chip *chip)
860 struct device *dev = &chip->pdev->dev;
862 if (!intel_use_ltr(chip))
865 dev_pm_qos_hide_latency_tolerance(dev);
866 dev->power.set_latency_tolerance = NULL;
869 static void byt_probe_slot(struct sdhci_pci_slot *slot)
871 struct mmc_host_ops *ops = &slot->host->mmc_host_ops;
872 struct device *dev = &slot->chip->pdev->dev;
873 struct mmc_host *mmc = slot->host->mmc;
877 byt_ocp_setting(slot->chip->pdev);
879 ops->execute_tuning = intel_execute_tuning;
880 ops->start_signal_voltage_switch = intel_start_signal_voltage_switch;
882 device_property_read_u32(dev, "max-frequency", &mmc->f_max);
885 slot->chip->slots[mmc->slotno] = slot;
886 intel_ltr_expose(slot->chip);
890 static void byt_add_debugfs(struct sdhci_pci_slot *slot)
892 struct intel_host *intel_host = sdhci_pci_priv(slot);
893 struct mmc_host *mmc = slot->host->mmc;
894 struct dentry *dir = mmc->debugfs_root;
896 if (!intel_use_ltr(slot->chip))
899 debugfs_create_x32("active_ltr", 0444, dir, &intel_host->active_ltr);
900 debugfs_create_x32("idle_ltr", 0444, dir, &intel_host->idle_ltr);
902 intel_cache_ltr(slot);
905 static int byt_add_host(struct sdhci_pci_slot *slot)
907 int ret = sdhci_add_host(slot->host);
910 byt_add_debugfs(slot);
914 static void byt_remove_slot(struct sdhci_pci_slot *slot, int dead)
916 struct mmc_host *mmc = slot->host->mmc;
919 intel_ltr_hide(slot->chip);
922 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
924 byt_probe_slot(slot);
925 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
926 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
927 MMC_CAP_CMD_DURING_TFR |
928 MMC_CAP_WAIT_WHILE_BUSY;
929 slot->hw_reset = sdhci_pci_int_hw_reset;
930 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
931 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
932 slot->host->mmc_host_ops.select_drive_strength =
933 intel_select_drive_strength;
937 static bool glk_broken_cqhci(struct sdhci_pci_slot *slot)
939 return slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC &&
940 (dmi_match(DMI_BIOS_VENDOR, "LENOVO") ||
941 dmi_match(DMI_SYS_VENDOR, "IRBIS"));
944 static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot)
946 int ret = byt_emmc_probe_slot(slot);
948 if (!glk_broken_cqhci(slot))
949 slot->host->mmc->caps2 |= MMC_CAP2_CQE;
951 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) {
952 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES,
953 slot->host->mmc_host_ops.hs400_enhanced_strobe =
954 intel_hs400_enhanced_strobe;
955 slot->host->mmc->caps2 |= MMC_CAP2_CQE_DCMD;
961 static const struct cqhci_host_ops glk_cqhci_ops = {
962 .enable = sdhci_cqe_enable,
963 .disable = sdhci_cqe_disable,
964 .dumpregs = sdhci_pci_dumpregs,
967 static int glk_emmc_add_host(struct sdhci_pci_slot *slot)
969 struct device *dev = &slot->chip->pdev->dev;
970 struct sdhci_host *host = slot->host;
971 struct cqhci_host *cq_host;
975 ret = sdhci_setup_host(host);
979 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL);
985 cq_host->mmio = host->ioaddr + 0x200;
986 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ;
987 cq_host->ops = &glk_cqhci_ops;
989 dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
991 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
993 ret = cqhci_init(cq_host, host->mmc, dma64);
997 ret = __sdhci_add_host(host);
1001 byt_add_debugfs(slot);
1006 sdhci_cleanup_host(host);
1011 #define GLK_RX_CTRL1 0x834
1012 #define GLK_TUN_VAL 0x840
1013 #define GLK_PATH_PLL GENMASK(13, 8)
1014 #define GLK_DLY GENMASK(6, 0)
1015 /* Workaround firmware failing to restore the tuning value */
1016 static void glk_rpm_retune_wa(struct sdhci_pci_chip *chip, bool susp)
1018 struct sdhci_pci_slot *slot = chip->slots[0];
1019 struct intel_host *intel_host = sdhci_pci_priv(slot);
1020 struct sdhci_host *host = slot->host;
1025 if (intel_host->rpm_retune_ok || !mmc_can_retune(host->mmc))
1028 glk_rx_ctrl1 = sdhci_readl(host, GLK_RX_CTRL1);
1029 glk_tun_val = sdhci_readl(host, GLK_TUN_VAL);
1032 intel_host->glk_rx_ctrl1 = glk_rx_ctrl1;
1033 intel_host->glk_tun_val = glk_tun_val;
1037 if (!intel_host->glk_tun_val)
1040 if (glk_rx_ctrl1 != intel_host->glk_rx_ctrl1) {
1041 intel_host->rpm_retune_ok = true;
1045 dly = FIELD_PREP(GLK_DLY, FIELD_GET(GLK_PATH_PLL, glk_rx_ctrl1) +
1046 (intel_host->glk_tun_val << 1));
1047 if (dly == FIELD_GET(GLK_DLY, glk_rx_ctrl1))
1050 glk_rx_ctrl1 = (glk_rx_ctrl1 & ~GLK_DLY) | dly;
1051 sdhci_writel(host, glk_rx_ctrl1, GLK_RX_CTRL1);
1053 intel_host->rpm_retune_ok = true;
1054 chip->rpm_retune = true;
1055 mmc_retune_needed(host->mmc);
1056 pr_info("%s: Requiring re-tune after rpm resume", mmc_hostname(host->mmc));
1059 static void glk_rpm_retune_chk(struct sdhci_pci_chip *chip, bool susp)
1061 if (chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC &&
1063 glk_rpm_retune_wa(chip, susp);
1066 static int glk_runtime_suspend(struct sdhci_pci_chip *chip)
1068 glk_rpm_retune_chk(chip, true);
1070 return sdhci_cqhci_runtime_suspend(chip);
1073 static int glk_runtime_resume(struct sdhci_pci_chip *chip)
1075 glk_rpm_retune_chk(chip, false);
1077 return sdhci_cqhci_runtime_resume(chip);
1082 static int ni_set_max_freq(struct sdhci_pci_slot *slot)
1085 unsigned long long max_freq;
1087 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev),
1088 "MXFQ", NULL, &max_freq);
1089 if (ACPI_FAILURE(status)) {
1090 dev_err(&slot->chip->pdev->dev,
1091 "MXFQ not found in acpi table\n");
1095 slot->host->mmc->f_max = max_freq * 1000000;
1100 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot)
1106 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
1110 byt_probe_slot(slot);
1112 err = ni_set_max_freq(slot);
1116 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
1117 MMC_CAP_WAIT_WHILE_BUSY;
1121 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
1123 byt_probe_slot(slot);
1124 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
1125 MMC_CAP_WAIT_WHILE_BUSY;
1129 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
1131 byt_probe_slot(slot);
1132 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY |
1133 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE;
1135 slot->cd_override_level = true;
1136 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD ||
1137 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD ||
1138 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD ||
1139 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD)
1140 slot->host->mmc_host_ops.get_cd = bxt_get_cd;
1142 if (slot->chip->pdev->subsystem_vendor == PCI_VENDOR_ID_NI &&
1143 slot->chip->pdev->subsystem_device == PCI_SUBDEVICE_ID_NI_78E3)
1144 slot->host->mmc->caps2 |= MMC_CAP2_AVOID_3_3V;
1149 #ifdef CONFIG_PM_SLEEP
1151 static int byt_resume(struct sdhci_pci_chip *chip)
1153 byt_ocp_setting(chip->pdev);
1155 return sdhci_pci_resume_host(chip);
1162 static int byt_runtime_resume(struct sdhci_pci_chip *chip)
1164 byt_ocp_setting(chip->pdev);
1166 return sdhci_pci_runtime_resume_host(chip);
1171 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
1172 #ifdef CONFIG_PM_SLEEP
1173 .resume = byt_resume,
1176 .runtime_resume = byt_runtime_resume,
1178 .allow_runtime_pm = true,
1179 .probe_slot = byt_emmc_probe_slot,
1180 .add_host = byt_add_host,
1181 .remove_slot = byt_remove_slot,
1182 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1184 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1185 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
1186 SDHCI_QUIRK2_STOP_WITH_TC,
1187 .ops = &sdhci_intel_byt_ops,
1188 .priv_size = sizeof(struct intel_host),
1191 static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = {
1192 .allow_runtime_pm = true,
1193 .probe_slot = glk_emmc_probe_slot,
1194 .add_host = glk_emmc_add_host,
1195 .remove_slot = byt_remove_slot,
1196 #ifdef CONFIG_PM_SLEEP
1197 .suspend = sdhci_cqhci_suspend,
1198 .resume = sdhci_cqhci_resume,
1201 .runtime_suspend = glk_runtime_suspend,
1202 .runtime_resume = glk_runtime_resume,
1204 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1206 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1207 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
1208 SDHCI_QUIRK2_STOP_WITH_TC,
1209 .ops = &sdhci_intel_glk_ops,
1210 .priv_size = sizeof(struct intel_host),
1213 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = {
1214 #ifdef CONFIG_PM_SLEEP
1215 .resume = byt_resume,
1218 .runtime_resume = byt_runtime_resume,
1220 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1222 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
1223 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1224 .allow_runtime_pm = true,
1225 .probe_slot = ni_byt_sdio_probe_slot,
1226 .add_host = byt_add_host,
1227 .remove_slot = byt_remove_slot,
1228 .ops = &sdhci_intel_byt_ops,
1229 .priv_size = sizeof(struct intel_host),
1232 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
1233 #ifdef CONFIG_PM_SLEEP
1234 .resume = byt_resume,
1237 .runtime_resume = byt_runtime_resume,
1239 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1241 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
1242 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1243 .allow_runtime_pm = true,
1244 .probe_slot = byt_sdio_probe_slot,
1245 .add_host = byt_add_host,
1246 .remove_slot = byt_remove_slot,
1247 .ops = &sdhci_intel_byt_ops,
1248 .priv_size = sizeof(struct intel_host),
1251 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
1252 #ifdef CONFIG_PM_SLEEP
1253 .resume = byt_resume,
1256 .runtime_resume = byt_runtime_resume,
1258 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1260 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
1261 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1262 SDHCI_QUIRK2_STOP_WITH_TC,
1263 .allow_runtime_pm = true,
1264 .own_cd_for_runtime_pm = true,
1265 .probe_slot = byt_sd_probe_slot,
1266 .add_host = byt_add_host,
1267 .remove_slot = byt_remove_slot,
1268 .ops = &sdhci_intel_byt_ops,
1269 .priv_size = sizeof(struct intel_host),
1272 /* Define Host controllers for Intel Merrifield platform */
1273 #define INTEL_MRFLD_EMMC_0 0
1274 #define INTEL_MRFLD_EMMC_1 1
1275 #define INTEL_MRFLD_SD 2
1276 #define INTEL_MRFLD_SDIO 3
1279 static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot)
1281 struct acpi_device *device, *child;
1283 device = ACPI_COMPANION(&slot->chip->pdev->dev);
1287 acpi_device_fix_up_power(device);
1288 list_for_each_entry(child, &device->children, node)
1289 if (child->status.present && child->status.enabled)
1290 acpi_device_fix_up_power(child);
1293 static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {}
1296 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot)
1298 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn);
1301 case INTEL_MRFLD_EMMC_0:
1302 case INTEL_MRFLD_EMMC_1:
1303 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
1304 MMC_CAP_8_BIT_DATA |
1307 case INTEL_MRFLD_SD:
1308 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1310 case INTEL_MRFLD_SDIO:
1311 /* Advertise 2.0v for compatibility with the SDIO card's OCR */
1312 slot->host->ocr_mask = MMC_VDD_20_21 | MMC_VDD_165_195;
1313 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
1314 MMC_CAP_POWER_OFF_CARD;
1320 intel_mrfld_mmc_fix_up_power_slot(slot);
1324 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = {
1325 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1326 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
1327 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1328 .allow_runtime_pm = true,
1329 .probe_slot = intel_mrfld_mmc_probe_slot,
1332 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
1337 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
1342 * Turn PMOS on [bit 0], set over current detection to 2.4 V
1343 * [bit 1:2] and enable over current debouncing [bit 6].
1350 return pci_write_config_byte(chip->pdev, 0xAE, scratch);
1353 static int jmicron_probe(struct sdhci_pci_chip *chip)
1358 if (chip->pdev->revision == 0) {
1359 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
1360 SDHCI_QUIRK_32BIT_DMA_SIZE |
1361 SDHCI_QUIRK_32BIT_ADMA_SIZE |
1362 SDHCI_QUIRK_RESET_AFTER_REQUEST |
1363 SDHCI_QUIRK_BROKEN_SMALL_PIO;
1367 * JMicron chips can have two interfaces to the same hardware
1368 * in order to work around limitations in Microsoft's driver.
1369 * We need to make sure we only bind to one of them.
1371 * This code assumes two things:
1373 * 1. The PCI code adds subfunctions in order.
1375 * 2. The MMC interface has a lower subfunction number
1376 * than the SD interface.
1378 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
1379 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
1380 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
1381 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
1384 struct pci_dev *sd_dev;
1387 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
1388 mmcdev, sd_dev)) != NULL) {
1389 if ((PCI_SLOT(chip->pdev->devfn) ==
1390 PCI_SLOT(sd_dev->devfn)) &&
1391 (chip->pdev->bus == sd_dev->bus))
1396 pci_dev_put(sd_dev);
1397 dev_info(&chip->pdev->dev, "Refusing to bind to "
1398 "secondary interface.\n");
1404 * JMicron chips need a bit of a nudge to enable the power
1407 ret = jmicron_pmos(chip, 1);
1409 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
1413 /* quirk for unsable RO-detection on JM388 chips */
1414 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
1415 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1416 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
1421 static void jmicron_enable_mmc(struct sdhci_host *host, int on)
1425 scratch = readb(host->ioaddr + 0xC0);
1432 writeb(scratch, host->ioaddr + 0xC0);
1435 static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
1437 if (slot->chip->pdev->revision == 0) {
1440 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
1441 version = (version & SDHCI_VENDOR_VER_MASK) >>
1442 SDHCI_VENDOR_VER_SHIFT;
1445 * Older versions of the chip have lots of nasty glitches
1446 * in the ADMA engine. It's best just to avoid it
1450 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1453 /* JM388 MMC doesn't support 1.8V while SD supports it */
1454 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1455 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
1456 MMC_VDD_29_30 | MMC_VDD_30_31 |
1457 MMC_VDD_165_195; /* allow 1.8V */
1458 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
1459 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
1463 * The secondary interface requires a bit set to get the
1466 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1467 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1468 jmicron_enable_mmc(slot->host, 1);
1470 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
1475 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
1480 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1481 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1482 jmicron_enable_mmc(slot->host, 0);
1485 #ifdef CONFIG_PM_SLEEP
1486 static int jmicron_suspend(struct sdhci_pci_chip *chip)
1490 ret = sdhci_pci_suspend_host(chip);
1494 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1495 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1496 for (i = 0; i < chip->num_slots; i++)
1497 jmicron_enable_mmc(chip->slots[i]->host, 0);
1503 static int jmicron_resume(struct sdhci_pci_chip *chip)
1507 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1508 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1509 for (i = 0; i < chip->num_slots; i++)
1510 jmicron_enable_mmc(chip->slots[i]->host, 1);
1513 ret = jmicron_pmos(chip, 1);
1515 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
1519 return sdhci_pci_resume_host(chip);
1523 static const struct sdhci_pci_fixes sdhci_jmicron = {
1524 .probe = jmicron_probe,
1526 .probe_slot = jmicron_probe_slot,
1527 .remove_slot = jmicron_remove_slot,
1529 #ifdef CONFIG_PM_SLEEP
1530 .suspend = jmicron_suspend,
1531 .resume = jmicron_resume,
1535 /* SysKonnect CardBus2SDIO extra registers */
1536 #define SYSKT_CTRL 0x200
1537 #define SYSKT_RDFIFO_STAT 0x204
1538 #define SYSKT_WRFIFO_STAT 0x208
1539 #define SYSKT_POWER_DATA 0x20c
1540 #define SYSKT_POWER_330 0xef
1541 #define SYSKT_POWER_300 0xf8
1542 #define SYSKT_POWER_184 0xcc
1543 #define SYSKT_POWER_CMD 0x20d
1544 #define SYSKT_POWER_START (1 << 7)
1545 #define SYSKT_POWER_STATUS 0x20e
1546 #define SYSKT_POWER_STATUS_OK (1 << 0)
1547 #define SYSKT_BOARD_REV 0x210
1548 #define SYSKT_CHIP_REV 0x211
1549 #define SYSKT_CONF_DATA 0x212
1550 #define SYSKT_CONF_DATA_1V8 (1 << 2)
1551 #define SYSKT_CONF_DATA_2V5 (1 << 1)
1552 #define SYSKT_CONF_DATA_3V3 (1 << 0)
1554 static int syskt_probe(struct sdhci_pci_chip *chip)
1556 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1557 chip->pdev->class &= ~0x0000FF;
1558 chip->pdev->class |= PCI_SDHCI_IFDMA;
1563 static int syskt_probe_slot(struct sdhci_pci_slot *slot)
1567 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
1568 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
1569 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
1570 "board rev %d.%d, chip rev %d.%d\n",
1571 board_rev >> 4, board_rev & 0xf,
1572 chip_rev >> 4, chip_rev & 0xf);
1573 if (chip_rev >= 0x20)
1574 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
1576 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
1577 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
1579 tm = 10; /* Wait max 1 ms */
1581 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
1582 if (ps & SYSKT_POWER_STATUS_OK)
1587 dev_err(&slot->chip->pdev->dev,
1588 "power regulator never stabilized");
1589 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
1596 static const struct sdhci_pci_fixes sdhci_syskt = {
1597 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
1598 .probe = syskt_probe,
1599 .probe_slot = syskt_probe_slot,
1602 static int via_probe(struct sdhci_pci_chip *chip)
1604 if (chip->pdev->revision == 0x10)
1605 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
1610 static const struct sdhci_pci_fixes sdhci_via = {
1614 static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
1616 slot->host->mmc->caps2 |= MMC_CAP2_HS200;
1620 static const struct sdhci_pci_fixes sdhci_rtsx = {
1621 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1622 SDHCI_QUIRK2_BROKEN_64_BIT_DMA |
1623 SDHCI_QUIRK2_BROKEN_DDR50,
1624 .probe_slot = rtsx_probe_slot,
1627 /*AMD chipset generation*/
1628 enum amd_chipset_gen {
1629 AMD_CHIPSET_BEFORE_ML,
1632 AMD_CHIPSET_UNKNOWN,
1636 #define AMD_SD_AUTO_PATTERN 0xB8
1637 #define AMD_MSLEEP_DURATION 4
1638 #define AMD_SD_MISC_CONTROL 0xD0
1639 #define AMD_MAX_TUNE_VALUE 0x0B
1640 #define AMD_AUTO_TUNE_SEL 0x10800
1641 #define AMD_FIFO_PTR 0x30
1642 #define AMD_BIT_MASK 0x1F
1644 static void amd_tuning_reset(struct sdhci_host *host)
1648 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1649 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING;
1650 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1652 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1653 val &= ~SDHCI_CTRL_EXEC_TUNING;
1654 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1657 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase)
1661 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val);
1662 val &= ~AMD_BIT_MASK;
1663 val |= (AMD_AUTO_TUNE_SEL | (phase << 1));
1664 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val);
1667 static void amd_enable_manual_tuning(struct pci_dev *pdev)
1671 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val);
1672 val |= AMD_FIFO_PTR;
1673 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val);
1676 static int amd_execute_tuning_hs200(struct sdhci_host *host, u32 opcode)
1678 struct sdhci_pci_slot *slot = sdhci_priv(host);
1679 struct pci_dev *pdev = slot->chip->pdev;
1681 u8 valid_win_max = 0;
1682 u8 valid_win_end = 0;
1683 u8 ctrl, tune_around;
1685 amd_tuning_reset(host);
1687 for (tune_around = 0; tune_around < 12; tune_around++) {
1688 amd_config_tuning_phase(pdev, tune_around);
1690 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
1692 msleep(AMD_MSLEEP_DURATION);
1693 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA;
1694 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET);
1695 } else if (++valid_win > valid_win_max) {
1696 valid_win_max = valid_win;
1697 valid_win_end = tune_around;
1701 if (!valid_win_max) {
1702 dev_err(&pdev->dev, "no tuning point found\n");
1706 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2);
1708 amd_enable_manual_tuning(pdev);
1710 host->mmc->retune_period = 0;
1715 static int amd_execute_tuning(struct mmc_host *mmc, u32 opcode)
1717 struct sdhci_host *host = mmc_priv(mmc);
1719 /* AMD requires custom HS200 tuning */
1720 if (host->timing == MMC_TIMING_MMC_HS200)
1721 return amd_execute_tuning_hs200(host, opcode);
1723 /* Otherwise perform standard SDHCI tuning */
1724 return sdhci_execute_tuning(mmc, opcode);
1727 static int amd_probe_slot(struct sdhci_pci_slot *slot)
1729 struct mmc_host_ops *ops = &slot->host->mmc_host_ops;
1731 ops->execute_tuning = amd_execute_tuning;
1736 static int amd_probe(struct sdhci_pci_chip *chip)
1738 struct pci_dev *smbus_dev;
1739 enum amd_chipset_gen gen;
1741 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1742 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
1744 gen = AMD_CHIPSET_BEFORE_ML;
1746 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1747 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL);
1749 if (smbus_dev->revision < 0x51)
1750 gen = AMD_CHIPSET_CZ;
1752 gen = AMD_CHIPSET_NL;
1754 gen = AMD_CHIPSET_UNKNOWN;
1758 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ)
1759 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
1764 static u32 sdhci_read_present_state(struct sdhci_host *host)
1766 return sdhci_readl(host, SDHCI_PRESENT_STATE);
1769 static void amd_sdhci_reset(struct sdhci_host *host, u8 mask)
1771 struct sdhci_pci_slot *slot = sdhci_priv(host);
1772 struct pci_dev *pdev = slot->chip->pdev;
1776 * SDHC 0x7906 requires a hard reset to clear all internal state.
1777 * Otherwise it can get into a bad state where the DATA lines are always
1780 if (pdev->device == 0x7906 && (mask & SDHCI_RESET_ALL)) {
1781 pci_clear_master(pdev);
1783 pci_save_state(pdev);
1785 pci_set_power_state(pdev, PCI_D3cold);
1786 pr_debug("%s: power_state=%u\n", mmc_hostname(host->mmc),
1787 pdev->current_state);
1788 pci_set_power_state(pdev, PCI_D0);
1790 pci_restore_state(pdev);
1793 * SDHCI_RESET_ALL says the card detect logic should not be
1794 * reset, but since we need to reset the entire controller
1795 * we should wait until the card detect logic has stabilized.
1797 * This normally takes about 40ms.
1800 sdhci_read_present_state,
1803 present_state & SDHCI_CD_STABLE,
1809 return sdhci_reset(host, mask);
1812 static const struct sdhci_ops amd_sdhci_pci_ops = {
1813 .set_clock = sdhci_set_clock,
1814 .enable_dma = sdhci_pci_enable_dma,
1815 .set_bus_width = sdhci_set_bus_width,
1816 .reset = amd_sdhci_reset,
1817 .set_uhs_signaling = sdhci_set_uhs_signaling,
1820 static const struct sdhci_pci_fixes sdhci_amd = {
1822 .ops = &amd_sdhci_pci_ops,
1823 .probe_slot = amd_probe_slot,
1826 static const struct pci_device_id pci_ids[] = {
1827 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh),
1828 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc),
1829 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc),
1830 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc),
1831 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712),
1832 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712),
1833 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714),
1834 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714),
1835 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe),
1836 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron),
1837 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron),
1838 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron),
1839 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron),
1840 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt),
1841 SDHCI_PCI_DEVICE(VIA, 95D0, via),
1842 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx),
1843 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk),
1844 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0),
1845 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2),
1846 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2),
1847 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd),
1848 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio),
1849 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio),
1850 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc),
1851 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc),
1852 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio),
1853 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio),
1854 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc),
1855 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio),
1856 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio),
1857 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd),
1858 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc),
1859 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc),
1860 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio),
1861 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd),
1862 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd),
1863 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio),
1864 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio),
1865 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc),
1866 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc),
1867 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc),
1868 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc),
1869 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio),
1870 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd),
1871 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc),
1872 SDHCI_PCI_DEVICE(INTEL, CDF_EMMC, intel_glk_emmc),
1873 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc),
1874 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio),
1875 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd),
1876 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc),
1877 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio),
1878 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd),
1879 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc),
1880 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio),
1881 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd),
1882 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc),
1883 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio),
1884 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd),
1885 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc),
1886 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd),
1887 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd),
1888 SDHCI_PCI_DEVICE(INTEL, ICP_EMMC, intel_glk_emmc),
1889 SDHCI_PCI_DEVICE(INTEL, ICP_SD, intel_byt_sd),
1890 SDHCI_PCI_DEVICE(INTEL, EHL_EMMC, intel_glk_emmc),
1891 SDHCI_PCI_DEVICE(INTEL, EHL_SD, intel_byt_sd),
1892 SDHCI_PCI_DEVICE(INTEL, CML_EMMC, intel_glk_emmc),
1893 SDHCI_PCI_DEVICE(INTEL, CML_SD, intel_byt_sd),
1894 SDHCI_PCI_DEVICE(INTEL, CMLH_SD, intel_byt_sd),
1895 SDHCI_PCI_DEVICE(INTEL, JSL_EMMC, intel_glk_emmc),
1896 SDHCI_PCI_DEVICE(INTEL, JSL_SD, intel_byt_sd),
1897 SDHCI_PCI_DEVICE(O2, 8120, o2),
1898 SDHCI_PCI_DEVICE(O2, 8220, o2),
1899 SDHCI_PCI_DEVICE(O2, 8221, o2),
1900 SDHCI_PCI_DEVICE(O2, 8320, o2),
1901 SDHCI_PCI_DEVICE(O2, 8321, o2),
1902 SDHCI_PCI_DEVICE(O2, FUJIN2, o2),
1903 SDHCI_PCI_DEVICE(O2, SDS0, o2),
1904 SDHCI_PCI_DEVICE(O2, SDS1, o2),
1905 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2),
1906 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2),
1907 SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan),
1908 SDHCI_PCI_DEVICE(SYNOPSYS, DWC_MSHC, snps),
1909 SDHCI_PCI_DEVICE(GLI, 9750, gl9750),
1910 SDHCI_PCI_DEVICE(GLI, 9755, gl9755),
1911 SDHCI_PCI_DEVICE(GLI, 9763E, gl9763e),
1912 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd),
1913 /* Generic SD host controller */
1914 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)},
1915 { /* end: all zeroes */ },
1918 MODULE_DEVICE_TABLE(pci, pci_ids);
1920 /*****************************************************************************\
1922 * SDHCI core callbacks *
1924 \*****************************************************************************/
1926 int sdhci_pci_enable_dma(struct sdhci_host *host)
1928 struct sdhci_pci_slot *slot;
1929 struct pci_dev *pdev;
1931 slot = sdhci_priv(host);
1932 pdev = slot->chip->pdev;
1934 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1935 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1936 (host->flags & SDHCI_USE_SDMA)) {
1937 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1938 "doesn't fully claim to support it.\n");
1941 pci_set_master(pdev);
1946 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
1948 struct sdhci_pci_slot *slot = sdhci_priv(host);
1949 int rst_n_gpio = slot->rst_n_gpio;
1951 if (!gpio_is_valid(rst_n_gpio))
1953 gpio_set_value_cansleep(rst_n_gpio, 0);
1954 /* For eMMC, minimum is 1us but give it 10us for good measure */
1956 gpio_set_value_cansleep(rst_n_gpio, 1);
1957 /* For eMMC, minimum is 200us but give it 300us for good measure */
1958 usleep_range(300, 1000);
1961 static void sdhci_pci_hw_reset(struct sdhci_host *host)
1963 struct sdhci_pci_slot *slot = sdhci_priv(host);
1966 slot->hw_reset(host);
1969 static const struct sdhci_ops sdhci_pci_ops = {
1970 .set_clock = sdhci_set_clock,
1971 .enable_dma = sdhci_pci_enable_dma,
1972 .set_bus_width = sdhci_set_bus_width,
1973 .reset = sdhci_reset,
1974 .set_uhs_signaling = sdhci_set_uhs_signaling,
1975 .hw_reset = sdhci_pci_hw_reset,
1978 /*****************************************************************************\
1982 \*****************************************************************************/
1984 #ifdef CONFIG_PM_SLEEP
1985 static int sdhci_pci_suspend(struct device *dev)
1987 struct sdhci_pci_chip *chip = dev_get_drvdata(dev);
1992 if (chip->fixes && chip->fixes->suspend)
1993 return chip->fixes->suspend(chip);
1995 return sdhci_pci_suspend_host(chip);
1998 static int sdhci_pci_resume(struct device *dev)
2000 struct sdhci_pci_chip *chip = dev_get_drvdata(dev);
2005 if (chip->fixes && chip->fixes->resume)
2006 return chip->fixes->resume(chip);
2008 return sdhci_pci_resume_host(chip);
2013 static int sdhci_pci_runtime_suspend(struct device *dev)
2015 struct sdhci_pci_chip *chip = dev_get_drvdata(dev);
2020 if (chip->fixes && chip->fixes->runtime_suspend)
2021 return chip->fixes->runtime_suspend(chip);
2023 return sdhci_pci_runtime_suspend_host(chip);
2026 static int sdhci_pci_runtime_resume(struct device *dev)
2028 struct sdhci_pci_chip *chip = dev_get_drvdata(dev);
2033 if (chip->fixes && chip->fixes->runtime_resume)
2034 return chip->fixes->runtime_resume(chip);
2036 return sdhci_pci_runtime_resume_host(chip);
2040 static const struct dev_pm_ops sdhci_pci_pm_ops = {
2041 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume)
2042 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
2043 sdhci_pci_runtime_resume, NULL)
2046 /*****************************************************************************\
2048 * Device probing/removal *
2050 \*****************************************************************************/
2052 static struct sdhci_pci_slot *sdhci_pci_probe_slot(
2053 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
2056 struct sdhci_pci_slot *slot;
2057 struct sdhci_host *host;
2058 int ret, bar = first_bar + slotno;
2059 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0;
2061 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
2062 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
2063 return ERR_PTR(-ENODEV);
2066 if (pci_resource_len(pdev, bar) < 0x100) {
2067 dev_err(&pdev->dev, "Invalid iomem size. You may "
2068 "experience problems.\n");
2071 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
2072 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
2073 return ERR_PTR(-ENODEV);
2076 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
2077 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
2078 return ERR_PTR(-ENODEV);
2081 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size);
2083 dev_err(&pdev->dev, "cannot allocate host\n");
2084 return ERR_CAST(host);
2087 slot = sdhci_priv(host);
2091 slot->rst_n_gpio = -EINVAL;
2092 slot->cd_gpio = -EINVAL;
2095 /* Retrieve platform data if there is any */
2096 if (*sdhci_pci_get_data)
2097 slot->data = sdhci_pci_get_data(pdev, slotno);
2100 if (slot->data->setup) {
2101 ret = slot->data->setup(slot->data);
2103 dev_err(&pdev->dev, "platform setup failed\n");
2107 slot->rst_n_gpio = slot->data->rst_n_gpio;
2108 slot->cd_gpio = slot->data->cd_gpio;
2111 host->hw_name = "PCI";
2112 host->ops = chip->fixes && chip->fixes->ops ?
2115 host->quirks = chip->quirks;
2116 host->quirks2 = chip->quirks2;
2118 host->irq = pdev->irq;
2120 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc));
2122 dev_err(&pdev->dev, "cannot request region\n");
2126 host->ioaddr = pcim_iomap_table(pdev)[bar];
2128 if (chip->fixes && chip->fixes->probe_slot) {
2129 ret = chip->fixes->probe_slot(slot);
2134 if (gpio_is_valid(slot->rst_n_gpio)) {
2135 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) {
2136 gpio_direction_output(slot->rst_n_gpio, 1);
2137 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
2138 slot->hw_reset = sdhci_pci_gpio_hw_reset;
2140 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
2141 slot->rst_n_gpio = -EINVAL;
2145 host->mmc->pm_caps = MMC_PM_KEEP_POWER;
2146 host->mmc->slotno = slotno;
2147 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
2149 if (device_can_wakeup(&pdev->dev))
2150 host->mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
2152 if (host->mmc->caps & MMC_CAP_CD_WAKE)
2153 device_init_wakeup(&pdev->dev, true);
2155 if (slot->cd_idx >= 0) {
2156 ret = mmc_gpiod_request_cd(host->mmc, "cd", slot->cd_idx,
2157 slot->cd_override_level, 0);
2158 if (ret && ret != -EPROBE_DEFER)
2159 ret = mmc_gpiod_request_cd(host->mmc, NULL,
2161 slot->cd_override_level,
2163 if (ret == -EPROBE_DEFER)
2167 dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
2172 if (chip->fixes && chip->fixes->add_host)
2173 ret = chip->fixes->add_host(slot);
2175 ret = sdhci_add_host(host);
2179 sdhci_pci_add_own_cd(slot);
2182 * Check if the chip needs a separate GPIO for card detect to wake up
2183 * from runtime suspend. If it is not there, don't allow runtime PM.
2184 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure.
2186 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
2187 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0)
2188 chip->allow_runtime_pm = false;
2193 if (chip->fixes && chip->fixes->remove_slot)
2194 chip->fixes->remove_slot(slot, 0);
2197 if (slot->data && slot->data->cleanup)
2198 slot->data->cleanup(slot->data);
2201 sdhci_free_host(host);
2203 return ERR_PTR(ret);
2206 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
2211 sdhci_pci_remove_own_cd(slot);
2214 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
2215 if (scratch == (u32)-1)
2218 sdhci_remove_host(slot->host, dead);
2220 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
2221 slot->chip->fixes->remove_slot(slot, dead);
2223 if (slot->data && slot->data->cleanup)
2224 slot->data->cleanup(slot->data);
2226 sdhci_free_host(slot->host);
2229 static void sdhci_pci_runtime_pm_allow(struct device *dev)
2231 pm_suspend_ignore_children(dev, 1);
2232 pm_runtime_set_autosuspend_delay(dev, 50);
2233 pm_runtime_use_autosuspend(dev);
2234 pm_runtime_allow(dev);
2235 /* Stay active until mmc core scans for a card */
2236 pm_runtime_put_noidle(dev);
2239 static void sdhci_pci_runtime_pm_forbid(struct device *dev)
2241 pm_runtime_forbid(dev);
2242 pm_runtime_get_noresume(dev);
2245 static int sdhci_pci_probe(struct pci_dev *pdev,
2246 const struct pci_device_id *ent)
2248 struct sdhci_pci_chip *chip;
2249 struct sdhci_pci_slot *slot;
2251 u8 slots, first_bar;
2254 BUG_ON(pdev == NULL);
2255 BUG_ON(ent == NULL);
2257 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
2258 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
2260 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
2264 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
2265 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
2267 BUG_ON(slots > MAX_SLOTS);
2269 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
2273 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
2275 if (first_bar > 5) {
2276 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
2280 ret = pcim_enable_device(pdev);
2284 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
2289 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
2291 chip->quirks = chip->fixes->quirks;
2292 chip->quirks2 = chip->fixes->quirks2;
2293 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
2295 chip->num_slots = slots;
2296 chip->pm_retune = true;
2297 chip->rpm_retune = true;
2299 pci_set_drvdata(pdev, chip);
2301 if (chip->fixes && chip->fixes->probe) {
2302 ret = chip->fixes->probe(chip);
2307 slots = chip->num_slots; /* Quirk may have changed this */
2309 for (i = 0; i < slots; i++) {
2310 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
2312 for (i--; i >= 0; i--)
2313 sdhci_pci_remove_slot(chip->slots[i]);
2314 return PTR_ERR(slot);
2317 chip->slots[i] = slot;
2320 if (chip->allow_runtime_pm)
2321 sdhci_pci_runtime_pm_allow(&pdev->dev);
2326 static void sdhci_pci_remove(struct pci_dev *pdev)
2329 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
2331 if (chip->allow_runtime_pm)
2332 sdhci_pci_runtime_pm_forbid(&pdev->dev);
2334 for (i = 0; i < chip->num_slots; i++)
2335 sdhci_pci_remove_slot(chip->slots[i]);
2338 static struct pci_driver sdhci_driver = {
2339 .name = "sdhci-pci",
2340 .id_table = pci_ids,
2341 .probe = sdhci_pci_probe,
2342 .remove = sdhci_pci_remove,
2344 .pm = &sdhci_pci_pm_ops
2348 module_pci_driver(sdhci_driver);
2350 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
2351 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
2352 MODULE_LICENSE("GPL");