drivers/mmc/host/sdhci-omap.c

   1 /**
   2  * SDHCI Controller driver for TI's OMAP SoCs
   3  *
   4  * Copyright (C) 2017 Texas Instruments
   5  * Author: Kishon Vijay Abraham I <kishon@ti.com>
   6  *
   7  * This program is free software: you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 of
   9  * the License as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <linux/delay.h>
  21 #include <linux/mmc/slot-gpio.h>
  22 #include <linux/module.h>
  23 #include <linux/of.h>
  24 #include <linux/of_device.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/regulator/consumer.h>
  28
  29 #include "sdhci-pltfm.h"
  30
  31 #define SDHCI_OMAP_CON          0x12c
  32 #define CON_DW8                 BIT(5)
  33 #define CON_DMA_MASTER          BIT(20)
  34 #define CON_DDR                 BIT(19)
  35 #define CON_CLKEXTFREE          BIT(16)
  36 #define CON_PADEN               BIT(15)
  37 #define CON_INIT                BIT(1)
  38 #define CON_OD                  BIT(0)
  39
  40 #define SDHCI_OMAP_CMD          0x20c
  41
  42 #define SDHCI_OMAP_PSTATE       0x0224
  43 #define PSTATE_DLEV_DAT0        BIT(20)
  44 #define PSTATE_DATI             BIT(1)
  45
  46 #define SDHCI_OMAP_HCTL         0x228
  47 #define HCTL_SDBP               BIT(8)
  48 #define HCTL_SDVS_SHIFT         9
  49 #define HCTL_SDVS_MASK          (0x7 << HCTL_SDVS_SHIFT)
  50 #define HCTL_SDVS_33            (0x7 << HCTL_SDVS_SHIFT)
  51 #define HCTL_SDVS_30            (0x6 << HCTL_SDVS_SHIFT)
  52 #define HCTL_SDVS_18            (0x5 << HCTL_SDVS_SHIFT)
  53
  54 #define SDHCI_OMAP_SYSCTL       0x22c
  55 #define SYSCTL_CEN              BIT(2)
  56 #define SYSCTL_CLKD_SHIFT       6
  57 #define SYSCTL_CLKD_MASK        0x3ff
  58
  59 #define SDHCI_OMAP_STAT         0x230
  60
  61 #define SDHCI_OMAP_IE           0x234
  62 #define INT_CC_EN               BIT(0)
  63
  64 #define SDHCI_OMAP_AC12         0x23c
  65 #define AC12_V1V8_SIGEN         BIT(19)
  66
  67 #define SDHCI_OMAP_CAPA         0x240
  68 #define CAPA_VS33               BIT(24)
  69 #define CAPA_VS30               BIT(25)
  70 #define CAPA_VS18               BIT(26)
  71
  72 #define SDHCI_OMAP_TIMEOUT      1               /* 1 msec */
  73
  74 #define SYSCTL_CLKD_MAX         0x3FF
  75
  76 #define IOV_1V8                 1800000         /* 180000 uV */
  77 #define IOV_3V0                 3000000         /* 300000 uV */
  78 #define IOV_3V3                 3300000         /* 330000 uV */
  79
  80 struct sdhci_omap_data {
  81         u32 offset;
  82 };
  83
  84 struct sdhci_omap_host {
  85         void __iomem            *base;
  86         struct device           *dev;
  87         struct  regulator       *pbias;
  88         bool                    pbias_enabled;
  89         struct sdhci_host       *host;
  90         u8                      bus_mode;
  91         u8                      power_mode;
  92 };
  93
  94 static inline u32 sdhci_omap_readl(struct sdhci_omap_host *host,
  95                                    unsigned int offset)
  96 {
  97         return readl(host->base + offset);
  98 }
  99
 100 static inline void sdhci_omap_writel(struct sdhci_omap_host *host,
 101                                      unsigned int offset, u32 data)
 102 {
 103         writel(data, host->base + offset);
 104 }
 105
 106 static int sdhci_omap_set_pbias(struct sdhci_omap_host *omap_host,
 107                                 bool power_on, unsigned int iov)
 108 {
 109         int ret;
 110         struct device *dev = omap_host->dev;
 111
 112         if (IS_ERR(omap_host->pbias))
 113                 return 0;
 114
 115         if (power_on) {
 116                 ret = regulator_set_voltage(omap_host->pbias, iov, iov);
 117                 if (ret) {
 118                         dev_err(dev, "pbias set voltage failed\n");
 119                         return ret;
 120                 }
 121
 122                 if (omap_host->pbias_enabled)
 123                         return 0;
 124
 125                 ret = regulator_enable(omap_host->pbias);
 126                 if (ret) {
 127                         dev_err(dev, "pbias reg enable fail\n");
 128                         return ret;
 129                 }
 130
 131                 omap_host->pbias_enabled = true;
 132         } else {
 133                 if (!omap_host->pbias_enabled)
 134                         return 0;
 135
 136                 ret = regulator_disable(omap_host->pbias);
 137                 if (ret) {
 138                         dev_err(dev, "pbias reg disable fail\n");
 139                         return ret;
 140                 }
 141                 omap_host->pbias_enabled = false;
 142         }
 143
 144         return 0;
 145 }
 146
 147 static int sdhci_omap_enable_iov(struct sdhci_omap_host *omap_host,
 148                                  unsigned int iov)
 149 {
 150         int ret;
 151         struct sdhci_host *host = omap_host->host;
 152         struct mmc_host *mmc = host->mmc;
 153
 154         ret = sdhci_omap_set_pbias(omap_host, false, 0);
 155         if (ret)
 156                 return ret;
 157
 158         if (!IS_ERR(mmc->supply.vqmmc)) {
 159                 ret = regulator_set_voltage(mmc->supply.vqmmc, iov, iov);
 160                 if (ret) {
 161                         dev_err(mmc_dev(mmc), "vqmmc set voltage failed\n");
 162                         return ret;
 163                 }
 164         }
 165
 166         ret = sdhci_omap_set_pbias(omap_host, true, iov);
 167         if (ret)
 168                 return ret;
 169
 170         return 0;
 171 }
 172
 173 static void sdhci_omap_conf_bus_power(struct sdhci_omap_host *omap_host,
 174                                       unsigned char signal_voltage)
 175 {
 176         u32 reg;
 177         ktime_t timeout;
 178
 179         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL);
 180         reg &= ~HCTL_SDVS_MASK;
 181
 182         if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
 183                 reg |= HCTL_SDVS_33;
 184         else
 185                 reg |= HCTL_SDVS_18;
 186
 187         sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, reg);
 188
 189         reg |= HCTL_SDBP;
 190         sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, reg);
 191
 192         /* wait 1ms */
 193         timeout = ktime_add_ms(ktime_get(), SDHCI_OMAP_TIMEOUT);
 194         while (!(sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL) & HCTL_SDBP)) {
 195                 if (WARN_ON(ktime_after(ktime_get(), timeout)))
 196                         return;
 197                 usleep_range(5, 10);
 198         }
 199 }
 200
 201 static int sdhci_omap_card_busy(struct mmc_host *mmc)
 202 {
 203         u32 reg, ac12;
 204         int ret = false;
 205         struct sdhci_host *host = mmc_priv(mmc);
 206         struct sdhci_pltfm_host *pltfm_host;
 207         struct sdhci_omap_host *omap_host;
 208         u32 ier = host->ier;
 209
 210         pltfm_host = sdhci_priv(host);
 211         omap_host = sdhci_pltfm_priv(pltfm_host);
 212
 213         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 214         ac12 = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
 215         reg &= ~CON_CLKEXTFREE;
 216         if (ac12 & AC12_V1V8_SIGEN)
 217                 reg |= CON_CLKEXTFREE;
 218         reg |= CON_PADEN;
 219         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 220
 221         disable_irq(host->irq);
 222         ier |= SDHCI_INT_CARD_INT;
 223         sdhci_writel(host, ier, SDHCI_INT_ENABLE);
 224         sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
 225
 226         /*
 227          * Delay is required for PSTATE to correctly reflect
 228          * DLEV/CLEV values after PADEN is set.
 229          */
 230         usleep_range(50, 100);
 231         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_PSTATE);
 232         if ((reg & PSTATE_DATI) || !(reg & PSTATE_DLEV_DAT0))
 233                 ret = true;
 234
 235         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 236         reg &= ~(CON_CLKEXTFREE | CON_PADEN);
 237         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 238
 239         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 240         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 241         enable_irq(host->irq);
 242
 243         return ret;
 244 }
 245
 246 static int sdhci_omap_start_signal_voltage_switch(struct mmc_host *mmc,
 247                                                   struct mmc_ios *ios)
 248 {
 249         u32 reg;
 250         int ret;
 251         unsigned int iov;
 252         struct sdhci_host *host = mmc_priv(mmc);
 253         struct sdhci_pltfm_host *pltfm_host;
 254         struct sdhci_omap_host *omap_host;
 255         struct device *dev;
 256
 257         pltfm_host = sdhci_priv(host);
 258         omap_host = sdhci_pltfm_priv(pltfm_host);
 259         dev = omap_host->dev;
 260
 261         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
 262                 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
 263                 if (!(reg & CAPA_VS33))
 264                         return -EOPNOTSUPP;
 265
 266                 sdhci_omap_conf_bus_power(omap_host, ios->signal_voltage);
 267
 268                 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
 269                 reg &= ~AC12_V1V8_SIGEN;
 270                 sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
 271
 272                 iov = IOV_3V3;
 273         } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
 274                 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
 275                 if (!(reg & CAPA_VS18))
 276                         return -EOPNOTSUPP;
 277
 278                 sdhci_omap_conf_bus_power(omap_host, ios->signal_voltage);
 279
 280                 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
 281                 reg |= AC12_V1V8_SIGEN;
 282                 sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
 283
 284                 iov = IOV_1V8;
 285         } else {
 286                 return -EOPNOTSUPP;
 287         }
 288
 289         ret = sdhci_omap_enable_iov(omap_host, iov);
 290         if (ret) {
 291                 dev_err(dev, "failed to switch IO voltage to %dmV\n", iov);
 292                 return ret;
 293         }
 294
 295         dev_dbg(dev, "IO voltage switched to %dmV\n", iov);
 296         return 0;
 297 }
 298
 299 static void sdhci_omap_set_power_mode(struct sdhci_omap_host *omap_host,
 300                                       u8 power_mode)
 301 {
 302         omap_host->power_mode = power_mode;
 303 }
 304
 305 static void sdhci_omap_set_bus_mode(struct sdhci_omap_host *omap_host,
 306                                     unsigned int mode)
 307 {
 308         u32 reg;
 309
 310         if (omap_host->bus_mode == mode)
 311                 return;
 312
 313         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 314         if (mode == MMC_BUSMODE_OPENDRAIN)
 315                 reg |= CON_OD;
 316         else
 317                 reg &= ~CON_OD;
 318         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 319
 320         omap_host->bus_mode = mode;
 321 }
 322
 323 static void sdhci_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 324 {
 325         struct sdhci_host *host = mmc_priv(mmc);
 326         struct sdhci_pltfm_host *pltfm_host;
 327         struct sdhci_omap_host *omap_host;
 328
 329         pltfm_host = sdhci_priv(host);
 330         omap_host = sdhci_pltfm_priv(pltfm_host);
 331
 332         sdhci_omap_set_bus_mode(omap_host, ios->bus_mode);
 333         sdhci_set_ios(mmc, ios);
 334         sdhci_omap_set_power_mode(omap_host, ios->power_mode);
 335 }
 336
 337 static u16 sdhci_omap_calc_divisor(struct sdhci_pltfm_host *host,
 338                                    unsigned int clock)
 339 {
 340         u16 dsor;
 341
 342         dsor = DIV_ROUND_UP(clk_get_rate(host->clk), clock);
 343         if (dsor > SYSCTL_CLKD_MAX)
 344                 dsor = SYSCTL_CLKD_MAX;
 345
 346         return dsor;
 347 }
 348
 349 static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host)
 350 {
 351         u32 reg;
 352
 353         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL);
 354         reg |= SYSCTL_CEN;
 355         sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, reg);
 356 }
 357
 358 static void sdhci_omap_stop_clock(struct sdhci_omap_host *omap_host)
 359 {
 360         u32 reg;
 361
 362         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL);
 363         reg &= ~SYSCTL_CEN;
 364         sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, reg);
 365 }
 366
 367 static void sdhci_omap_set_clock(struct sdhci_host *host, unsigned int clock)
 368 {
 369         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 370         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 371         unsigned long clkdiv;
 372
 373         sdhci_omap_stop_clock(omap_host);
 374
 375         if (!clock)
 376                 return;
 377
 378         clkdiv = sdhci_omap_calc_divisor(pltfm_host, clock);
 379         clkdiv = (clkdiv & SYSCTL_CLKD_MASK) << SYSCTL_CLKD_SHIFT;
 380         sdhci_enable_clk(host, clkdiv);
 381
 382         sdhci_omap_start_clock(omap_host);
 383 }
 384
 385 static void sdhci_omap_set_power(struct sdhci_host *host, unsigned char mode,
 386                           unsigned short vdd)
 387 {
 388         struct mmc_host *mmc = host->mmc;
 389
 390         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
 391 }
 392
 393 static int sdhci_omap_enable_dma(struct sdhci_host *host)
 394 {
 395         u32 reg;
 396         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 397         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 398
 399         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 400         reg |= CON_DMA_MASTER;
 401         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 402
 403         return 0;
 404 }
 405
 406 static unsigned int sdhci_omap_get_min_clock(struct sdhci_host *host)
 407 {
 408         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 409
 410         return clk_get_rate(pltfm_host->clk) / SYSCTL_CLKD_MAX;
 411 }
 412
 413 static void sdhci_omap_set_bus_width(struct sdhci_host *host, int width)
 414 {
 415         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 416         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 417         u32 reg;
 418
 419         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 420         if (width == MMC_BUS_WIDTH_8)
 421                 reg |= CON_DW8;
 422         else
 423                 reg &= ~CON_DW8;
 424         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 425
 426         sdhci_set_bus_width(host, width);
 427 }
 428
 429 static void sdhci_omap_init_74_clocks(struct sdhci_host *host, u8 power_mode)
 430 {
 431         u32 reg;
 432         ktime_t timeout;
 433         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 434         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 435
 436         if (omap_host->power_mode == power_mode)
 437                 return;
 438
 439         if (power_mode != MMC_POWER_ON)
 440                 return;
 441
 442         disable_irq(host->irq);
 443
 444         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 445         reg |= CON_INIT;
 446         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 447         sdhci_omap_writel(omap_host, SDHCI_OMAP_CMD, 0x0);
 448
 449         /* wait 1ms */
 450         timeout = ktime_add_ms(ktime_get(), SDHCI_OMAP_TIMEOUT);
 451         while (!(sdhci_omap_readl(omap_host, SDHCI_OMAP_STAT) & INT_CC_EN)) {
 452                 if (WARN_ON(ktime_after(ktime_get(), timeout)))
 453                         return;
 454                 usleep_range(5, 10);
 455         }
 456
 457         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 458         reg &= ~CON_INIT;
 459         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 460         sdhci_omap_writel(omap_host, SDHCI_OMAP_STAT, INT_CC_EN);
 461
 462         enable_irq(host->irq);
 463 }
 464
 465 static void sdhci_omap_set_uhs_signaling(struct sdhci_host *host,
 466                                          unsigned int timing)
 467 {
 468         u32 reg;
 469         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 470         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 471
 472         sdhci_omap_stop_clock(omap_host);
 473
 474         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 475         if (timing == MMC_TIMING_UHS_DDR50 || timing == MMC_TIMING_MMC_DDR52)
 476                 reg |= CON_DDR;
 477         else
 478                 reg &= ~CON_DDR;
 479         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 480
 481         sdhci_set_uhs_signaling(host, timing);
 482         sdhci_omap_start_clock(omap_host);
 483 }
 484
 485 static struct sdhci_ops sdhci_omap_ops = {
 486         .set_clock = sdhci_omap_set_clock,
 487         .set_power = sdhci_omap_set_power,
 488         .enable_dma = sdhci_omap_enable_dma,
 489         .get_max_clock = sdhci_pltfm_clk_get_max_clock,
 490         .get_min_clock = sdhci_omap_get_min_clock,
 491         .set_bus_width = sdhci_omap_set_bus_width,
 492         .platform_send_init_74_clocks = sdhci_omap_init_74_clocks,
 493         .reset = sdhci_reset,
 494         .set_uhs_signaling = sdhci_omap_set_uhs_signaling,
 495 };
 496
 497 static int sdhci_omap_set_capabilities(struct sdhci_omap_host *omap_host)
 498 {
 499         u32 reg;
 500         int ret = 0;
 501         struct device *dev = omap_host->dev;
 502         struct regulator *vqmmc;
 503
 504         vqmmc = regulator_get(dev, "vqmmc");
 505         if (IS_ERR(vqmmc)) {
 506                 ret = PTR_ERR(vqmmc);
 507                 goto reg_put;
 508         }
 509
 510         /* voltage capabilities might be set by boot loader, clear it */
 511         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
 512         reg &= ~(CAPA_VS18 | CAPA_VS30 | CAPA_VS33);
 513
 514         if (regulator_is_supported_voltage(vqmmc, IOV_3V3, IOV_3V3))
 515                 reg |= CAPA_VS33;
 516         if (regulator_is_supported_voltage(vqmmc, IOV_1V8, IOV_1V8))
 517                 reg |= CAPA_VS18;
 518
 519         sdhci_omap_writel(omap_host, SDHCI_OMAP_CAPA, reg);
 520
 521 reg_put:
 522         regulator_put(vqmmc);
 523
 524         return ret;
 525 }
 526
 527 static const struct sdhci_pltfm_data sdhci_omap_pdata = {
 528         .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
 529                   SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
 530                   SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
 531                   SDHCI_QUIRK_NO_HISPD_BIT |
 532                   SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
 533         .quirks2 = SDHCI_QUIRK2_NO_1_8_V |
 534                    SDHCI_QUIRK2_ACMD23_BROKEN |
 535                    SDHCI_QUIRK2_RSP_136_HAS_CRC,
 536         .ops = &sdhci_omap_ops,
 537 };
 538
 539 static const struct sdhci_omap_data dra7_data = {
 540         .offset = 0x200,
 541 };
 542
 543 static const struct of_device_id omap_sdhci_match[] = {
 544         { .compatible = "ti,dra7-sdhci", .data = &dra7_data },
 545         {},
 546 };
 547 MODULE_DEVICE_TABLE(of, omap_sdhci_match);
 548
 549 static int sdhci_omap_probe(struct platform_device *pdev)
 550 {
 551         int ret;
 552         u32 offset;
 553         struct device *dev = &pdev->dev;
 554         struct sdhci_host *host;
 555         struct sdhci_pltfm_host *pltfm_host;
 556         struct sdhci_omap_host *omap_host;
 557         struct mmc_host *mmc;
 558         const struct of_device_id *match;
 559         struct sdhci_omap_data *data;
 560
 561         match = of_match_device(omap_sdhci_match, dev);
 562         if (!match)
 563                 return -EINVAL;
 564
 565         data = (struct sdhci_omap_data *)match->data;
 566         if (!data) {
 567                 dev_err(dev, "no sdhci omap data\n");
 568                 return -EINVAL;
 569         }
 570         offset = data->offset;
 571
 572         host = sdhci_pltfm_init(pdev, &sdhci_omap_pdata,
 573                                 sizeof(*omap_host));
 574         if (IS_ERR(host)) {
 575                 dev_err(dev, "Failed sdhci_pltfm_init\n");
 576                 return PTR_ERR(host);
 577         }
 578
 579         pltfm_host = sdhci_priv(host);
 580         omap_host = sdhci_pltfm_priv(pltfm_host);
 581         omap_host->host = host;
 582         omap_host->base = host->ioaddr;
 583         omap_host->dev = dev;
 584         omap_host->power_mode = MMC_POWER_UNDEFINED;
 585         host->ioaddr += offset;
 586
 587         mmc = host->mmc;
 588         ret = mmc_of_parse(mmc);
 589         if (ret)
 590                 goto err_pltfm_free;
 591
 592         pltfm_host->clk = devm_clk_get(dev, "fck");
 593         if (IS_ERR(pltfm_host->clk)) {
 594                 ret = PTR_ERR(pltfm_host->clk);
 595                 goto err_pltfm_free;
 596         }
 597
 598         ret = clk_set_rate(pltfm_host->clk, mmc->f_max);
 599         if (ret) {
 600                 dev_err(dev, "failed to set clock to %d\n", mmc->f_max);
 601                 goto err_pltfm_free;
 602         }
 603
 604         omap_host->pbias = devm_regulator_get_optional(dev, "pbias");
 605         if (IS_ERR(omap_host->pbias)) {
 606                 ret = PTR_ERR(omap_host->pbias);
 607                 if (ret != -ENODEV)
 608                         goto err_pltfm_free;
 609                 dev_dbg(dev, "unable to get pbias regulator %d\n", ret);
 610         }
 611         omap_host->pbias_enabled = false;
 612
 613         /*
 614          * omap_device_pm_domain has callbacks to enable the main
 615          * functional clock, interface clock and also configure the
 616          * SYSCONFIG register of omap devices. The callback will be invoked
 617          * as part of pm_runtime_get_sync.
 618          */
 619         pm_runtime_enable(dev);
 620         ret = pm_runtime_get_sync(dev);
 621         if (ret < 0) {
 622                 dev_err(dev, "pm_runtime_get_sync failed\n");
 623                 pm_runtime_put_noidle(dev);
 624                 goto err_rpm_disable;
 625         }
 626
 627         ret = sdhci_omap_set_capabilities(omap_host);
 628         if (ret) {
 629                 dev_err(dev, "failed to set system capabilities\n");
 630                 goto err_put_sync;
 631         }
 632
 633         host->mmc_host_ops.get_ro = mmc_gpio_get_ro;
 634         host->mmc_host_ops.start_signal_voltage_switch =
 635                                         sdhci_omap_start_signal_voltage_switch;
 636         host->mmc_host_ops.set_ios = sdhci_omap_set_ios;
 637         host->mmc_host_ops.card_busy = sdhci_omap_card_busy;
 638
 639         sdhci_read_caps(host);
 640         host->caps |= SDHCI_CAN_DO_ADMA2;
 641
 642         ret = sdhci_add_host(host);
 643         if (ret)
 644                 goto err_put_sync;
 645
 646         return 0;
 647
 648 err_put_sync:
 649         pm_runtime_put_sync(dev);
 650
 651 err_rpm_disable:
 652         pm_runtime_disable(dev);
 653
 654 err_pltfm_free:
 655         sdhci_pltfm_free(pdev);
 656         return ret;
 657 }
 658
 659 static int sdhci_omap_remove(struct platform_device *pdev)
 660 {
 661         struct device *dev = &pdev->dev;
 662         struct sdhci_host *host = platform_get_drvdata(pdev);
 663
 664         sdhci_remove_host(host, true);
 665         pm_runtime_put_sync(dev);
 666         pm_runtime_disable(dev);
 667         sdhci_pltfm_free(pdev);
 668
 669         return 0;
 670 }
 671
 672 static struct platform_driver sdhci_omap_driver = {
 673         .probe = sdhci_omap_probe,
 674         .remove = sdhci_omap_remove,
 675         .driver = {
 676                    .name = "sdhci-omap",
 677                    .of_match_table = omap_sdhci_match,
 678                   },
 679 };
 680
 681 module_platform_driver(sdhci_omap_driver);
 682
 683 MODULE_DESCRIPTION("SDHCI driver for OMAP SoCs");
 684 MODULE_AUTHOR("Texas Instruments Inc.");
 685 MODULE_LICENSE("GPL v2");
 686 MODULE_ALIAS("platform:sdhci_omap");