drivers/mmc/host/sdhci-omap.c

   1 /**
   2  * SDHCI Controller driver for TI's OMAP SoCs
   3  *
   4  * Copyright (C) 2017 Texas Instruments
   5  * Author: Kishon Vijay Abraham I <kishon@ti.com>
   6  *
   7  * This program is free software: you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 of
   9  * the License as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <linux/delay.h>
  21 #include <linux/mmc/slot-gpio.h>
  22 #include <linux/module.h>
  23 #include <linux/of.h>
  24 #include <linux/of_device.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/regulator/consumer.h>
  28 #include <linux/pinctrl/consumer.h>
  29 #include <linux/sys_soc.h>
  30
  31 #include "sdhci-pltfm.h"
  32
  33 #define SDHCI_OMAP_CON          0x12c
  34 #define CON_DW8                 BIT(5)
  35 #define CON_DMA_MASTER          BIT(20)
  36 #define CON_DDR                 BIT(19)
  37 #define CON_CLKEXTFREE          BIT(16)
  38 #define CON_PADEN               BIT(15)
  39 #define CON_CTPL                BIT(11)
  40 #define CON_INIT                BIT(1)
  41 #define CON_OD                  BIT(0)
  42
  43 #define SDHCI_OMAP_DLL          0x0134
  44 #define DLL_SWT                 BIT(20)
  45 #define DLL_FORCE_SR_C_SHIFT    13
  46 #define DLL_FORCE_SR_C_MASK     (0x7f << DLL_FORCE_SR_C_SHIFT)
  47 #define DLL_FORCE_VALUE         BIT(12)
  48 #define DLL_CALIB               BIT(1)
  49
  50 #define SDHCI_OMAP_CMD          0x20c
  51
  52 #define SDHCI_OMAP_PSTATE       0x0224
  53 #define PSTATE_DLEV_DAT0        BIT(20)
  54 #define PSTATE_DATI             BIT(1)
  55
  56 #define SDHCI_OMAP_HCTL         0x228
  57 #define HCTL_SDBP               BIT(8)
  58 #define HCTL_SDVS_SHIFT         9
  59 #define HCTL_SDVS_MASK          (0x7 << HCTL_SDVS_SHIFT)
  60 #define HCTL_SDVS_33            (0x7 << HCTL_SDVS_SHIFT)
  61 #define HCTL_SDVS_30            (0x6 << HCTL_SDVS_SHIFT)
  62 #define HCTL_SDVS_18            (0x5 << HCTL_SDVS_SHIFT)
  63
  64 #define SDHCI_OMAP_SYSCTL       0x22c
  65 #define SYSCTL_CEN              BIT(2)
  66 #define SYSCTL_CLKD_SHIFT       6
  67 #define SYSCTL_CLKD_MASK        0x3ff
  68
  69 #define SDHCI_OMAP_STAT         0x230
  70
  71 #define SDHCI_OMAP_IE           0x234
  72 #define INT_CC_EN               BIT(0)
  73
  74 #define SDHCI_OMAP_AC12         0x23c
  75 #define AC12_V1V8_SIGEN         BIT(19)
  76 #define AC12_SCLK_SEL           BIT(23)
  77
  78 #define SDHCI_OMAP_CAPA         0x240
  79 #define CAPA_VS33               BIT(24)
  80 #define CAPA_VS30               BIT(25)
  81 #define CAPA_VS18               BIT(26)
  82
  83 #define SDHCI_OMAP_CAPA2        0x0244
  84 #define CAPA2_TSDR50            BIT(13)
  85
  86 #define SDHCI_OMAP_TIMEOUT      1               /* 1 msec */
  87
  88 #define SYSCTL_CLKD_MAX         0x3FF
  89
  90 #define IOV_1V8                 1800000         /* 180000 uV */
  91 #define IOV_3V0                 3000000         /* 300000 uV */
  92 #define IOV_3V3                 3300000         /* 330000 uV */
  93
  94 #define MAX_PHASE_DELAY         0x7C
  95
  96 /* sdhci-omap controller flags */
  97 #define SDHCI_OMAP_REQUIRE_IODELAY      BIT(0)
  98
  99 struct sdhci_omap_data {
 100         u32 offset;
 101         u8 flags;
 102 };
 103
 104 struct sdhci_omap_host {
 105         char                    *version;
 106         void __iomem            *base;
 107         struct device           *dev;
 108         struct  regulator       *pbias;
 109         bool                    pbias_enabled;
 110         struct sdhci_host       *host;
 111         u8                      bus_mode;
 112         u8                      power_mode;
 113         u8                      timing;
 114         u8                      flags;
 115
 116         struct pinctrl          *pinctrl;
 117         struct pinctrl_state    **pinctrl_state;
 118 };
 119
 120 static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host);
 121 static void sdhci_omap_stop_clock(struct sdhci_omap_host *omap_host);
 122
 123 static inline u32 sdhci_omap_readl(struct sdhci_omap_host *host,
 124                                    unsigned int offset)
 125 {
 126         return readl(host->base + offset);
 127 }
 128
 129 static inline void sdhci_omap_writel(struct sdhci_omap_host *host,
 130                                      unsigned int offset, u32 data)
 131 {
 132         writel(data, host->base + offset);
 133 }
 134
 135 static int sdhci_omap_set_pbias(struct sdhci_omap_host *omap_host,
 136                                 bool power_on, unsigned int iov)
 137 {
 138         int ret;
 139         struct device *dev = omap_host->dev;
 140
 141         if (IS_ERR(omap_host->pbias))
 142                 return 0;
 143
 144         if (power_on) {
 145                 ret = regulator_set_voltage(omap_host->pbias, iov, iov);
 146                 if (ret) {
 147                         dev_err(dev, "pbias set voltage failed\n");
 148                         return ret;
 149                 }
 150
 151                 if (omap_host->pbias_enabled)
 152                         return 0;
 153
 154                 ret = regulator_enable(omap_host->pbias);
 155                 if (ret) {
 156                         dev_err(dev, "pbias reg enable fail\n");
 157                         return ret;
 158                 }
 159
 160                 omap_host->pbias_enabled = true;
 161         } else {
 162                 if (!omap_host->pbias_enabled)
 163                         return 0;
 164
 165                 ret = regulator_disable(omap_host->pbias);
 166                 if (ret) {
 167                         dev_err(dev, "pbias reg disable fail\n");
 168                         return ret;
 169                 }
 170                 omap_host->pbias_enabled = false;
 171         }
 172
 173         return 0;
 174 }
 175
 176 static int sdhci_omap_enable_iov(struct sdhci_omap_host *omap_host,
 177                                  unsigned int iov)
 178 {
 179         int ret;
 180         struct sdhci_host *host = omap_host->host;
 181         struct mmc_host *mmc = host->mmc;
 182
 183         ret = sdhci_omap_set_pbias(omap_host, false, 0);
 184         if (ret)
 185                 return ret;
 186
 187         if (!IS_ERR(mmc->supply.vqmmc)) {
 188                 ret = regulator_set_voltage(mmc->supply.vqmmc, iov, iov);
 189                 if (ret) {
 190                         dev_err(mmc_dev(mmc), "vqmmc set voltage failed\n");
 191                         return ret;
 192                 }
 193         }
 194
 195         ret = sdhci_omap_set_pbias(omap_host, true, iov);
 196         if (ret)
 197                 return ret;
 198
 199         return 0;
 200 }
 201
 202 static void sdhci_omap_conf_bus_power(struct sdhci_omap_host *omap_host,
 203                                       unsigned char signal_voltage)
 204 {
 205         u32 reg;
 206         ktime_t timeout;
 207
 208         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL);
 209         reg &= ~HCTL_SDVS_MASK;
 210
 211         if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
 212                 reg |= HCTL_SDVS_33;
 213         else
 214                 reg |= HCTL_SDVS_18;
 215
 216         sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, reg);
 217
 218         reg |= HCTL_SDBP;
 219         sdhci_omap_writel(omap_host, SDHCI_OMAP_HCTL, reg);
 220
 221         /* wait 1ms */
 222         timeout = ktime_add_ms(ktime_get(), SDHCI_OMAP_TIMEOUT);
 223         while (!(sdhci_omap_readl(omap_host, SDHCI_OMAP_HCTL) & HCTL_SDBP)) {
 224                 if (WARN_ON(ktime_after(ktime_get(), timeout)))
 225                         return;
 226                 usleep_range(5, 10);
 227         }
 228 }
 229
 230 static void sdhci_omap_enable_sdio_irq(struct mmc_host *mmc, int enable)
 231 {
 232         struct sdhci_host *host = mmc_priv(mmc);
 233         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 234         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 235         u32 reg;
 236
 237         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 238         if (enable)
 239                 reg |= (CON_CTPL | CON_CLKEXTFREE);
 240         else
 241                 reg &= ~(CON_CTPL | CON_CLKEXTFREE);
 242         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 243
 244         sdhci_enable_sdio_irq(mmc, enable);
 245 }
 246
 247 static inline void sdhci_omap_set_dll(struct sdhci_omap_host *omap_host,
 248                                       int count)
 249 {
 250         int i;
 251         u32 reg;
 252
 253         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
 254         reg |= DLL_FORCE_VALUE;
 255         reg &= ~DLL_FORCE_SR_C_MASK;
 256         reg |= (count << DLL_FORCE_SR_C_SHIFT);
 257         sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
 258
 259         reg |= DLL_CALIB;
 260         sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
 261         for (i = 0; i < 1000; i++) {
 262                 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
 263                 if (reg & DLL_CALIB)
 264                         break;
 265         }
 266         reg &= ~DLL_CALIB;
 267         sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
 268 }
 269
 270 static void sdhci_omap_disable_tuning(struct sdhci_omap_host *omap_host)
 271 {
 272         u32 reg;
 273
 274         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
 275         reg &= ~AC12_SCLK_SEL;
 276         sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
 277
 278         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
 279         reg &= ~(DLL_FORCE_VALUE | DLL_SWT);
 280         sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
 281 }
 282
 283 static int sdhci_omap_execute_tuning(struct mmc_host *mmc, u32 opcode)
 284 {
 285         struct sdhci_host *host = mmc_priv(mmc);
 286         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 287         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 288         struct device *dev = omap_host->dev;
 289         struct mmc_ios *ios = &mmc->ios;
 290         u32 start_window = 0, max_window = 0;
 291         u8 cur_match, prev_match = 0;
 292         u32 length = 0, max_len = 0;
 293         u32 ier = host->ier;
 294         u32 phase_delay = 0;
 295         int ret = 0;
 296         u32 reg;
 297
 298         pltfm_host = sdhci_priv(host);
 299         omap_host = sdhci_pltfm_priv(pltfm_host);
 300         dev = omap_host->dev;
 301
 302         /* clock tuning is not needed for upto 52MHz */
 303         if (ios->clock <= 52000000)
 304                 return 0;
 305
 306         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA2);
 307         if (ios->timing == MMC_TIMING_UHS_SDR50 && !(reg & CAPA2_TSDR50))
 308                 return 0;
 309
 310         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
 311         reg |= DLL_SWT;
 312         sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
 313
 314         /*
 315          * OMAP5/DRA74X/DRA72x Errata i802:
 316          * DCRC error interrupts (MMCHS_STAT[21] DCRC=0x1) can occur
 317          * during the tuning procedure. So disable it during the
 318          * tuning procedure.
 319          */
 320         ier &= ~SDHCI_INT_DATA_CRC;
 321         sdhci_writel(host, ier, SDHCI_INT_ENABLE);
 322         sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
 323
 324         while (phase_delay <= MAX_PHASE_DELAY) {
 325                 sdhci_omap_set_dll(omap_host, phase_delay);
 326
 327                 cur_match = !mmc_send_tuning(mmc, opcode, NULL);
 328                 if (cur_match) {
 329                         if (prev_match) {
 330                                 length++;
 331                         } else {
 332                                 start_window = phase_delay;
 333                                 length = 1;
 334                         }
 335                 }
 336
 337                 if (length > max_len) {
 338                         max_window = start_window;
 339                         max_len = length;
 340                 }
 341
 342                 prev_match = cur_match;
 343                 phase_delay += 4;
 344         }
 345
 346         if (!max_len) {
 347                 dev_err(dev, "Unable to find match\n");
 348                 ret = -EIO;
 349                 goto tuning_error;
 350         }
 351
 352         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
 353         if (!(reg & AC12_SCLK_SEL)) {
 354                 ret = -EIO;
 355                 goto tuning_error;
 356         }
 357
 358         phase_delay = max_window + 4 * (max_len >> 1);
 359         sdhci_omap_set_dll(omap_host, phase_delay);
 360
 361         goto ret;
 362
 363 tuning_error:
 364         dev_err(dev, "Tuning failed\n");
 365         sdhci_omap_disable_tuning(omap_host);
 366
 367 ret:
 368         sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
 369         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 370         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 371         return ret;
 372 }
 373
 374 static int sdhci_omap_card_busy(struct mmc_host *mmc)
 375 {
 376         u32 reg, ac12;
 377         int ret = false;
 378         struct sdhci_host *host = mmc_priv(mmc);
 379         struct sdhci_pltfm_host *pltfm_host;
 380         struct sdhci_omap_host *omap_host;
 381         u32 ier = host->ier;
 382
 383         pltfm_host = sdhci_priv(host);
 384         omap_host = sdhci_pltfm_priv(pltfm_host);
 385
 386         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 387         ac12 = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
 388         reg &= ~CON_CLKEXTFREE;
 389         if (ac12 & AC12_V1V8_SIGEN)
 390                 reg |= CON_CLKEXTFREE;
 391         reg |= CON_PADEN;
 392         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 393
 394         disable_irq(host->irq);
 395         ier |= SDHCI_INT_CARD_INT;
 396         sdhci_writel(host, ier, SDHCI_INT_ENABLE);
 397         sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
 398
 399         /*
 400          * Delay is required for PSTATE to correctly reflect
 401          * DLEV/CLEV values after PADEN is set.
 402          */
 403         usleep_range(50, 100);
 404         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_PSTATE);
 405         if ((reg & PSTATE_DATI) || !(reg & PSTATE_DLEV_DAT0))
 406                 ret = true;
 407
 408         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 409         reg &= ~(CON_CLKEXTFREE | CON_PADEN);
 410         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 411
 412         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 413         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 414         enable_irq(host->irq);
 415
 416         return ret;
 417 }
 418
 419 static int sdhci_omap_start_signal_voltage_switch(struct mmc_host *mmc,
 420                                                   struct mmc_ios *ios)
 421 {
 422         u32 reg;
 423         int ret;
 424         unsigned int iov;
 425         struct sdhci_host *host = mmc_priv(mmc);
 426         struct sdhci_pltfm_host *pltfm_host;
 427         struct sdhci_omap_host *omap_host;
 428         struct device *dev;
 429
 430         pltfm_host = sdhci_priv(host);
 431         omap_host = sdhci_pltfm_priv(pltfm_host);
 432         dev = omap_host->dev;
 433
 434         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
 435                 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
 436                 if (!(reg & CAPA_VS33))
 437                         return -EOPNOTSUPP;
 438
 439                 sdhci_omap_conf_bus_power(omap_host, ios->signal_voltage);
 440
 441                 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
 442                 reg &= ~AC12_V1V8_SIGEN;
 443                 sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
 444
 445                 iov = IOV_3V3;
 446         } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
 447                 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
 448                 if (!(reg & CAPA_VS18))
 449                         return -EOPNOTSUPP;
 450
 451                 sdhci_omap_conf_bus_power(omap_host, ios->signal_voltage);
 452
 453                 reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
 454                 reg |= AC12_V1V8_SIGEN;
 455                 sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
 456
 457                 iov = IOV_1V8;
 458         } else {
 459                 return -EOPNOTSUPP;
 460         }
 461
 462         ret = sdhci_omap_enable_iov(omap_host, iov);
 463         if (ret) {
 464                 dev_err(dev, "failed to switch IO voltage to %dmV\n", iov);
 465                 return ret;
 466         }
 467
 468         dev_dbg(dev, "IO voltage switched to %dmV\n", iov);
 469         return 0;
 470 }
 471
 472 static void sdhci_omap_set_timing(struct sdhci_omap_host *omap_host, u8 timing)
 473 {
 474         int ret;
 475         struct pinctrl_state *pinctrl_state;
 476         struct device *dev = omap_host->dev;
 477
 478         if (!(omap_host->flags & SDHCI_OMAP_REQUIRE_IODELAY))
 479                 return;
 480
 481         if (omap_host->timing == timing)
 482                 return;
 483
 484         sdhci_omap_stop_clock(omap_host);
 485
 486         pinctrl_state = omap_host->pinctrl_state[timing];
 487         ret = pinctrl_select_state(omap_host->pinctrl, pinctrl_state);
 488         if (ret) {
 489                 dev_err(dev, "failed to select pinctrl state\n");
 490                 return;
 491         }
 492
 493         sdhci_omap_start_clock(omap_host);
 494         omap_host->timing = timing;
 495 }
 496
 497 static void sdhci_omap_set_power_mode(struct sdhci_omap_host *omap_host,
 498                                       u8 power_mode)
 499 {
 500         if (omap_host->bus_mode == MMC_POWER_OFF)
 501                 sdhci_omap_disable_tuning(omap_host);
 502         omap_host->power_mode = power_mode;
 503 }
 504
 505 static void sdhci_omap_set_bus_mode(struct sdhci_omap_host *omap_host,
 506                                     unsigned int mode)
 507 {
 508         u32 reg;
 509
 510         if (omap_host->bus_mode == mode)
 511                 return;
 512
 513         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 514         if (mode == MMC_BUSMODE_OPENDRAIN)
 515                 reg |= CON_OD;
 516         else
 517                 reg &= ~CON_OD;
 518         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 519
 520         omap_host->bus_mode = mode;
 521 }
 522
 523 static void sdhci_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 524 {
 525         struct sdhci_host *host = mmc_priv(mmc);
 526         struct sdhci_pltfm_host *pltfm_host;
 527         struct sdhci_omap_host *omap_host;
 528
 529         pltfm_host = sdhci_priv(host);
 530         omap_host = sdhci_pltfm_priv(pltfm_host);
 531
 532         sdhci_omap_set_bus_mode(omap_host, ios->bus_mode);
 533         sdhci_omap_set_timing(omap_host, ios->timing);
 534         sdhci_set_ios(mmc, ios);
 535         sdhci_omap_set_power_mode(omap_host, ios->power_mode);
 536 }
 537
 538 static u16 sdhci_omap_calc_divisor(struct sdhci_pltfm_host *host,
 539                                    unsigned int clock)
 540 {
 541         u16 dsor;
 542
 543         dsor = DIV_ROUND_UP(clk_get_rate(host->clk), clock);
 544         if (dsor > SYSCTL_CLKD_MAX)
 545                 dsor = SYSCTL_CLKD_MAX;
 546
 547         return dsor;
 548 }
 549
 550 static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host)
 551 {
 552         u32 reg;
 553
 554         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL);
 555         reg |= SYSCTL_CEN;
 556         sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, reg);
 557 }
 558
 559 static void sdhci_omap_stop_clock(struct sdhci_omap_host *omap_host)
 560 {
 561         u32 reg;
 562
 563         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_SYSCTL);
 564         reg &= ~SYSCTL_CEN;
 565         sdhci_omap_writel(omap_host, SDHCI_OMAP_SYSCTL, reg);
 566 }
 567
 568 static void sdhci_omap_set_clock(struct sdhci_host *host, unsigned int clock)
 569 {
 570         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 571         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 572         unsigned long clkdiv;
 573
 574         sdhci_omap_stop_clock(omap_host);
 575
 576         if (!clock)
 577                 return;
 578
 579         clkdiv = sdhci_omap_calc_divisor(pltfm_host, clock);
 580         clkdiv = (clkdiv & SYSCTL_CLKD_MASK) << SYSCTL_CLKD_SHIFT;
 581         sdhci_enable_clk(host, clkdiv);
 582
 583         sdhci_omap_start_clock(omap_host);
 584 }
 585
 586 static void sdhci_omap_set_power(struct sdhci_host *host, unsigned char mode,
 587                           unsigned short vdd)
 588 {
 589         struct mmc_host *mmc = host->mmc;
 590
 591         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
 592 }
 593
 594 static int sdhci_omap_enable_dma(struct sdhci_host *host)
 595 {
 596         u32 reg;
 597         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 598         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 599
 600         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 601         reg |= CON_DMA_MASTER;
 602         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 603
 604         return 0;
 605 }
 606
 607 static unsigned int sdhci_omap_get_min_clock(struct sdhci_host *host)
 608 {
 609         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 610
 611         return clk_get_rate(pltfm_host->clk) / SYSCTL_CLKD_MAX;
 612 }
 613
 614 static void sdhci_omap_set_bus_width(struct sdhci_host *host, int width)
 615 {
 616         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 617         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 618         u32 reg;
 619
 620         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 621         if (width == MMC_BUS_WIDTH_8)
 622                 reg |= CON_DW8;
 623         else
 624                 reg &= ~CON_DW8;
 625         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 626
 627         sdhci_set_bus_width(host, width);
 628 }
 629
 630 static void sdhci_omap_init_74_clocks(struct sdhci_host *host, u8 power_mode)
 631 {
 632         u32 reg;
 633         ktime_t timeout;
 634         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 635         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 636
 637         if (omap_host->power_mode == power_mode)
 638                 return;
 639
 640         if (power_mode != MMC_POWER_ON)
 641                 return;
 642
 643         disable_irq(host->irq);
 644
 645         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 646         reg |= CON_INIT;
 647         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 648         sdhci_omap_writel(omap_host, SDHCI_OMAP_CMD, 0x0);
 649
 650         /* wait 1ms */
 651         timeout = ktime_add_ms(ktime_get(), SDHCI_OMAP_TIMEOUT);
 652         while (!(sdhci_omap_readl(omap_host, SDHCI_OMAP_STAT) & INT_CC_EN)) {
 653                 if (WARN_ON(ktime_after(ktime_get(), timeout)))
 654                         return;
 655                 usleep_range(5, 10);
 656         }
 657
 658         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 659         reg &= ~CON_INIT;
 660         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 661         sdhci_omap_writel(omap_host, SDHCI_OMAP_STAT, INT_CC_EN);
 662
 663         enable_irq(host->irq);
 664 }
 665
 666 static void sdhci_omap_set_uhs_signaling(struct sdhci_host *host,
 667                                          unsigned int timing)
 668 {
 669         u32 reg;
 670         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 671         struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
 672
 673         sdhci_omap_stop_clock(omap_host);
 674
 675         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
 676         if (timing == MMC_TIMING_UHS_DDR50 || timing == MMC_TIMING_MMC_DDR52)
 677                 reg |= CON_DDR;
 678         else
 679                 reg &= ~CON_DDR;
 680         sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
 681
 682         sdhci_set_uhs_signaling(host, timing);
 683         sdhci_omap_start_clock(omap_host);
 684 }
 685
 686 static struct sdhci_ops sdhci_omap_ops = {
 687         .set_clock = sdhci_omap_set_clock,
 688         .set_power = sdhci_omap_set_power,
 689         .enable_dma = sdhci_omap_enable_dma,
 690         .get_max_clock = sdhci_pltfm_clk_get_max_clock,
 691         .get_min_clock = sdhci_omap_get_min_clock,
 692         .set_bus_width = sdhci_omap_set_bus_width,
 693         .platform_send_init_74_clocks = sdhci_omap_init_74_clocks,
 694         .reset = sdhci_reset,
 695         .set_uhs_signaling = sdhci_omap_set_uhs_signaling,
 696 };
 697
 698 static int sdhci_omap_set_capabilities(struct sdhci_omap_host *omap_host)
 699 {
 700         u32 reg;
 701         int ret = 0;
 702         struct device *dev = omap_host->dev;
 703         struct regulator *vqmmc;
 704
 705         vqmmc = regulator_get(dev, "vqmmc");
 706         if (IS_ERR(vqmmc)) {
 707                 ret = PTR_ERR(vqmmc);
 708                 goto reg_put;
 709         }
 710
 711         /* voltage capabilities might be set by boot loader, clear it */
 712         reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
 713         reg &= ~(CAPA_VS18 | CAPA_VS30 | CAPA_VS33);
 714
 715         if (regulator_is_supported_voltage(vqmmc, IOV_3V3, IOV_3V3))
 716                 reg |= CAPA_VS33;
 717         if (regulator_is_supported_voltage(vqmmc, IOV_1V8, IOV_1V8))
 718                 reg |= CAPA_VS18;
 719
 720         sdhci_omap_writel(omap_host, SDHCI_OMAP_CAPA, reg);
 721
 722 reg_put:
 723         regulator_put(vqmmc);
 724
 725         return ret;
 726 }
 727
 728 static const struct sdhci_pltfm_data sdhci_omap_pdata = {
 729         .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
 730                   SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
 731                   SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
 732                   SDHCI_QUIRK_NO_HISPD_BIT |
 733                   SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
 734         .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN |
 735                    SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
 736                    SDHCI_QUIRK2_RSP_136_HAS_CRC |
 737                    SDHCI_QUIRK2_DISABLE_HW_TIMEOUT,
 738         .ops = &sdhci_omap_ops,
 739 };
 740
 741 static const struct sdhci_omap_data k2g_data = {
 742         .offset = 0x200,
 743 };
 744
 745 static const struct sdhci_omap_data dra7_data = {
 746         .offset = 0x200,
 747         .flags  = SDHCI_OMAP_REQUIRE_IODELAY,
 748 };
 749
 750 static const struct of_device_id omap_sdhci_match[] = {
 751         { .compatible = "ti,dra7-sdhci", .data = &dra7_data },
 752         { .compatible = "ti,k2g-sdhci", .data = &k2g_data },
 753         {},
 754 };
 755 MODULE_DEVICE_TABLE(of, omap_sdhci_match);
 756
 757 static struct pinctrl_state
 758 *sdhci_omap_iodelay_pinctrl_state(struct sdhci_omap_host *omap_host, char *mode,
 759                                   u32 *caps, u32 capmask)
 760 {
 761         struct device *dev = omap_host->dev;
 762         char *version = omap_host->version;
 763         struct pinctrl_state *pinctrl_state = ERR_PTR(-ENODEV);
 764         char str[20];
 765
 766         if (!(*caps & capmask))
 767                 goto ret;
 768
 769         if (version) {
 770                 snprintf(str, 20, "%s-%s", mode, version);
 771                 pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, str);
 772         }
 773
 774         if (IS_ERR(pinctrl_state))
 775                 pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, mode);
 776
 777         if (IS_ERR(pinctrl_state)) {
 778                 dev_err(dev, "no pinctrl state for %s mode", mode);
 779                 *caps &= ~capmask;
 780         }
 781
 782 ret:
 783         return pinctrl_state;
 784 }
 785
 786 static int sdhci_omap_config_iodelay_pinctrl_state(struct sdhci_omap_host
 787                                                    *omap_host)
 788 {
 789         struct device *dev = omap_host->dev;
 790         struct sdhci_host *host = omap_host->host;
 791         struct mmc_host *mmc = host->mmc;
 792         u32 *caps = &mmc->caps;
 793         u32 *caps2 = &mmc->caps2;
 794         struct pinctrl_state *state;
 795         struct pinctrl_state **pinctrl_state;
 796
 797         if (!(omap_host->flags & SDHCI_OMAP_REQUIRE_IODELAY))
 798                 return 0;
 799
 800         pinctrl_state = devm_kzalloc(dev, sizeof(*pinctrl_state) *
 801                                      (MMC_TIMING_MMC_HS200 + 1), GFP_KERNEL);
 802         if (!pinctrl_state)
 803                 return -ENOMEM;
 804
 805         omap_host->pinctrl = devm_pinctrl_get(omap_host->dev);
 806         if (IS_ERR(omap_host->pinctrl)) {
 807                 dev_err(dev, "Cannot get pinctrl\n");
 808                 return PTR_ERR(omap_host->pinctrl);
 809         }
 810
 811         state = pinctrl_lookup_state(omap_host->pinctrl, "default");
 812         if (IS_ERR(state)) {
 813                 dev_err(dev, "no pinctrl state for default mode\n");
 814                 return PTR_ERR(state);
 815         }
 816         pinctrl_state[MMC_TIMING_LEGACY] = state;
 817
 818         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr104", caps,
 819                                                  MMC_CAP_UHS_SDR104);
 820         if (!IS_ERR(state))
 821                 pinctrl_state[MMC_TIMING_UHS_SDR104] = state;
 822
 823         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr50", caps,
 824                                                  MMC_CAP_UHS_DDR50);
 825         if (!IS_ERR(state))
 826                 pinctrl_state[MMC_TIMING_UHS_DDR50] = state;
 827
 828         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr50", caps,
 829                                                  MMC_CAP_UHS_SDR50);
 830         if (!IS_ERR(state))
 831                 pinctrl_state[MMC_TIMING_UHS_SDR50] = state;
 832
 833         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr25", caps,
 834                                                  MMC_CAP_UHS_SDR25);
 835         if (!IS_ERR(state))
 836                 pinctrl_state[MMC_TIMING_UHS_SDR25] = state;
 837
 838         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr12", caps,
 839                                                  MMC_CAP_UHS_SDR12);
 840         if (!IS_ERR(state))
 841                 pinctrl_state[MMC_TIMING_UHS_SDR12] = state;
 842
 843         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_1_8v", caps,
 844                                                  MMC_CAP_1_8V_DDR);
 845         if (!IS_ERR(state)) {
 846                 pinctrl_state[MMC_TIMING_MMC_DDR52] = state;
 847         } else {
 848                 state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_3_3v",
 849                                                          caps,
 850                                                          MMC_CAP_3_3V_DDR);
 851                 if (!IS_ERR(state))
 852                         pinctrl_state[MMC_TIMING_MMC_DDR52] = state;
 853         }
 854
 855         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps,
 856                                                  MMC_CAP_SD_HIGHSPEED);
 857         if (!IS_ERR(state))
 858                 pinctrl_state[MMC_TIMING_SD_HS] = state;
 859
 860         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps,
 861                                                  MMC_CAP_MMC_HIGHSPEED);
 862         if (!IS_ERR(state))
 863                 pinctrl_state[MMC_TIMING_MMC_HS] = state;
 864
 865         state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs200_1_8v", caps2,
 866                                                  MMC_CAP2_HS200_1_8V_SDR);
 867         if (!IS_ERR(state))
 868                 pinctrl_state[MMC_TIMING_MMC_HS200] = state;
 869
 870         omap_host->pinctrl_state = pinctrl_state;
 871
 872         return 0;
 873 }
 874
 875 static const struct soc_device_attribute sdhci_omap_soc_devices[] = {
 876         {
 877                 .machine = "DRA7[45]*",
 878                 .revision = "ES1.[01]",
 879         },
 880         {
 881                 /* sentinel */
 882         }
 883 };
 884
 885 static int sdhci_omap_probe(struct platform_device *pdev)
 886 {
 887         int ret;
 888         u32 offset;
 889         struct device *dev = &pdev->dev;
 890         struct sdhci_host *host;
 891         struct sdhci_pltfm_host *pltfm_host;
 892         struct sdhci_omap_host *omap_host;
 893         struct mmc_host *mmc;
 894         const struct of_device_id *match;
 895         struct sdhci_omap_data *data;
 896         const struct soc_device_attribute *soc;
 897
 898         match = of_match_device(omap_sdhci_match, dev);
 899         if (!match)
 900                 return -EINVAL;
 901
 902         data = (struct sdhci_omap_data *)match->data;
 903         if (!data) {
 904                 dev_err(dev, "no sdhci omap data\n");
 905                 return -EINVAL;
 906         }
 907         offset = data->offset;
 908
 909         host = sdhci_pltfm_init(pdev, &sdhci_omap_pdata,
 910                                 sizeof(*omap_host));
 911         if (IS_ERR(host)) {
 912                 dev_err(dev, "Failed sdhci_pltfm_init\n");
 913                 return PTR_ERR(host);
 914         }
 915
 916         pltfm_host = sdhci_priv(host);
 917         omap_host = sdhci_pltfm_priv(pltfm_host);
 918         omap_host->host = host;
 919         omap_host->base = host->ioaddr;
 920         omap_host->dev = dev;
 921         omap_host->power_mode = MMC_POWER_UNDEFINED;
 922         omap_host->timing = MMC_TIMING_LEGACY;
 923         omap_host->flags = data->flags;
 924         host->ioaddr += offset;
 925
 926         mmc = host->mmc;
 927         sdhci_get_of_property(pdev);
 928         ret = mmc_of_parse(mmc);
 929         if (ret)
 930                 goto err_pltfm_free;
 931
 932         soc = soc_device_match(sdhci_omap_soc_devices);
 933         if (soc) {
 934                 omap_host->version = "rev11";
 935                 if (!strcmp(dev_name(dev), "4809c000.mmc"))
 936                         mmc->f_max = 96000000;
 937                 if (!strcmp(dev_name(dev), "480b4000.mmc"))
 938                         mmc->f_max = 48000000;
 939                 if (!strcmp(dev_name(dev), "480ad000.mmc"))
 940                         mmc->f_max = 48000000;
 941         }
 942
 943         pltfm_host->clk = devm_clk_get(dev, "fck");
 944         if (IS_ERR(pltfm_host->clk)) {
 945                 ret = PTR_ERR(pltfm_host->clk);
 946                 goto err_pltfm_free;
 947         }
 948
 949         ret = clk_set_rate(pltfm_host->clk, mmc->f_max);
 950         if (ret) {
 951                 dev_err(dev, "failed to set clock to %d\n", mmc->f_max);
 952                 goto err_pltfm_free;
 953         }
 954
 955         omap_host->pbias = devm_regulator_get_optional(dev, "pbias");
 956         if (IS_ERR(omap_host->pbias)) {
 957                 ret = PTR_ERR(omap_host->pbias);
 958                 if (ret != -ENODEV)
 959                         goto err_pltfm_free;
 960                 dev_dbg(dev, "unable to get pbias regulator %d\n", ret);
 961         }
 962         omap_host->pbias_enabled = false;
 963
 964         /*
 965          * omap_device_pm_domain has callbacks to enable the main
 966          * functional clock, interface clock and also configure the
 967          * SYSCONFIG register of omap devices. The callback will be invoked
 968          * as part of pm_runtime_get_sync.
 969          */
 970         pm_runtime_enable(dev);
 971         ret = pm_runtime_get_sync(dev);
 972         if (ret < 0) {
 973                 dev_err(dev, "pm_runtime_get_sync failed\n");
 974                 pm_runtime_put_noidle(dev);
 975                 goto err_rpm_disable;
 976         }
 977
 978         ret = sdhci_omap_set_capabilities(omap_host);
 979         if (ret) {
 980                 dev_err(dev, "failed to set system capabilities\n");
 981                 goto err_put_sync;
 982         }
 983
 984         host->mmc_host_ops.get_ro = mmc_gpio_get_ro;
 985         host->mmc_host_ops.start_signal_voltage_switch =
 986                                         sdhci_omap_start_signal_voltage_switch;
 987         host->mmc_host_ops.set_ios = sdhci_omap_set_ios;
 988         host->mmc_host_ops.card_busy = sdhci_omap_card_busy;
 989         host->mmc_host_ops.execute_tuning = sdhci_omap_execute_tuning;
 990         host->mmc_host_ops.enable_sdio_irq = sdhci_omap_enable_sdio_irq;
 991
 992         ret = sdhci_setup_host(host);
 993         if (ret)
 994                 goto err_put_sync;
 995
 996         ret = sdhci_omap_config_iodelay_pinctrl_state(omap_host);
 997         if (ret)
 998                 goto err_cleanup_host;
 999
1000         ret = __sdhci_add_host(host);
1001         if (ret)
1002                 goto err_cleanup_host;
1003
1004         return 0;
1005
1006 err_cleanup_host:
1007         sdhci_cleanup_host(host);
1008
1009 err_put_sync:
1010         pm_runtime_put_sync(dev);
1011
1012 err_rpm_disable:
1013         pm_runtime_disable(dev);
1014
1015 err_pltfm_free:
1016         sdhci_pltfm_free(pdev);
1017         return ret;
1018 }
1019
1020 static int sdhci_omap_remove(struct platform_device *pdev)
1021 {
1022         struct device *dev = &pdev->dev;
1023         struct sdhci_host *host = platform_get_drvdata(pdev);
1024
1025         sdhci_remove_host(host, true);
1026         pm_runtime_put_sync(dev);
1027         pm_runtime_disable(dev);
1028         sdhci_pltfm_free(pdev);
1029
1030         return 0;
1031 }
1032
1033 static struct platform_driver sdhci_omap_driver = {
1034         .probe = sdhci_omap_probe,
1035         .remove = sdhci_omap_remove,
1036         .driver = {
1037                    .name = "sdhci-omap",
1038                    .of_match_table = omap_sdhci_match,
1039                   },
1040 };
1041
1042 module_platform_driver(sdhci_omap_driver);
1043
1044 MODULE_DESCRIPTION("SDHCI driver for OMAP SoCs");
1045 MODULE_AUTHOR("Texas Instruments Inc.");
1046 MODULE_LICENSE("GPL v2");
1047 MODULE_ALIAS("platform:sdhci_omap");