2 * Arasan Secure Digital Host Controller Interface.
3 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
4 * Copyright (c) 2012 Wind River Systems, Inc.
5 * Copyright (C) 2013 Pengutronix e.K.
6 * Copyright (C) 2013 Xilinx Inc.
8 * Based on sdhci-of-esdhc.c
10 * Copyright (c) 2007 Freescale Semiconductor, Inc.
11 * Copyright (c) 2009 MontaVista Software, Inc.
13 * Authors: Xiaobo Xie <X.Xie@freescale.com>
14 * Anton Vorontsov <avorontsov@ru.mvista.com>
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or (at
19 * your option) any later version.
22 #include <linux/clk-provider.h>
23 #include <linux/mfd/syscon.h>
24 #include <linux/module.h>
25 #include <linux/of_device.h>
26 #include <linux/phy/phy.h>
27 #include <linux/regmap.h>
31 #include "sdhci-pltfm.h"
33 #define SDHCI_ARASAN_VENDOR_REGISTER 0x78
34 #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200
35 #define VENDOR_ENHANCED_STROBE BIT(0)
37 #define PHY_CLK_TOO_SLOW_HZ 400000
40 * On some SoCs the syscon area has a feature where the upper 16-bits of
41 * each 32-bit register act as a write mask for the lower 16-bits. This allows
42 * atomic updates of the register without locking. This macro is used on SoCs
43 * that have that feature.
45 #define HIWORD_UPDATE(val, mask, shift) \
46 ((val) << (shift) | (mask) << ((shift) + 16))
49 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
51 * @reg: Offset within the syscon of the register containing this field
52 * @width: Number of bits for this field
53 * @shift: Bit offset within @reg of this field (or -1 if not avail)
55 struct sdhci_arasan_soc_ctl_field {
62 * struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers
64 * It's up to the licensee of the Arsan IP block to make these available
65 * somewhere if needed. Presumably these will be scattered somewhere that's
66 * accessible via the syscon API.
68 * @baseclkfreq: Where to find corecfg_baseclkfreq
69 * @clockmultiplier: Where to find corecfg_clockmultiplier
70 * @hiword_update: If true, use HIWORD_UPDATE to access the syscon
72 struct sdhci_arasan_soc_ctl_map {
73 struct sdhci_arasan_soc_ctl_field baseclkfreq;
74 struct sdhci_arasan_soc_ctl_field clockmultiplier;
79 * struct sdhci_arasan_data
80 * @host: Pointer to the main SDHCI host structure.
81 * @clk_ahb: Pointer to the AHB clock
82 * @phy: Pointer to the generic phy
83 * @is_phy_on: True if the PHY is on; false if not.
84 * @sdcardclk_hw: Struct for the clock we might provide to a PHY.
85 * @sdcardclk: Pointer to normal 'struct clock' for sdcardclk_hw.
86 * @soc_ctl_base: Pointer to regmap for syscon for soc_ctl registers.
87 * @soc_ctl_map: Map to get offsets into soc_ctl registers.
89 struct sdhci_arasan_data {
90 struct sdhci_host *host;
96 struct clk_hw sdcardclk_hw;
97 struct clk *sdcardclk;
99 struct regmap *soc_ctl_base;
100 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
101 unsigned int quirks; /* Arasan deviations from spec */
103 /* Controller does not have CD wired and will not function normally without */
104 #define SDHCI_ARASAN_QUIRK_FORCE_CDTEST BIT(0)
105 /* Controller immediately reports SDHCI_CLOCK_INT_STABLE after enabling the
106 * internal clock even when the clock isn't stable */
107 #define SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE BIT(1)
110 struct sdhci_arasan_of_data {
111 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
112 const struct sdhci_pltfm_data *pdata;
115 static const struct sdhci_arasan_soc_ctl_map rk3399_soc_ctl_map = {
116 .baseclkfreq = { .reg = 0xf000, .width = 8, .shift = 8 },
117 .clockmultiplier = { .reg = 0xf02c, .width = 8, .shift = 0},
118 .hiword_update = true,
122 * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers
124 * This function allows writing to fields in sdhci_arasan_soc_ctl_map.
125 * Note that if a field is specified as not available (shift < 0) then
126 * this function will silently return an error code. It will be noisy
127 * and print errors for any other (unexpected) errors.
129 * @host: The sdhci_host
130 * @fld: The field to write to
131 * @val: The value to write
133 static int sdhci_arasan_syscon_write(struct sdhci_host *host,
134 const struct sdhci_arasan_soc_ctl_field *fld,
137 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
138 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
139 struct regmap *soc_ctl_base = sdhci_arasan->soc_ctl_base;
141 u16 width = fld->width;
142 s16 shift = fld->shift;
146 * Silently return errors for shift < 0 so caller doesn't have
147 * to check for fields which are optional. For fields that
148 * are required then caller needs to do something special
154 if (sdhci_arasan->soc_ctl_map->hiword_update)
155 ret = regmap_write(soc_ctl_base, reg,
156 HIWORD_UPDATE(val, GENMASK(width, 0),
159 ret = regmap_update_bits(soc_ctl_base, reg,
160 GENMASK(shift + width, shift),
163 /* Yell about (unexpected) regmap errors */
165 pr_warn("%s: Regmap write fail: %d\n",
166 mmc_hostname(host->mmc), ret);
171 static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock)
173 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
174 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
175 bool ctrl_phy = false;
177 if (!IS_ERR(sdhci_arasan->phy)) {
178 if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) {
180 * If PHY off, set clock to max speed and power PHY on.
182 * Although PHY docs apparently suggest power cycling
183 * when changing the clock the PHY doesn't like to be
184 * powered on while at low speeds like those used in ID
185 * mode. Even worse is powering the PHY on while the
188 * To workaround the PHY limitations, the best we can
189 * do is to power it on at a faster speed and then slam
190 * through low speeds without power cycling.
192 sdhci_set_clock(host, host->max_clk);
193 phy_power_on(sdhci_arasan->phy);
194 sdhci_arasan->is_phy_on = true;
197 * We'll now fall through to the below case with
198 * ctrl_phy = false (so we won't turn off/on). The
199 * sdhci_set_clock() will set the real clock.
201 } else if (clock > PHY_CLK_TOO_SLOW_HZ) {
203 * At higher clock speeds the PHY is fine being power
204 * cycled and docs say you _should_ power cycle when
205 * changing clock speeds.
211 if (ctrl_phy && sdhci_arasan->is_phy_on) {
212 phy_power_off(sdhci_arasan->phy);
213 sdhci_arasan->is_phy_on = false;
216 sdhci_set_clock(host, clock);
218 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE)
220 * Some controllers immediately report SDHCI_CLOCK_INT_STABLE
221 * after enabling the clock even though the clock is not
222 * stable. Trying to use a clock without waiting here results
223 * in EILSEQ while detecting some older/slower cards. The
224 * chosen delay is the maximum delay from sdhci_set_clock.
229 phy_power_on(sdhci_arasan->phy);
230 sdhci_arasan->is_phy_on = true;
234 static void sdhci_arasan_hs400_enhanced_strobe(struct mmc_host *mmc,
238 struct sdhci_host *host = mmc_priv(mmc);
240 vendor = sdhci_readl(host, SDHCI_ARASAN_VENDOR_REGISTER);
241 if (ios->enhanced_strobe)
242 vendor |= VENDOR_ENHANCED_STROBE;
244 vendor &= ~VENDOR_ENHANCED_STROBE;
246 sdhci_writel(host, vendor, SDHCI_ARASAN_VENDOR_REGISTER);
249 static void sdhci_arasan_reset(struct sdhci_host *host, u8 mask)
252 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
253 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
255 sdhci_reset(host, mask);
257 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) {
258 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
259 ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN;
260 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
264 static int sdhci_arasan_voltage_switch(struct mmc_host *mmc,
267 switch (ios->signal_voltage) {
268 case MMC_SIGNAL_VOLTAGE_180:
270 * Plese don't switch to 1V8 as arasan,5.1 doesn't
271 * actually refer to this setting to indicate the
272 * signal voltage and the state machine will be broken
273 * actually if we force to enable 1V8. That's something
274 * like broken quirk but we could work around here.
277 case MMC_SIGNAL_VOLTAGE_330:
278 case MMC_SIGNAL_VOLTAGE_120:
279 /* We don't support 3V3 and 1V2 */
286 static void sdhci_arasan_set_power(struct sdhci_host *host, unsigned char mode,
289 if (!IS_ERR(host->mmc->supply.vmmc)) {
290 struct mmc_host *mmc = host->mmc;
292 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
294 sdhci_set_power_noreg(host, mode, vdd);
297 static const struct sdhci_ops sdhci_arasan_ops = {
298 .set_clock = sdhci_arasan_set_clock,
299 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
300 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
301 .set_bus_width = sdhci_set_bus_width,
302 .reset = sdhci_arasan_reset,
303 .set_uhs_signaling = sdhci_set_uhs_signaling,
304 .set_power = sdhci_arasan_set_power,
307 static const struct sdhci_pltfm_data sdhci_arasan_pdata = {
308 .ops = &sdhci_arasan_ops,
309 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
310 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
311 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
312 SDHCI_QUIRK2_STOP_WITH_TC,
315 static struct sdhci_arasan_of_data sdhci_arasan_data = {
316 .pdata = &sdhci_arasan_pdata,
319 static u32 sdhci_arasan_cqhci_irq(struct sdhci_host *host, u32 intmask)
324 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
327 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
332 static void sdhci_arasan_dumpregs(struct mmc_host *mmc)
334 sdhci_dumpregs(mmc_priv(mmc));
337 static void sdhci_arasan_cqe_enable(struct mmc_host *mmc)
339 struct sdhci_host *host = mmc_priv(mmc);
342 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
343 while (reg & SDHCI_DATA_AVAILABLE) {
344 sdhci_readl(host, SDHCI_BUFFER);
345 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
348 sdhci_cqe_enable(mmc);
351 static const struct cqhci_host_ops sdhci_arasan_cqhci_ops = {
352 .enable = sdhci_arasan_cqe_enable,
353 .disable = sdhci_cqe_disable,
354 .dumpregs = sdhci_arasan_dumpregs,
357 static const struct sdhci_ops sdhci_arasan_cqe_ops = {
358 .set_clock = sdhci_arasan_set_clock,
359 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
360 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
361 .set_bus_width = sdhci_set_bus_width,
362 .reset = sdhci_arasan_reset,
363 .set_uhs_signaling = sdhci_set_uhs_signaling,
364 .set_power = sdhci_arasan_set_power,
365 .irq = sdhci_arasan_cqhci_irq,
368 static const struct sdhci_pltfm_data sdhci_arasan_cqe_pdata = {
369 .ops = &sdhci_arasan_cqe_ops,
370 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
371 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
372 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
375 static struct sdhci_arasan_of_data sdhci_arasan_rk3399_data = {
376 .soc_ctl_map = &rk3399_soc_ctl_map,
377 .pdata = &sdhci_arasan_cqe_pdata,
380 #ifdef CONFIG_PM_SLEEP
382 * sdhci_arasan_suspend - Suspend method for the driver
383 * @dev: Address of the device structure
384 * Returns 0 on success and error value on error
386 * Put the device in a low power state.
388 static int sdhci_arasan_suspend(struct device *dev)
390 struct sdhci_host *host = dev_get_drvdata(dev);
391 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
392 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
395 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
396 mmc_retune_needed(host->mmc);
398 if (sdhci_arasan->has_cqe) {
399 ret = cqhci_suspend(host->mmc);
404 ret = sdhci_suspend_host(host);
408 if (!IS_ERR(sdhci_arasan->phy) && sdhci_arasan->is_phy_on) {
409 ret = phy_power_off(sdhci_arasan->phy);
411 dev_err(dev, "Cannot power off phy.\n");
412 sdhci_resume_host(host);
415 sdhci_arasan->is_phy_on = false;
418 clk_disable(pltfm_host->clk);
419 clk_disable(sdhci_arasan->clk_ahb);
425 * sdhci_arasan_resume - Resume method for the driver
426 * @dev: Address of the device structure
427 * Returns 0 on success and error value on error
429 * Resume operation after suspend
431 static int sdhci_arasan_resume(struct device *dev)
433 struct sdhci_host *host = dev_get_drvdata(dev);
434 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
435 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
438 ret = clk_enable(sdhci_arasan->clk_ahb);
440 dev_err(dev, "Cannot enable AHB clock.\n");
444 ret = clk_enable(pltfm_host->clk);
446 dev_err(dev, "Cannot enable SD clock.\n");
450 if (!IS_ERR(sdhci_arasan->phy) && host->mmc->actual_clock) {
451 ret = phy_power_on(sdhci_arasan->phy);
453 dev_err(dev, "Cannot power on phy.\n");
456 sdhci_arasan->is_phy_on = true;
459 ret = sdhci_resume_host(host);
461 dev_err(dev, "Cannot resume host.\n");
465 if (sdhci_arasan->has_cqe)
466 return cqhci_resume(host->mmc);
470 #endif /* ! CONFIG_PM_SLEEP */
472 static SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops, sdhci_arasan_suspend,
473 sdhci_arasan_resume);
475 static const struct of_device_id sdhci_arasan_of_match[] = {
476 /* SoC-specific compatible strings w/ soc_ctl_map */
478 .compatible = "rockchip,rk3399-sdhci-5.1",
479 .data = &sdhci_arasan_rk3399_data,
481 /* Generic compatible below here */
483 .compatible = "arasan,sdhci-8.9a",
484 .data = &sdhci_arasan_data,
487 .compatible = "arasan,sdhci-5.1",
488 .data = &sdhci_arasan_data,
491 .compatible = "arasan,sdhci-4.9a",
492 .data = &sdhci_arasan_data,
496 MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match);
499 * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate
501 * Return the current actual rate of the SD card clock. This can be used
502 * to communicate with out PHY.
504 * @hw: Pointer to the hardware clock structure.
505 * @parent_rate The parent rate (should be rate of clk_xin).
506 * Returns the card clock rate.
508 static unsigned long sdhci_arasan_sdcardclk_recalc_rate(struct clk_hw *hw,
509 unsigned long parent_rate)
512 struct sdhci_arasan_data *sdhci_arasan =
513 container_of(hw, struct sdhci_arasan_data, sdcardclk_hw);
514 struct sdhci_host *host = sdhci_arasan->host;
516 return host->mmc->actual_clock;
519 static const struct clk_ops arasan_sdcardclk_ops = {
520 .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
524 * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier
526 * The corecfg_clockmultiplier is supposed to contain clock multiplier
527 * value of programmable clock generator.
530 * - Many existing devices don't seem to do this and work fine. To keep
531 * compatibility for old hardware where the device tree doesn't provide a
532 * register map, this function is a noop if a soc_ctl_map hasn't been provided
534 * - The value of corecfg_clockmultiplier should sync with that of corresponding
535 * value reading from sdhci_capability_register. So this function is called
536 * once at probe time and never called again.
538 * @host: The sdhci_host
540 static void sdhci_arasan_update_clockmultiplier(struct sdhci_host *host,
543 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
544 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
545 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
546 sdhci_arasan->soc_ctl_map;
548 /* Having a map is optional */
552 /* If we have a map, we expect to have a syscon */
553 if (!sdhci_arasan->soc_ctl_base) {
554 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
555 mmc_hostname(host->mmc));
559 sdhci_arasan_syscon_write(host, &soc_ctl_map->clockmultiplier, value);
563 * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq
565 * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin. This
566 * function can be used to make that happen.
569 * - Many existing devices don't seem to do this and work fine. To keep
570 * compatibility for old hardware where the device tree doesn't provide a
571 * register map, this function is a noop if a soc_ctl_map hasn't been provided
573 * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider
574 * to achieve lower clock rates. That means that this function is called once
575 * at probe time and never called again.
577 * @host: The sdhci_host
579 static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host)
581 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
582 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
583 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
584 sdhci_arasan->soc_ctl_map;
585 u32 mhz = DIV_ROUND_CLOSEST(clk_get_rate(pltfm_host->clk), 1000000);
587 /* Having a map is optional */
591 /* If we have a map, we expect to have a syscon */
592 if (!sdhci_arasan->soc_ctl_base) {
593 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
594 mmc_hostname(host->mmc));
598 sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz);
602 * sdhci_arasan_register_sdclk - Register the sdclk for a PHY to use
604 * Some PHY devices need to know what the actual card clock is. In order for
605 * them to find out, we'll provide a clock through the common clock framework
608 * Note: without seriously re-architecting SDHCI's clock code and testing on
609 * all platforms, there's no way to create a totally beautiful clock here
610 * with all clock ops implemented. Instead, we'll just create a clock that can
611 * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock
612 * framework that we're doing things behind its back. This should be sufficient
613 * to create nice clean device tree bindings and later (if needed) we can try
614 * re-architecting SDHCI if we see some benefit to it.
616 * @sdhci_arasan: Our private data structure.
617 * @clk_xin: Pointer to the functional clock
618 * @dev: Pointer to our struct device.
619 * Returns 0 on success and error value on error
621 static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan,
625 struct device_node *np = dev->of_node;
626 struct clk_init_data sdcardclk_init;
627 const char *parent_clk_name;
630 /* Providing a clock to the PHY is optional; no error if missing */
631 if (!of_find_property(np, "#clock-cells", NULL))
634 ret = of_property_read_string_index(np, "clock-output-names", 0,
635 &sdcardclk_init.name);
637 dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
641 parent_clk_name = __clk_get_name(clk_xin);
642 sdcardclk_init.parent_names = &parent_clk_name;
643 sdcardclk_init.num_parents = 1;
644 sdcardclk_init.flags = CLK_GET_RATE_NOCACHE;
645 sdcardclk_init.ops = &arasan_sdcardclk_ops;
647 sdhci_arasan->sdcardclk_hw.init = &sdcardclk_init;
648 sdhci_arasan->sdcardclk =
649 devm_clk_register(dev, &sdhci_arasan->sdcardclk_hw);
650 sdhci_arasan->sdcardclk_hw.init = NULL;
652 ret = of_clk_add_provider(np, of_clk_src_simple_get,
653 sdhci_arasan->sdcardclk);
655 dev_err(dev, "Failed to add clock provider\n");
661 * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk()
663 * Should be called any time we're exiting and sdhci_arasan_register_sdclk()
666 * @dev: Pointer to our struct device.
668 static void sdhci_arasan_unregister_sdclk(struct device *dev)
670 struct device_node *np = dev->of_node;
672 if (!of_find_property(np, "#clock-cells", NULL))
675 of_clk_del_provider(dev->of_node);
678 static int sdhci_arasan_add_host(struct sdhci_arasan_data *sdhci_arasan)
680 struct sdhci_host *host = sdhci_arasan->host;
681 struct cqhci_host *cq_host;
685 if (!sdhci_arasan->has_cqe)
686 return sdhci_add_host(host);
688 ret = sdhci_setup_host(host);
692 cq_host = devm_kzalloc(host->mmc->parent,
693 sizeof(*cq_host), GFP_KERNEL);
699 cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR;
700 cq_host->ops = &sdhci_arasan_cqhci_ops;
702 dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
704 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
706 ret = cqhci_init(cq_host, host->mmc, dma64);
710 ret = __sdhci_add_host(host);
717 sdhci_cleanup_host(host);
721 static int sdhci_arasan_probe(struct platform_device *pdev)
724 const struct of_device_id *match;
725 struct device_node *node;
727 struct sdhci_host *host;
728 struct sdhci_pltfm_host *pltfm_host;
729 struct sdhci_arasan_data *sdhci_arasan;
730 struct device_node *np = pdev->dev.of_node;
731 const struct sdhci_arasan_of_data *data;
733 match = of_match_node(sdhci_arasan_of_match, pdev->dev.of_node);
735 host = sdhci_pltfm_init(pdev, data->pdata, sizeof(*sdhci_arasan));
738 return PTR_ERR(host);
740 pltfm_host = sdhci_priv(host);
741 sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
742 sdhci_arasan->host = host;
744 sdhci_arasan->soc_ctl_map = data->soc_ctl_map;
746 node = of_parse_phandle(pdev->dev.of_node, "arasan,soc-ctl-syscon", 0);
748 sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node);
751 if (IS_ERR(sdhci_arasan->soc_ctl_base)) {
752 ret = PTR_ERR(sdhci_arasan->soc_ctl_base);
753 if (ret != -EPROBE_DEFER)
754 dev_err(&pdev->dev, "Can't get syscon: %d\n",
760 sdhci_arasan->clk_ahb = devm_clk_get(&pdev->dev, "clk_ahb");
761 if (IS_ERR(sdhci_arasan->clk_ahb)) {
762 dev_err(&pdev->dev, "clk_ahb clock not found.\n");
763 ret = PTR_ERR(sdhci_arasan->clk_ahb);
767 clk_xin = devm_clk_get(&pdev->dev, "clk_xin");
768 if (IS_ERR(clk_xin)) {
769 dev_err(&pdev->dev, "clk_xin clock not found.\n");
770 ret = PTR_ERR(clk_xin);
774 ret = clk_prepare_enable(sdhci_arasan->clk_ahb);
776 dev_err(&pdev->dev, "Unable to enable AHB clock.\n");
780 ret = clk_prepare_enable(clk_xin);
782 dev_err(&pdev->dev, "Unable to enable SD clock.\n");
786 sdhci_get_of_property(pdev);
788 if (of_property_read_bool(np, "xlnx,fails-without-test-cd"))
789 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST;
791 if (of_property_read_bool(np, "xlnx,int-clock-stable-broken"))
792 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE;
794 pltfm_host->clk = clk_xin;
796 if (of_device_is_compatible(pdev->dev.of_node,
797 "rockchip,rk3399-sdhci-5.1"))
798 sdhci_arasan_update_clockmultiplier(host, 0x0);
800 sdhci_arasan_update_baseclkfreq(host);
802 ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, &pdev->dev);
804 goto clk_disable_all;
806 ret = mmc_of_parse(host->mmc);
808 if (ret != -EPROBE_DEFER)
809 dev_err(&pdev->dev, "parsing dt failed (%d)\n", ret);
813 sdhci_arasan->phy = ERR_PTR(-ENODEV);
814 if (of_device_is_compatible(pdev->dev.of_node,
815 "arasan,sdhci-5.1")) {
816 sdhci_arasan->phy = devm_phy_get(&pdev->dev,
818 if (IS_ERR(sdhci_arasan->phy)) {
819 ret = PTR_ERR(sdhci_arasan->phy);
820 dev_err(&pdev->dev, "No phy for arasan,sdhci-5.1.\n");
824 ret = phy_init(sdhci_arasan->phy);
826 dev_err(&pdev->dev, "phy_init err.\n");
830 host->mmc_host_ops.hs400_enhanced_strobe =
831 sdhci_arasan_hs400_enhanced_strobe;
832 host->mmc_host_ops.start_signal_voltage_switch =
833 sdhci_arasan_voltage_switch;
834 sdhci_arasan->has_cqe = true;
835 host->mmc->caps2 |= MMC_CAP2_CQE;
837 if (!of_property_read_bool(np, "disable-cqe-dcmd"))
838 host->mmc->caps2 |= MMC_CAP2_CQE_DCMD;
841 ret = sdhci_arasan_add_host(sdhci_arasan);
848 if (!IS_ERR(sdhci_arasan->phy))
849 phy_exit(sdhci_arasan->phy);
851 sdhci_arasan_unregister_sdclk(&pdev->dev);
853 clk_disable_unprepare(clk_xin);
855 clk_disable_unprepare(sdhci_arasan->clk_ahb);
857 sdhci_pltfm_free(pdev);
861 static int sdhci_arasan_remove(struct platform_device *pdev)
864 struct sdhci_host *host = platform_get_drvdata(pdev);
865 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
866 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
867 struct clk *clk_ahb = sdhci_arasan->clk_ahb;
869 if (!IS_ERR(sdhci_arasan->phy)) {
870 if (sdhci_arasan->is_phy_on)
871 phy_power_off(sdhci_arasan->phy);
872 phy_exit(sdhci_arasan->phy);
875 sdhci_arasan_unregister_sdclk(&pdev->dev);
877 ret = sdhci_pltfm_unregister(pdev);
879 clk_disable_unprepare(clk_ahb);
884 static struct platform_driver sdhci_arasan_driver = {
886 .name = "sdhci-arasan",
887 .of_match_table = sdhci_arasan_of_match,
888 .pm = &sdhci_arasan_dev_pm_ops,
890 .probe = sdhci_arasan_probe,
891 .remove = sdhci_arasan_remove,
894 module_platform_driver(sdhci_arasan_driver);
896 MODULE_DESCRIPTION("Driver for the Arasan SDHCI Controller");
897 MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>");
898 MODULE_LICENSE("GPL");