drivers/mmc/host/sdhci-msm.c

   1 /*
   2  * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
   3  *
   4  * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 and
   8  * only version 2 as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/of_device.h>
  19 #include <linux/delay.h>
  20 #include <linux/mmc/mmc.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/slab.h>
  23 #include <linux/iopoll.h>
  24 #include <linux/regulator/consumer.h>
  25
  26 #include "sdhci-pltfm.h"
  27
  28 #define CORE_MCI_VERSION                0x50
  29 #define CORE_VERSION_MAJOR_SHIFT        28
  30 #define CORE_VERSION_MAJOR_MASK         (0xf << CORE_VERSION_MAJOR_SHIFT)
  31 #define CORE_VERSION_MINOR_MASK         0xff
  32
  33 #define CORE_MCI_GENERICS               0x70
  34 #define SWITCHABLE_SIGNALING_VOLTAGE    BIT(29)
  35
  36 #define CORE_HC_MODE            0x78
  37 #define HC_MODE_EN              0x1
  38 #define CORE_POWER              0x0
  39 #define CORE_SW_RST             BIT(7)
  40 #define FF_CLK_SW_RST_DIS       BIT(13)
  41
  42 #define CORE_PWRCTL_STATUS      0xdc
  43 #define CORE_PWRCTL_MASK        0xe0
  44 #define CORE_PWRCTL_CLEAR       0xe4
  45 #define CORE_PWRCTL_CTL         0xe8
  46 #define CORE_PWRCTL_BUS_OFF     BIT(0)
  47 #define CORE_PWRCTL_BUS_ON      BIT(1)
  48 #define CORE_PWRCTL_IO_LOW      BIT(2)
  49 #define CORE_PWRCTL_IO_HIGH     BIT(3)
  50 #define CORE_PWRCTL_BUS_SUCCESS BIT(0)
  51 #define CORE_PWRCTL_IO_SUCCESS  BIT(2)
  52 #define REQ_BUS_OFF             BIT(0)
  53 #define REQ_BUS_ON              BIT(1)
  54 #define REQ_IO_LOW              BIT(2)
  55 #define REQ_IO_HIGH             BIT(3)
  56 #define INT_MASK                0xf
  57 #define MAX_PHASES              16
  58 #define CORE_DLL_LOCK           BIT(7)
  59 #define CORE_DDR_DLL_LOCK       BIT(11)
  60 #define CORE_DLL_EN             BIT(16)
  61 #define CORE_CDR_EN             BIT(17)
  62 #define CORE_CK_OUT_EN          BIT(18)
  63 #define CORE_CDR_EXT_EN         BIT(19)
  64 #define CORE_DLL_PDN            BIT(29)
  65 #define CORE_DLL_RST            BIT(30)
  66 #define CORE_DLL_CONFIG         0x100
  67 #define CORE_CMD_DAT_TRACK_SEL  BIT(0)
  68 #define CORE_DLL_STATUS         0x108
  69
  70 #define CORE_DLL_CONFIG_2       0x1b4
  71 #define CORE_DDR_CAL_EN         BIT(0)
  72 #define CORE_FLL_CYCLE_CNT      BIT(18)
  73 #define CORE_DLL_CLOCK_DISABLE  BIT(21)
  74
  75 #define CORE_VENDOR_SPEC        0x10c
  76 #define CORE_VENDOR_SPEC_POR_VAL        0xa1c
  77 #define CORE_CLK_PWRSAVE        BIT(1)
  78 #define CORE_HC_MCLK_SEL_DFLT   (2 << 8)
  79 #define CORE_HC_MCLK_SEL_HS400  (3 << 8)
  80 #define CORE_HC_MCLK_SEL_MASK   (3 << 8)
  81 #define CORE_HC_SELECT_IN_EN    BIT(18)
  82 #define CORE_HC_SELECT_IN_HS400 (6 << 19)
  83 #define CORE_HC_SELECT_IN_MASK  (7 << 19)
  84
  85 #define CORE_3_0V_SUPPORT       (1 << 25)
  86 #define CORE_1_8V_SUPPORT       (1 << 26)
  87
  88 #define CORE_CSR_CDC_CTLR_CFG0          0x130
  89 #define CORE_SW_TRIG_FULL_CALIB         BIT(16)
  90 #define CORE_HW_AUTOCAL_ENA             BIT(17)
  91
  92 #define CORE_CSR_CDC_CTLR_CFG1          0x134
  93 #define CORE_CSR_CDC_CAL_TIMER_CFG0     0x138
  94 #define CORE_TIMER_ENA                  BIT(16)
  95
  96 #define CORE_CSR_CDC_CAL_TIMER_CFG1     0x13C
  97 #define CORE_CSR_CDC_REFCOUNT_CFG       0x140
  98 #define CORE_CSR_CDC_COARSE_CAL_CFG     0x144
  99 #define CORE_CDC_OFFSET_CFG             0x14C
 100 #define CORE_CSR_CDC_DELAY_CFG          0x150
 101 #define CORE_CDC_SLAVE_DDA_CFG          0x160
 102 #define CORE_CSR_CDC_STATUS0            0x164
 103 #define CORE_CALIBRATION_DONE           BIT(0)
 104
 105 #define CORE_CDC_ERROR_CODE_MASK        0x7000000
 106
 107 #define CORE_CSR_CDC_GEN_CFG            0x178
 108 #define CORE_CDC_SWITCH_BYPASS_OFF      BIT(0)
 109 #define CORE_CDC_SWITCH_RC_EN           BIT(1)
 110
 111 #define CORE_DDR_200_CFG                0x184
 112 #define CORE_CDC_T4_DLY_SEL             BIT(0)
 113 #define CORE_CMDIN_RCLK_EN              BIT(1)
 114 #define CORE_START_CDC_TRAFFIC          BIT(6)
 115 #define CORE_VENDOR_SPEC3       0x1b0
 116 #define CORE_PWRSAVE_DLL        BIT(3)
 117
 118 #define CORE_DDR_CONFIG         0x1b8
 119 #define DDR_CONFIG_POR_VAL      0x80040853
 120
 121 #define CORE_VENDOR_SPEC_CAPABILITIES0  0x11c
 122
 123 #define INVALID_TUNING_PHASE    -1
 124 #define SDHCI_MSM_MIN_CLOCK     400000
 125 #define CORE_FREQ_100MHZ        (100 * 1000 * 1000)
 126
 127 #define CDR_SELEXT_SHIFT        20
 128 #define CDR_SELEXT_MASK         (0xf << CDR_SELEXT_SHIFT)
 129 #define CMUX_SHIFT_PHASE_SHIFT  24
 130 #define CMUX_SHIFT_PHASE_MASK   (7 << CMUX_SHIFT_PHASE_SHIFT)
 131
 132 #define MSM_MMC_AUTOSUSPEND_DELAY_MS    50
 133
 134 /* Timeout value to avoid infinite waiting for pwr_irq */
 135 #define MSM_PWR_IRQ_TIMEOUT_MS 5000
 136
 137 struct sdhci_msm_host {
 138         struct platform_device *pdev;
 139         void __iomem *core_mem; /* MSM SDCC mapped address */
 140         int pwr_irq;            /* power irq */
 141         struct clk *bus_clk;    /* SDHC bus voter clock */
 142         struct clk *xo_clk;     /* TCXO clk needed for FLL feature of cm_dll*/
 143         struct clk_bulk_data bulk_clks[4]; /* core, iface, cal, sleep clocks */
 144         unsigned long clk_rate;
 145         struct mmc_host *mmc;
 146         bool use_14lpp_dll_reset;
 147         bool tuning_done;
 148         bool calibration_done;
 149         u8 saved_tuning_phase;
 150         bool use_cdclp533;
 151         u32 curr_pwr_state;
 152         u32 curr_io_level;
 153         wait_queue_head_t pwr_irq_wait;
 154         bool pwr_irq_flag;
 155         u32 caps_0;
 156 };
 157
 158 static unsigned int msm_get_clock_rate_for_bus_mode(struct sdhci_host *host,
 159                                                     unsigned int clock)
 160 {
 161         struct mmc_ios ios = host->mmc->ios;
 162         /*
 163          * The SDHC requires internal clock frequency to be double the
 164          * actual clock that will be set for DDR mode. The controller
 165          * uses the faster clock(100/400MHz) for some of its parts and
 166          * send the actual required clock (50/200MHz) to the card.
 167          */
 168         if (ios.timing == MMC_TIMING_UHS_DDR50 ||
 169             ios.timing == MMC_TIMING_MMC_DDR52 ||
 170             ios.timing == MMC_TIMING_MMC_HS400 ||
 171             host->flags & SDHCI_HS400_TUNING)
 172                 clock *= 2;
 173         return clock;
 174 }
 175
 176 static void msm_set_clock_rate_for_bus_mode(struct sdhci_host *host,
 177                                             unsigned int clock)
 178 {
 179         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 180         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 181         struct mmc_ios curr_ios = host->mmc->ios;
 182         struct clk *core_clk = msm_host->bulk_clks[0].clk;
 183         int rc;
 184
 185         clock = msm_get_clock_rate_for_bus_mode(host, clock);
 186         rc = clk_set_rate(core_clk, clock);
 187         if (rc) {
 188                 pr_err("%s: Failed to set clock at rate %u at timing %d\n",
 189                        mmc_hostname(host->mmc), clock,
 190                        curr_ios.timing);
 191                 return;
 192         }
 193         msm_host->clk_rate = clock;
 194         pr_debug("%s: Setting clock at rate %lu at timing %d\n",
 195                  mmc_hostname(host->mmc), clk_get_rate(core_clk),
 196                  curr_ios.timing);
 197 }
 198
 199 /* Platform specific tuning */
 200 static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, u8 poll)
 201 {
 202         u32 wait_cnt = 50;
 203         u8 ck_out_en;
 204         struct mmc_host *mmc = host->mmc;
 205
 206         /* Poll for CK_OUT_EN bit.  max. poll time = 50us */
 207         ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) &
 208                         CORE_CK_OUT_EN);
 209
 210         while (ck_out_en != poll) {
 211                 if (--wait_cnt == 0) {
 212                         dev_err(mmc_dev(mmc), "%s: CK_OUT_EN bit is not %d\n",
 213                                mmc_hostname(mmc), poll);
 214                         return -ETIMEDOUT;
 215                 }
 216                 udelay(1);
 217
 218                 ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) &
 219                                 CORE_CK_OUT_EN);
 220         }
 221
 222         return 0;
 223 }
 224
 225 static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase)
 226 {
 227         int rc;
 228         static const u8 grey_coded_phase_table[] = {
 229                 0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4,
 230                 0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8
 231         };
 232         unsigned long flags;
 233         u32 config;
 234         struct mmc_host *mmc = host->mmc;
 235
 236         if (phase > 0xf)
 237                 return -EINVAL;
 238
 239         spin_lock_irqsave(&host->lock, flags);
 240
 241         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 242         config &= ~(CORE_CDR_EN | CORE_CK_OUT_EN);
 243         config |= (CORE_CDR_EXT_EN | CORE_DLL_EN);
 244         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 245
 246         /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */
 247         rc = msm_dll_poll_ck_out_en(host, 0);
 248         if (rc)
 249                 goto err_out;
 250
 251         /*
 252          * Write the selected DLL clock output phase (0 ... 15)
 253          * to CDR_SELEXT bit field of DLL_CONFIG register.
 254          */
 255         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 256         config &= ~CDR_SELEXT_MASK;
 257         config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT;
 258         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 259
 260         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 261         config |= CORE_CK_OUT_EN;
 262         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 263
 264         /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */
 265         rc = msm_dll_poll_ck_out_en(host, 1);
 266         if (rc)
 267                 goto err_out;
 268
 269         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 270         config |= CORE_CDR_EN;
 271         config &= ~CORE_CDR_EXT_EN;
 272         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 273         goto out;
 274
 275 err_out:
 276         dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n",
 277                mmc_hostname(mmc), phase);
 278 out:
 279         spin_unlock_irqrestore(&host->lock, flags);
 280         return rc;
 281 }
 282
 283 /*
 284  * Find out the greatest range of consecuitive selected
 285  * DLL clock output phases that can be used as sampling
 286  * setting for SD3.0 UHS-I card read operation (in SDR104
 287  * timing mode) or for eMMC4.5 card read operation (in
 288  * HS400/HS200 timing mode).
 289  * Select the 3/4 of the range and configure the DLL with the
 290  * selected DLL clock output phase.
 291  */
 292
 293 static int msm_find_most_appropriate_phase(struct sdhci_host *host,
 294                                            u8 *phase_table, u8 total_phases)
 295 {
 296         int ret;
 297         u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} };
 298         u8 phases_per_row[MAX_PHASES] = { 0 };
 299         int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0;
 300         int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0;
 301         bool phase_0_found = false, phase_15_found = false;
 302         struct mmc_host *mmc = host->mmc;
 303
 304         if (!total_phases || (total_phases > MAX_PHASES)) {
 305                 dev_err(mmc_dev(mmc), "%s: Invalid argument: total_phases=%d\n",
 306                        mmc_hostname(mmc), total_phases);
 307                 return -EINVAL;
 308         }
 309
 310         for (cnt = 0; cnt < total_phases; cnt++) {
 311                 ranges[row_index][col_index] = phase_table[cnt];
 312                 phases_per_row[row_index] += 1;
 313                 col_index++;
 314
 315                 if ((cnt + 1) == total_phases) {
 316                         continue;
 317                 /* check if next phase in phase_table is consecutive or not */
 318                 } else if ((phase_table[cnt] + 1) != phase_table[cnt + 1]) {
 319                         row_index++;
 320                         col_index = 0;
 321                 }
 322         }
 323
 324         if (row_index >= MAX_PHASES)
 325                 return -EINVAL;
 326
 327         /* Check if phase-0 is present in first valid window? */
 328         if (!ranges[0][0]) {
 329                 phase_0_found = true;
 330                 phase_0_raw_index = 0;
 331                 /* Check if cycle exist between 2 valid windows */
 332                 for (cnt = 1; cnt <= row_index; cnt++) {
 333                         if (phases_per_row[cnt]) {
 334                                 for (i = 0; i < phases_per_row[cnt]; i++) {
 335                                         if (ranges[cnt][i] == 15) {
 336                                                 phase_15_found = true;
 337                                                 phase_15_raw_index = cnt;
 338                                                 break;
 339                                         }
 340                                 }
 341                         }
 342                 }
 343         }
 344
 345         /* If 2 valid windows form cycle then merge them as single window */
 346         if (phase_0_found && phase_15_found) {
 347                 /* number of phases in raw where phase 0 is present */
 348                 u8 phases_0 = phases_per_row[phase_0_raw_index];
 349                 /* number of phases in raw where phase 15 is present */
 350                 u8 phases_15 = phases_per_row[phase_15_raw_index];
 351
 352                 if (phases_0 + phases_15 >= MAX_PHASES)
 353                         /*
 354                          * If there are more than 1 phase windows then total
 355                          * number of phases in both the windows should not be
 356                          * more than or equal to MAX_PHASES.
 357                          */
 358                         return -EINVAL;
 359
 360                 /* Merge 2 cyclic windows */
 361                 i = phases_15;
 362                 for (cnt = 0; cnt < phases_0; cnt++) {
 363                         ranges[phase_15_raw_index][i] =
 364                             ranges[phase_0_raw_index][cnt];
 365                         if (++i >= MAX_PHASES)
 366                                 break;
 367                 }
 368
 369                 phases_per_row[phase_0_raw_index] = 0;
 370                 phases_per_row[phase_15_raw_index] = phases_15 + phases_0;
 371         }
 372
 373         for (cnt = 0; cnt <= row_index; cnt++) {
 374                 if (phases_per_row[cnt] > curr_max) {
 375                         curr_max = phases_per_row[cnt];
 376                         selected_row_index = cnt;
 377                 }
 378         }
 379
 380         i = (curr_max * 3) / 4;
 381         if (i)
 382                 i--;
 383
 384         ret = ranges[selected_row_index][i];
 385
 386         if (ret >= MAX_PHASES) {
 387                 ret = -EINVAL;
 388                 dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n",
 389                        mmc_hostname(mmc), ret);
 390         }
 391
 392         return ret;
 393 }
 394
 395 static inline void msm_cm_dll_set_freq(struct sdhci_host *host)
 396 {
 397         u32 mclk_freq = 0, config;
 398
 399         /* Program the MCLK value to MCLK_FREQ bit field */
 400         if (host->clock <= 112000000)
 401                 mclk_freq = 0;
 402         else if (host->clock <= 125000000)
 403                 mclk_freq = 1;
 404         else if (host->clock <= 137000000)
 405                 mclk_freq = 2;
 406         else if (host->clock <= 150000000)
 407                 mclk_freq = 3;
 408         else if (host->clock <= 162000000)
 409                 mclk_freq = 4;
 410         else if (host->clock <= 175000000)
 411                 mclk_freq = 5;
 412         else if (host->clock <= 187000000)
 413                 mclk_freq = 6;
 414         else if (host->clock <= 200000000)
 415                 mclk_freq = 7;
 416
 417         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 418         config &= ~CMUX_SHIFT_PHASE_MASK;
 419         config |= mclk_freq << CMUX_SHIFT_PHASE_SHIFT;
 420         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 421 }
 422
 423 /* Initialize the DLL (Programmable Delay Line) */
 424 static int msm_init_cm_dll(struct sdhci_host *host)
 425 {
 426         struct mmc_host *mmc = host->mmc;
 427         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 428         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 429         int wait_cnt = 50;
 430         unsigned long flags;
 431         u32 config;
 432
 433         spin_lock_irqsave(&host->lock, flags);
 434
 435         /*
 436          * Make sure that clock is always enabled when DLL
 437          * tuning is in progress. Keeping PWRSAVE ON may
 438          * turn off the clock.
 439          */
 440         config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
 441         config &= ~CORE_CLK_PWRSAVE;
 442         writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
 443
 444         if (msm_host->use_14lpp_dll_reset) {
 445                 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 446                 config &= ~CORE_CK_OUT_EN;
 447                 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 448
 449                 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
 450                 config |= CORE_DLL_CLOCK_DISABLE;
 451                 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2);
 452         }
 453
 454         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 455         config |= CORE_DLL_RST;
 456         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 457
 458         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 459         config |= CORE_DLL_PDN;
 460         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 461         msm_cm_dll_set_freq(host);
 462
 463         if (msm_host->use_14lpp_dll_reset &&
 464             !IS_ERR_OR_NULL(msm_host->xo_clk)) {
 465                 u32 mclk_freq = 0;
 466
 467                 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
 468                 config &= CORE_FLL_CYCLE_CNT;
 469                 if (config)
 470                         mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 8),
 471                                         clk_get_rate(msm_host->xo_clk));
 472                 else
 473                         mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 4),
 474                                         clk_get_rate(msm_host->xo_clk));
 475
 476                 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
 477                 config &= ~(0xFF << 10);
 478                 config |= mclk_freq << 10;
 479
 480                 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2);
 481                 /* wait for 5us before enabling DLL clock */
 482                 udelay(5);
 483         }
 484
 485         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 486         config &= ~CORE_DLL_RST;
 487         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 488
 489         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 490         config &= ~CORE_DLL_PDN;
 491         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 492
 493         if (msm_host->use_14lpp_dll_reset) {
 494                 msm_cm_dll_set_freq(host);
 495                 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
 496                 config &= ~CORE_DLL_CLOCK_DISABLE;
 497                 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2);
 498         }
 499
 500         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 501         config |= CORE_DLL_EN;
 502         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 503
 504         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 505         config |= CORE_CK_OUT_EN;
 506         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 507
 508         /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */
 509         while (!(readl_relaxed(host->ioaddr + CORE_DLL_STATUS) &
 510                  CORE_DLL_LOCK)) {
 511                 /* max. wait for 50us sec for LOCK bit to be set */
 512                 if (--wait_cnt == 0) {
 513                         dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n",
 514                                mmc_hostname(mmc));
 515                         spin_unlock_irqrestore(&host->lock, flags);
 516                         return -ETIMEDOUT;
 517                 }
 518                 udelay(1);
 519         }
 520
 521         spin_unlock_irqrestore(&host->lock, flags);
 522         return 0;
 523 }
 524
 525 static void msm_hc_select_default(struct sdhci_host *host)
 526 {
 527         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 528         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 529         u32 config;
 530
 531         if (!msm_host->use_cdclp533) {
 532                 config = readl_relaxed(host->ioaddr +
 533                                 CORE_VENDOR_SPEC3);
 534                 config &= ~CORE_PWRSAVE_DLL;
 535                 writel_relaxed(config, host->ioaddr +
 536                                 CORE_VENDOR_SPEC3);
 537         }
 538
 539         config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
 540         config &= ~CORE_HC_MCLK_SEL_MASK;
 541         config |= CORE_HC_MCLK_SEL_DFLT;
 542         writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
 543
 544         /*
 545          * Disable HC_SELECT_IN to be able to use the UHS mode select
 546          * configuration from Host Control2 register for all other
 547          * modes.
 548          * Write 0 to HC_SELECT_IN and HC_SELECT_IN_EN field
 549          * in VENDOR_SPEC_FUNC
 550          */
 551         config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
 552         config &= ~CORE_HC_SELECT_IN_EN;
 553         config &= ~CORE_HC_SELECT_IN_MASK;
 554         writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
 555
 556         /*
 557          * Make sure above writes impacting free running MCLK are completed
 558          * before changing the clk_rate at GCC.
 559          */
 560         wmb();
 561 }
 562
 563 static void msm_hc_select_hs400(struct sdhci_host *host)
 564 {
 565         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 566         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 567         struct mmc_ios ios = host->mmc->ios;
 568         u32 config, dll_lock;
 569         int rc;
 570
 571         /* Select the divided clock (free running MCLK/2) */
 572         config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
 573         config &= ~CORE_HC_MCLK_SEL_MASK;
 574         config |= CORE_HC_MCLK_SEL_HS400;
 575
 576         writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
 577         /*
 578          * Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC
 579          * register
 580          */
 581         if ((msm_host->tuning_done || ios.enhanced_strobe) &&
 582             !msm_host->calibration_done) {
 583                 config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
 584                 config |= CORE_HC_SELECT_IN_HS400;
 585                 config |= CORE_HC_SELECT_IN_EN;
 586                 writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
 587         }
 588         if (!msm_host->clk_rate && !msm_host->use_cdclp533) {
 589                 /*
 590                  * Poll on DLL_LOCK or DDR_DLL_LOCK bits in
 591                  * CORE_DLL_STATUS to be set.  This should get set
 592                  * within 15 us at 200 MHz.
 593                  */
 594                 rc = readl_relaxed_poll_timeout(host->ioaddr +
 595                                                 CORE_DLL_STATUS,
 596                                                 dll_lock,
 597                                                 (dll_lock &
 598                                                 (CORE_DLL_LOCK |
 599                                                 CORE_DDR_DLL_LOCK)), 10,
 600                                                 1000);
 601                 if (rc == -ETIMEDOUT)
 602                         pr_err("%s: Unable to get DLL_LOCK/DDR_DLL_LOCK, dll_status: 0x%08x\n",
 603                                mmc_hostname(host->mmc), dll_lock);
 604         }
 605         /*
 606          * Make sure above writes impacting free running MCLK are completed
 607          * before changing the clk_rate at GCC.
 608          */
 609         wmb();
 610 }
 611
 612 /*
 613  * sdhci_msm_hc_select_mode :- In general all timing modes are
 614  * controlled via UHS mode select in Host Control2 register.
 615  * eMMC specific HS200/HS400 doesn't have their respective modes
 616  * defined here, hence we use these values.
 617  *
 618  * HS200 - SDR104 (Since they both are equivalent in functionality)
 619  * HS400 - This involves multiple configurations
 620  *              Initially SDR104 - when tuning is required as HS200
 621  *              Then when switching to DDR @ 400MHz (HS400) we use
 622  *              the vendor specific HC_SELECT_IN to control the mode.
 623  *
 624  * In addition to controlling the modes we also need to select the
 625  * correct input clock for DLL depending on the mode.
 626  *
 627  * HS400 - divided clock (free running MCLK/2)
 628  * All other modes - default (free running MCLK)
 629  */
 630 static void sdhci_msm_hc_select_mode(struct sdhci_host *host)
 631 {
 632         struct mmc_ios ios = host->mmc->ios;
 633
 634         if (ios.timing == MMC_TIMING_MMC_HS400 ||
 635             host->flags & SDHCI_HS400_TUNING)
 636                 msm_hc_select_hs400(host);
 637         else
 638                 msm_hc_select_default(host);
 639 }
 640
 641 static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host)
 642 {
 643         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 644         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 645         u32 config, calib_done;
 646         int ret;
 647
 648         pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
 649
 650         /*
 651          * Retuning in HS400 (DDR mode) will fail, just reset the
 652          * tuning block and restore the saved tuning phase.
 653          */
 654         ret = msm_init_cm_dll(host);
 655         if (ret)
 656                 goto out;
 657
 658         /* Set the selected phase in delay line hw block */
 659         ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
 660         if (ret)
 661                 goto out;
 662
 663         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 664         config |= CORE_CMD_DAT_TRACK_SEL;
 665         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 666
 667         config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
 668         config &= ~CORE_CDC_T4_DLY_SEL;
 669         writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
 670
 671         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
 672         config &= ~CORE_CDC_SWITCH_BYPASS_OFF;
 673         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
 674
 675         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
 676         config |= CORE_CDC_SWITCH_RC_EN;
 677         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
 678
 679         config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
 680         config &= ~CORE_START_CDC_TRAFFIC;
 681         writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
 682
 683         /* Perform CDC Register Initialization Sequence */
 684
 685         writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 686         writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1);
 687         writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
 688         writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1);
 689         writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG);
 690         writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG);
 691         writel_relaxed(0x4E2, host->ioaddr + CORE_CSR_CDC_DELAY_CFG);
 692         writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG);
 693         writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG);
 694
 695         /* CDC HW Calibration */
 696
 697         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 698         config |= CORE_SW_TRIG_FULL_CALIB;
 699         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 700
 701         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 702         config &= ~CORE_SW_TRIG_FULL_CALIB;
 703         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 704
 705         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 706         config |= CORE_HW_AUTOCAL_ENA;
 707         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 708
 709         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
 710         config |= CORE_TIMER_ENA;
 711         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
 712
 713         ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_CSR_CDC_STATUS0,
 714                                          calib_done,
 715                                          (calib_done & CORE_CALIBRATION_DONE),
 716                                          1, 50);
 717
 718         if (ret == -ETIMEDOUT) {
 719                 pr_err("%s: %s: CDC calibration was not completed\n",
 720                        mmc_hostname(host->mmc), __func__);
 721                 goto out;
 722         }
 723
 724         ret = readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0)
 725                         & CORE_CDC_ERROR_CODE_MASK;
 726         if (ret) {
 727                 pr_err("%s: %s: CDC error code %d\n",
 728                        mmc_hostname(host->mmc), __func__, ret);
 729                 ret = -EINVAL;
 730                 goto out;
 731         }
 732
 733         config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
 734         config |= CORE_START_CDC_TRAFFIC;
 735         writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
 736 out:
 737         pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
 738                  __func__, ret);
 739         return ret;
 740 }
 741
 742 static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host)
 743 {
 744         struct mmc_host *mmc = host->mmc;
 745         u32 dll_status, config;
 746         int ret;
 747
 748         pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
 749
 750         /*
 751          * Currently the CORE_DDR_CONFIG register defaults to desired
 752          * configuration on reset. Currently reprogramming the power on
 753          * reset (POR) value in case it might have been modified by
 754          * bootloaders. In the future, if this changes, then the desired
 755          * values will need to be programmed appropriately.
 756          */
 757         writel_relaxed(DDR_CONFIG_POR_VAL, host->ioaddr + CORE_DDR_CONFIG);
 758
 759         if (mmc->ios.enhanced_strobe) {
 760                 config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
 761                 config |= CORE_CMDIN_RCLK_EN;
 762                 writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
 763         }
 764
 765         config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
 766         config |= CORE_DDR_CAL_EN;
 767         writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2);
 768
 769         ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_DLL_STATUS,
 770                                          dll_status,
 771                                          (dll_status & CORE_DDR_DLL_LOCK),
 772                                          10, 1000);
 773
 774         if (ret == -ETIMEDOUT) {
 775                 pr_err("%s: %s: CM_DLL_SDC4 calibration was not completed\n",
 776                        mmc_hostname(host->mmc), __func__);
 777                 goto out;
 778         }
 779
 780         config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC3);
 781         config |= CORE_PWRSAVE_DLL;
 782         writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC3);
 783
 784         /*
 785          * Drain writebuffer to ensure above DLL calibration
 786          * and PWRSAVE DLL is enabled.
 787          */
 788         wmb();
 789 out:
 790         pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
 791                  __func__, ret);
 792         return ret;
 793 }
 794
 795 static int sdhci_msm_hs400_dll_calibration(struct sdhci_host *host)
 796 {
 797         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 798         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 799         struct mmc_host *mmc = host->mmc;
 800         int ret;
 801         u32 config;
 802
 803         pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
 804
 805         /*
 806          * Retuning in HS400 (DDR mode) will fail, just reset the
 807          * tuning block and restore the saved tuning phase.
 808          */
 809         ret = msm_init_cm_dll(host);
 810         if (ret)
 811                 goto out;
 812
 813         if (!mmc->ios.enhanced_strobe) {
 814                 /* Set the selected phase in delay line hw block */
 815                 ret = msm_config_cm_dll_phase(host,
 816                                               msm_host->saved_tuning_phase);
 817                 if (ret)
 818                         goto out;
 819                 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 820                 config |= CORE_CMD_DAT_TRACK_SEL;
 821                 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 822         }
 823
 824         if (msm_host->use_cdclp533)
 825                 ret = sdhci_msm_cdclp533_calibration(host);
 826         else
 827                 ret = sdhci_msm_cm_dll_sdc4_calibration(host);
 828 out:
 829         pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
 830                  __func__, ret);
 831         return ret;
 832 }
 833
 834 static int sdhci_msm_execute_tuning(struct mmc_host *mmc, u32 opcode)
 835 {
 836         struct sdhci_host *host = mmc_priv(mmc);
 837         int tuning_seq_cnt = 3;
 838         u8 phase, tuned_phases[16], tuned_phase_cnt = 0;
 839         int rc;
 840         struct mmc_ios ios = host->mmc->ios;
 841         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 842         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 843
 844         /*
 845          * Tuning is required for SDR104, HS200 and HS400 cards and
 846          * if clock frequency is greater than 100MHz in these modes.
 847          */
 848         if (host->clock <= CORE_FREQ_100MHZ ||
 849             !(ios.timing == MMC_TIMING_MMC_HS400 ||
 850             ios.timing == MMC_TIMING_MMC_HS200 ||
 851             ios.timing == MMC_TIMING_UHS_SDR104))
 852                 return 0;
 853
 854         /*
 855          * For HS400 tuning in HS200 timing requires:
 856          * - select MCLK/2 in VENDOR_SPEC
 857          * - program MCLK to 400MHz (or nearest supported) in GCC
 858          */
 859         if (host->flags & SDHCI_HS400_TUNING) {
 860                 sdhci_msm_hc_select_mode(host);
 861                 msm_set_clock_rate_for_bus_mode(host, ios.clock);
 862                 host->flags &= ~SDHCI_HS400_TUNING;
 863         }
 864
 865 retry:
 866         /* First of all reset the tuning block */
 867         rc = msm_init_cm_dll(host);
 868         if (rc)
 869                 return rc;
 870
 871         phase = 0;
 872         do {
 873                 /* Set the phase in delay line hw block */
 874                 rc = msm_config_cm_dll_phase(host, phase);
 875                 if (rc)
 876                         return rc;
 877
 878                 msm_host->saved_tuning_phase = phase;
 879                 rc = mmc_send_tuning(mmc, opcode, NULL);
 880                 if (!rc) {
 881                         /* Tuning is successful at this tuning point */
 882                         tuned_phases[tuned_phase_cnt++] = phase;
 883                         dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n",
 884                                  mmc_hostname(mmc), phase);
 885                 }
 886         } while (++phase < ARRAY_SIZE(tuned_phases));
 887
 888         if (tuned_phase_cnt) {
 889                 rc = msm_find_most_appropriate_phase(host, tuned_phases,
 890                                                      tuned_phase_cnt);
 891                 if (rc < 0)
 892                         return rc;
 893                 else
 894                         phase = rc;
 895
 896                 /*
 897                  * Finally set the selected phase in delay
 898                  * line hw block.
 899                  */
 900                 rc = msm_config_cm_dll_phase(host, phase);
 901                 if (rc)
 902                         return rc;
 903                 dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n",
 904                          mmc_hostname(mmc), phase);
 905         } else {
 906                 if (--tuning_seq_cnt)
 907                         goto retry;
 908                 /* Tuning failed */
 909                 dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n",
 910                        mmc_hostname(mmc));
 911                 rc = -EIO;
 912         }
 913
 914         if (!rc)
 915                 msm_host->tuning_done = true;
 916         return rc;
 917 }
 918
 919 /*
 920  * sdhci_msm_hs400 - Calibrate the DLL for HS400 bus speed mode operation.
 921  * This needs to be done for both tuning and enhanced_strobe mode.
 922  * DLL operation is only needed for clock > 100MHz. For clock <= 100MHz
 923  * fixed feedback clock is used.
 924  */
 925 static void sdhci_msm_hs400(struct sdhci_host *host, struct mmc_ios *ios)
 926 {
 927         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 928         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 929         int ret;
 930
 931         if (host->clock > CORE_FREQ_100MHZ &&
 932             (msm_host->tuning_done || ios->enhanced_strobe) &&
 933             !msm_host->calibration_done) {
 934                 ret = sdhci_msm_hs400_dll_calibration(host);
 935                 if (!ret)
 936                         msm_host->calibration_done = true;
 937                 else
 938                         pr_err("%s: Failed to calibrate DLL for hs400 mode (%d)\n",
 939                                mmc_hostname(host->mmc), ret);
 940         }
 941 }
 942
 943 static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
 944                                         unsigned int uhs)
 945 {
 946         struct mmc_host *mmc = host->mmc;
 947         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 948         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 949         u16 ctrl_2;
 950         u32 config;
 951
 952         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 953         /* Select Bus Speed Mode for host */
 954         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
 955         switch (uhs) {
 956         case MMC_TIMING_UHS_SDR12:
 957                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
 958                 break;
 959         case MMC_TIMING_UHS_SDR25:
 960                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
 961                 break;
 962         case MMC_TIMING_UHS_SDR50:
 963                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
 964                 break;
 965         case MMC_TIMING_MMC_HS400:
 966         case MMC_TIMING_MMC_HS200:
 967         case MMC_TIMING_UHS_SDR104:
 968                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
 969                 break;
 970         case MMC_TIMING_UHS_DDR50:
 971         case MMC_TIMING_MMC_DDR52:
 972                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
 973                 break;
 974         }
 975
 976         /*
 977          * When clock frequency is less than 100MHz, the feedback clock must be
 978          * provided and DLL must not be used so that tuning can be skipped. To
 979          * provide feedback clock, the mode selection can be any value less
 980          * than 3'b011 in bits [2:0] of HOST CONTROL2 register.
 981          */
 982         if (host->clock <= CORE_FREQ_100MHZ) {
 983                 if (uhs == MMC_TIMING_MMC_HS400 ||
 984                     uhs == MMC_TIMING_MMC_HS200 ||
 985                     uhs == MMC_TIMING_UHS_SDR104)
 986                         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
 987                 /*
 988                  * DLL is not required for clock <= 100MHz
 989                  * Thus, make sure DLL it is disabled when not required
 990                  */
 991                 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 992                 config |= CORE_DLL_RST;
 993                 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 994
 995                 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
 996                 config |= CORE_DLL_PDN;
 997                 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
 998
 999                 /*
1000                  * The DLL needs to be restored and CDCLP533 recalibrated
1001                  * when the clock frequency is set back to 400MHz.
1002                  */
1003                 msm_host->calibration_done = false;
1004         }
1005
1006         dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",
1007                 mmc_hostname(host->mmc), host->clock, uhs, ctrl_2);
1008         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1009
1010         if (mmc->ios.timing == MMC_TIMING_MMC_HS400)
1011                 sdhci_msm_hs400(host, &mmc->ios);
1012 }
1013
1014 static inline void sdhci_msm_init_pwr_irq_wait(struct sdhci_msm_host *msm_host)
1015 {
1016         init_waitqueue_head(&msm_host->pwr_irq_wait);
1017 }
1018
1019 static inline void sdhci_msm_complete_pwr_irq_wait(
1020                 struct sdhci_msm_host *msm_host)
1021 {
1022         wake_up(&msm_host->pwr_irq_wait);
1023 }
1024
1025 /*
1026  * sdhci_msm_check_power_status API should be called when registers writes
1027  * which can toggle sdhci IO bus ON/OFF or change IO lines HIGH/LOW happens.
1028  * To what state the register writes will change the IO lines should be passed
1029  * as the argument req_type. This API will check whether the IO line's state
1030  * is already the expected state and will wait for power irq only if
1031  * power irq is expected to be trigerred based on the current IO line state
1032  * and expected IO line state.
1033  */
1034 static void sdhci_msm_check_power_status(struct sdhci_host *host, u32 req_type)
1035 {
1036         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1037         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1038         bool done = false;
1039         u32 val;
1040
1041         pr_debug("%s: %s: request %d curr_pwr_state %x curr_io_level %x\n",
1042                         mmc_hostname(host->mmc), __func__, req_type,
1043                         msm_host->curr_pwr_state, msm_host->curr_io_level);
1044
1045         /*
1046          * The power interrupt will not be generated for signal voltage
1047          * switches if SWITCHABLE_SIGNALING_VOLTAGE in MCI_GENERICS is not set.
1048          */
1049         val = readl(msm_host->core_mem + CORE_MCI_GENERICS);
1050         if ((req_type & REQ_IO_HIGH || req_type & REQ_IO_LOW) &&
1051             !(val & SWITCHABLE_SIGNALING_VOLTAGE)) {
1052                 return;
1053         }
1054
1055         /*
1056          * The IRQ for request type IO High/LOW will be generated when -
1057          * there is a state change in 1.8V enable bit (bit 3) of
1058          * SDHCI_HOST_CONTROL2 register. The reset state of that bit is 0
1059          * which indicates 3.3V IO voltage. So, when MMC core layer tries
1060          * to set it to 3.3V before card detection happens, the
1061          * IRQ doesn't get triggered as there is no state change in this bit.
1062          * The driver already handles this case by changing the IO voltage
1063          * level to high as part of controller power up sequence. Hence, check
1064          * for host->pwr to handle a case where IO voltage high request is
1065          * issued even before controller power up.
1066          */
1067         if ((req_type & REQ_IO_HIGH) && !host->pwr) {
1068                 pr_debug("%s: do not wait for power IRQ that never comes, req_type: %d\n",
1069                                 mmc_hostname(host->mmc), req_type);
1070                 return;
1071         }
1072         if ((req_type & msm_host->curr_pwr_state) ||
1073                         (req_type & msm_host->curr_io_level))
1074                 done = true;
1075         /*
1076          * This is needed here to handle cases where register writes will
1077          * not change the current bus state or io level of the controller.
1078          * In this case, no power irq will be triggerred and we should
1079          * not wait.
1080          */
1081         if (!done) {
1082                 if (!wait_event_timeout(msm_host->pwr_irq_wait,
1083                                 msm_host->pwr_irq_flag,
1084                                 msecs_to_jiffies(MSM_PWR_IRQ_TIMEOUT_MS)))
1085                         dev_warn(&msm_host->pdev->dev,
1086                                  "%s: pwr_irq for req: (%d) timed out\n",
1087                                  mmc_hostname(host->mmc), req_type);
1088         }
1089         pr_debug("%s: %s: request %d done\n", mmc_hostname(host->mmc),
1090                         __func__, req_type);
1091 }
1092
1093 static void sdhci_msm_dump_pwr_ctrl_regs(struct sdhci_host *host)
1094 {
1095         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1096         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1097
1098         pr_err("%s: PWRCTL_STATUS: 0x%08x | PWRCTL_MASK: 0x%08x | PWRCTL_CTL: 0x%08x\n",
1099                         mmc_hostname(host->mmc),
1100                         readl_relaxed(msm_host->core_mem + CORE_PWRCTL_STATUS),
1101                         readl_relaxed(msm_host->core_mem + CORE_PWRCTL_MASK),
1102                         readl_relaxed(msm_host->core_mem + CORE_PWRCTL_CTL));
1103 }
1104
1105 static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq)
1106 {
1107         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1108         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1109         u32 irq_status, irq_ack = 0;
1110         int retry = 10;
1111         u32 pwr_state = 0, io_level = 0;
1112
1113
1114         irq_status = readl_relaxed(msm_host->core_mem + CORE_PWRCTL_STATUS);
1115         irq_status &= INT_MASK;
1116
1117         writel_relaxed(irq_status, msm_host->core_mem + CORE_PWRCTL_CLEAR);
1118
1119         /*
1120          * There is a rare HW scenario where the first clear pulse could be
1121          * lost when actual reset and clear/read of status register is
1122          * happening at a time. Hence, retry for at least 10 times to make
1123          * sure status register is cleared. Otherwise, this will result in
1124          * a spurious power IRQ resulting in system instability.
1125          */
1126         while (irq_status & readl_relaxed(msm_host->core_mem +
1127                                 CORE_PWRCTL_STATUS)) {
1128                 if (retry == 0) {
1129                         pr_err("%s: Timedout clearing (0x%x) pwrctl status register\n",
1130                                         mmc_hostname(host->mmc), irq_status);
1131                         sdhci_msm_dump_pwr_ctrl_regs(host);
1132                         WARN_ON(1);
1133                         break;
1134                 }
1135                 writel_relaxed(irq_status,
1136                                 msm_host->core_mem + CORE_PWRCTL_CLEAR);
1137                 retry--;
1138                 udelay(10);
1139         }
1140
1141         /* Handle BUS ON/OFF*/
1142         if (irq_status & CORE_PWRCTL_BUS_ON) {
1143                 pwr_state = REQ_BUS_ON;
1144                 io_level = REQ_IO_HIGH;
1145                 irq_ack |= CORE_PWRCTL_BUS_SUCCESS;
1146         }
1147         if (irq_status & CORE_PWRCTL_BUS_OFF) {
1148                 pwr_state = REQ_BUS_OFF;
1149                 io_level = REQ_IO_LOW;
1150                 irq_ack |= CORE_PWRCTL_BUS_SUCCESS;
1151         }
1152         /* Handle IO LOW/HIGH */
1153         if (irq_status & CORE_PWRCTL_IO_LOW) {
1154                 io_level = REQ_IO_LOW;
1155                 irq_ack |= CORE_PWRCTL_IO_SUCCESS;
1156         }
1157         if (irq_status & CORE_PWRCTL_IO_HIGH) {
1158                 io_level = REQ_IO_HIGH;
1159                 irq_ack |= CORE_PWRCTL_IO_SUCCESS;
1160         }
1161
1162         /*
1163          * The driver has to acknowledge the interrupt, switch voltages and
1164          * report back if it succeded or not to this register. The voltage
1165          * switches are handled by the sdhci core, so just report success.
1166          */
1167         writel_relaxed(irq_ack, msm_host->core_mem + CORE_PWRCTL_CTL);
1168
1169         if (pwr_state)
1170                 msm_host->curr_pwr_state = pwr_state;
1171         if (io_level)
1172                 msm_host->curr_io_level = io_level;
1173
1174         pr_debug("%s: %s: Handled IRQ(%d), irq_status=0x%x, ack=0x%x\n",
1175                 mmc_hostname(msm_host->mmc), __func__, irq, irq_status,
1176                 irq_ack);
1177 }
1178
1179 static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data)
1180 {
1181         struct sdhci_host *host = (struct sdhci_host *)data;
1182         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1183         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1184
1185         sdhci_msm_handle_pwr_irq(host, irq);
1186         msm_host->pwr_irq_flag = 1;
1187         sdhci_msm_complete_pwr_irq_wait(msm_host);
1188
1189
1190         return IRQ_HANDLED;
1191 }
1192
1193 static unsigned int sdhci_msm_get_max_clock(struct sdhci_host *host)
1194 {
1195         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1196         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1197         struct clk *core_clk = msm_host->bulk_clks[0].clk;
1198
1199         return clk_round_rate(core_clk, ULONG_MAX);
1200 }
1201
1202 static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host)
1203 {
1204         return SDHCI_MSM_MIN_CLOCK;
1205 }
1206
1207 /**
1208  * __sdhci_msm_set_clock - sdhci_msm clock control.
1209  *
1210  * Description:
1211  * MSM controller does not use internal divider and
1212  * instead directly control the GCC clock as per
1213  * HW recommendation.
1214  **/
1215 static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
1216 {
1217         u16 clk;
1218         /*
1219          * Keep actual_clock as zero -
1220          * - since there is no divider used so no need of having actual_clock.
1221          * - MSM controller uses SDCLK for data timeout calculation. If
1222          *   actual_clock is zero, host->clock is taken for calculation.
1223          */
1224         host->mmc->actual_clock = 0;
1225
1226         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1227
1228         if (clock == 0)
1229                 return;
1230
1231         /*
1232          * MSM controller do not use clock divider.
1233          * Thus read SDHCI_CLOCK_CONTROL and only enable
1234          * clock with no divider value programmed.
1235          */
1236         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1237         sdhci_enable_clk(host, clk);
1238 }
1239
1240 /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
1241 static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
1242 {
1243         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1244         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1245
1246         if (!clock) {
1247                 msm_host->clk_rate = clock;
1248                 goto out;
1249         }
1250
1251         sdhci_msm_hc_select_mode(host);
1252
1253         msm_set_clock_rate_for_bus_mode(host, clock);
1254 out:
1255         __sdhci_msm_set_clock(host, clock);
1256 }
1257
1258 /*
1259  * Platform specific register write functions. This is so that, if any
1260  * register write needs to be followed up by platform specific actions,
1261  * they can be added here. These functions can go to sleep when writes
1262  * to certain registers are done.
1263  * These functions are relying on sdhci_set_ios not using spinlock.
1264  */
1265 static int __sdhci_msm_check_write(struct sdhci_host *host, u16 val, int reg)
1266 {
1267         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1268         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1269         u32 req_type = 0;
1270
1271         switch (reg) {
1272         case SDHCI_HOST_CONTROL2:
1273                 req_type = (val & SDHCI_CTRL_VDD_180) ? REQ_IO_LOW :
1274                         REQ_IO_HIGH;
1275                 break;
1276         case SDHCI_SOFTWARE_RESET:
1277                 if (host->pwr && (val & SDHCI_RESET_ALL))
1278                         req_type = REQ_BUS_OFF;
1279                 break;
1280         case SDHCI_POWER_CONTROL:
1281                 req_type = !val ? REQ_BUS_OFF : REQ_BUS_ON;
1282                 break;
1283         }
1284
1285         if (req_type) {
1286                 msm_host->pwr_irq_flag = 0;
1287                 /*
1288                  * Since this register write may trigger a power irq, ensure
1289                  * all previous register writes are complete by this point.
1290                  */
1291                 mb();
1292         }
1293         return req_type;
1294 }
1295
1296 /* This function may sleep*/
1297 static void sdhci_msm_writew(struct sdhci_host *host, u16 val, int reg)
1298 {
1299         u32 req_type = 0;
1300
1301         req_type = __sdhci_msm_check_write(host, val, reg);
1302         writew_relaxed(val, host->ioaddr + reg);
1303
1304         if (req_type)
1305                 sdhci_msm_check_power_status(host, req_type);
1306 }
1307
1308 /* This function may sleep*/
1309 static void sdhci_msm_writeb(struct sdhci_host *host, u8 val, int reg)
1310 {
1311         u32 req_type = 0;
1312
1313         req_type = __sdhci_msm_check_write(host, val, reg);
1314
1315         writeb_relaxed(val, host->ioaddr + reg);
1316
1317         if (req_type)
1318                 sdhci_msm_check_power_status(host, req_type);
1319 }
1320
1321 static void sdhci_msm_set_regulator_caps(struct sdhci_msm_host *msm_host)
1322 {
1323         struct mmc_host *mmc = msm_host->mmc;
1324         struct regulator *supply = mmc->supply.vqmmc;
1325         u32 caps = 0;
1326
1327         if (!IS_ERR(mmc->supply.vqmmc)) {
1328                 if (regulator_is_supported_voltage(supply, 1700000, 1950000))
1329                         caps |= CORE_1_8V_SUPPORT;
1330                 if (regulator_is_supported_voltage(supply, 2700000, 3600000))
1331                         caps |= CORE_3_0V_SUPPORT;
1332
1333                 if (!caps)
1334                         pr_warn("%s: 1.8/3V not supported for vqmmc\n",
1335                                         mmc_hostname(mmc));
1336         }
1337
1338         msm_host->caps_0 |= caps;
1339         pr_debug("%s: supported caps: 0x%08x\n", mmc_hostname(mmc), caps);
1340 }
1341
1342 static const struct of_device_id sdhci_msm_dt_match[] = {
1343         { .compatible = "qcom,sdhci-msm-v4" },
1344         {},
1345 };
1346
1347 MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match);
1348
1349 static const struct sdhci_ops sdhci_msm_ops = {
1350         .reset = sdhci_reset,
1351         .set_clock = sdhci_msm_set_clock,
1352         .get_min_clock = sdhci_msm_get_min_clock,
1353         .get_max_clock = sdhci_msm_get_max_clock,
1354         .set_bus_width = sdhci_set_bus_width,
1355         .set_uhs_signaling = sdhci_msm_set_uhs_signaling,
1356         .write_w = sdhci_msm_writew,
1357         .write_b = sdhci_msm_writeb,
1358 };
1359
1360 static const struct sdhci_pltfm_data sdhci_msm_pdata = {
1361         .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
1362                   SDHCI_QUIRK_NO_CARD_NO_RESET |
1363                   SDHCI_QUIRK_SINGLE_POWER_WRITE |
1364                   SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1365         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1366         .ops = &sdhci_msm_ops,
1367 };
1368
1369 static int sdhci_msm_probe(struct platform_device *pdev)
1370 {
1371         struct sdhci_host *host;
1372         struct sdhci_pltfm_host *pltfm_host;
1373         struct sdhci_msm_host *msm_host;
1374         struct resource *core_memres;
1375         struct clk *clk;
1376         int ret;
1377         u16 host_version, core_minor;
1378         u32 core_version, config;
1379         u8 core_major;
1380
1381         host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host));
1382         if (IS_ERR(host))
1383                 return PTR_ERR(host);
1384
1385         host->sdma_boundary = 0;
1386         pltfm_host = sdhci_priv(host);
1387         msm_host = sdhci_pltfm_priv(pltfm_host);
1388         msm_host->mmc = host->mmc;
1389         msm_host->pdev = pdev;
1390
1391         ret = mmc_of_parse(host->mmc);
1392         if (ret)
1393                 goto pltfm_free;
1394
1395         sdhci_get_of_property(pdev);
1396
1397         msm_host->saved_tuning_phase = INVALID_TUNING_PHASE;
1398
1399         /* Setup SDCC bus voter clock. */
1400         msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
1401         if (!IS_ERR(msm_host->bus_clk)) {
1402                 /* Vote for max. clk rate for max. performance */
1403                 ret = clk_set_rate(msm_host->bus_clk, INT_MAX);
1404                 if (ret)
1405                         goto pltfm_free;
1406                 ret = clk_prepare_enable(msm_host->bus_clk);
1407                 if (ret)
1408                         goto pltfm_free;
1409         }
1410
1411         /* Setup main peripheral bus clock */
1412         clk = devm_clk_get(&pdev->dev, "iface");
1413         if (IS_ERR(clk)) {
1414                 ret = PTR_ERR(clk);
1415                 dev_err(&pdev->dev, "Peripheral clk setup failed (%d)\n", ret);
1416                 goto bus_clk_disable;
1417         }
1418         msm_host->bulk_clks[1].clk = clk;
1419
1420         /* Setup SDC MMC clock */
1421         clk = devm_clk_get(&pdev->dev, "core");
1422         if (IS_ERR(clk)) {
1423                 ret = PTR_ERR(clk);
1424                 dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret);
1425                 goto bus_clk_disable;
1426         }
1427         msm_host->bulk_clks[0].clk = clk;
1428
1429         /* Vote for maximum clock rate for maximum performance */
1430         ret = clk_set_rate(clk, INT_MAX);
1431         if (ret)
1432                 dev_warn(&pdev->dev, "core clock boost failed\n");
1433
1434         clk = devm_clk_get(&pdev->dev, "cal");
1435         if (IS_ERR(clk))
1436                 clk = NULL;
1437         msm_host->bulk_clks[2].clk = clk;
1438
1439         clk = devm_clk_get(&pdev->dev, "sleep");
1440         if (IS_ERR(clk))
1441                 clk = NULL;
1442         msm_host->bulk_clks[3].clk = clk;
1443
1444         ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks),
1445                                       msm_host->bulk_clks);
1446         if (ret)
1447                 goto bus_clk_disable;
1448
1449         /*
1450          * xo clock is needed for FLL feature of cm_dll.
1451          * In case if xo clock is not mentioned in DT, warn and proceed.
1452          */
1453         msm_host->xo_clk = devm_clk_get(&pdev->dev, "xo");
1454         if (IS_ERR(msm_host->xo_clk)) {
1455                 ret = PTR_ERR(msm_host->xo_clk);
1456                 dev_warn(&pdev->dev, "TCXO clk not present (%d)\n", ret);
1457         }
1458
1459         core_memres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1460         msm_host->core_mem = devm_ioremap_resource(&pdev->dev, core_memres);
1461
1462         if (IS_ERR(msm_host->core_mem)) {
1463                 dev_err(&pdev->dev, "Failed to remap registers\n");
1464                 ret = PTR_ERR(msm_host->core_mem);
1465                 goto clk_disable;
1466         }
1467
1468         /* Reset the vendor spec register to power on reset state */
1469         writel_relaxed(CORE_VENDOR_SPEC_POR_VAL,
1470                        host->ioaddr + CORE_VENDOR_SPEC);
1471
1472         /* Set HC_MODE_EN bit in HC_MODE register */
1473         writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE));
1474
1475         config = readl_relaxed(msm_host->core_mem + CORE_HC_MODE);
1476         config |= FF_CLK_SW_RST_DIS;
1477         writel_relaxed(config, msm_host->core_mem + CORE_HC_MODE);
1478
1479         host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
1480         dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n",
1481                 host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >>
1482                                SDHCI_VENDOR_VER_SHIFT));
1483
1484         core_version = readl_relaxed(msm_host->core_mem + CORE_MCI_VERSION);
1485         core_major = (core_version & CORE_VERSION_MAJOR_MASK) >>
1486                       CORE_VERSION_MAJOR_SHIFT;
1487         core_minor = core_version & CORE_VERSION_MINOR_MASK;
1488         dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n",
1489                 core_version, core_major, core_minor);
1490
1491         if (core_major == 1 && core_minor >= 0x42)
1492                 msm_host->use_14lpp_dll_reset = true;
1493
1494         /*
1495          * SDCC 5 controller with major version 1, minor version 0x34 and later
1496          * with HS 400 mode support will use CM DLL instead of CDC LP 533 DLL.
1497          */
1498         if (core_major == 1 && core_minor < 0x34)
1499                 msm_host->use_cdclp533 = true;
1500
1501         /*
1502          * Support for some capabilities is not advertised by newer
1503          * controller versions and must be explicitly enabled.
1504          */
1505         if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
1506                 config = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES);
1507                 config |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
1508                 writel_relaxed(config, host->ioaddr +
1509                                CORE_VENDOR_SPEC_CAPABILITIES0);
1510         }
1511
1512         /*
1513          * Power on reset state may trigger power irq if previous status of
1514          * PWRCTL was either BUS_ON or IO_HIGH_V. So before enabling pwr irq
1515          * interrupt in GIC, any pending power irq interrupt should be
1516          * acknowledged. Otherwise power irq interrupt handler would be
1517          * fired prematurely.
1518          */
1519         sdhci_msm_handle_pwr_irq(host, 0);
1520
1521         /*
1522          * Ensure that above writes are propogated before interrupt enablement
1523          * in GIC.
1524          */
1525         mb();
1526
1527         /* Setup IRQ for handling power/voltage tasks with PMIC */
1528         msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq");
1529         if (msm_host->pwr_irq < 0) {
1530                 dev_err(&pdev->dev, "Get pwr_irq failed (%d)\n",
1531                         msm_host->pwr_irq);
1532                 ret = msm_host->pwr_irq;
1533                 goto clk_disable;
1534         }
1535
1536         sdhci_msm_init_pwr_irq_wait(msm_host);
1537         /* Enable pwr irq interrupts */
1538         writel_relaxed(INT_MASK, msm_host->core_mem + CORE_PWRCTL_MASK);
1539
1540         ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL,
1541                                         sdhci_msm_pwr_irq, IRQF_ONESHOT,
1542                                         dev_name(&pdev->dev), host);
1543         if (ret) {
1544                 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", ret);
1545                 goto clk_disable;
1546         }
1547
1548         pm_runtime_get_noresume(&pdev->dev);
1549         pm_runtime_set_active(&pdev->dev);
1550         pm_runtime_enable(&pdev->dev);
1551         pm_runtime_set_autosuspend_delay(&pdev->dev,
1552                                          MSM_MMC_AUTOSUSPEND_DELAY_MS);
1553         pm_runtime_use_autosuspend(&pdev->dev);
1554
1555         host->mmc_host_ops.execute_tuning = sdhci_msm_execute_tuning;
1556         ret = sdhci_add_host(host);
1557         if (ret)
1558                 goto pm_runtime_disable;
1559         sdhci_msm_set_regulator_caps(msm_host);
1560
1561         pm_runtime_mark_last_busy(&pdev->dev);
1562         pm_runtime_put_autosuspend(&pdev->dev);
1563
1564         return 0;
1565
1566 pm_runtime_disable:
1567         pm_runtime_disable(&pdev->dev);
1568         pm_runtime_set_suspended(&pdev->dev);
1569         pm_runtime_put_noidle(&pdev->dev);
1570 clk_disable:
1571         clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
1572                                    msm_host->bulk_clks);
1573 bus_clk_disable:
1574         if (!IS_ERR(msm_host->bus_clk))
1575                 clk_disable_unprepare(msm_host->bus_clk);
1576 pltfm_free:
1577         sdhci_pltfm_free(pdev);
1578         return ret;
1579 }
1580
1581 static int sdhci_msm_remove(struct platform_device *pdev)
1582 {
1583         struct sdhci_host *host = platform_get_drvdata(pdev);
1584         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1585         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1586         int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) ==
1587                     0xffffffff);
1588
1589         sdhci_remove_host(host, dead);
1590
1591         pm_runtime_get_sync(&pdev->dev);
1592         pm_runtime_disable(&pdev->dev);
1593         pm_runtime_put_noidle(&pdev->dev);
1594
1595         clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
1596                                    msm_host->bulk_clks);
1597         if (!IS_ERR(msm_host->bus_clk))
1598                 clk_disable_unprepare(msm_host->bus_clk);
1599         sdhci_pltfm_free(pdev);
1600         return 0;
1601 }
1602
1603 #ifdef CONFIG_PM
1604 static int sdhci_msm_runtime_suspend(struct device *dev)
1605 {
1606         struct sdhci_host *host = dev_get_drvdata(dev);
1607         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1608         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1609
1610         clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
1611                                    msm_host->bulk_clks);
1612
1613         return 0;
1614 }
1615
1616 static int sdhci_msm_runtime_resume(struct device *dev)
1617 {
1618         struct sdhci_host *host = dev_get_drvdata(dev);
1619         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1620         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1621
1622         return clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks),
1623                                        msm_host->bulk_clks);
1624 }
1625 #endif
1626
1627 static const struct dev_pm_ops sdhci_msm_pm_ops = {
1628         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1629                                 pm_runtime_force_resume)
1630         SET_RUNTIME_PM_OPS(sdhci_msm_runtime_suspend,
1631                            sdhci_msm_runtime_resume,
1632                            NULL)
1633 };
1634
1635 static struct platform_driver sdhci_msm_driver = {
1636         .probe = sdhci_msm_probe,
1637         .remove = sdhci_msm_remove,
1638         .driver = {
1639                    .name = "sdhci_msm",
1640                    .of_match_table = sdhci_msm_dt_match,
1641                    .pm = &sdhci_msm_pm_ops,
1642         },
1643 };
1644
1645 module_platform_driver(sdhci_msm_driver);
1646
1647 MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver");
1648 MODULE_LICENSE("GPL v2");