2 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
4 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 and
8 * only version 2 as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/module.h>
18 #include <linux/of_device.h>
19 #include <linux/delay.h>
20 #include <linux/mmc/mmc.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/slab.h>
23 #include <linux/iopoll.h>
24 #include <linux/regulator/consumer.h>
26 #include "sdhci-pltfm.h"
28 #define CORE_MCI_VERSION 0x50
29 #define CORE_VERSION_MAJOR_SHIFT 28
30 #define CORE_VERSION_MAJOR_MASK (0xf << CORE_VERSION_MAJOR_SHIFT)
31 #define CORE_VERSION_MINOR_MASK 0xff
33 #define CORE_MCI_GENERICS 0x70
34 #define SWITCHABLE_SIGNALING_VOLTAGE BIT(29)
36 #define CORE_HC_MODE 0x78
37 #define HC_MODE_EN 0x1
38 #define CORE_POWER 0x0
39 #define CORE_SW_RST BIT(7)
40 #define FF_CLK_SW_RST_DIS BIT(13)
42 #define CORE_PWRCTL_STATUS 0xdc
43 #define CORE_PWRCTL_MASK 0xe0
44 #define CORE_PWRCTL_CLEAR 0xe4
45 #define CORE_PWRCTL_CTL 0xe8
46 #define CORE_PWRCTL_BUS_OFF BIT(0)
47 #define CORE_PWRCTL_BUS_ON BIT(1)
48 #define CORE_PWRCTL_IO_LOW BIT(2)
49 #define CORE_PWRCTL_IO_HIGH BIT(3)
50 #define CORE_PWRCTL_BUS_SUCCESS BIT(0)
51 #define CORE_PWRCTL_IO_SUCCESS BIT(2)
52 #define REQ_BUS_OFF BIT(0)
53 #define REQ_BUS_ON BIT(1)
54 #define REQ_IO_LOW BIT(2)
55 #define REQ_IO_HIGH BIT(3)
58 #define CORE_DLL_LOCK BIT(7)
59 #define CORE_DDR_DLL_LOCK BIT(11)
60 #define CORE_DLL_EN BIT(16)
61 #define CORE_CDR_EN BIT(17)
62 #define CORE_CK_OUT_EN BIT(18)
63 #define CORE_CDR_EXT_EN BIT(19)
64 #define CORE_DLL_PDN BIT(29)
65 #define CORE_DLL_RST BIT(30)
66 #define CORE_DLL_CONFIG 0x100
67 #define CORE_CMD_DAT_TRACK_SEL BIT(0)
68 #define CORE_DLL_STATUS 0x108
70 #define CORE_DLL_CONFIG_2 0x1b4
71 #define CORE_DDR_CAL_EN BIT(0)
72 #define CORE_FLL_CYCLE_CNT BIT(18)
73 #define CORE_DLL_CLOCK_DISABLE BIT(21)
75 #define CORE_VENDOR_SPEC 0x10c
76 #define CORE_VENDOR_SPEC_POR_VAL 0xa1c
77 #define CORE_CLK_PWRSAVE BIT(1)
78 #define CORE_HC_MCLK_SEL_DFLT (2 << 8)
79 #define CORE_HC_MCLK_SEL_HS400 (3 << 8)
80 #define CORE_HC_MCLK_SEL_MASK (3 << 8)
81 #define CORE_IO_PAD_PWR_SWITCH_EN (1 << 15)
82 #define CORE_IO_PAD_PWR_SWITCH (1 << 16)
83 #define CORE_HC_SELECT_IN_EN BIT(18)
84 #define CORE_HC_SELECT_IN_HS400 (6 << 19)
85 #define CORE_HC_SELECT_IN_MASK (7 << 19)
87 #define CORE_3_0V_SUPPORT (1 << 25)
88 #define CORE_1_8V_SUPPORT (1 << 26)
89 #define CORE_VOLT_SUPPORT (CORE_3_0V_SUPPORT | CORE_1_8V_SUPPORT)
91 #define CORE_CSR_CDC_CTLR_CFG0 0x130
92 #define CORE_SW_TRIG_FULL_CALIB BIT(16)
93 #define CORE_HW_AUTOCAL_ENA BIT(17)
95 #define CORE_CSR_CDC_CTLR_CFG1 0x134
96 #define CORE_CSR_CDC_CAL_TIMER_CFG0 0x138
97 #define CORE_TIMER_ENA BIT(16)
99 #define CORE_CSR_CDC_CAL_TIMER_CFG1 0x13C
100 #define CORE_CSR_CDC_REFCOUNT_CFG 0x140
101 #define CORE_CSR_CDC_COARSE_CAL_CFG 0x144
102 #define CORE_CDC_OFFSET_CFG 0x14C
103 #define CORE_CSR_CDC_DELAY_CFG 0x150
104 #define CORE_CDC_SLAVE_DDA_CFG 0x160
105 #define CORE_CSR_CDC_STATUS0 0x164
106 #define CORE_CALIBRATION_DONE BIT(0)
108 #define CORE_CDC_ERROR_CODE_MASK 0x7000000
110 #define CORE_CSR_CDC_GEN_CFG 0x178
111 #define CORE_CDC_SWITCH_BYPASS_OFF BIT(0)
112 #define CORE_CDC_SWITCH_RC_EN BIT(1)
114 #define CORE_DDR_200_CFG 0x184
115 #define CORE_CDC_T4_DLY_SEL BIT(0)
116 #define CORE_CMDIN_RCLK_EN BIT(1)
117 #define CORE_START_CDC_TRAFFIC BIT(6)
118 #define CORE_VENDOR_SPEC3 0x1b0
119 #define CORE_PWRSAVE_DLL BIT(3)
121 #define CORE_DDR_CONFIG 0x1b8
122 #define DDR_CONFIG_POR_VAL 0x80040853
124 #define CORE_VENDOR_SPEC_CAPABILITIES0 0x11c
126 #define INVALID_TUNING_PHASE -1
127 #define SDHCI_MSM_MIN_CLOCK 400000
128 #define CORE_FREQ_100MHZ (100 * 1000 * 1000)
130 #define CDR_SELEXT_SHIFT 20
131 #define CDR_SELEXT_MASK (0xf << CDR_SELEXT_SHIFT)
132 #define CMUX_SHIFT_PHASE_SHIFT 24
133 #define CMUX_SHIFT_PHASE_MASK (7 << CMUX_SHIFT_PHASE_SHIFT)
135 #define MSM_MMC_AUTOSUSPEND_DELAY_MS 50
137 /* Timeout value to avoid infinite waiting for pwr_irq */
138 #define MSM_PWR_IRQ_TIMEOUT_MS 5000
140 struct sdhci_msm_host {
141 struct platform_device *pdev;
142 void __iomem *core_mem; /* MSM SDCC mapped address */
143 int pwr_irq; /* power irq */
144 struct clk *bus_clk; /* SDHC bus voter clock */
145 struct clk *xo_clk; /* TCXO clk needed for FLL feature of cm_dll*/
146 struct clk_bulk_data bulk_clks[4]; /* core, iface, cal, sleep clocks */
147 unsigned long clk_rate;
148 struct mmc_host *mmc;
149 bool use_14lpp_dll_reset;
151 bool calibration_done;
152 u8 saved_tuning_phase;
156 wait_queue_head_t pwr_irq_wait;
161 static unsigned int msm_get_clock_rate_for_bus_mode(struct sdhci_host *host,
164 struct mmc_ios ios = host->mmc->ios;
166 * The SDHC requires internal clock frequency to be double the
167 * actual clock that will be set for DDR mode. The controller
168 * uses the faster clock(100/400MHz) for some of its parts and
169 * send the actual required clock (50/200MHz) to the card.
171 if (ios.timing == MMC_TIMING_UHS_DDR50 ||
172 ios.timing == MMC_TIMING_MMC_DDR52 ||
173 ios.timing == MMC_TIMING_MMC_HS400 ||
174 host->flags & SDHCI_HS400_TUNING)
179 static void msm_set_clock_rate_for_bus_mode(struct sdhci_host *host,
182 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
183 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
184 struct mmc_ios curr_ios = host->mmc->ios;
185 struct clk *core_clk = msm_host->bulk_clks[0].clk;
188 clock = msm_get_clock_rate_for_bus_mode(host, clock);
189 rc = clk_set_rate(core_clk, clock);
191 pr_err("%s: Failed to set clock at rate %u at timing %d\n",
192 mmc_hostname(host->mmc), clock,
196 msm_host->clk_rate = clock;
197 pr_debug("%s: Setting clock at rate %lu at timing %d\n",
198 mmc_hostname(host->mmc), clk_get_rate(core_clk),
202 /* Platform specific tuning */
203 static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, u8 poll)
207 struct mmc_host *mmc = host->mmc;
209 /* Poll for CK_OUT_EN bit. max. poll time = 50us */
210 ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) &
213 while (ck_out_en != poll) {
214 if (--wait_cnt == 0) {
215 dev_err(mmc_dev(mmc), "%s: CK_OUT_EN bit is not %d\n",
216 mmc_hostname(mmc), poll);
221 ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) &
228 static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase)
231 static const u8 grey_coded_phase_table[] = {
232 0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4,
233 0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8
237 struct mmc_host *mmc = host->mmc;
242 spin_lock_irqsave(&host->lock, flags);
244 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
245 config &= ~(CORE_CDR_EN | CORE_CK_OUT_EN);
246 config |= (CORE_CDR_EXT_EN | CORE_DLL_EN);
247 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
249 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */
250 rc = msm_dll_poll_ck_out_en(host, 0);
255 * Write the selected DLL clock output phase (0 ... 15)
256 * to CDR_SELEXT bit field of DLL_CONFIG register.
258 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
259 config &= ~CDR_SELEXT_MASK;
260 config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT;
261 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
263 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
264 config |= CORE_CK_OUT_EN;
265 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
267 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */
268 rc = msm_dll_poll_ck_out_en(host, 1);
272 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
273 config |= CORE_CDR_EN;
274 config &= ~CORE_CDR_EXT_EN;
275 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
279 dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n",
280 mmc_hostname(mmc), phase);
282 spin_unlock_irqrestore(&host->lock, flags);
287 * Find out the greatest range of consecuitive selected
288 * DLL clock output phases that can be used as sampling
289 * setting for SD3.0 UHS-I card read operation (in SDR104
290 * timing mode) or for eMMC4.5 card read operation (in
291 * HS400/HS200 timing mode).
292 * Select the 3/4 of the range and configure the DLL with the
293 * selected DLL clock output phase.
296 static int msm_find_most_appropriate_phase(struct sdhci_host *host,
297 u8 *phase_table, u8 total_phases)
300 u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} };
301 u8 phases_per_row[MAX_PHASES] = { 0 };
302 int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0;
303 int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0;
304 bool phase_0_found = false, phase_15_found = false;
305 struct mmc_host *mmc = host->mmc;
307 if (!total_phases || (total_phases > MAX_PHASES)) {
308 dev_err(mmc_dev(mmc), "%s: Invalid argument: total_phases=%d\n",
309 mmc_hostname(mmc), total_phases);
313 for (cnt = 0; cnt < total_phases; cnt++) {
314 ranges[row_index][col_index] = phase_table[cnt];
315 phases_per_row[row_index] += 1;
318 if ((cnt + 1) == total_phases) {
320 /* check if next phase in phase_table is consecutive or not */
321 } else if ((phase_table[cnt] + 1) != phase_table[cnt + 1]) {
327 if (row_index >= MAX_PHASES)
330 /* Check if phase-0 is present in first valid window? */
332 phase_0_found = true;
333 phase_0_raw_index = 0;
334 /* Check if cycle exist between 2 valid windows */
335 for (cnt = 1; cnt <= row_index; cnt++) {
336 if (phases_per_row[cnt]) {
337 for (i = 0; i < phases_per_row[cnt]; i++) {
338 if (ranges[cnt][i] == 15) {
339 phase_15_found = true;
340 phase_15_raw_index = cnt;
348 /* If 2 valid windows form cycle then merge them as single window */
349 if (phase_0_found && phase_15_found) {
350 /* number of phases in raw where phase 0 is present */
351 u8 phases_0 = phases_per_row[phase_0_raw_index];
352 /* number of phases in raw where phase 15 is present */
353 u8 phases_15 = phases_per_row[phase_15_raw_index];
355 if (phases_0 + phases_15 >= MAX_PHASES)
357 * If there are more than 1 phase windows then total
358 * number of phases in both the windows should not be
359 * more than or equal to MAX_PHASES.
363 /* Merge 2 cyclic windows */
365 for (cnt = 0; cnt < phases_0; cnt++) {
366 ranges[phase_15_raw_index][i] =
367 ranges[phase_0_raw_index][cnt];
368 if (++i >= MAX_PHASES)
372 phases_per_row[phase_0_raw_index] = 0;
373 phases_per_row[phase_15_raw_index] = phases_15 + phases_0;
376 for (cnt = 0; cnt <= row_index; cnt++) {
377 if (phases_per_row[cnt] > curr_max) {
378 curr_max = phases_per_row[cnt];
379 selected_row_index = cnt;
383 i = (curr_max * 3) / 4;
387 ret = ranges[selected_row_index][i];
389 if (ret >= MAX_PHASES) {
391 dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n",
392 mmc_hostname(mmc), ret);
398 static inline void msm_cm_dll_set_freq(struct sdhci_host *host)
400 u32 mclk_freq = 0, config;
402 /* Program the MCLK value to MCLK_FREQ bit field */
403 if (host->clock <= 112000000)
405 else if (host->clock <= 125000000)
407 else if (host->clock <= 137000000)
409 else if (host->clock <= 150000000)
411 else if (host->clock <= 162000000)
413 else if (host->clock <= 175000000)
415 else if (host->clock <= 187000000)
417 else if (host->clock <= 200000000)
420 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
421 config &= ~CMUX_SHIFT_PHASE_MASK;
422 config |= mclk_freq << CMUX_SHIFT_PHASE_SHIFT;
423 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
426 /* Initialize the DLL (Programmable Delay Line) */
427 static int msm_init_cm_dll(struct sdhci_host *host)
429 struct mmc_host *mmc = host->mmc;
430 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
431 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
436 spin_lock_irqsave(&host->lock, flags);
439 * Make sure that clock is always enabled when DLL
440 * tuning is in progress. Keeping PWRSAVE ON may
441 * turn off the clock.
443 config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
444 config &= ~CORE_CLK_PWRSAVE;
445 writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
447 if (msm_host->use_14lpp_dll_reset) {
448 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
449 config &= ~CORE_CK_OUT_EN;
450 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
452 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
453 config |= CORE_DLL_CLOCK_DISABLE;
454 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2);
457 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
458 config |= CORE_DLL_RST;
459 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
461 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
462 config |= CORE_DLL_PDN;
463 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
464 msm_cm_dll_set_freq(host);
466 if (msm_host->use_14lpp_dll_reset &&
467 !IS_ERR_OR_NULL(msm_host->xo_clk)) {
470 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
471 config &= CORE_FLL_CYCLE_CNT;
473 mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 8),
474 clk_get_rate(msm_host->xo_clk));
476 mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 4),
477 clk_get_rate(msm_host->xo_clk));
479 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
480 config &= ~(0xFF << 10);
481 config |= mclk_freq << 10;
483 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2);
484 /* wait for 5us before enabling DLL clock */
488 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
489 config &= ~CORE_DLL_RST;
490 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
492 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
493 config &= ~CORE_DLL_PDN;
494 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
496 if (msm_host->use_14lpp_dll_reset) {
497 msm_cm_dll_set_freq(host);
498 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
499 config &= ~CORE_DLL_CLOCK_DISABLE;
500 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2);
503 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
504 config |= CORE_DLL_EN;
505 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
507 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
508 config |= CORE_CK_OUT_EN;
509 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
511 /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */
512 while (!(readl_relaxed(host->ioaddr + CORE_DLL_STATUS) &
514 /* max. wait for 50us sec for LOCK bit to be set */
515 if (--wait_cnt == 0) {
516 dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n",
518 spin_unlock_irqrestore(&host->lock, flags);
524 spin_unlock_irqrestore(&host->lock, flags);
528 static void msm_hc_select_default(struct sdhci_host *host)
530 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
531 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
534 if (!msm_host->use_cdclp533) {
535 config = readl_relaxed(host->ioaddr +
537 config &= ~CORE_PWRSAVE_DLL;
538 writel_relaxed(config, host->ioaddr +
542 config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
543 config &= ~CORE_HC_MCLK_SEL_MASK;
544 config |= CORE_HC_MCLK_SEL_DFLT;
545 writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
548 * Disable HC_SELECT_IN to be able to use the UHS mode select
549 * configuration from Host Control2 register for all other
551 * Write 0 to HC_SELECT_IN and HC_SELECT_IN_EN field
552 * in VENDOR_SPEC_FUNC
554 config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
555 config &= ~CORE_HC_SELECT_IN_EN;
556 config &= ~CORE_HC_SELECT_IN_MASK;
557 writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
560 * Make sure above writes impacting free running MCLK are completed
561 * before changing the clk_rate at GCC.
566 static void msm_hc_select_hs400(struct sdhci_host *host)
568 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
569 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
570 struct mmc_ios ios = host->mmc->ios;
571 u32 config, dll_lock;
574 /* Select the divided clock (free running MCLK/2) */
575 config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
576 config &= ~CORE_HC_MCLK_SEL_MASK;
577 config |= CORE_HC_MCLK_SEL_HS400;
579 writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
581 * Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC
584 if ((msm_host->tuning_done || ios.enhanced_strobe) &&
585 !msm_host->calibration_done) {
586 config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
587 config |= CORE_HC_SELECT_IN_HS400;
588 config |= CORE_HC_SELECT_IN_EN;
589 writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
591 if (!msm_host->clk_rate && !msm_host->use_cdclp533) {
593 * Poll on DLL_LOCK or DDR_DLL_LOCK bits in
594 * CORE_DLL_STATUS to be set. This should get set
595 * within 15 us at 200 MHz.
597 rc = readl_relaxed_poll_timeout(host->ioaddr +
602 CORE_DDR_DLL_LOCK)), 10,
604 if (rc == -ETIMEDOUT)
605 pr_err("%s: Unable to get DLL_LOCK/DDR_DLL_LOCK, dll_status: 0x%08x\n",
606 mmc_hostname(host->mmc), dll_lock);
609 * Make sure above writes impacting free running MCLK are completed
610 * before changing the clk_rate at GCC.
616 * sdhci_msm_hc_select_mode :- In general all timing modes are
617 * controlled via UHS mode select in Host Control2 register.
618 * eMMC specific HS200/HS400 doesn't have their respective modes
619 * defined here, hence we use these values.
621 * HS200 - SDR104 (Since they both are equivalent in functionality)
622 * HS400 - This involves multiple configurations
623 * Initially SDR104 - when tuning is required as HS200
624 * Then when switching to DDR @ 400MHz (HS400) we use
625 * the vendor specific HC_SELECT_IN to control the mode.
627 * In addition to controlling the modes we also need to select the
628 * correct input clock for DLL depending on the mode.
630 * HS400 - divided clock (free running MCLK/2)
631 * All other modes - default (free running MCLK)
633 static void sdhci_msm_hc_select_mode(struct sdhci_host *host)
635 struct mmc_ios ios = host->mmc->ios;
637 if (ios.timing == MMC_TIMING_MMC_HS400 ||
638 host->flags & SDHCI_HS400_TUNING)
639 msm_hc_select_hs400(host);
641 msm_hc_select_default(host);
644 static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host)
646 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
647 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
648 u32 config, calib_done;
651 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
654 * Retuning in HS400 (DDR mode) will fail, just reset the
655 * tuning block and restore the saved tuning phase.
657 ret = msm_init_cm_dll(host);
661 /* Set the selected phase in delay line hw block */
662 ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
666 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
667 config |= CORE_CMD_DAT_TRACK_SEL;
668 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
670 config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
671 config &= ~CORE_CDC_T4_DLY_SEL;
672 writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
674 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
675 config &= ~CORE_CDC_SWITCH_BYPASS_OFF;
676 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
678 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
679 config |= CORE_CDC_SWITCH_RC_EN;
680 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
682 config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
683 config &= ~CORE_START_CDC_TRAFFIC;
684 writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
686 /* Perform CDC Register Initialization Sequence */
688 writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
689 writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1);
690 writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
691 writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1);
692 writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG);
693 writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG);
694 writel_relaxed(0x4E2, host->ioaddr + CORE_CSR_CDC_DELAY_CFG);
695 writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG);
696 writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG);
698 /* CDC HW Calibration */
700 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
701 config |= CORE_SW_TRIG_FULL_CALIB;
702 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
704 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
705 config &= ~CORE_SW_TRIG_FULL_CALIB;
706 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
708 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
709 config |= CORE_HW_AUTOCAL_ENA;
710 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
712 config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
713 config |= CORE_TIMER_ENA;
714 writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
716 ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_CSR_CDC_STATUS0,
718 (calib_done & CORE_CALIBRATION_DONE),
721 if (ret == -ETIMEDOUT) {
722 pr_err("%s: %s: CDC calibration was not completed\n",
723 mmc_hostname(host->mmc), __func__);
727 ret = readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0)
728 & CORE_CDC_ERROR_CODE_MASK;
730 pr_err("%s: %s: CDC error code %d\n",
731 mmc_hostname(host->mmc), __func__, ret);
736 config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
737 config |= CORE_START_CDC_TRAFFIC;
738 writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
740 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
745 static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host)
747 struct mmc_host *mmc = host->mmc;
748 u32 dll_status, config;
751 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
754 * Currently the CORE_DDR_CONFIG register defaults to desired
755 * configuration on reset. Currently reprogramming the power on
756 * reset (POR) value in case it might have been modified by
757 * bootloaders. In the future, if this changes, then the desired
758 * values will need to be programmed appropriately.
760 writel_relaxed(DDR_CONFIG_POR_VAL, host->ioaddr + CORE_DDR_CONFIG);
762 if (mmc->ios.enhanced_strobe) {
763 config = readl_relaxed(host->ioaddr + CORE_DDR_200_CFG);
764 config |= CORE_CMDIN_RCLK_EN;
765 writel_relaxed(config, host->ioaddr + CORE_DDR_200_CFG);
768 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG_2);
769 config |= CORE_DDR_CAL_EN;
770 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG_2);
772 ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_DLL_STATUS,
774 (dll_status & CORE_DDR_DLL_LOCK),
777 if (ret == -ETIMEDOUT) {
778 pr_err("%s: %s: CM_DLL_SDC4 calibration was not completed\n",
779 mmc_hostname(host->mmc), __func__);
783 config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC3);
784 config |= CORE_PWRSAVE_DLL;
785 writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC3);
788 * Drain writebuffer to ensure above DLL calibration
789 * and PWRSAVE DLL is enabled.
793 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
798 static int sdhci_msm_hs400_dll_calibration(struct sdhci_host *host)
800 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
801 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
802 struct mmc_host *mmc = host->mmc;
806 pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
809 * Retuning in HS400 (DDR mode) will fail, just reset the
810 * tuning block and restore the saved tuning phase.
812 ret = msm_init_cm_dll(host);
816 if (!mmc->ios.enhanced_strobe) {
817 /* Set the selected phase in delay line hw block */
818 ret = msm_config_cm_dll_phase(host,
819 msm_host->saved_tuning_phase);
822 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
823 config |= CORE_CMD_DAT_TRACK_SEL;
824 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
827 if (msm_host->use_cdclp533)
828 ret = sdhci_msm_cdclp533_calibration(host);
830 ret = sdhci_msm_cm_dll_sdc4_calibration(host);
832 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
837 static int sdhci_msm_execute_tuning(struct mmc_host *mmc, u32 opcode)
839 struct sdhci_host *host = mmc_priv(mmc);
840 int tuning_seq_cnt = 3;
841 u8 phase, tuned_phases[16], tuned_phase_cnt = 0;
843 struct mmc_ios ios = host->mmc->ios;
844 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
845 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
848 * Tuning is required for SDR104, HS200 and HS400 cards and
849 * if clock frequency is greater than 100MHz in these modes.
851 if (host->clock <= CORE_FREQ_100MHZ ||
852 !(ios.timing == MMC_TIMING_MMC_HS400 ||
853 ios.timing == MMC_TIMING_MMC_HS200 ||
854 ios.timing == MMC_TIMING_UHS_SDR104))
858 * For HS400 tuning in HS200 timing requires:
859 * - select MCLK/2 in VENDOR_SPEC
860 * - program MCLK to 400MHz (or nearest supported) in GCC
862 if (host->flags & SDHCI_HS400_TUNING) {
863 sdhci_msm_hc_select_mode(host);
864 msm_set_clock_rate_for_bus_mode(host, ios.clock);
865 host->flags &= ~SDHCI_HS400_TUNING;
869 /* First of all reset the tuning block */
870 rc = msm_init_cm_dll(host);
876 /* Set the phase in delay line hw block */
877 rc = msm_config_cm_dll_phase(host, phase);
881 msm_host->saved_tuning_phase = phase;
882 rc = mmc_send_tuning(mmc, opcode, NULL);
884 /* Tuning is successful at this tuning point */
885 tuned_phases[tuned_phase_cnt++] = phase;
886 dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n",
887 mmc_hostname(mmc), phase);
889 } while (++phase < ARRAY_SIZE(tuned_phases));
891 if (tuned_phase_cnt) {
892 rc = msm_find_most_appropriate_phase(host, tuned_phases,
900 * Finally set the selected phase in delay
903 rc = msm_config_cm_dll_phase(host, phase);
906 dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n",
907 mmc_hostname(mmc), phase);
909 if (--tuning_seq_cnt)
912 dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n",
918 msm_host->tuning_done = true;
923 * sdhci_msm_hs400 - Calibrate the DLL for HS400 bus speed mode operation.
924 * This needs to be done for both tuning and enhanced_strobe mode.
925 * DLL operation is only needed for clock > 100MHz. For clock <= 100MHz
926 * fixed feedback clock is used.
928 static void sdhci_msm_hs400(struct sdhci_host *host, struct mmc_ios *ios)
930 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
931 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
934 if (host->clock > CORE_FREQ_100MHZ &&
935 (msm_host->tuning_done || ios->enhanced_strobe) &&
936 !msm_host->calibration_done) {
937 ret = sdhci_msm_hs400_dll_calibration(host);
939 msm_host->calibration_done = true;
941 pr_err("%s: Failed to calibrate DLL for hs400 mode (%d)\n",
942 mmc_hostname(host->mmc), ret);
946 static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
949 struct mmc_host *mmc = host->mmc;
950 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
951 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
955 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
956 /* Select Bus Speed Mode for host */
957 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
959 case MMC_TIMING_UHS_SDR12:
960 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
962 case MMC_TIMING_UHS_SDR25:
963 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
965 case MMC_TIMING_UHS_SDR50:
966 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
968 case MMC_TIMING_MMC_HS400:
969 case MMC_TIMING_MMC_HS200:
970 case MMC_TIMING_UHS_SDR104:
971 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
973 case MMC_TIMING_UHS_DDR50:
974 case MMC_TIMING_MMC_DDR52:
975 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
980 * When clock frequency is less than 100MHz, the feedback clock must be
981 * provided and DLL must not be used so that tuning can be skipped. To
982 * provide feedback clock, the mode selection can be any value less
983 * than 3'b011 in bits [2:0] of HOST CONTROL2 register.
985 if (host->clock <= CORE_FREQ_100MHZ) {
986 if (uhs == MMC_TIMING_MMC_HS400 ||
987 uhs == MMC_TIMING_MMC_HS200 ||
988 uhs == MMC_TIMING_UHS_SDR104)
989 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
991 * DLL is not required for clock <= 100MHz
992 * Thus, make sure DLL it is disabled when not required
994 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
995 config |= CORE_DLL_RST;
996 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
998 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
999 config |= CORE_DLL_PDN;
1000 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
1003 * The DLL needs to be restored and CDCLP533 recalibrated
1004 * when the clock frequency is set back to 400MHz.
1006 msm_host->calibration_done = false;
1009 dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",
1010 mmc_hostname(host->mmc), host->clock, uhs, ctrl_2);
1011 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1013 if (mmc->ios.timing == MMC_TIMING_MMC_HS400)
1014 sdhci_msm_hs400(host, &mmc->ios);
1017 static inline void sdhci_msm_init_pwr_irq_wait(struct sdhci_msm_host *msm_host)
1019 init_waitqueue_head(&msm_host->pwr_irq_wait);
1022 static inline void sdhci_msm_complete_pwr_irq_wait(
1023 struct sdhci_msm_host *msm_host)
1025 wake_up(&msm_host->pwr_irq_wait);
1029 * sdhci_msm_check_power_status API should be called when registers writes
1030 * which can toggle sdhci IO bus ON/OFF or change IO lines HIGH/LOW happens.
1031 * To what state the register writes will change the IO lines should be passed
1032 * as the argument req_type. This API will check whether the IO line's state
1033 * is already the expected state and will wait for power irq only if
1034 * power irq is expected to be trigerred based on the current IO line state
1035 * and expected IO line state.
1037 static void sdhci_msm_check_power_status(struct sdhci_host *host, u32 req_type)
1039 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1040 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1044 pr_debug("%s: %s: request %d curr_pwr_state %x curr_io_level %x\n",
1045 mmc_hostname(host->mmc), __func__, req_type,
1046 msm_host->curr_pwr_state, msm_host->curr_io_level);
1049 * The power interrupt will not be generated for signal voltage
1050 * switches if SWITCHABLE_SIGNALING_VOLTAGE in MCI_GENERICS is not set.
1052 val = readl(msm_host->core_mem + CORE_MCI_GENERICS);
1053 if ((req_type & REQ_IO_HIGH || req_type & REQ_IO_LOW) &&
1054 !(val & SWITCHABLE_SIGNALING_VOLTAGE)) {
1059 * The IRQ for request type IO High/LOW will be generated when -
1060 * there is a state change in 1.8V enable bit (bit 3) of
1061 * SDHCI_HOST_CONTROL2 register. The reset state of that bit is 0
1062 * which indicates 3.3V IO voltage. So, when MMC core layer tries
1063 * to set it to 3.3V before card detection happens, the
1064 * IRQ doesn't get triggered as there is no state change in this bit.
1065 * The driver already handles this case by changing the IO voltage
1066 * level to high as part of controller power up sequence. Hence, check
1067 * for host->pwr to handle a case where IO voltage high request is
1068 * issued even before controller power up.
1070 if ((req_type & REQ_IO_HIGH) && !host->pwr) {
1071 pr_debug("%s: do not wait for power IRQ that never comes, req_type: %d\n",
1072 mmc_hostname(host->mmc), req_type);
1075 if ((req_type & msm_host->curr_pwr_state) ||
1076 (req_type & msm_host->curr_io_level))
1079 * This is needed here to handle cases where register writes will
1080 * not change the current bus state or io level of the controller.
1081 * In this case, no power irq will be triggerred and we should
1085 if (!wait_event_timeout(msm_host->pwr_irq_wait,
1086 msm_host->pwr_irq_flag,
1087 msecs_to_jiffies(MSM_PWR_IRQ_TIMEOUT_MS)))
1088 dev_warn(&msm_host->pdev->dev,
1089 "%s: pwr_irq for req: (%d) timed out\n",
1090 mmc_hostname(host->mmc), req_type);
1092 pr_debug("%s: %s: request %d done\n", mmc_hostname(host->mmc),
1093 __func__, req_type);
1096 static void sdhci_msm_dump_pwr_ctrl_regs(struct sdhci_host *host)
1098 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1099 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1101 pr_err("%s: PWRCTL_STATUS: 0x%08x | PWRCTL_MASK: 0x%08x | PWRCTL_CTL: 0x%08x\n",
1102 mmc_hostname(host->mmc),
1103 readl_relaxed(msm_host->core_mem + CORE_PWRCTL_STATUS),
1104 readl_relaxed(msm_host->core_mem + CORE_PWRCTL_MASK),
1105 readl_relaxed(msm_host->core_mem + CORE_PWRCTL_CTL));
1108 static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq)
1110 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1111 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1112 u32 irq_status, irq_ack = 0;
1114 u32 pwr_state = 0, io_level = 0;
1117 irq_status = readl_relaxed(msm_host->core_mem + CORE_PWRCTL_STATUS);
1118 irq_status &= INT_MASK;
1120 writel_relaxed(irq_status, msm_host->core_mem + CORE_PWRCTL_CLEAR);
1123 * There is a rare HW scenario where the first clear pulse could be
1124 * lost when actual reset and clear/read of status register is
1125 * happening at a time. Hence, retry for at least 10 times to make
1126 * sure status register is cleared. Otherwise, this will result in
1127 * a spurious power IRQ resulting in system instability.
1129 while (irq_status & readl_relaxed(msm_host->core_mem +
1130 CORE_PWRCTL_STATUS)) {
1132 pr_err("%s: Timedout clearing (0x%x) pwrctl status register\n",
1133 mmc_hostname(host->mmc), irq_status);
1134 sdhci_msm_dump_pwr_ctrl_regs(host);
1138 writel_relaxed(irq_status,
1139 msm_host->core_mem + CORE_PWRCTL_CLEAR);
1144 /* Handle BUS ON/OFF*/
1145 if (irq_status & CORE_PWRCTL_BUS_ON) {
1146 pwr_state = REQ_BUS_ON;
1147 io_level = REQ_IO_HIGH;
1148 irq_ack |= CORE_PWRCTL_BUS_SUCCESS;
1150 if (irq_status & CORE_PWRCTL_BUS_OFF) {
1151 pwr_state = REQ_BUS_OFF;
1152 io_level = REQ_IO_LOW;
1153 irq_ack |= CORE_PWRCTL_BUS_SUCCESS;
1155 /* Handle IO LOW/HIGH */
1156 if (irq_status & CORE_PWRCTL_IO_LOW) {
1157 io_level = REQ_IO_LOW;
1158 irq_ack |= CORE_PWRCTL_IO_SUCCESS;
1160 if (irq_status & CORE_PWRCTL_IO_HIGH) {
1161 io_level = REQ_IO_HIGH;
1162 irq_ack |= CORE_PWRCTL_IO_SUCCESS;
1166 * The driver has to acknowledge the interrupt, switch voltages and
1167 * report back if it succeded or not to this register. The voltage
1168 * switches are handled by the sdhci core, so just report success.
1170 writel_relaxed(irq_ack, msm_host->core_mem + CORE_PWRCTL_CTL);
1173 * If we don't have info regarding the voltage levels supported by
1174 * regulators, don't change the IO PAD PWR SWITCH.
1176 if (msm_host->caps_0 & CORE_VOLT_SUPPORT) {
1179 * We should unset IO PAD PWR switch only if the register write
1180 * can set IO lines high and the regulator also switches to 3 V.
1181 * Else, we should keep the IO PAD PWR switch set.
1182 * This is applicable to certain targets where eMMC vccq supply
1183 * is only 1.8V. In such targets, even during REQ_IO_HIGH, the
1184 * IO PAD PWR switch must be kept set to reflect actual
1185 * regulator voltage. This way, during initialization of
1186 * controllers with only 1.8V, we will set the IO PAD bit
1187 * without waiting for a REQ_IO_LOW.
1189 config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
1190 new_config = config;
1192 if ((io_level & REQ_IO_HIGH) &&
1193 (msm_host->caps_0 & CORE_3_0V_SUPPORT))
1194 new_config &= ~CORE_IO_PAD_PWR_SWITCH;
1195 else if ((io_level & REQ_IO_LOW) ||
1196 (msm_host->caps_0 & CORE_1_8V_SUPPORT))
1197 new_config |= CORE_IO_PAD_PWR_SWITCH;
1199 if (config ^ new_config)
1200 writel_relaxed(new_config,
1201 host->ioaddr + CORE_VENDOR_SPEC);
1205 msm_host->curr_pwr_state = pwr_state;
1207 msm_host->curr_io_level = io_level;
1209 pr_debug("%s: %s: Handled IRQ(%d), irq_status=0x%x, ack=0x%x\n",
1210 mmc_hostname(msm_host->mmc), __func__, irq, irq_status,
1214 static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data)
1216 struct sdhci_host *host = (struct sdhci_host *)data;
1217 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1218 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1220 sdhci_msm_handle_pwr_irq(host, irq);
1221 msm_host->pwr_irq_flag = 1;
1222 sdhci_msm_complete_pwr_irq_wait(msm_host);
1228 static unsigned int sdhci_msm_get_max_clock(struct sdhci_host *host)
1230 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1231 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1232 struct clk *core_clk = msm_host->bulk_clks[0].clk;
1234 return clk_round_rate(core_clk, ULONG_MAX);
1237 static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host)
1239 return SDHCI_MSM_MIN_CLOCK;
1243 * __sdhci_msm_set_clock - sdhci_msm clock control.
1246 * MSM controller does not use internal divider and
1247 * instead directly control the GCC clock as per
1248 * HW recommendation.
1250 static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
1254 * Keep actual_clock as zero -
1255 * - since there is no divider used so no need of having actual_clock.
1256 * - MSM controller uses SDCLK for data timeout calculation. If
1257 * actual_clock is zero, host->clock is taken for calculation.
1259 host->mmc->actual_clock = 0;
1261 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1267 * MSM controller do not use clock divider.
1268 * Thus read SDHCI_CLOCK_CONTROL and only enable
1269 * clock with no divider value programmed.
1271 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1272 sdhci_enable_clk(host, clk);
1275 /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
1276 static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
1278 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1279 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1282 msm_host->clk_rate = clock;
1286 sdhci_msm_hc_select_mode(host);
1288 msm_set_clock_rate_for_bus_mode(host, clock);
1290 __sdhci_msm_set_clock(host, clock);
1294 * Platform specific register write functions. This is so that, if any
1295 * register write needs to be followed up by platform specific actions,
1296 * they can be added here. These functions can go to sleep when writes
1297 * to certain registers are done.
1298 * These functions are relying on sdhci_set_ios not using spinlock.
1300 static int __sdhci_msm_check_write(struct sdhci_host *host, u16 val, int reg)
1302 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1303 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1307 case SDHCI_HOST_CONTROL2:
1308 req_type = (val & SDHCI_CTRL_VDD_180) ? REQ_IO_LOW :
1311 case SDHCI_SOFTWARE_RESET:
1312 if (host->pwr && (val & SDHCI_RESET_ALL))
1313 req_type = REQ_BUS_OFF;
1315 case SDHCI_POWER_CONTROL:
1316 req_type = !val ? REQ_BUS_OFF : REQ_BUS_ON;
1321 msm_host->pwr_irq_flag = 0;
1323 * Since this register write may trigger a power irq, ensure
1324 * all previous register writes are complete by this point.
1331 /* This function may sleep*/
1332 static void sdhci_msm_writew(struct sdhci_host *host, u16 val, int reg)
1336 req_type = __sdhci_msm_check_write(host, val, reg);
1337 writew_relaxed(val, host->ioaddr + reg);
1340 sdhci_msm_check_power_status(host, req_type);
1343 /* This function may sleep*/
1344 static void sdhci_msm_writeb(struct sdhci_host *host, u8 val, int reg)
1348 req_type = __sdhci_msm_check_write(host, val, reg);
1350 writeb_relaxed(val, host->ioaddr + reg);
1353 sdhci_msm_check_power_status(host, req_type);
1356 static void sdhci_msm_set_regulator_caps(struct sdhci_msm_host *msm_host)
1358 struct mmc_host *mmc = msm_host->mmc;
1359 struct regulator *supply = mmc->supply.vqmmc;
1360 u32 caps = 0, config;
1361 struct sdhci_host *host = mmc_priv(mmc);
1363 if (!IS_ERR(mmc->supply.vqmmc)) {
1364 if (regulator_is_supported_voltage(supply, 1700000, 1950000))
1365 caps |= CORE_1_8V_SUPPORT;
1366 if (regulator_is_supported_voltage(supply, 2700000, 3600000))
1367 caps |= CORE_3_0V_SUPPORT;
1370 pr_warn("%s: 1.8/3V not supported for vqmmc\n",
1376 * Set the PAD_PWR_SWITCH_EN bit so that the PAD_PWR_SWITCH
1377 * bit can be used as required later on.
1379 u32 io_level = msm_host->curr_io_level;
1381 config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
1382 config |= CORE_IO_PAD_PWR_SWITCH_EN;
1384 if ((io_level & REQ_IO_HIGH) && (caps & CORE_3_0V_SUPPORT))
1385 config &= ~CORE_IO_PAD_PWR_SWITCH;
1386 else if ((io_level & REQ_IO_LOW) || (caps & CORE_1_8V_SUPPORT))
1387 config |= CORE_IO_PAD_PWR_SWITCH;
1389 writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
1391 msm_host->caps_0 |= caps;
1392 pr_debug("%s: supported caps: 0x%08x\n", mmc_hostname(mmc), caps);
1395 static const struct of_device_id sdhci_msm_dt_match[] = {
1396 { .compatible = "qcom,sdhci-msm-v4" },
1400 MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match);
1402 static const struct sdhci_ops sdhci_msm_ops = {
1403 .reset = sdhci_reset,
1404 .set_clock = sdhci_msm_set_clock,
1405 .get_min_clock = sdhci_msm_get_min_clock,
1406 .get_max_clock = sdhci_msm_get_max_clock,
1407 .set_bus_width = sdhci_set_bus_width,
1408 .set_uhs_signaling = sdhci_msm_set_uhs_signaling,
1409 .write_w = sdhci_msm_writew,
1410 .write_b = sdhci_msm_writeb,
1413 static const struct sdhci_pltfm_data sdhci_msm_pdata = {
1414 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
1415 SDHCI_QUIRK_SINGLE_POWER_WRITE |
1416 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1417 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1418 .ops = &sdhci_msm_ops,
1421 static int sdhci_msm_probe(struct platform_device *pdev)
1423 struct sdhci_host *host;
1424 struct sdhci_pltfm_host *pltfm_host;
1425 struct sdhci_msm_host *msm_host;
1426 struct resource *core_memres;
1429 u16 host_version, core_minor;
1430 u32 core_version, config;
1433 host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host));
1435 return PTR_ERR(host);
1437 host->sdma_boundary = 0;
1438 pltfm_host = sdhci_priv(host);
1439 msm_host = sdhci_pltfm_priv(pltfm_host);
1440 msm_host->mmc = host->mmc;
1441 msm_host->pdev = pdev;
1443 ret = mmc_of_parse(host->mmc);
1447 sdhci_get_of_property(pdev);
1449 msm_host->saved_tuning_phase = INVALID_TUNING_PHASE;
1451 /* Setup SDCC bus voter clock. */
1452 msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
1453 if (!IS_ERR(msm_host->bus_clk)) {
1454 /* Vote for max. clk rate for max. performance */
1455 ret = clk_set_rate(msm_host->bus_clk, INT_MAX);
1458 ret = clk_prepare_enable(msm_host->bus_clk);
1463 /* Setup main peripheral bus clock */
1464 clk = devm_clk_get(&pdev->dev, "iface");
1467 dev_err(&pdev->dev, "Peripheral clk setup failed (%d)\n", ret);
1468 goto bus_clk_disable;
1470 msm_host->bulk_clks[1].clk = clk;
1472 /* Setup SDC MMC clock */
1473 clk = devm_clk_get(&pdev->dev, "core");
1476 dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret);
1477 goto bus_clk_disable;
1479 msm_host->bulk_clks[0].clk = clk;
1481 /* Vote for maximum clock rate for maximum performance */
1482 ret = clk_set_rate(clk, INT_MAX);
1484 dev_warn(&pdev->dev, "core clock boost failed\n");
1486 clk = devm_clk_get(&pdev->dev, "cal");
1489 msm_host->bulk_clks[2].clk = clk;
1491 clk = devm_clk_get(&pdev->dev, "sleep");
1494 msm_host->bulk_clks[3].clk = clk;
1496 ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks),
1497 msm_host->bulk_clks);
1499 goto bus_clk_disable;
1502 * xo clock is needed for FLL feature of cm_dll.
1503 * In case if xo clock is not mentioned in DT, warn and proceed.
1505 msm_host->xo_clk = devm_clk_get(&pdev->dev, "xo");
1506 if (IS_ERR(msm_host->xo_clk)) {
1507 ret = PTR_ERR(msm_host->xo_clk);
1508 dev_warn(&pdev->dev, "TCXO clk not present (%d)\n", ret);
1511 core_memres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1512 msm_host->core_mem = devm_ioremap_resource(&pdev->dev, core_memres);
1514 if (IS_ERR(msm_host->core_mem)) {
1515 dev_err(&pdev->dev, "Failed to remap registers\n");
1516 ret = PTR_ERR(msm_host->core_mem);
1520 /* Reset the vendor spec register to power on reset state */
1521 writel_relaxed(CORE_VENDOR_SPEC_POR_VAL,
1522 host->ioaddr + CORE_VENDOR_SPEC);
1524 /* Set HC_MODE_EN bit in HC_MODE register */
1525 writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE));
1527 config = readl_relaxed(msm_host->core_mem + CORE_HC_MODE);
1528 config |= FF_CLK_SW_RST_DIS;
1529 writel_relaxed(config, msm_host->core_mem + CORE_HC_MODE);
1531 host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
1532 dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n",
1533 host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >>
1534 SDHCI_VENDOR_VER_SHIFT));
1536 core_version = readl_relaxed(msm_host->core_mem + CORE_MCI_VERSION);
1537 core_major = (core_version & CORE_VERSION_MAJOR_MASK) >>
1538 CORE_VERSION_MAJOR_SHIFT;
1539 core_minor = core_version & CORE_VERSION_MINOR_MASK;
1540 dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n",
1541 core_version, core_major, core_minor);
1543 if (core_major == 1 && core_minor >= 0x42)
1544 msm_host->use_14lpp_dll_reset = true;
1547 * SDCC 5 controller with major version 1, minor version 0x34 and later
1548 * with HS 400 mode support will use CM DLL instead of CDC LP 533 DLL.
1550 if (core_major == 1 && core_minor < 0x34)
1551 msm_host->use_cdclp533 = true;
1554 * Support for some capabilities is not advertised by newer
1555 * controller versions and must be explicitly enabled.
1557 if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
1558 config = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES);
1559 config |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
1560 writel_relaxed(config, host->ioaddr +
1561 CORE_VENDOR_SPEC_CAPABILITIES0);
1565 * Power on reset state may trigger power irq if previous status of
1566 * PWRCTL was either BUS_ON or IO_HIGH_V. So before enabling pwr irq
1567 * interrupt in GIC, any pending power irq interrupt should be
1568 * acknowledged. Otherwise power irq interrupt handler would be
1569 * fired prematurely.
1571 sdhci_msm_handle_pwr_irq(host, 0);
1574 * Ensure that above writes are propogated before interrupt enablement
1579 /* Setup IRQ for handling power/voltage tasks with PMIC */
1580 msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq");
1581 if (msm_host->pwr_irq < 0) {
1582 dev_err(&pdev->dev, "Get pwr_irq failed (%d)\n",
1584 ret = msm_host->pwr_irq;
1588 sdhci_msm_init_pwr_irq_wait(msm_host);
1589 /* Enable pwr irq interrupts */
1590 writel_relaxed(INT_MASK, msm_host->core_mem + CORE_PWRCTL_MASK);
1592 ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL,
1593 sdhci_msm_pwr_irq, IRQF_ONESHOT,
1594 dev_name(&pdev->dev), host);
1596 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", ret);
1600 pm_runtime_get_noresume(&pdev->dev);
1601 pm_runtime_set_active(&pdev->dev);
1602 pm_runtime_enable(&pdev->dev);
1603 pm_runtime_set_autosuspend_delay(&pdev->dev,
1604 MSM_MMC_AUTOSUSPEND_DELAY_MS);
1605 pm_runtime_use_autosuspend(&pdev->dev);
1607 host->mmc_host_ops.execute_tuning = sdhci_msm_execute_tuning;
1608 ret = sdhci_add_host(host);
1610 goto pm_runtime_disable;
1611 sdhci_msm_set_regulator_caps(msm_host);
1613 pm_runtime_mark_last_busy(&pdev->dev);
1614 pm_runtime_put_autosuspend(&pdev->dev);
1619 pm_runtime_disable(&pdev->dev);
1620 pm_runtime_set_suspended(&pdev->dev);
1621 pm_runtime_put_noidle(&pdev->dev);
1623 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
1624 msm_host->bulk_clks);
1626 if (!IS_ERR(msm_host->bus_clk))
1627 clk_disable_unprepare(msm_host->bus_clk);
1629 sdhci_pltfm_free(pdev);
1633 static int sdhci_msm_remove(struct platform_device *pdev)
1635 struct sdhci_host *host = platform_get_drvdata(pdev);
1636 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1637 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1638 int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) ==
1641 sdhci_remove_host(host, dead);
1643 pm_runtime_get_sync(&pdev->dev);
1644 pm_runtime_disable(&pdev->dev);
1645 pm_runtime_put_noidle(&pdev->dev);
1647 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
1648 msm_host->bulk_clks);
1649 if (!IS_ERR(msm_host->bus_clk))
1650 clk_disable_unprepare(msm_host->bus_clk);
1651 sdhci_pltfm_free(pdev);
1656 static int sdhci_msm_runtime_suspend(struct device *dev)
1658 struct sdhci_host *host = dev_get_drvdata(dev);
1659 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1660 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1662 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
1663 msm_host->bulk_clks);
1668 static int sdhci_msm_runtime_resume(struct device *dev)
1670 struct sdhci_host *host = dev_get_drvdata(dev);
1671 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1672 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1674 return clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks),
1675 msm_host->bulk_clks);
1679 static const struct dev_pm_ops sdhci_msm_pm_ops = {
1680 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1681 pm_runtime_force_resume)
1682 SET_RUNTIME_PM_OPS(sdhci_msm_runtime_suspend,
1683 sdhci_msm_runtime_resume,
1687 static struct platform_driver sdhci_msm_driver = {
1688 .probe = sdhci_msm_probe,
1689 .remove = sdhci_msm_remove,
1691 .name = "sdhci_msm",
1692 .of_match_table = sdhci_msm_dt_match,
1693 .pm = &sdhci_msm_pm_ops,
1697 module_platform_driver(sdhci_msm_driver);
1699 MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver");
1700 MODULE_LICENSE("GPL v2");