drivers/mmc/host/sdhci-msm.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
   4  *
   5  * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
   6  */
   7
   8 #include <linux/module.h>
   9 #include <linux/of_device.h>
  10 #include <linux/delay.h>
  11 #include <linux/mmc/mmc.h>
  12 #include <linux/pm_runtime.h>
  13 #include <linux/slab.h>
  14 #include <linux/iopoll.h>
  15 #include <linux/regulator/consumer.h>
  16
  17 #include "sdhci-pltfm.h"
  18
  19 #define CORE_MCI_VERSION                0x50
  20 #define CORE_VERSION_MAJOR_SHIFT        28
  21 #define CORE_VERSION_MAJOR_MASK         (0xf << CORE_VERSION_MAJOR_SHIFT)
  22 #define CORE_VERSION_MINOR_MASK         0xff
  23
  24 #define CORE_MCI_GENERICS               0x70
  25 #define SWITCHABLE_SIGNALING_VOLTAGE    BIT(29)
  26
  27 #define HC_MODE_EN              0x1
  28 #define CORE_POWER              0x0
  29 #define CORE_SW_RST             BIT(7)
  30 #define FF_CLK_SW_RST_DIS       BIT(13)
  31
  32 #define CORE_PWRCTL_BUS_OFF     BIT(0)
  33 #define CORE_PWRCTL_BUS_ON      BIT(1)
  34 #define CORE_PWRCTL_IO_LOW      BIT(2)
  35 #define CORE_PWRCTL_IO_HIGH     BIT(3)
  36 #define CORE_PWRCTL_BUS_SUCCESS BIT(0)
  37 #define CORE_PWRCTL_IO_SUCCESS  BIT(2)
  38 #define REQ_BUS_OFF             BIT(0)
  39 #define REQ_BUS_ON              BIT(1)
  40 #define REQ_IO_LOW              BIT(2)
  41 #define REQ_IO_HIGH             BIT(3)
  42 #define INT_MASK                0xf
  43 #define MAX_PHASES              16
  44 #define CORE_DLL_LOCK           BIT(7)
  45 #define CORE_DDR_DLL_LOCK       BIT(11)
  46 #define CORE_DLL_EN             BIT(16)
  47 #define CORE_CDR_EN             BIT(17)
  48 #define CORE_CK_OUT_EN          BIT(18)
  49 #define CORE_CDR_EXT_EN         BIT(19)
  50 #define CORE_DLL_PDN            BIT(29)
  51 #define CORE_DLL_RST            BIT(30)
  52 #define CORE_CMD_DAT_TRACK_SEL  BIT(0)
  53
  54 #define CORE_DDR_CAL_EN         BIT(0)
  55 #define CORE_FLL_CYCLE_CNT      BIT(18)
  56 #define CORE_DLL_CLOCK_DISABLE  BIT(21)
  57
  58 #define CORE_VENDOR_SPEC_POR_VAL 0xa1c
  59 #define CORE_CLK_PWRSAVE        BIT(1)
  60 #define CORE_HC_MCLK_SEL_DFLT   (2 << 8)
  61 #define CORE_HC_MCLK_SEL_HS400  (3 << 8)
  62 #define CORE_HC_MCLK_SEL_MASK   (3 << 8)
  63 #define CORE_IO_PAD_PWR_SWITCH_EN       (1 << 15)
  64 #define CORE_IO_PAD_PWR_SWITCH  (1 << 16)
  65 #define CORE_HC_SELECT_IN_EN    BIT(18)
  66 #define CORE_HC_SELECT_IN_HS400 (6 << 19)
  67 #define CORE_HC_SELECT_IN_MASK  (7 << 19)
  68
  69 #define CORE_3_0V_SUPPORT       (1 << 25)
  70 #define CORE_1_8V_SUPPORT       (1 << 26)
  71 #define CORE_VOLT_SUPPORT       (CORE_3_0V_SUPPORT | CORE_1_8V_SUPPORT)
  72
  73 #define CORE_CSR_CDC_CTLR_CFG0          0x130
  74 #define CORE_SW_TRIG_FULL_CALIB         BIT(16)
  75 #define CORE_HW_AUTOCAL_ENA             BIT(17)
  76
  77 #define CORE_CSR_CDC_CTLR_CFG1          0x134
  78 #define CORE_CSR_CDC_CAL_TIMER_CFG0     0x138
  79 #define CORE_TIMER_ENA                  BIT(16)
  80
  81 #define CORE_CSR_CDC_CAL_TIMER_CFG1     0x13C
  82 #define CORE_CSR_CDC_REFCOUNT_CFG       0x140
  83 #define CORE_CSR_CDC_COARSE_CAL_CFG     0x144
  84 #define CORE_CDC_OFFSET_CFG             0x14C
  85 #define CORE_CSR_CDC_DELAY_CFG          0x150
  86 #define CORE_CDC_SLAVE_DDA_CFG          0x160
  87 #define CORE_CSR_CDC_STATUS0            0x164
  88 #define CORE_CALIBRATION_DONE           BIT(0)
  89
  90 #define CORE_CDC_ERROR_CODE_MASK        0x7000000
  91
  92 #define CORE_CSR_CDC_GEN_CFG            0x178
  93 #define CORE_CDC_SWITCH_BYPASS_OFF      BIT(0)
  94 #define CORE_CDC_SWITCH_RC_EN           BIT(1)
  95
  96 #define CORE_CDC_T4_DLY_SEL             BIT(0)
  97 #define CORE_CMDIN_RCLK_EN              BIT(1)
  98 #define CORE_START_CDC_TRAFFIC          BIT(6)
  99
 100 #define CORE_PWRSAVE_DLL        BIT(3)
 101
 102 #define DDR_CONFIG_POR_VAL      0x80040853
 103
 104
 105 #define INVALID_TUNING_PHASE    -1
 106 #define SDHCI_MSM_MIN_CLOCK     400000
 107 #define CORE_FREQ_100MHZ        (100 * 1000 * 1000)
 108
 109 #define CDR_SELEXT_SHIFT        20
 110 #define CDR_SELEXT_MASK         (0xf << CDR_SELEXT_SHIFT)
 111 #define CMUX_SHIFT_PHASE_SHIFT  24
 112 #define CMUX_SHIFT_PHASE_MASK   (7 << CMUX_SHIFT_PHASE_SHIFT)
 113
 114 #define MSM_MMC_AUTOSUSPEND_DELAY_MS    50
 115
 116 /* Timeout value to avoid infinite waiting for pwr_irq */
 117 #define MSM_PWR_IRQ_TIMEOUT_MS 5000
 118
 119 #define msm_host_readl(msm_host, host, offset) \
 120         msm_host->var_ops->msm_readl_relaxed(host, offset)
 121
 122 #define msm_host_writel(msm_host, val, host, offset) \
 123         msm_host->var_ops->msm_writel_relaxed(val, host, offset)
 124
 125 struct sdhci_msm_offset {
 126         u32 core_hc_mode;
 127         u32 core_mci_data_cnt;
 128         u32 core_mci_status;
 129         u32 core_mci_fifo_cnt;
 130         u32 core_mci_version;
 131         u32 core_generics;
 132         u32 core_testbus_config;
 133         u32 core_testbus_sel2_bit;
 134         u32 core_testbus_ena;
 135         u32 core_testbus_sel2;
 136         u32 core_pwrctl_status;
 137         u32 core_pwrctl_mask;
 138         u32 core_pwrctl_clear;
 139         u32 core_pwrctl_ctl;
 140         u32 core_sdcc_debug_reg;
 141         u32 core_dll_config;
 142         u32 core_dll_status;
 143         u32 core_vendor_spec;
 144         u32 core_vendor_spec_adma_err_addr0;
 145         u32 core_vendor_spec_adma_err_addr1;
 146         u32 core_vendor_spec_func2;
 147         u32 core_vendor_spec_capabilities0;
 148         u32 core_ddr_200_cfg;
 149         u32 core_vendor_spec3;
 150         u32 core_dll_config_2;
 151         u32 core_ddr_config;
 152         u32 core_ddr_config_2;
 153 };
 154
 155 static const struct sdhci_msm_offset sdhci_msm_v5_offset = {
 156         .core_mci_data_cnt = 0x35c,
 157         .core_mci_status = 0x324,
 158         .core_mci_fifo_cnt = 0x308,
 159         .core_mci_version = 0x318,
 160         .core_generics = 0x320,
 161         .core_testbus_config = 0x32c,
 162         .core_testbus_sel2_bit = 3,
 163         .core_testbus_ena = (1 << 31),
 164         .core_testbus_sel2 = (1 << 3),
 165         .core_pwrctl_status = 0x240,
 166         .core_pwrctl_mask = 0x244,
 167         .core_pwrctl_clear = 0x248,
 168         .core_pwrctl_ctl = 0x24c,
 169         .core_sdcc_debug_reg = 0x358,
 170         .core_dll_config = 0x200,
 171         .core_dll_status = 0x208,
 172         .core_vendor_spec = 0x20c,
 173         .core_vendor_spec_adma_err_addr0 = 0x214,
 174         .core_vendor_spec_adma_err_addr1 = 0x218,
 175         .core_vendor_spec_func2 = 0x210,
 176         .core_vendor_spec_capabilities0 = 0x21c,
 177         .core_ddr_200_cfg = 0x224,
 178         .core_vendor_spec3 = 0x250,
 179         .core_dll_config_2 = 0x254,
 180         .core_ddr_config = 0x258,
 181         .core_ddr_config_2 = 0x25c,
 182 };
 183
 184 static const struct sdhci_msm_offset sdhci_msm_mci_offset = {
 185         .core_hc_mode = 0x78,
 186         .core_mci_data_cnt = 0x30,
 187         .core_mci_status = 0x34,
 188         .core_mci_fifo_cnt = 0x44,
 189         .core_mci_version = 0x050,
 190         .core_generics = 0x70,
 191         .core_testbus_config = 0x0cc,
 192         .core_testbus_sel2_bit = 4,
 193         .core_testbus_ena = (1 << 3),
 194         .core_testbus_sel2 = (1 << 4),
 195         .core_pwrctl_status = 0xdc,
 196         .core_pwrctl_mask = 0xe0,
 197         .core_pwrctl_clear = 0xe4,
 198         .core_pwrctl_ctl = 0xe8,
 199         .core_sdcc_debug_reg = 0x124,
 200         .core_dll_config = 0x100,
 201         .core_dll_status = 0x108,
 202         .core_vendor_spec = 0x10c,
 203         .core_vendor_spec_adma_err_addr0 = 0x114,
 204         .core_vendor_spec_adma_err_addr1 = 0x118,
 205         .core_vendor_spec_func2 = 0x110,
 206         .core_vendor_spec_capabilities0 = 0x11c,
 207         .core_ddr_200_cfg = 0x184,
 208         .core_vendor_spec3 = 0x1b0,
 209         .core_dll_config_2 = 0x1b4,
 210         .core_ddr_config = 0x1b8,
 211         .core_ddr_config_2 = 0x1bc,
 212 };
 213
 214 struct sdhci_msm_variant_ops {
 215         u32 (*msm_readl_relaxed)(struct sdhci_host *host, u32 offset);
 216         void (*msm_writel_relaxed)(u32 val, struct sdhci_host *host,
 217                         u32 offset);
 218 };
 219
 220 /*
 221  * From V5, register spaces have changed. Wrap this info in a structure
 222  * and choose the data_structure based on version info mentioned in DT.
 223  */
 224 struct sdhci_msm_variant_info {
 225         bool mci_removed;
 226         bool restore_dll_config;
 227         const struct sdhci_msm_variant_ops *var_ops;
 228         const struct sdhci_msm_offset *offset;
 229 };
 230
 231 struct sdhci_msm_host {
 232         struct platform_device *pdev;
 233         void __iomem *core_mem; /* MSM SDCC mapped address */
 234         int pwr_irq;            /* power irq */
 235         struct clk *bus_clk;    /* SDHC bus voter clock */
 236         struct clk *xo_clk;     /* TCXO clk needed for FLL feature of cm_dll*/
 237         struct clk_bulk_data bulk_clks[4]; /* core, iface, cal, sleep clocks */
 238         unsigned long clk_rate;
 239         struct mmc_host *mmc;
 240         bool use_14lpp_dll_reset;
 241         bool tuning_done;
 242         bool calibration_done;
 243         u8 saved_tuning_phase;
 244         bool use_cdclp533;
 245         u32 curr_pwr_state;
 246         u32 curr_io_level;
 247         wait_queue_head_t pwr_irq_wait;
 248         bool pwr_irq_flag;
 249         u32 caps_0;
 250         bool mci_removed;
 251         bool restore_dll_config;
 252         const struct sdhci_msm_variant_ops *var_ops;
 253         const struct sdhci_msm_offset *offset;
 254         bool use_cdr;
 255         u32 transfer_mode;
 256 };
 257
 258 static const struct sdhci_msm_offset *sdhci_priv_msm_offset(struct sdhci_host *host)
 259 {
 260         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 261         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 262
 263         return msm_host->offset;
 264 }
 265
 266 /*
 267  * APIs to read/write to vendor specific registers which were there in the
 268  * core_mem region before MCI was removed.
 269  */
 270 static u32 sdhci_msm_mci_variant_readl_relaxed(struct sdhci_host *host,
 271                 u32 offset)
 272 {
 273         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 274         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 275
 276         return readl_relaxed(msm_host->core_mem + offset);
 277 }
 278
 279 static u32 sdhci_msm_v5_variant_readl_relaxed(struct sdhci_host *host,
 280                 u32 offset)
 281 {
 282         return readl_relaxed(host->ioaddr + offset);
 283 }
 284
 285 static void sdhci_msm_mci_variant_writel_relaxed(u32 val,
 286                 struct sdhci_host *host, u32 offset)
 287 {
 288         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 289         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 290
 291         writel_relaxed(val, msm_host->core_mem + offset);
 292 }
 293
 294 static void sdhci_msm_v5_variant_writel_relaxed(u32 val,
 295                 struct sdhci_host *host, u32 offset)
 296 {
 297         writel_relaxed(val, host->ioaddr + offset);
 298 }
 299
 300 static unsigned int msm_get_clock_rate_for_bus_mode(struct sdhci_host *host,
 301                                                     unsigned int clock)
 302 {
 303         struct mmc_ios ios = host->mmc->ios;
 304         /*
 305          * The SDHC requires internal clock frequency to be double the
 306          * actual clock that will be set for DDR mode. The controller
 307          * uses the faster clock(100/400MHz) for some of its parts and
 308          * send the actual required clock (50/200MHz) to the card.
 309          */
 310         if (ios.timing == MMC_TIMING_UHS_DDR50 ||
 311             ios.timing == MMC_TIMING_MMC_DDR52 ||
 312             ios.timing == MMC_TIMING_MMC_HS400 ||
 313             host->flags & SDHCI_HS400_TUNING)
 314                 clock *= 2;
 315         return clock;
 316 }
 317
 318 static void msm_set_clock_rate_for_bus_mode(struct sdhci_host *host,
 319                                             unsigned int clock)
 320 {
 321         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 322         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 323         struct mmc_ios curr_ios = host->mmc->ios;
 324         struct clk *core_clk = msm_host->bulk_clks[0].clk;
 325         int rc;
 326
 327         clock = msm_get_clock_rate_for_bus_mode(host, clock);
 328         rc = clk_set_rate(core_clk, clock);
 329         if (rc) {
 330                 pr_err("%s: Failed to set clock at rate %u at timing %d\n",
 331                        mmc_hostname(host->mmc), clock,
 332                        curr_ios.timing);
 333                 return;
 334         }
 335         msm_host->clk_rate = clock;
 336         pr_debug("%s: Setting clock at rate %lu at timing %d\n",
 337                  mmc_hostname(host->mmc), clk_get_rate(core_clk),
 338                  curr_ios.timing);
 339 }
 340
 341 /* Platform specific tuning */
 342 static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, u8 poll)
 343 {
 344         u32 wait_cnt = 50;
 345         u8 ck_out_en;
 346         struct mmc_host *mmc = host->mmc;
 347         const struct sdhci_msm_offset *msm_offset =
 348                                         sdhci_priv_msm_offset(host);
 349
 350         /* Poll for CK_OUT_EN bit.  max. poll time = 50us */
 351         ck_out_en = !!(readl_relaxed(host->ioaddr +
 352                         msm_offset->core_dll_config) & CORE_CK_OUT_EN);
 353
 354         while (ck_out_en != poll) {
 355                 if (--wait_cnt == 0) {
 356                         dev_err(mmc_dev(mmc), "%s: CK_OUT_EN bit is not %d\n",
 357                                mmc_hostname(mmc), poll);
 358                         return -ETIMEDOUT;
 359                 }
 360                 udelay(1);
 361
 362                 ck_out_en = !!(readl_relaxed(host->ioaddr +
 363                         msm_offset->core_dll_config) & CORE_CK_OUT_EN);
 364         }
 365
 366         return 0;
 367 }
 368
 369 static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase)
 370 {
 371         int rc;
 372         static const u8 grey_coded_phase_table[] = {
 373                 0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4,
 374                 0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8
 375         };
 376         unsigned long flags;
 377         u32 config;
 378         struct mmc_host *mmc = host->mmc;
 379         const struct sdhci_msm_offset *msm_offset =
 380                                         sdhci_priv_msm_offset(host);
 381
 382         if (phase > 0xf)
 383                 return -EINVAL;
 384
 385         spin_lock_irqsave(&host->lock, flags);
 386
 387         config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
 388         config &= ~(CORE_CDR_EN | CORE_CK_OUT_EN);
 389         config |= (CORE_CDR_EXT_EN | CORE_DLL_EN);
 390         writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
 391
 392         /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */
 393         rc = msm_dll_poll_ck_out_en(host, 0);
 394         if (rc)
 395                 goto err_out;
 396
 397         /*
 398          * Write the selected DLL clock output phase (0 ... 15)
 399          * to CDR_SELEXT bit field of DLL_CONFIG register.
 400          */
 401         config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
 402         config &= ~CDR_SELEXT_MASK;
 403         config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT;
 404         writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
 405
 406         config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
 407         config |= CORE_CK_OUT_EN;
 408         writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
 409
 410         /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */
 411         rc = msm_dll_poll_ck_out_en(host, 1);
 412         if (rc)
 413                 goto err_out;
 414
 415         config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
 416         config |= CORE_CDR_EN;
 417         config &= ~CORE_CDR_EXT_EN;
 418         writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
 419         goto out;
 420
 421 err_out:
 422         dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n",
 423                mmc_hostname(mmc), phase);
 424 out:
 425         spin_unlock_irqrestore(&host->lock, flags);
 426         return rc;
 427 }
 428
 429 /*
 430  * Find out the greatest range of consecuitive selected
 431  * DLL clock output phases that can be used as sampling
 432  * setting for SD3.0 UHS-I card read operation (in SDR104
 433  * timing mode) or for eMMC4.5 card read operation (in
 434  * HS400/HS200 timing mode).
 435  * Select the 3/4 of the range and configure the DLL with the
 436  * selected DLL clock output phase.
 437  */
 438
 439 static int msm_find_most_appropriate_phase(struct sdhci_host *host,
 440                                            u8 *phase_table, u8 total_phases)
 441 {
 442         int ret;
 443         u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} };
 444         u8 phases_per_row[MAX_PHASES] = { 0 };
 445         int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0;
 446         int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0;
 447         bool phase_0_found = false, phase_15_found = false;
 448         struct mmc_host *mmc = host->mmc;
 449
 450         if (!total_phases || (total_phases > MAX_PHASES)) {
 451                 dev_err(mmc_dev(mmc), "%s: Invalid argument: total_phases=%d\n",
 452                        mmc_hostname(mmc), total_phases);
 453                 return -EINVAL;
 454         }
 455
 456         for (cnt = 0; cnt < total_phases; cnt++) {
 457                 ranges[row_index][col_index] = phase_table[cnt];
 458                 phases_per_row[row_index] += 1;
 459                 col_index++;
 460
 461                 if ((cnt + 1) == total_phases) {
 462                         continue;
 463                 /* check if next phase in phase_table is consecutive or not */
 464                 } else if ((phase_table[cnt] + 1) != phase_table[cnt + 1]) {
 465                         row_index++;
 466                         col_index = 0;
 467                 }
 468         }
 469
 470         if (row_index >= MAX_PHASES)
 471                 return -EINVAL;
 472
 473         /* Check if phase-0 is present in first valid window? */
 474         if (!ranges[0][0]) {
 475                 phase_0_found = true;
 476                 phase_0_raw_index = 0;
 477                 /* Check if cycle exist between 2 valid windows */
 478                 for (cnt = 1; cnt <= row_index; cnt++) {
 479                         if (phases_per_row[cnt]) {
 480                                 for (i = 0; i < phases_per_row[cnt]; i++) {
 481                                         if (ranges[cnt][i] == 15) {
 482                                                 phase_15_found = true;
 483                                                 phase_15_raw_index = cnt;
 484                                                 break;
 485                                         }
 486                                 }
 487                         }
 488                 }
 489         }
 490
 491         /* If 2 valid windows form cycle then merge them as single window */
 492         if (phase_0_found && phase_15_found) {
 493                 /* number of phases in raw where phase 0 is present */
 494                 u8 phases_0 = phases_per_row[phase_0_raw_index];
 495                 /* number of phases in raw where phase 15 is present */
 496                 u8 phases_15 = phases_per_row[phase_15_raw_index];
 497
 498                 if (phases_0 + phases_15 >= MAX_PHASES)
 499                         /*
 500                          * If there are more than 1 phase windows then total
 501                          * number of phases in both the windows should not be
 502                          * more than or equal to MAX_PHASES.
 503                          */
 504                         return -EINVAL;
 505
 506                 /* Merge 2 cyclic windows */
 507                 i = phases_15;
 508                 for (cnt = 0; cnt < phases_0; cnt++) {
 509                         ranges[phase_15_raw_index][i] =
 510                             ranges[phase_0_raw_index][cnt];
 511                         if (++i >= MAX_PHASES)
 512                                 break;
 513                 }
 514
 515                 phases_per_row[phase_0_raw_index] = 0;
 516                 phases_per_row[phase_15_raw_index] = phases_15 + phases_0;
 517         }
 518
 519         for (cnt = 0; cnt <= row_index; cnt++) {
 520                 if (phases_per_row[cnt] > curr_max) {
 521                         curr_max = phases_per_row[cnt];
 522                         selected_row_index = cnt;
 523                 }
 524         }
 525
 526         i = (curr_max * 3) / 4;
 527         if (i)
 528                 i--;
 529
 530         ret = ranges[selected_row_index][i];
 531
 532         if (ret >= MAX_PHASES) {
 533                 ret = -EINVAL;
 534                 dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n",
 535                        mmc_hostname(mmc), ret);
 536         }
 537
 538         return ret;
 539 }
 540
 541 static inline void msm_cm_dll_set_freq(struct sdhci_host *host)
 542 {
 543         u32 mclk_freq = 0, config;
 544         const struct sdhci_msm_offset *msm_offset =
 545                                         sdhci_priv_msm_offset(host);
 546
 547         /* Program the MCLK value to MCLK_FREQ bit field */
 548         if (host->clock <= 112000000)
 549                 mclk_freq = 0;
 550         else if (host->clock <= 125000000)
 551                 mclk_freq = 1;
 552         else if (host->clock <= 137000000)
 553                 mclk_freq = 2;
 554         else if (host->clock <= 150000000)
 555                 mclk_freq = 3;
 556         else if (host->clock <= 162000000)
 557                 mclk_freq = 4;
 558         else if (host->clock <= 175000000)
 559                 mclk_freq = 5;
 560         else if (host->clock <= 187000000)
 561                 mclk_freq = 6;
 562         else if (host->clock <= 200000000)
 563                 mclk_freq = 7;
 564
 565         config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
 566         config &= ~CMUX_SHIFT_PHASE_MASK;
 567         config |= mclk_freq << CMUX_SHIFT_PHASE_SHIFT;
 568         writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
 569 }
 570
 571 /* Initialize the DLL (Programmable Delay Line) */
 572 static int msm_init_cm_dll(struct sdhci_host *host)
 573 {
 574         struct mmc_host *mmc = host->mmc;
 575         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 576         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 577         int wait_cnt = 50;
 578         unsigned long flags;
 579         u32 config;
 580         const struct sdhci_msm_offset *msm_offset =
 581                                         msm_host->offset;
 582
 583         spin_lock_irqsave(&host->lock, flags);
 584
 585         /*
 586          * Make sure that clock is always enabled when DLL
 587          * tuning is in progress. Keeping PWRSAVE ON may
 588          * turn off the clock.
 589          */
 590         config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
 591         config &= ~CORE_CLK_PWRSAVE;
 592         writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
 593
 594         if (msm_host->use_14lpp_dll_reset) {
 595                 config = readl_relaxed(host->ioaddr +
 596                                 msm_offset->core_dll_config);
 597                 config &= ~CORE_CK_OUT_EN;
 598                 writel_relaxed(config, host->ioaddr +
 599                                 msm_offset->core_dll_config);
 600
 601                 config = readl_relaxed(host->ioaddr +
 602                                 msm_offset->core_dll_config_2);
 603                 config |= CORE_DLL_CLOCK_DISABLE;
 604                 writel_relaxed(config, host->ioaddr +
 605                                 msm_offset->core_dll_config_2);
 606         }
 607
 608         config = readl_relaxed(host->ioaddr +
 609                         msm_offset->core_dll_config);
 610         config |= CORE_DLL_RST;
 611         writel_relaxed(config, host->ioaddr +
 612                         msm_offset->core_dll_config);
 613
 614         config = readl_relaxed(host->ioaddr +
 615                         msm_offset->core_dll_config);
 616         config |= CORE_DLL_PDN;
 617         writel_relaxed(config, host->ioaddr +
 618                         msm_offset->core_dll_config);
 619         msm_cm_dll_set_freq(host);
 620
 621         if (msm_host->use_14lpp_dll_reset &&
 622             !IS_ERR_OR_NULL(msm_host->xo_clk)) {
 623                 u32 mclk_freq = 0;
 624
 625                 config = readl_relaxed(host->ioaddr +
 626                                 msm_offset->core_dll_config_2);
 627                 config &= CORE_FLL_CYCLE_CNT;
 628                 if (config)
 629                         mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 8),
 630                                         clk_get_rate(msm_host->xo_clk));
 631                 else
 632                         mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 4),
 633                                         clk_get_rate(msm_host->xo_clk));
 634
 635                 config = readl_relaxed(host->ioaddr +
 636                                 msm_offset->core_dll_config_2);
 637                 config &= ~(0xFF << 10);
 638                 config |= mclk_freq << 10;
 639
 640                 writel_relaxed(config, host->ioaddr +
 641                                 msm_offset->core_dll_config_2);
 642                 /* wait for 5us before enabling DLL clock */
 643                 udelay(5);
 644         }
 645
 646         config = readl_relaxed(host->ioaddr +
 647                         msm_offset->core_dll_config);
 648         config &= ~CORE_DLL_RST;
 649         writel_relaxed(config, host->ioaddr +
 650                         msm_offset->core_dll_config);
 651
 652         config = readl_relaxed(host->ioaddr +
 653                         msm_offset->core_dll_config);
 654         config &= ~CORE_DLL_PDN;
 655         writel_relaxed(config, host->ioaddr +
 656                         msm_offset->core_dll_config);
 657
 658         if (msm_host->use_14lpp_dll_reset) {
 659                 msm_cm_dll_set_freq(host);
 660                 config = readl_relaxed(host->ioaddr +
 661                                 msm_offset->core_dll_config_2);
 662                 config &= ~CORE_DLL_CLOCK_DISABLE;
 663                 writel_relaxed(config, host->ioaddr +
 664                                 msm_offset->core_dll_config_2);
 665         }
 666
 667         config = readl_relaxed(host->ioaddr +
 668                         msm_offset->core_dll_config);
 669         config |= CORE_DLL_EN;
 670         writel_relaxed(config, host->ioaddr +
 671                         msm_offset->core_dll_config);
 672
 673         config = readl_relaxed(host->ioaddr +
 674                         msm_offset->core_dll_config);
 675         config |= CORE_CK_OUT_EN;
 676         writel_relaxed(config, host->ioaddr +
 677                         msm_offset->core_dll_config);
 678
 679         /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */
 680         while (!(readl_relaxed(host->ioaddr + msm_offset->core_dll_status) &
 681                  CORE_DLL_LOCK)) {
 682                 /* max. wait for 50us sec for LOCK bit to be set */
 683                 if (--wait_cnt == 0) {
 684                         dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n",
 685                                mmc_hostname(mmc));
 686                         spin_unlock_irqrestore(&host->lock, flags);
 687                         return -ETIMEDOUT;
 688                 }
 689                 udelay(1);
 690         }
 691
 692         spin_unlock_irqrestore(&host->lock, flags);
 693         return 0;
 694 }
 695
 696 static void msm_hc_select_default(struct sdhci_host *host)
 697 {
 698         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 699         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 700         u32 config;
 701         const struct sdhci_msm_offset *msm_offset =
 702                                         msm_host->offset;
 703
 704         if (!msm_host->use_cdclp533) {
 705                 config = readl_relaxed(host->ioaddr +
 706                                 msm_offset->core_vendor_spec3);
 707                 config &= ~CORE_PWRSAVE_DLL;
 708                 writel_relaxed(config, host->ioaddr +
 709                                 msm_offset->core_vendor_spec3);
 710         }
 711
 712         config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
 713         config &= ~CORE_HC_MCLK_SEL_MASK;
 714         config |= CORE_HC_MCLK_SEL_DFLT;
 715         writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
 716
 717         /*
 718          * Disable HC_SELECT_IN to be able to use the UHS mode select
 719          * configuration from Host Control2 register for all other
 720          * modes.
 721          * Write 0 to HC_SELECT_IN and HC_SELECT_IN_EN field
 722          * in VENDOR_SPEC_FUNC
 723          */
 724         config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
 725         config &= ~CORE_HC_SELECT_IN_EN;
 726         config &= ~CORE_HC_SELECT_IN_MASK;
 727         writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
 728
 729         /*
 730          * Make sure above writes impacting free running MCLK are completed
 731          * before changing the clk_rate at GCC.
 732          */
 733         wmb();
 734 }
 735
 736 static void msm_hc_select_hs400(struct sdhci_host *host)
 737 {
 738         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 739         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 740         struct mmc_ios ios = host->mmc->ios;
 741         u32 config, dll_lock;
 742         int rc;
 743         const struct sdhci_msm_offset *msm_offset =
 744                                         msm_host->offset;
 745
 746         /* Select the divided clock (free running MCLK/2) */
 747         config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
 748         config &= ~CORE_HC_MCLK_SEL_MASK;
 749         config |= CORE_HC_MCLK_SEL_HS400;
 750
 751         writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
 752         /*
 753          * Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC
 754          * register
 755          */
 756         if ((msm_host->tuning_done || ios.enhanced_strobe) &&
 757             !msm_host->calibration_done) {
 758                 config = readl_relaxed(host->ioaddr +
 759                                 msm_offset->core_vendor_spec);
 760                 config |= CORE_HC_SELECT_IN_HS400;
 761                 config |= CORE_HC_SELECT_IN_EN;
 762                 writel_relaxed(config, host->ioaddr +
 763                                 msm_offset->core_vendor_spec);
 764         }
 765         if (!msm_host->clk_rate && !msm_host->use_cdclp533) {
 766                 /*
 767                  * Poll on DLL_LOCK or DDR_DLL_LOCK bits in
 768                  * core_dll_status to be set. This should get set
 769                  * within 15 us at 200 MHz.
 770                  */
 771                 rc = readl_relaxed_poll_timeout(host->ioaddr +
 772                                                 msm_offset->core_dll_status,
 773                                                 dll_lock,
 774                                                 (dll_lock &
 775                                                 (CORE_DLL_LOCK |
 776                                                 CORE_DDR_DLL_LOCK)), 10,
 777                                                 1000);
 778                 if (rc == -ETIMEDOUT)
 779                         pr_err("%s: Unable to get DLL_LOCK/DDR_DLL_LOCK, dll_status: 0x%08x\n",
 780                                mmc_hostname(host->mmc), dll_lock);
 781         }
 782         /*
 783          * Make sure above writes impacting free running MCLK are completed
 784          * before changing the clk_rate at GCC.
 785          */
 786         wmb();
 787 }
 788
 789 /*
 790  * sdhci_msm_hc_select_mode :- In general all timing modes are
 791  * controlled via UHS mode select in Host Control2 register.
 792  * eMMC specific HS200/HS400 doesn't have their respective modes
 793  * defined here, hence we use these values.
 794  *
 795  * HS200 - SDR104 (Since they both are equivalent in functionality)
 796  * HS400 - This involves multiple configurations
 797  *              Initially SDR104 - when tuning is required as HS200
 798  *              Then when switching to DDR @ 400MHz (HS400) we use
 799  *              the vendor specific HC_SELECT_IN to control the mode.
 800  *
 801  * In addition to controlling the modes we also need to select the
 802  * correct input clock for DLL depending on the mode.
 803  *
 804  * HS400 - divided clock (free running MCLK/2)
 805  * All other modes - default (free running MCLK)
 806  */
 807 static void sdhci_msm_hc_select_mode(struct sdhci_host *host)
 808 {
 809         struct mmc_ios ios = host->mmc->ios;
 810
 811         if (ios.timing == MMC_TIMING_MMC_HS400 ||
 812             host->flags & SDHCI_HS400_TUNING)
 813                 msm_hc_select_hs400(host);
 814         else
 815                 msm_hc_select_default(host);
 816 }
 817
 818 static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host)
 819 {
 820         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 821         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 822         u32 config, calib_done;
 823         int ret;
 824         const struct sdhci_msm_offset *msm_offset =
 825                                         msm_host->offset;
 826
 827         pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
 828
 829         /*
 830          * Retuning in HS400 (DDR mode) will fail, just reset the
 831          * tuning block and restore the saved tuning phase.
 832          */
 833         ret = msm_init_cm_dll(host);
 834         if (ret)
 835                 goto out;
 836
 837         /* Set the selected phase in delay line hw block */
 838         ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
 839         if (ret)
 840                 goto out;
 841
 842         config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
 843         config |= CORE_CMD_DAT_TRACK_SEL;
 844         writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
 845
 846         config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
 847         config &= ~CORE_CDC_T4_DLY_SEL;
 848         writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
 849
 850         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
 851         config &= ~CORE_CDC_SWITCH_BYPASS_OFF;
 852         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
 853
 854         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
 855         config |= CORE_CDC_SWITCH_RC_EN;
 856         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
 857
 858         config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
 859         config &= ~CORE_START_CDC_TRAFFIC;
 860         writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
 861
 862         /* Perform CDC Register Initialization Sequence */
 863
 864         writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 865         writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1);
 866         writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
 867         writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1);
 868         writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG);
 869         writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG);
 870         writel_relaxed(0x4E2, host->ioaddr + CORE_CSR_CDC_DELAY_CFG);
 871         writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG);
 872         writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG);
 873
 874         /* CDC HW Calibration */
 875
 876         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 877         config |= CORE_SW_TRIG_FULL_CALIB;
 878         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 879
 880         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 881         config &= ~CORE_SW_TRIG_FULL_CALIB;
 882         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 883
 884         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 885         config |= CORE_HW_AUTOCAL_ENA;
 886         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
 887
 888         config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
 889         config |= CORE_TIMER_ENA;
 890         writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
 891
 892         ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_CSR_CDC_STATUS0,
 893                                          calib_done,
 894                                          (calib_done & CORE_CALIBRATION_DONE),
 895                                          1, 50);
 896
 897         if (ret == -ETIMEDOUT) {
 898                 pr_err("%s: %s: CDC calibration was not completed\n",
 899                        mmc_hostname(host->mmc), __func__);
 900                 goto out;
 901         }
 902
 903         ret = readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0)
 904                         & CORE_CDC_ERROR_CODE_MASK;
 905         if (ret) {
 906                 pr_err("%s: %s: CDC error code %d\n",
 907                        mmc_hostname(host->mmc), __func__, ret);
 908                 ret = -EINVAL;
 909                 goto out;
 910         }
 911
 912         config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
 913         config |= CORE_START_CDC_TRAFFIC;
 914         writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
 915 out:
 916         pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
 917                  __func__, ret);
 918         return ret;
 919 }
 920
 921 static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host)
 922 {
 923         struct mmc_host *mmc = host->mmc;
 924         u32 dll_status, config;
 925         int ret;
 926         const struct sdhci_msm_offset *msm_offset =
 927                                         sdhci_priv_msm_offset(host);
 928
 929         pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
 930
 931         /*
 932          * Currently the core_ddr_config register defaults to desired
 933          * configuration on reset. Currently reprogramming the power on
 934          * reset (POR) value in case it might have been modified by
 935          * bootloaders. In the future, if this changes, then the desired
 936          * values will need to be programmed appropriately.
 937          */
 938         writel_relaxed(DDR_CONFIG_POR_VAL, host->ioaddr +
 939                         msm_offset->core_ddr_config);
 940
 941         if (mmc->ios.enhanced_strobe) {
 942                 config = readl_relaxed(host->ioaddr +
 943                                 msm_offset->core_ddr_200_cfg);
 944                 config |= CORE_CMDIN_RCLK_EN;
 945                 writel_relaxed(config, host->ioaddr +
 946                                 msm_offset->core_ddr_200_cfg);
 947         }
 948
 949         config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2);
 950         config |= CORE_DDR_CAL_EN;
 951         writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config_2);
 952
 953         ret = readl_relaxed_poll_timeout(host->ioaddr +
 954                                         msm_offset->core_dll_status,
 955                                         dll_status,
 956                                         (dll_status & CORE_DDR_DLL_LOCK),
 957                                         10, 1000);
 958
 959         if (ret == -ETIMEDOUT) {
 960                 pr_err("%s: %s: CM_DLL_SDC4 calibration was not completed\n",
 961                        mmc_hostname(host->mmc), __func__);
 962                 goto out;
 963         }
 964
 965         config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec3);
 966         config |= CORE_PWRSAVE_DLL;
 967         writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec3);
 968
 969         /*
 970          * Drain writebuffer to ensure above DLL calibration
 971          * and PWRSAVE DLL is enabled.
 972          */
 973         wmb();
 974 out:
 975         pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
 976                  __func__, ret);
 977         return ret;
 978 }
 979
 980 static int sdhci_msm_hs400_dll_calibration(struct sdhci_host *host)
 981 {
 982         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 983         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 984         struct mmc_host *mmc = host->mmc;
 985         int ret;
 986         u32 config;
 987         const struct sdhci_msm_offset *msm_offset =
 988                                         msm_host->offset;
 989
 990         pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
 991
 992         /*
 993          * Retuning in HS400 (DDR mode) will fail, just reset the
 994          * tuning block and restore the saved tuning phase.
 995          */
 996         ret = msm_init_cm_dll(host);
 997         if (ret)
 998                 goto out;
 999
1000         if (!mmc->ios.enhanced_strobe) {
1001                 /* Set the selected phase in delay line hw block */
1002                 ret = msm_config_cm_dll_phase(host,
1003                                               msm_host->saved_tuning_phase);
1004                 if (ret)
1005                         goto out;
1006                 config = readl_relaxed(host->ioaddr +
1007                                 msm_offset->core_dll_config);
1008                 config |= CORE_CMD_DAT_TRACK_SEL;
1009                 writel_relaxed(config, host->ioaddr +
1010                                 msm_offset->core_dll_config);
1011         }
1012
1013         if (msm_host->use_cdclp533)
1014                 ret = sdhci_msm_cdclp533_calibration(host);
1015         else
1016                 ret = sdhci_msm_cm_dll_sdc4_calibration(host);
1017 out:
1018         pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
1019                  __func__, ret);
1020         return ret;
1021 }
1022
1023 static bool sdhci_msm_is_tuning_needed(struct sdhci_host *host)
1024 {
1025         struct mmc_ios *ios = &host->mmc->ios;
1026
1027         /*
1028          * Tuning is required for SDR104, HS200 and HS400 cards and
1029          * if clock frequency is greater than 100MHz in these modes.
1030          */
1031         if (host->clock <= CORE_FREQ_100MHZ ||
1032             !(ios->timing == MMC_TIMING_MMC_HS400 ||
1033             ios->timing == MMC_TIMING_MMC_HS200 ||
1034             ios->timing == MMC_TIMING_UHS_SDR104) ||
1035             ios->enhanced_strobe)
1036                 return false;
1037
1038         return true;
1039 }
1040
1041 static int sdhci_msm_restore_sdr_dll_config(struct sdhci_host *host)
1042 {
1043         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1044         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1045         int ret;
1046
1047         /*
1048          * SDR DLL comes into picture only for timing modes which needs
1049          * tuning.
1050          */
1051         if (!sdhci_msm_is_tuning_needed(host))
1052                 return 0;
1053
1054         /* Reset the tuning block */
1055         ret = msm_init_cm_dll(host);
1056         if (ret)
1057                 return ret;
1058
1059         /* Restore the tuning block */
1060         ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
1061
1062         return ret;
1063 }
1064
1065 static void sdhci_msm_set_cdr(struct sdhci_host *host, bool enable)
1066 {
1067         const struct sdhci_msm_offset *msm_offset = sdhci_priv_msm_offset(host);
1068         u32 config, oldconfig = readl_relaxed(host->ioaddr +
1069                                               msm_offset->core_dll_config);
1070
1071         config = oldconfig;
1072         if (enable) {
1073                 config |= CORE_CDR_EN;
1074                 config &= ~CORE_CDR_EXT_EN;
1075         } else {
1076                 config &= ~CORE_CDR_EN;
1077                 config |= CORE_CDR_EXT_EN;
1078         }
1079
1080         if (config != oldconfig) {
1081                 writel_relaxed(config, host->ioaddr +
1082                                msm_offset->core_dll_config);
1083         }
1084 }
1085
1086 static int sdhci_msm_execute_tuning(struct mmc_host *mmc, u32 opcode)
1087 {
1088         struct sdhci_host *host = mmc_priv(mmc);
1089         int tuning_seq_cnt = 3;
1090         u8 phase, tuned_phases[16], tuned_phase_cnt = 0;
1091         int rc;
1092         struct mmc_ios ios = host->mmc->ios;
1093         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1094         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1095
1096         if (!sdhci_msm_is_tuning_needed(host)) {
1097                 msm_host->use_cdr = false;
1098                 sdhci_msm_set_cdr(host, false);
1099                 return 0;
1100         }
1101
1102         /* Clock-Data-Recovery used to dynamically adjust RX sampling point */
1103         msm_host->use_cdr = true;
1104
1105         /*
1106          * For HS400 tuning in HS200 timing requires:
1107          * - select MCLK/2 in VENDOR_SPEC
1108          * - program MCLK to 400MHz (or nearest supported) in GCC
1109          */
1110         if (host->flags & SDHCI_HS400_TUNING) {
1111                 sdhci_msm_hc_select_mode(host);
1112                 msm_set_clock_rate_for_bus_mode(host, ios.clock);
1113                 host->flags &= ~SDHCI_HS400_TUNING;
1114         }
1115
1116 retry:
1117         /* First of all reset the tuning block */
1118         rc = msm_init_cm_dll(host);
1119         if (rc)
1120                 return rc;
1121
1122         phase = 0;
1123         do {
1124                 /* Set the phase in delay line hw block */
1125                 rc = msm_config_cm_dll_phase(host, phase);
1126                 if (rc)
1127                         return rc;
1128
1129                 rc = mmc_send_tuning(mmc, opcode, NULL);
1130                 if (!rc) {
1131                         /* Tuning is successful at this tuning point */
1132                         tuned_phases[tuned_phase_cnt++] = phase;
1133                         dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n",
1134                                  mmc_hostname(mmc), phase);
1135                 }
1136         } while (++phase < ARRAY_SIZE(tuned_phases));
1137
1138         if (tuned_phase_cnt) {
1139                 rc = msm_find_most_appropriate_phase(host, tuned_phases,
1140                                                      tuned_phase_cnt);
1141                 if (rc < 0)
1142                         return rc;
1143                 else
1144                         phase = rc;
1145
1146                 /*
1147                  * Finally set the selected phase in delay
1148                  * line hw block.
1149                  */
1150                 rc = msm_config_cm_dll_phase(host, phase);
1151                 if (rc)
1152                         return rc;
1153                 msm_host->saved_tuning_phase = phase;
1154                 dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n",
1155                          mmc_hostname(mmc), phase);
1156         } else {
1157                 if (--tuning_seq_cnt)
1158                         goto retry;
1159                 /* Tuning failed */
1160                 dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n",
1161                        mmc_hostname(mmc));
1162                 rc = -EIO;
1163         }
1164
1165         if (!rc)
1166                 msm_host->tuning_done = true;
1167         return rc;
1168 }
1169
1170 /*
1171  * sdhci_msm_hs400 - Calibrate the DLL for HS400 bus speed mode operation.
1172  * This needs to be done for both tuning and enhanced_strobe mode.
1173  * DLL operation is only needed for clock > 100MHz. For clock <= 100MHz
1174  * fixed feedback clock is used.
1175  */
1176 static void sdhci_msm_hs400(struct sdhci_host *host, struct mmc_ios *ios)
1177 {
1178         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1179         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1180         int ret;
1181
1182         if (host->clock > CORE_FREQ_100MHZ &&
1183             (msm_host->tuning_done || ios->enhanced_strobe) &&
1184             !msm_host->calibration_done) {
1185                 ret = sdhci_msm_hs400_dll_calibration(host);
1186                 if (!ret)
1187                         msm_host->calibration_done = true;
1188                 else
1189                         pr_err("%s: Failed to calibrate DLL for hs400 mode (%d)\n",
1190                                mmc_hostname(host->mmc), ret);
1191         }
1192 }
1193
1194 static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
1195                                         unsigned int uhs)
1196 {
1197         struct mmc_host *mmc = host->mmc;
1198         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1199         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1200         u16 ctrl_2;
1201         u32 config;
1202         const struct sdhci_msm_offset *msm_offset =
1203                                         msm_host->offset;
1204
1205         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1206         /* Select Bus Speed Mode for host */
1207         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1208         switch (uhs) {
1209         case MMC_TIMING_UHS_SDR12:
1210                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1211                 break;
1212         case MMC_TIMING_UHS_SDR25:
1213                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1214                 break;
1215         case MMC_TIMING_UHS_SDR50:
1216                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1217                 break;
1218         case MMC_TIMING_MMC_HS400:
1219         case MMC_TIMING_MMC_HS200:
1220         case MMC_TIMING_UHS_SDR104:
1221                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1222                 break;
1223         case MMC_TIMING_UHS_DDR50:
1224         case MMC_TIMING_MMC_DDR52:
1225                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1226                 break;
1227         }
1228
1229         /*
1230          * When clock frequency is less than 100MHz, the feedback clock must be
1231          * provided and DLL must not be used so that tuning can be skipped. To
1232          * provide feedback clock, the mode selection can be any value less
1233          * than 3'b011 in bits [2:0] of HOST CONTROL2 register.
1234          */
1235         if (host->clock <= CORE_FREQ_100MHZ) {
1236                 if (uhs == MMC_TIMING_MMC_HS400 ||
1237                     uhs == MMC_TIMING_MMC_HS200 ||
1238                     uhs == MMC_TIMING_UHS_SDR104)
1239                         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1240                 /*
1241                  * DLL is not required for clock <= 100MHz
1242                  * Thus, make sure DLL it is disabled when not required
1243                  */
1244                 config = readl_relaxed(host->ioaddr +
1245                                 msm_offset->core_dll_config);
1246                 config |= CORE_DLL_RST;
1247                 writel_relaxed(config, host->ioaddr +
1248                                 msm_offset->core_dll_config);
1249
1250                 config = readl_relaxed(host->ioaddr +
1251                                 msm_offset->core_dll_config);
1252                 config |= CORE_DLL_PDN;
1253                 writel_relaxed(config, host->ioaddr +
1254                                 msm_offset->core_dll_config);
1255
1256                 /*
1257                  * The DLL needs to be restored and CDCLP533 recalibrated
1258                  * when the clock frequency is set back to 400MHz.
1259                  */
1260                 msm_host->calibration_done = false;
1261         }
1262
1263         dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",
1264                 mmc_hostname(host->mmc), host->clock, uhs, ctrl_2);
1265         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1266
1267         if (mmc->ios.timing == MMC_TIMING_MMC_HS400)
1268                 sdhci_msm_hs400(host, &mmc->ios);
1269 }
1270
1271 static inline void sdhci_msm_init_pwr_irq_wait(struct sdhci_msm_host *msm_host)
1272 {
1273         init_waitqueue_head(&msm_host->pwr_irq_wait);
1274 }
1275
1276 static inline void sdhci_msm_complete_pwr_irq_wait(
1277                 struct sdhci_msm_host *msm_host)
1278 {
1279         wake_up(&msm_host->pwr_irq_wait);
1280 }
1281
1282 /*
1283  * sdhci_msm_check_power_status API should be called when registers writes
1284  * which can toggle sdhci IO bus ON/OFF or change IO lines HIGH/LOW happens.
1285  * To what state the register writes will change the IO lines should be passed
1286  * as the argument req_type. This API will check whether the IO line's state
1287  * is already the expected state and will wait for power irq only if
1288  * power irq is expected to be trigerred based on the current IO line state
1289  * and expected IO line state.
1290  */
1291 static void sdhci_msm_check_power_status(struct sdhci_host *host, u32 req_type)
1292 {
1293         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1294         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1295         bool done = false;
1296         u32 val = SWITCHABLE_SIGNALING_VOLTAGE;
1297         const struct sdhci_msm_offset *msm_offset =
1298                                         msm_host->offset;
1299
1300         pr_debug("%s: %s: request %d curr_pwr_state %x curr_io_level %x\n",
1301                         mmc_hostname(host->mmc), __func__, req_type,
1302                         msm_host->curr_pwr_state, msm_host->curr_io_level);
1303
1304         /*
1305          * The power interrupt will not be generated for signal voltage
1306          * switches if SWITCHABLE_SIGNALING_VOLTAGE in MCI_GENERICS is not set.
1307          * Since sdhci-msm-v5, this bit has been removed and SW must consider
1308          * it as always set.
1309          */
1310         if (!msm_host->mci_removed)
1311                 val = msm_host_readl(msm_host, host,
1312                                 msm_offset->core_generics);
1313         if ((req_type & REQ_IO_HIGH || req_type & REQ_IO_LOW) &&
1314             !(val & SWITCHABLE_SIGNALING_VOLTAGE)) {
1315                 return;
1316         }
1317
1318         /*
1319          * The IRQ for request type IO High/LOW will be generated when -
1320          * there is a state change in 1.8V enable bit (bit 3) of
1321          * SDHCI_HOST_CONTROL2 register. The reset state of that bit is 0
1322          * which indicates 3.3V IO voltage. So, when MMC core layer tries
1323          * to set it to 3.3V before card detection happens, the
1324          * IRQ doesn't get triggered as there is no state change in this bit.
1325          * The driver already handles this case by changing the IO voltage
1326          * level to high as part of controller power up sequence. Hence, check
1327          * for host->pwr to handle a case where IO voltage high request is
1328          * issued even before controller power up.
1329          */
1330         if ((req_type & REQ_IO_HIGH) && !host->pwr) {
1331                 pr_debug("%s: do not wait for power IRQ that never comes, req_type: %d\n",
1332                                 mmc_hostname(host->mmc), req_type);
1333                 return;
1334         }
1335         if ((req_type & msm_host->curr_pwr_state) ||
1336                         (req_type & msm_host->curr_io_level))
1337                 done = true;
1338         /*
1339          * This is needed here to handle cases where register writes will
1340          * not change the current bus state or io level of the controller.
1341          * In this case, no power irq will be triggerred and we should
1342          * not wait.
1343          */
1344         if (!done) {
1345                 if (!wait_event_timeout(msm_host->pwr_irq_wait,
1346                                 msm_host->pwr_irq_flag,
1347                                 msecs_to_jiffies(MSM_PWR_IRQ_TIMEOUT_MS)))
1348                         dev_warn(&msm_host->pdev->dev,
1349                                  "%s: pwr_irq for req: (%d) timed out\n",
1350                                  mmc_hostname(host->mmc), req_type);
1351         }
1352         pr_debug("%s: %s: request %d done\n", mmc_hostname(host->mmc),
1353                         __func__, req_type);
1354 }
1355
1356 static void sdhci_msm_dump_pwr_ctrl_regs(struct sdhci_host *host)
1357 {
1358         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1359         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1360         const struct sdhci_msm_offset *msm_offset =
1361                                         msm_host->offset;
1362
1363         pr_err("%s: PWRCTL_STATUS: 0x%08x | PWRCTL_MASK: 0x%08x | PWRCTL_CTL: 0x%08x\n",
1364                 mmc_hostname(host->mmc),
1365                 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_status),
1366                 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_mask),
1367                 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_ctl));
1368 }
1369
1370 static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq)
1371 {
1372         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1373         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1374         u32 irq_status, irq_ack = 0;
1375         int retry = 10;
1376         u32 pwr_state = 0, io_level = 0;
1377         u32 config;
1378         const struct sdhci_msm_offset *msm_offset = msm_host->offset;
1379
1380         irq_status = msm_host_readl(msm_host, host,
1381                         msm_offset->core_pwrctl_status);
1382         irq_status &= INT_MASK;
1383
1384         msm_host_writel(msm_host, irq_status, host,
1385                         msm_offset->core_pwrctl_clear);
1386
1387         /*
1388          * There is a rare HW scenario where the first clear pulse could be
1389          * lost when actual reset and clear/read of status register is
1390          * happening at a time. Hence, retry for at least 10 times to make
1391          * sure status register is cleared. Otherwise, this will result in
1392          * a spurious power IRQ resulting in system instability.
1393          */
1394         while (irq_status & msm_host_readl(msm_host, host,
1395                                 msm_offset->core_pwrctl_status)) {
1396                 if (retry == 0) {
1397                         pr_err("%s: Timedout clearing (0x%x) pwrctl status register\n",
1398                                         mmc_hostname(host->mmc), irq_status);
1399                         sdhci_msm_dump_pwr_ctrl_regs(host);
1400                         WARN_ON(1);
1401                         break;
1402                 }
1403                 msm_host_writel(msm_host, irq_status, host,
1404                         msm_offset->core_pwrctl_clear);
1405                 retry--;
1406                 udelay(10);
1407         }
1408
1409         /* Handle BUS ON/OFF*/
1410         if (irq_status & CORE_PWRCTL_BUS_ON) {
1411                 pwr_state = REQ_BUS_ON;
1412                 io_level = REQ_IO_HIGH;
1413                 irq_ack |= CORE_PWRCTL_BUS_SUCCESS;
1414         }
1415         if (irq_status & CORE_PWRCTL_BUS_OFF) {
1416                 pwr_state = REQ_BUS_OFF;
1417                 io_level = REQ_IO_LOW;
1418                 irq_ack |= CORE_PWRCTL_BUS_SUCCESS;
1419         }
1420         /* Handle IO LOW/HIGH */
1421         if (irq_status & CORE_PWRCTL_IO_LOW) {
1422                 io_level = REQ_IO_LOW;
1423                 irq_ack |= CORE_PWRCTL_IO_SUCCESS;
1424         }
1425         if (irq_status & CORE_PWRCTL_IO_HIGH) {
1426                 io_level = REQ_IO_HIGH;
1427                 irq_ack |= CORE_PWRCTL_IO_SUCCESS;
1428         }
1429
1430         /*
1431          * The driver has to acknowledge the interrupt, switch voltages and
1432          * report back if it succeded or not to this register. The voltage
1433          * switches are handled by the sdhci core, so just report success.
1434          */
1435         msm_host_writel(msm_host, irq_ack, host,
1436                         msm_offset->core_pwrctl_ctl);
1437
1438         /*
1439          * If we don't have info regarding the voltage levels supported by
1440          * regulators, don't change the IO PAD PWR SWITCH.
1441          */
1442         if (msm_host->caps_0 & CORE_VOLT_SUPPORT) {
1443                 u32 new_config;
1444                 /*
1445                  * We should unset IO PAD PWR switch only if the register write
1446                  * can set IO lines high and the regulator also switches to 3 V.
1447                  * Else, we should keep the IO PAD PWR switch set.
1448                  * This is applicable to certain targets where eMMC vccq supply
1449                  * is only 1.8V. In such targets, even during REQ_IO_HIGH, the
1450                  * IO PAD PWR switch must be kept set to reflect actual
1451                  * regulator voltage. This way, during initialization of
1452                  * controllers with only 1.8V, we will set the IO PAD bit
1453                  * without waiting for a REQ_IO_LOW.
1454                  */
1455                 config = readl_relaxed(host->ioaddr +
1456                                 msm_offset->core_vendor_spec);
1457                 new_config = config;
1458
1459                 if ((io_level & REQ_IO_HIGH) &&
1460                                 (msm_host->caps_0 & CORE_3_0V_SUPPORT))
1461                         new_config &= ~CORE_IO_PAD_PWR_SWITCH;
1462                 else if ((io_level & REQ_IO_LOW) ||
1463                                 (msm_host->caps_0 & CORE_1_8V_SUPPORT))
1464                         new_config |= CORE_IO_PAD_PWR_SWITCH;
1465
1466                 if (config ^ new_config)
1467                         writel_relaxed(new_config, host->ioaddr +
1468                                         msm_offset->core_vendor_spec);
1469         }
1470
1471         if (pwr_state)
1472                 msm_host->curr_pwr_state = pwr_state;
1473         if (io_level)
1474                 msm_host->curr_io_level = io_level;
1475
1476         pr_debug("%s: %s: Handled IRQ(%d), irq_status=0x%x, ack=0x%x\n",
1477                 mmc_hostname(msm_host->mmc), __func__, irq, irq_status,
1478                 irq_ack);
1479 }
1480
1481 static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data)
1482 {
1483         struct sdhci_host *host = (struct sdhci_host *)data;
1484         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1485         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1486
1487         sdhci_msm_handle_pwr_irq(host, irq);
1488         msm_host->pwr_irq_flag = 1;
1489         sdhci_msm_complete_pwr_irq_wait(msm_host);
1490
1491
1492         return IRQ_HANDLED;
1493 }
1494
1495 static unsigned int sdhci_msm_get_max_clock(struct sdhci_host *host)
1496 {
1497         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1498         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1499         struct clk *core_clk = msm_host->bulk_clks[0].clk;
1500
1501         return clk_round_rate(core_clk, ULONG_MAX);
1502 }
1503
1504 static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host)
1505 {
1506         return SDHCI_MSM_MIN_CLOCK;
1507 }
1508
1509 /**
1510  * __sdhci_msm_set_clock - sdhci_msm clock control.
1511  *
1512  * Description:
1513  * MSM controller does not use internal divider and
1514  * instead directly control the GCC clock as per
1515  * HW recommendation.
1516  **/
1517 static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
1518 {
1519         u16 clk;
1520         /*
1521          * Keep actual_clock as zero -
1522          * - since there is no divider used so no need of having actual_clock.
1523          * - MSM controller uses SDCLK for data timeout calculation. If
1524          *   actual_clock is zero, host->clock is taken for calculation.
1525          */
1526         host->mmc->actual_clock = 0;
1527
1528         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1529
1530         if (clock == 0)
1531                 return;
1532
1533         /*
1534          * MSM controller do not use clock divider.
1535          * Thus read SDHCI_CLOCK_CONTROL and only enable
1536          * clock with no divider value programmed.
1537          */
1538         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1539         sdhci_enable_clk(host, clk);
1540 }
1541
1542 /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
1543 static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
1544 {
1545         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1546         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1547
1548         if (!clock) {
1549                 msm_host->clk_rate = clock;
1550                 goto out;
1551         }
1552
1553         sdhci_msm_hc_select_mode(host);
1554
1555         msm_set_clock_rate_for_bus_mode(host, clock);
1556 out:
1557         __sdhci_msm_set_clock(host, clock);
1558 }
1559
1560 /*
1561  * Platform specific register write functions. This is so that, if any
1562  * register write needs to be followed up by platform specific actions,
1563  * they can be added here. These functions can go to sleep when writes
1564  * to certain registers are done.
1565  * These functions are relying on sdhci_set_ios not using spinlock.
1566  */
1567 static int __sdhci_msm_check_write(struct sdhci_host *host, u16 val, int reg)
1568 {
1569         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1570         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1571         u32 req_type = 0;
1572
1573         switch (reg) {
1574         case SDHCI_HOST_CONTROL2:
1575                 req_type = (val & SDHCI_CTRL_VDD_180) ? REQ_IO_LOW :
1576                         REQ_IO_HIGH;
1577                 break;
1578         case SDHCI_SOFTWARE_RESET:
1579                 if (host->pwr && (val & SDHCI_RESET_ALL))
1580                         req_type = REQ_BUS_OFF;
1581                 break;
1582         case SDHCI_POWER_CONTROL:
1583                 req_type = !val ? REQ_BUS_OFF : REQ_BUS_ON;
1584                 break;
1585         case SDHCI_TRANSFER_MODE:
1586                 msm_host->transfer_mode = val;
1587                 break;
1588         case SDHCI_COMMAND:
1589                 if (!msm_host->use_cdr)
1590                         break;
1591                 if ((msm_host->transfer_mode & SDHCI_TRNS_READ) &&
1592                     SDHCI_GET_CMD(val) != MMC_SEND_TUNING_BLOCK_HS200 &&
1593                     SDHCI_GET_CMD(val) != MMC_SEND_TUNING_BLOCK)
1594                         sdhci_msm_set_cdr(host, true);
1595                 else
1596                         sdhci_msm_set_cdr(host, false);
1597                 break;
1598         }
1599
1600         if (req_type) {
1601                 msm_host->pwr_irq_flag = 0;
1602                 /*
1603                  * Since this register write may trigger a power irq, ensure
1604                  * all previous register writes are complete by this point.
1605                  */
1606                 mb();
1607         }
1608         return req_type;
1609 }
1610
1611 /* This function may sleep*/
1612 static void sdhci_msm_writew(struct sdhci_host *host, u16 val, int reg)
1613 {
1614         u32 req_type = 0;
1615
1616         req_type = __sdhci_msm_check_write(host, val, reg);
1617         writew_relaxed(val, host->ioaddr + reg);
1618
1619         if (req_type)
1620                 sdhci_msm_check_power_status(host, req_type);
1621 }
1622
1623 /* This function may sleep*/
1624 static void sdhci_msm_writeb(struct sdhci_host *host, u8 val, int reg)
1625 {
1626         u32 req_type = 0;
1627
1628         req_type = __sdhci_msm_check_write(host, val, reg);
1629
1630         writeb_relaxed(val, host->ioaddr + reg);
1631
1632         if (req_type)
1633                 sdhci_msm_check_power_status(host, req_type);
1634 }
1635
1636 static void sdhci_msm_set_regulator_caps(struct sdhci_msm_host *msm_host)
1637 {
1638         struct mmc_host *mmc = msm_host->mmc;
1639         struct regulator *supply = mmc->supply.vqmmc;
1640         u32 caps = 0, config;
1641         struct sdhci_host *host = mmc_priv(mmc);
1642         const struct sdhci_msm_offset *msm_offset = msm_host->offset;
1643
1644         if (!IS_ERR(mmc->supply.vqmmc)) {
1645                 if (regulator_is_supported_voltage(supply, 1700000, 1950000))
1646                         caps |= CORE_1_8V_SUPPORT;
1647                 if (regulator_is_supported_voltage(supply, 2700000, 3600000))
1648                         caps |= CORE_3_0V_SUPPORT;
1649
1650                 if (!caps)
1651                         pr_warn("%s: 1.8/3V not supported for vqmmc\n",
1652                                         mmc_hostname(mmc));
1653         }
1654
1655         if (caps) {
1656                 /*
1657                  * Set the PAD_PWR_SWITCH_EN bit so that the PAD_PWR_SWITCH
1658                  * bit can be used as required later on.
1659                  */
1660                 u32 io_level = msm_host->curr_io_level;
1661
1662                 config = readl_relaxed(host->ioaddr +
1663                                 msm_offset->core_vendor_spec);
1664                 config |= CORE_IO_PAD_PWR_SWITCH_EN;
1665
1666                 if ((io_level & REQ_IO_HIGH) && (caps & CORE_3_0V_SUPPORT))
1667                         config &= ~CORE_IO_PAD_PWR_SWITCH;
1668                 else if ((io_level & REQ_IO_LOW) || (caps & CORE_1_8V_SUPPORT))
1669                         config |= CORE_IO_PAD_PWR_SWITCH;
1670
1671                 writel_relaxed(config,
1672                                 host->ioaddr + msm_offset->core_vendor_spec);
1673         }
1674         msm_host->caps_0 |= caps;
1675         pr_debug("%s: supported caps: 0x%08x\n", mmc_hostname(mmc), caps);
1676 }
1677
1678 static const struct sdhci_msm_variant_ops mci_var_ops = {
1679         .msm_readl_relaxed = sdhci_msm_mci_variant_readl_relaxed,
1680         .msm_writel_relaxed = sdhci_msm_mci_variant_writel_relaxed,
1681 };
1682
1683 static const struct sdhci_msm_variant_ops v5_var_ops = {
1684         .msm_readl_relaxed = sdhci_msm_v5_variant_readl_relaxed,
1685         .msm_writel_relaxed = sdhci_msm_v5_variant_writel_relaxed,
1686 };
1687
1688 static const struct sdhci_msm_variant_info sdhci_msm_mci_var = {
1689         .var_ops = &mci_var_ops,
1690         .offset = &sdhci_msm_mci_offset,
1691 };
1692
1693 static const struct sdhci_msm_variant_info sdhci_msm_v5_var = {
1694         .mci_removed = true,
1695         .var_ops = &v5_var_ops,
1696         .offset = &sdhci_msm_v5_offset,
1697 };
1698
1699 static const struct sdhci_msm_variant_info sdm845_sdhci_var = {
1700         .mci_removed = true,
1701         .restore_dll_config = true,
1702         .var_ops = &v5_var_ops,
1703         .offset = &sdhci_msm_v5_offset,
1704 };
1705
1706 static const struct of_device_id sdhci_msm_dt_match[] = {
1707         {.compatible = "qcom,sdhci-msm-v4", .data = &sdhci_msm_mci_var},
1708         {.compatible = "qcom,sdhci-msm-v5", .data = &sdhci_msm_v5_var},
1709         {.compatible = "qcom,sdm845-sdhci", .data = &sdm845_sdhci_var},
1710         {},
1711 };
1712
1713 MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match);
1714
1715 static const struct sdhci_ops sdhci_msm_ops = {
1716         .reset = sdhci_reset,
1717         .set_clock = sdhci_msm_set_clock,
1718         .get_min_clock = sdhci_msm_get_min_clock,
1719         .get_max_clock = sdhci_msm_get_max_clock,
1720         .set_bus_width = sdhci_set_bus_width,
1721         .set_uhs_signaling = sdhci_msm_set_uhs_signaling,
1722         .write_w = sdhci_msm_writew,
1723         .write_b = sdhci_msm_writeb,
1724 };
1725
1726 static const struct sdhci_pltfm_data sdhci_msm_pdata = {
1727         .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
1728                   SDHCI_QUIRK_SINGLE_POWER_WRITE |
1729                   SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1730         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1731         .ops = &sdhci_msm_ops,
1732 };
1733
1734 static int sdhci_msm_probe(struct platform_device *pdev)
1735 {
1736         struct sdhci_host *host;
1737         struct sdhci_pltfm_host *pltfm_host;
1738         struct sdhci_msm_host *msm_host;
1739         struct resource *core_memres;
1740         struct clk *clk;
1741         int ret;
1742         u16 host_version, core_minor;
1743         u32 core_version, config;
1744         u8 core_major;
1745         const struct sdhci_msm_offset *msm_offset;
1746         const struct sdhci_msm_variant_info *var_info;
1747
1748         host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host));
1749         if (IS_ERR(host))
1750                 return PTR_ERR(host);
1751
1752         host->sdma_boundary = 0;
1753         pltfm_host = sdhci_priv(host);
1754         msm_host = sdhci_pltfm_priv(pltfm_host);
1755         msm_host->mmc = host->mmc;
1756         msm_host->pdev = pdev;
1757
1758         ret = mmc_of_parse(host->mmc);
1759         if (ret)
1760                 goto pltfm_free;
1761
1762         /*
1763          * Based on the compatible string, load the required msm host info from
1764          * the data associated with the version info.
1765          */
1766         var_info = of_device_get_match_data(&pdev->dev);
1767
1768         msm_host->mci_removed = var_info->mci_removed;
1769         msm_host->restore_dll_config = var_info->restore_dll_config;
1770         msm_host->var_ops = var_info->var_ops;
1771         msm_host->offset = var_info->offset;
1772
1773         msm_offset = msm_host->offset;
1774
1775         sdhci_get_of_property(pdev);
1776
1777         msm_host->saved_tuning_phase = INVALID_TUNING_PHASE;
1778
1779         /* Setup SDCC bus voter clock. */
1780         msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
1781         if (!IS_ERR(msm_host->bus_clk)) {
1782                 /* Vote for max. clk rate for max. performance */
1783                 ret = clk_set_rate(msm_host->bus_clk, INT_MAX);
1784                 if (ret)
1785                         goto pltfm_free;
1786                 ret = clk_prepare_enable(msm_host->bus_clk);
1787                 if (ret)
1788                         goto pltfm_free;
1789         }
1790
1791         /* Setup main peripheral bus clock */
1792         clk = devm_clk_get(&pdev->dev, "iface");
1793         if (IS_ERR(clk)) {
1794                 ret = PTR_ERR(clk);
1795                 dev_err(&pdev->dev, "Peripheral clk setup failed (%d)\n", ret);
1796                 goto bus_clk_disable;
1797         }
1798         msm_host->bulk_clks[1].clk = clk;
1799
1800         /* Setup SDC MMC clock */
1801         clk = devm_clk_get(&pdev->dev, "core");
1802         if (IS_ERR(clk)) {
1803                 ret = PTR_ERR(clk);
1804                 dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret);
1805                 goto bus_clk_disable;
1806         }
1807         msm_host->bulk_clks[0].clk = clk;
1808
1809         /* Vote for maximum clock rate for maximum performance */
1810         ret = clk_set_rate(clk, INT_MAX);
1811         if (ret)
1812                 dev_warn(&pdev->dev, "core clock boost failed\n");
1813
1814         clk = devm_clk_get(&pdev->dev, "cal");
1815         if (IS_ERR(clk))
1816                 clk = NULL;
1817         msm_host->bulk_clks[2].clk = clk;
1818
1819         clk = devm_clk_get(&pdev->dev, "sleep");
1820         if (IS_ERR(clk))
1821                 clk = NULL;
1822         msm_host->bulk_clks[3].clk = clk;
1823
1824         ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks),
1825                                       msm_host->bulk_clks);
1826         if (ret)
1827                 goto bus_clk_disable;
1828
1829         /*
1830          * xo clock is needed for FLL feature of cm_dll.
1831          * In case if xo clock is not mentioned in DT, warn and proceed.
1832          */
1833         msm_host->xo_clk = devm_clk_get(&pdev->dev, "xo");
1834         if (IS_ERR(msm_host->xo_clk)) {
1835                 ret = PTR_ERR(msm_host->xo_clk);
1836                 dev_warn(&pdev->dev, "TCXO clk not present (%d)\n", ret);
1837         }
1838
1839         if (!msm_host->mci_removed) {
1840                 core_memres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1841                 msm_host->core_mem = devm_ioremap_resource(&pdev->dev,
1842                                 core_memres);
1843
1844                 if (IS_ERR(msm_host->core_mem)) {
1845                         ret = PTR_ERR(msm_host->core_mem);
1846                         goto clk_disable;
1847                 }
1848         }
1849
1850         /* Reset the vendor spec register to power on reset state */
1851         writel_relaxed(CORE_VENDOR_SPEC_POR_VAL,
1852                         host->ioaddr + msm_offset->core_vendor_spec);
1853
1854         if (!msm_host->mci_removed) {
1855                 /* Set HC_MODE_EN bit in HC_MODE register */
1856                 msm_host_writel(msm_host, HC_MODE_EN, host,
1857                                 msm_offset->core_hc_mode);
1858                 config = msm_host_readl(msm_host, host,
1859                                 msm_offset->core_hc_mode);
1860                 config |= FF_CLK_SW_RST_DIS;
1861                 msm_host_writel(msm_host, config, host,
1862                                 msm_offset->core_hc_mode);
1863         }
1864
1865         host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
1866         dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n",
1867                 host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >>
1868                                SDHCI_VENDOR_VER_SHIFT));
1869
1870         core_version = msm_host_readl(msm_host, host,
1871                         msm_offset->core_mci_version);
1872         core_major = (core_version & CORE_VERSION_MAJOR_MASK) >>
1873                       CORE_VERSION_MAJOR_SHIFT;
1874         core_minor = core_version & CORE_VERSION_MINOR_MASK;
1875         dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n",
1876                 core_version, core_major, core_minor);
1877
1878         if (core_major == 1 && core_minor >= 0x42)
1879                 msm_host->use_14lpp_dll_reset = true;
1880
1881         /*
1882          * SDCC 5 controller with major version 1, minor version 0x34 and later
1883          * with HS 400 mode support will use CM DLL instead of CDC LP 533 DLL.
1884          */
1885         if (core_major == 1 && core_minor < 0x34)
1886                 msm_host->use_cdclp533 = true;
1887
1888         /*
1889          * Support for some capabilities is not advertised by newer
1890          * controller versions and must be explicitly enabled.
1891          */
1892         if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
1893                 config = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES);
1894                 config |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
1895                 writel_relaxed(config, host->ioaddr +
1896                                 msm_offset->core_vendor_spec_capabilities0);
1897         }
1898
1899         /*
1900          * Power on reset state may trigger power irq if previous status of
1901          * PWRCTL was either BUS_ON or IO_HIGH_V. So before enabling pwr irq
1902          * interrupt in GIC, any pending power irq interrupt should be
1903          * acknowledged. Otherwise power irq interrupt handler would be
1904          * fired prematurely.
1905          */
1906         sdhci_msm_handle_pwr_irq(host, 0);
1907
1908         /*
1909          * Ensure that above writes are propogated before interrupt enablement
1910          * in GIC.
1911          */
1912         mb();
1913
1914         /* Setup IRQ for handling power/voltage tasks with PMIC */
1915         msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq");
1916         if (msm_host->pwr_irq < 0) {
1917                 dev_err(&pdev->dev, "Get pwr_irq failed (%d)\n",
1918                         msm_host->pwr_irq);
1919                 ret = msm_host->pwr_irq;
1920                 goto clk_disable;
1921         }
1922
1923         sdhci_msm_init_pwr_irq_wait(msm_host);
1924         /* Enable pwr irq interrupts */
1925         msm_host_writel(msm_host, INT_MASK, host,
1926                 msm_offset->core_pwrctl_mask);
1927
1928         ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL,
1929                                         sdhci_msm_pwr_irq, IRQF_ONESHOT,
1930                                         dev_name(&pdev->dev), host);
1931         if (ret) {
1932                 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", ret);
1933                 goto clk_disable;
1934         }
1935
1936         pm_runtime_get_noresume(&pdev->dev);
1937         pm_runtime_set_active(&pdev->dev);
1938         pm_runtime_enable(&pdev->dev);
1939         pm_runtime_set_autosuspend_delay(&pdev->dev,
1940                                          MSM_MMC_AUTOSUSPEND_DELAY_MS);
1941         pm_runtime_use_autosuspend(&pdev->dev);
1942
1943         host->mmc_host_ops.execute_tuning = sdhci_msm_execute_tuning;
1944         ret = sdhci_add_host(host);
1945         if (ret)
1946                 goto pm_runtime_disable;
1947         sdhci_msm_set_regulator_caps(msm_host);
1948
1949         pm_runtime_mark_last_busy(&pdev->dev);
1950         pm_runtime_put_autosuspend(&pdev->dev);
1951
1952         return 0;
1953
1954 pm_runtime_disable:
1955         pm_runtime_disable(&pdev->dev);
1956         pm_runtime_set_suspended(&pdev->dev);
1957         pm_runtime_put_noidle(&pdev->dev);
1958 clk_disable:
1959         clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
1960                                    msm_host->bulk_clks);
1961 bus_clk_disable:
1962         if (!IS_ERR(msm_host->bus_clk))
1963                 clk_disable_unprepare(msm_host->bus_clk);
1964 pltfm_free:
1965         sdhci_pltfm_free(pdev);
1966         return ret;
1967 }
1968
1969 static int sdhci_msm_remove(struct platform_device *pdev)
1970 {
1971         struct sdhci_host *host = platform_get_drvdata(pdev);
1972         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1973         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1974         int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) ==
1975                     0xffffffff);
1976
1977         sdhci_remove_host(host, dead);
1978
1979         pm_runtime_get_sync(&pdev->dev);
1980         pm_runtime_disable(&pdev->dev);
1981         pm_runtime_put_noidle(&pdev->dev);
1982
1983         clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
1984                                    msm_host->bulk_clks);
1985         if (!IS_ERR(msm_host->bus_clk))
1986                 clk_disable_unprepare(msm_host->bus_clk);
1987         sdhci_pltfm_free(pdev);
1988         return 0;
1989 }
1990
1991 static __maybe_unused int sdhci_msm_runtime_suspend(struct device *dev)
1992 {
1993         struct sdhci_host *host = dev_get_drvdata(dev);
1994         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1995         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1996
1997         clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
1998                                    msm_host->bulk_clks);
1999
2000         return 0;
2001 }
2002
2003 static __maybe_unused int sdhci_msm_runtime_resume(struct device *dev)
2004 {
2005         struct sdhci_host *host = dev_get_drvdata(dev);
2006         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2007         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2008         int ret;
2009
2010         ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks),
2011                                        msm_host->bulk_clks);
2012         if (ret)
2013                 return ret;
2014         /*
2015          * Whenever core-clock is gated dynamically, it's needed to
2016          * restore the SDR DLL settings when the clock is ungated.
2017          */
2018         if (msm_host->restore_dll_config && msm_host->clk_rate)
2019                 return sdhci_msm_restore_sdr_dll_config(host);
2020
2021         return 0;
2022 }
2023
2024 static const struct dev_pm_ops sdhci_msm_pm_ops = {
2025         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2026                                 pm_runtime_force_resume)
2027         SET_RUNTIME_PM_OPS(sdhci_msm_runtime_suspend,
2028                            sdhci_msm_runtime_resume,
2029                            NULL)
2030 };
2031
2032 static struct platform_driver sdhci_msm_driver = {
2033         .probe = sdhci_msm_probe,
2034         .remove = sdhci_msm_remove,
2035         .driver = {
2036                    .name = "sdhci_msm",
2037                    .of_match_table = sdhci_msm_dt_match,
2038                    .pm = &sdhci_msm_pm_ops,
2039         },
2040 };
2041
2042 module_platform_driver(sdhci_msm_driver);
2043
2044 MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver");
2045 MODULE_LICENSE("GPL v2");