2 * Freescale eSDHC i.MX controller driver for the platform bus.
4 * derived from the OF-version.
6 * Copyright (c) 2010 Pengutronix e.K.
7 * Author: Wolfram Sang <kernel@pengutronix.de>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/clk.h>
18 #include <linux/gpio.h>
19 #include <linux/module.h>
20 #include <linux/slab.h>
21 #include <linux/mmc/host.h>
22 #include <linux/mmc/mmc.h>
23 #include <linux/mmc/sdio.h>
24 #include <linux/mmc/slot-gpio.h>
26 #include <linux/of_device.h>
27 #include <linux/of_gpio.h>
28 #include <linux/pinctrl/consumer.h>
29 #include <linux/platform_data/mmc-esdhc-imx.h>
30 #include <linux/pm_runtime.h>
31 #include "sdhci-pltfm.h"
32 #include "sdhci-esdhc.h"
34 #define ESDHC_CTRL_D3CD 0x08
35 /* VENDOR SPEC register */
36 #define ESDHC_VENDOR_SPEC 0xc0
37 #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1)
38 #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1)
39 #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
40 #define ESDHC_WTMK_LVL 0x44
41 #define ESDHC_MIX_CTRL 0x48
42 #define ESDHC_MIX_CTRL_DDREN (1 << 3)
43 #define ESDHC_MIX_CTRL_AC23EN (1 << 7)
44 #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22)
45 #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23)
46 #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25)
47 /* Bits 3 and 6 are not SDHCI standard definitions */
48 #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7
50 #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000
52 /* dll control register */
53 #define ESDHC_DLL_CTRL 0x60
54 #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9
55 #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8
57 /* tune control register */
58 #define ESDHC_TUNE_CTRL_STATUS 0x68
59 #define ESDHC_TUNE_CTRL_STEP 1
60 #define ESDHC_TUNE_CTRL_MIN 0
61 #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
63 #define ESDHC_TUNING_CTRL 0xcc
64 #define ESDHC_STD_TUNING_EN (1 << 24)
65 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
66 #define ESDHC_TUNING_START_TAP 0x1
69 #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz"
70 #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz"
73 * Our interpretation of the SDHCI_HOST_CONTROL register
75 #define ESDHC_CTRL_4BITBUS (0x1 << 1)
76 #define ESDHC_CTRL_8BITBUS (0x2 << 1)
77 #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
80 * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC:
81 * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
82 * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
83 * Define this macro DMA error INT for fsl eSDHC
85 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28)
88 * The CMDTYPE of the CMD register (offset 0xE) should be set to
89 * "11" when the STOP CMD12 is issued on imx53 to abort one
90 * open ended multi-blk IO. Otherwise the TC INT wouldn't
92 * In exact block transfer, the controller doesn't complete the
93 * operations automatically as required at the end of the
94 * transfer and remains on hold if the abort command is not sent.
95 * As a result, the TC flag is not asserted and SW received timeout
96 * exeception. Bit1 of Vendor Spec registor is used to fix it.
98 #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1)
100 * The flag enables the workaround for ESDHC errata ENGcm07207 which
101 * affects i.MX25 and i.MX35.
103 #define ESDHC_FLAG_ENGCM07207 BIT(2)
105 * The flag tells that the ESDHC controller is an USDHC block that is
106 * integrated on the i.MX6 series.
108 #define ESDHC_FLAG_USDHC BIT(3)
109 /* The IP supports manual tuning process */
110 #define ESDHC_FLAG_MAN_TUNING BIT(4)
111 /* The IP supports standard tuning process */
112 #define ESDHC_FLAG_STD_TUNING BIT(5)
113 /* The IP has SDHCI_CAPABILITIES_1 register */
114 #define ESDHC_FLAG_HAVE_CAP1 BIT(6)
116 * The IP has errata ERR004536
117 * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
118 * when reading data from the card
120 #define ESDHC_FLAG_ERR004536 BIT(7)
121 /* The IP supports HS200 mode */
122 #define ESDHC_FLAG_HS200 BIT(8)
124 struct esdhc_soc_data {
128 static struct esdhc_soc_data esdhc_imx25_data = {
129 .flags = ESDHC_FLAG_ENGCM07207,
132 static struct esdhc_soc_data esdhc_imx35_data = {
133 .flags = ESDHC_FLAG_ENGCM07207,
136 static struct esdhc_soc_data esdhc_imx51_data = {
140 static struct esdhc_soc_data esdhc_imx53_data = {
141 .flags = ESDHC_FLAG_MULTIBLK_NO_INT,
144 static struct esdhc_soc_data usdhc_imx6q_data = {
145 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING,
148 static struct esdhc_soc_data usdhc_imx6sl_data = {
149 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
150 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536
154 static struct esdhc_soc_data usdhc_imx6sx_data = {
155 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
156 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200,
159 struct pltfm_imx_data {
161 struct pinctrl *pinctrl;
162 struct pinctrl_state *pins_default;
163 struct pinctrl_state *pins_100mhz;
164 struct pinctrl_state *pins_200mhz;
165 const struct esdhc_soc_data *socdata;
166 struct esdhc_platform_data boarddata;
171 NO_CMD_PENDING, /* no multiblock command pending*/
172 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
173 WAIT_FOR_INT, /* sent CMD12, waiting for response INT */
178 static const struct platform_device_id imx_esdhc_devtype[] = {
180 .name = "sdhci-esdhc-imx25",
181 .driver_data = (kernel_ulong_t) &esdhc_imx25_data,
183 .name = "sdhci-esdhc-imx35",
184 .driver_data = (kernel_ulong_t) &esdhc_imx35_data,
186 .name = "sdhci-esdhc-imx51",
187 .driver_data = (kernel_ulong_t) &esdhc_imx51_data,
192 MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype);
194 static const struct of_device_id imx_esdhc_dt_ids[] = {
195 { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
196 { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
197 { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
198 { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
199 { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
200 { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
201 { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
204 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
206 static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
208 return data->socdata == &esdhc_imx25_data;
211 static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
213 return data->socdata == &esdhc_imx53_data;
216 static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
218 return data->socdata == &usdhc_imx6q_data;
221 static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
223 return !!(data->socdata->flags & ESDHC_FLAG_USDHC);
226 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
228 void __iomem *base = host->ioaddr + (reg & ~0x3);
229 u32 shift = (reg & 0x3) * 8;
231 writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
234 static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
236 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
237 struct pltfm_imx_data *imx_data = pltfm_host->priv;
238 u32 val = readl(host->ioaddr + reg);
240 if (unlikely(reg == SDHCI_PRESENT_STATE)) {
242 /* save the least 20 bits */
243 val = fsl_prss & 0x000FFFFF;
244 /* move dat[0-3] bits */
245 val |= (fsl_prss & 0x0F000000) >> 4;
246 /* move cmd line bit */
247 val |= (fsl_prss & 0x00800000) << 1;
250 if (unlikely(reg == SDHCI_CAPABILITIES)) {
251 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */
252 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
255 /* In FSL esdhc IC module, only bit20 is used to indicate the
256 * ADMA2 capability of esdhc, but this bit is messed up on
257 * some SOCs (e.g. on MX25, MX35 this bit is set, but they
258 * don't actually support ADMA2). So set the BROKEN_ADMA
259 * uirk on MX25/35 platforms.
262 if (val & SDHCI_CAN_DO_ADMA1) {
263 val &= ~SDHCI_CAN_DO_ADMA1;
264 val |= SDHCI_CAN_DO_ADMA2;
268 if (unlikely(reg == SDHCI_CAPABILITIES_1)) {
269 if (esdhc_is_usdhc(imx_data)) {
270 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
271 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
273 /* imx6q/dl does not have cap_1 register, fake one */
274 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
275 | SDHCI_SUPPORT_SDR50
276 | SDHCI_USE_SDR50_TUNING;
280 if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
282 val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT;
283 val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT;
284 val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT;
287 if (unlikely(reg == SDHCI_INT_STATUS)) {
288 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
289 val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
290 val |= SDHCI_INT_ADMA_ERROR;
294 * mask off the interrupt we get in response to the manually
297 if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
298 ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
299 val &= ~SDHCI_INT_RESPONSE;
300 writel(SDHCI_INT_RESPONSE, host->ioaddr +
302 imx_data->multiblock_status = NO_CMD_PENDING;
309 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
311 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
312 struct pltfm_imx_data *imx_data = pltfm_host->priv;
315 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
316 if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) {
318 * Clear and then set D3CD bit to avoid missing the
319 * card interrupt. This is a eSDHC controller problem
320 * so we need to apply the following workaround: clear
321 * and set D3CD bit will make eSDHC re-sample the card
322 * interrupt. In case a card interrupt was lost,
323 * re-sample it by the following steps.
325 data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
326 data &= ~ESDHC_CTRL_D3CD;
327 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
328 data |= ESDHC_CTRL_D3CD;
329 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
332 if (val & SDHCI_INT_ADMA_ERROR) {
333 val &= ~SDHCI_INT_ADMA_ERROR;
334 val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
338 if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
339 && (reg == SDHCI_INT_STATUS)
340 && (val & SDHCI_INT_DATA_END))) {
342 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
343 v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
344 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
346 if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
348 /* send a manual CMD12 with RESPTYP=none */
349 data = MMC_STOP_TRANSMISSION << 24 |
350 SDHCI_CMD_ABORTCMD << 16;
351 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
352 imx_data->multiblock_status = WAIT_FOR_INT;
356 writel(val, host->ioaddr + reg);
359 static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
361 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
362 struct pltfm_imx_data *imx_data = pltfm_host->priv;
366 if (unlikely(reg == SDHCI_HOST_VERSION)) {
368 if (esdhc_is_usdhc(imx_data)) {
370 * The usdhc register returns a wrong host version.
373 return SDHCI_SPEC_300;
377 if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
378 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
379 if (val & ESDHC_VENDOR_SPEC_VSELECT)
380 ret |= SDHCI_CTRL_VDD_180;
382 if (esdhc_is_usdhc(imx_data)) {
383 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
384 val = readl(host->ioaddr + ESDHC_MIX_CTRL);
385 else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
386 /* the std tuning bits is in ACMD12_ERR for imx6sl */
387 val = readl(host->ioaddr + SDHCI_ACMD12_ERR);
390 if (val & ESDHC_MIX_CTRL_EXE_TUNE)
391 ret |= SDHCI_CTRL_EXEC_TUNING;
392 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
393 ret |= SDHCI_CTRL_TUNED_CLK;
395 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
400 if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
401 if (esdhc_is_usdhc(imx_data)) {
402 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
403 ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
405 if (m & ESDHC_MIX_CTRL_AC23EN) {
406 ret &= ~ESDHC_MIX_CTRL_AC23EN;
407 ret |= SDHCI_TRNS_AUTO_CMD23;
410 ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
416 return readw(host->ioaddr + reg);
419 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
421 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
422 struct pltfm_imx_data *imx_data = pltfm_host->priv;
426 case SDHCI_CLOCK_CONTROL:
427 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
428 if (val & SDHCI_CLOCK_CARD_EN)
429 new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
431 new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
432 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
434 case SDHCI_HOST_CONTROL2:
435 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
436 if (val & SDHCI_CTRL_VDD_180)
437 new_val |= ESDHC_VENDOR_SPEC_VSELECT;
439 new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
440 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
441 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
442 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
443 if (val & SDHCI_CTRL_TUNED_CLK)
444 new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL;
446 new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
447 writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);
448 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
449 u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR);
450 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
451 if (val & SDHCI_CTRL_TUNED_CLK) {
452 v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
454 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
455 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
458 if (val & SDHCI_CTRL_EXEC_TUNING) {
459 v |= ESDHC_MIX_CTRL_EXE_TUNE;
460 m |= ESDHC_MIX_CTRL_FBCLK_SEL;
462 v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
465 writel(v, host->ioaddr + SDHCI_ACMD12_ERR);
466 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
469 case SDHCI_TRANSFER_MODE:
470 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
471 && (host->cmd->opcode == SD_IO_RW_EXTENDED)
472 && (host->cmd->data->blocks > 1)
473 && (host->cmd->data->flags & MMC_DATA_READ)) {
475 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
476 v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
477 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
480 if (esdhc_is_usdhc(imx_data)) {
481 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
483 if (val & SDHCI_TRNS_AUTO_CMD23) {
484 val &= ~SDHCI_TRNS_AUTO_CMD23;
485 val |= ESDHC_MIX_CTRL_AC23EN;
487 m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
488 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
491 * Postpone this write, we must do it together with a
492 * command write that is down below.
494 imx_data->scratchpad = val;
498 if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
499 val |= SDHCI_CMD_ABORTCMD;
501 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
502 (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
503 imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
505 if (esdhc_is_usdhc(imx_data))
507 host->ioaddr + SDHCI_TRANSFER_MODE);
509 writel(val << 16 | imx_data->scratchpad,
510 host->ioaddr + SDHCI_TRANSFER_MODE);
512 case SDHCI_BLOCK_SIZE:
513 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
516 esdhc_clrset_le(host, 0xffff, val, reg);
519 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
521 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
522 struct pltfm_imx_data *imx_data = pltfm_host->priv;
527 case SDHCI_POWER_CONTROL:
529 * FSL put some DMA bits here
530 * If your board has a regulator, code should be here
533 case SDHCI_HOST_CONTROL:
534 /* FSL messed up here, so we need to manually compose it. */
535 new_val = val & SDHCI_CTRL_LED;
536 /* ensure the endianness */
537 new_val |= ESDHC_HOST_CONTROL_LE;
538 /* bits 8&9 are reserved on mx25 */
539 if (!is_imx25_esdhc(imx_data)) {
540 /* DMA mode bits are shifted */
541 new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
545 * Do not touch buswidth bits here. This is done in
546 * esdhc_pltfm_bus_width.
547 * Do not touch the D3CD bit either which is used for the
548 * SDIO interrupt errata workaround.
550 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
552 esdhc_clrset_le(host, mask, new_val, reg);
555 esdhc_clrset_le(host, 0xff, val, reg);
558 * The esdhc has a design violation to SDHC spec which tells
559 * that software reset should not affect card detection circuit.
560 * But esdhc clears its SYSCTL register bits [0..2] during the
561 * software reset. This will stop those clocks that card detection
562 * circuit relies on. To work around it, we turn the clocks on back
563 * to keep card detection circuit functional.
565 if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) {
566 esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
568 * The reset on usdhc fails to clear MIX_CTRL register.
569 * Do it manually here.
571 if (esdhc_is_usdhc(imx_data)) {
572 /* the tuning bits should be kept during reset */
573 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
574 writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
575 host->ioaddr + ESDHC_MIX_CTRL);
576 imx_data->is_ddr = 0;
581 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
583 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
585 return pltfm_host->clock;
588 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
590 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
592 return pltfm_host->clock / 256 / 16;
595 static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
598 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
599 struct pltfm_imx_data *imx_data = pltfm_host->priv;
600 unsigned int host_clock = pltfm_host->clock;
606 host->mmc->actual_clock = 0;
608 if (esdhc_is_usdhc(imx_data)) {
609 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
610 writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
611 host->ioaddr + ESDHC_VENDOR_SPEC);
616 if (esdhc_is_usdhc(imx_data) && !imx_data->is_ddr)
619 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
620 temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
622 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
624 while (host_clock / pre_div / 16 > clock && pre_div < 256)
627 while (host_clock / pre_div / div > clock && div < 16)
630 host->mmc->actual_clock = host_clock / pre_div / div;
631 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
632 clock, host->mmc->actual_clock);
634 if (imx_data->is_ddr)
640 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
641 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
642 | (div << ESDHC_DIVIDER_SHIFT)
643 | (pre_div << ESDHC_PREDIV_SHIFT));
644 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
646 if (esdhc_is_usdhc(imx_data)) {
647 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
648 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
649 host->ioaddr + ESDHC_VENDOR_SPEC);
655 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
657 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
658 struct pltfm_imx_data *imx_data = pltfm_host->priv;
659 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
661 switch (boarddata->wp_type) {
663 return mmc_gpio_get_ro(host->mmc);
664 case ESDHC_WP_CONTROLLER:
665 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
666 SDHCI_WRITE_PROTECT);
674 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
679 case MMC_BUS_WIDTH_8:
680 ctrl = ESDHC_CTRL_8BITBUS;
682 case MMC_BUS_WIDTH_4:
683 ctrl = ESDHC_CTRL_4BITBUS;
690 esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
694 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
698 /* FIXME: delay a bit for card to be ready for next tuning due to errors */
701 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
702 reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
703 ESDHC_MIX_CTRL_FBCLK_SEL;
704 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
705 writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
706 dev_dbg(mmc_dev(host->mmc),
707 "tunning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
708 val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
711 static void esdhc_post_tuning(struct sdhci_host *host)
715 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
716 reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
717 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
720 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
722 int min, max, avg, ret;
724 /* find the mininum delay first which can pass tuning */
725 min = ESDHC_TUNE_CTRL_MIN;
726 while (min < ESDHC_TUNE_CTRL_MAX) {
727 esdhc_prepare_tuning(host, min);
728 if (!mmc_send_tuning(host->mmc))
730 min += ESDHC_TUNE_CTRL_STEP;
733 /* find the maxinum delay which can not pass tuning */
734 max = min + ESDHC_TUNE_CTRL_STEP;
735 while (max < ESDHC_TUNE_CTRL_MAX) {
736 esdhc_prepare_tuning(host, max);
737 if (mmc_send_tuning(host->mmc)) {
738 max -= ESDHC_TUNE_CTRL_STEP;
741 max += ESDHC_TUNE_CTRL_STEP;
744 /* use average delay to get the best timing */
745 avg = (min + max) / 2;
746 esdhc_prepare_tuning(host, avg);
747 ret = mmc_send_tuning(host->mmc);
748 esdhc_post_tuning(host);
750 dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n",
751 ret ? "failed" : "passed", avg, ret);
756 static int esdhc_change_pinstate(struct sdhci_host *host,
759 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
760 struct pltfm_imx_data *imx_data = pltfm_host->priv;
761 struct pinctrl_state *pinctrl;
763 dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
765 if (IS_ERR(imx_data->pinctrl) ||
766 IS_ERR(imx_data->pins_default) ||
767 IS_ERR(imx_data->pins_100mhz) ||
768 IS_ERR(imx_data->pins_200mhz))
772 case MMC_TIMING_UHS_SDR50:
773 pinctrl = imx_data->pins_100mhz;
775 case MMC_TIMING_UHS_SDR104:
776 case MMC_TIMING_MMC_HS200:
777 pinctrl = imx_data->pins_200mhz;
780 /* back to default state for other legacy timing */
781 pinctrl = imx_data->pins_default;
784 return pinctrl_select_state(imx_data->pinctrl, pinctrl);
787 static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
789 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
790 struct pltfm_imx_data *imx_data = pltfm_host->priv;
791 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
794 case MMC_TIMING_UHS_SDR12:
795 case MMC_TIMING_UHS_SDR25:
796 case MMC_TIMING_UHS_SDR50:
797 case MMC_TIMING_UHS_SDR104:
798 case MMC_TIMING_MMC_HS200:
800 case MMC_TIMING_UHS_DDR50:
801 case MMC_TIMING_MMC_DDR52:
802 writel(readl(host->ioaddr + ESDHC_MIX_CTRL) |
803 ESDHC_MIX_CTRL_DDREN,
804 host->ioaddr + ESDHC_MIX_CTRL);
805 imx_data->is_ddr = 1;
806 if (boarddata->delay_line) {
808 v = boarddata->delay_line <<
809 ESDHC_DLL_OVERRIDE_VAL_SHIFT |
810 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT);
811 if (is_imx53_esdhc(imx_data))
813 writel(v, host->ioaddr + ESDHC_DLL_CTRL);
818 esdhc_change_pinstate(host, timing);
821 static void esdhc_reset(struct sdhci_host *host, u8 mask)
823 sdhci_reset(host, mask);
825 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
826 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
829 static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host)
831 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
832 struct pltfm_imx_data *imx_data = pltfm_host->priv;
834 return esdhc_is_usdhc(imx_data) ? 1 << 28 : 1 << 27;
837 static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
839 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
840 struct pltfm_imx_data *imx_data = pltfm_host->priv;
842 /* use maximum timeout counter */
843 sdhci_writeb(host, esdhc_is_usdhc(imx_data) ? 0xF : 0xE,
844 SDHCI_TIMEOUT_CONTROL);
847 static struct sdhci_ops sdhci_esdhc_ops = {
848 .read_l = esdhc_readl_le,
849 .read_w = esdhc_readw_le,
850 .write_l = esdhc_writel_le,
851 .write_w = esdhc_writew_le,
852 .write_b = esdhc_writeb_le,
853 .set_clock = esdhc_pltfm_set_clock,
854 .get_max_clock = esdhc_pltfm_get_max_clock,
855 .get_min_clock = esdhc_pltfm_get_min_clock,
856 .get_max_timeout_count = esdhc_get_max_timeout_count,
857 .get_ro = esdhc_pltfm_get_ro,
858 .set_timeout = esdhc_set_timeout,
859 .set_bus_width = esdhc_pltfm_set_bus_width,
860 .set_uhs_signaling = esdhc_set_uhs_signaling,
861 .reset = esdhc_reset,
864 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
865 .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
866 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
867 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
868 | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
869 .ops = &sdhci_esdhc_ops,
874 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
875 struct sdhci_host *host,
876 struct pltfm_imx_data *imx_data)
878 struct device_node *np = pdev->dev.of_node;
879 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
882 if (of_get_property(np, "fsl,wp-controller", NULL))
883 boarddata->wp_type = ESDHC_WP_CONTROLLER;
885 boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
886 if (gpio_is_valid(boarddata->wp_gpio))
887 boarddata->wp_type = ESDHC_WP_GPIO;
889 if (of_find_property(np, "no-1-8-v", NULL))
890 boarddata->support_vsel = false;
892 boarddata->support_vsel = true;
894 if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
895 boarddata->delay_line = 0;
897 mmc_of_parse_voltage(np, &host->ocr_mask);
899 /* sdr50 and sdr104 needs work on 1.8v signal voltage */
900 if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data) &&
901 !IS_ERR(imx_data->pins_default)) {
902 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
903 ESDHC_PINCTRL_STATE_100MHZ);
904 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
905 ESDHC_PINCTRL_STATE_200MHZ);
906 if (IS_ERR(imx_data->pins_100mhz) ||
907 IS_ERR(imx_data->pins_200mhz)) {
908 dev_warn(mmc_dev(host->mmc),
909 "could not get ultra high speed state, work on normal mode\n");
911 * fall back to not support uhs by specify no 1.8v quirk
913 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
916 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
919 /* call to generic mmc_of_parse to support additional capabilities */
920 ret = mmc_of_parse(host->mmc);
924 if (!IS_ERR_VALUE(mmc_gpio_get_cd(host->mmc)))
925 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
931 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
932 struct sdhci_host *host,
933 struct pltfm_imx_data *imx_data)
939 static int sdhci_esdhc_imx_probe_nondt(struct platform_device *pdev,
940 struct sdhci_host *host,
941 struct pltfm_imx_data *imx_data)
943 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
946 if (!host->mmc->parent->platform_data) {
947 dev_err(mmc_dev(host->mmc), "no board data!\n");
951 imx_data->boarddata = *((struct esdhc_platform_data *)
952 host->mmc->parent->platform_data);
954 if (boarddata->wp_type == ESDHC_WP_GPIO) {
955 err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio);
957 dev_err(mmc_dev(host->mmc),
958 "failed to request write-protect gpio!\n");
961 host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
965 switch (boarddata->cd_type) {
967 err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0);
969 dev_err(mmc_dev(host->mmc),
970 "failed to request card-detect gpio!\n");
975 case ESDHC_CD_CONTROLLER:
976 /* we have a working card_detect back */
977 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
980 case ESDHC_CD_PERMANENT:
981 host->mmc->caps |= MMC_CAP_NONREMOVABLE;
988 switch (boarddata->max_bus_width) {
990 host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA;
993 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
997 host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
1004 static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
1006 const struct of_device_id *of_id =
1007 of_match_device(imx_esdhc_dt_ids, &pdev->dev);
1008 struct sdhci_pltfm_host *pltfm_host;
1009 struct sdhci_host *host;
1011 struct pltfm_imx_data *imx_data;
1013 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 0);
1015 return PTR_ERR(host);
1017 pltfm_host = sdhci_priv(host);
1019 imx_data = devm_kzalloc(&pdev->dev, sizeof(*imx_data), GFP_KERNEL);
1025 imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *)
1026 pdev->id_entry->driver_data;
1027 pltfm_host->priv = imx_data;
1029 imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1030 if (IS_ERR(imx_data->clk_ipg)) {
1031 err = PTR_ERR(imx_data->clk_ipg);
1035 imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1036 if (IS_ERR(imx_data->clk_ahb)) {
1037 err = PTR_ERR(imx_data->clk_ahb);
1041 imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
1042 if (IS_ERR(imx_data->clk_per)) {
1043 err = PTR_ERR(imx_data->clk_per);
1047 pltfm_host->clk = imx_data->clk_per;
1048 pltfm_host->clock = clk_get_rate(pltfm_host->clk);
1049 clk_prepare_enable(imx_data->clk_per);
1050 clk_prepare_enable(imx_data->clk_ipg);
1051 clk_prepare_enable(imx_data->clk_ahb);
1053 imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
1054 if (IS_ERR(imx_data->pinctrl)) {
1055 err = PTR_ERR(imx_data->pinctrl);
1059 imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl,
1060 PINCTRL_STATE_DEFAULT);
1061 if (IS_ERR(imx_data->pins_default))
1062 dev_warn(mmc_dev(host->mmc), "could not get default state\n");
1064 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
1066 if (imx_data->socdata->flags & ESDHC_FLAG_ENGCM07207)
1067 /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */
1068 host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK
1069 | SDHCI_QUIRK_BROKEN_ADMA;
1072 * The imx6q ROM code will change the default watermark level setting
1073 * to something insane. Change it back here.
1075 if (esdhc_is_usdhc(imx_data)) {
1076 writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL);
1077 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
1078 host->mmc->caps |= MMC_CAP_1_8V_DDR;
1080 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200))
1081 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
1084 * errata ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
1085 * TO1.1, it's harmless for MX6SL
1087 writel(readl(host->ioaddr + 0x6c) | BIT(7),
1088 host->ioaddr + 0x6c);
1091 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
1092 sdhci_esdhc_ops.platform_execute_tuning =
1093 esdhc_executing_tuning;
1095 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
1096 writel(readl(host->ioaddr + ESDHC_TUNING_CTRL) |
1097 ESDHC_STD_TUNING_EN | ESDHC_TUNING_START_TAP,
1098 host->ioaddr + ESDHC_TUNING_CTRL);
1100 if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
1101 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1104 err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
1106 err = sdhci_esdhc_imx_probe_nondt(pdev, host, imx_data);
1110 err = sdhci_add_host(host);
1114 pm_runtime_set_active(&pdev->dev);
1115 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1116 pm_runtime_use_autosuspend(&pdev->dev);
1117 pm_suspend_ignore_children(&pdev->dev, 1);
1118 pm_runtime_enable(&pdev->dev);
1123 clk_disable_unprepare(imx_data->clk_per);
1124 clk_disable_unprepare(imx_data->clk_ipg);
1125 clk_disable_unprepare(imx_data->clk_ahb);
1127 sdhci_pltfm_free(pdev);
1131 static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
1133 struct sdhci_host *host = platform_get_drvdata(pdev);
1134 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1135 struct pltfm_imx_data *imx_data = pltfm_host->priv;
1136 int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
1138 pm_runtime_get_sync(&pdev->dev);
1139 pm_runtime_disable(&pdev->dev);
1140 pm_runtime_put_noidle(&pdev->dev);
1142 sdhci_remove_host(host, dead);
1144 clk_disable_unprepare(imx_data->clk_per);
1145 clk_disable_unprepare(imx_data->clk_ipg);
1146 clk_disable_unprepare(imx_data->clk_ahb);
1148 sdhci_pltfm_free(pdev);
1154 static int sdhci_esdhc_runtime_suspend(struct device *dev)
1156 struct sdhci_host *host = dev_get_drvdata(dev);
1157 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1158 struct pltfm_imx_data *imx_data = pltfm_host->priv;
1161 ret = sdhci_runtime_suspend_host(host);
1163 if (!sdhci_sdio_irq_enabled(host)) {
1164 clk_disable_unprepare(imx_data->clk_per);
1165 clk_disable_unprepare(imx_data->clk_ipg);
1167 clk_disable_unprepare(imx_data->clk_ahb);
1172 static int sdhci_esdhc_runtime_resume(struct device *dev)
1174 struct sdhci_host *host = dev_get_drvdata(dev);
1175 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1176 struct pltfm_imx_data *imx_data = pltfm_host->priv;
1178 if (!sdhci_sdio_irq_enabled(host)) {
1179 clk_prepare_enable(imx_data->clk_per);
1180 clk_prepare_enable(imx_data->clk_ipg);
1182 clk_prepare_enable(imx_data->clk_ahb);
1184 return sdhci_runtime_resume_host(host);
1188 static const struct dev_pm_ops sdhci_esdhc_pmops = {
1189 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pltfm_suspend, sdhci_pltfm_resume)
1190 SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend,
1191 sdhci_esdhc_runtime_resume, NULL)
1194 static struct platform_driver sdhci_esdhc_imx_driver = {
1196 .name = "sdhci-esdhc-imx",
1197 .of_match_table = imx_esdhc_dt_ids,
1198 .pm = &sdhci_esdhc_pmops,
1200 .id_table = imx_esdhc_devtype,
1201 .probe = sdhci_esdhc_imx_probe,
1202 .remove = sdhci_esdhc_imx_remove,
1205 module_platform_driver(sdhci_esdhc_imx_driver);
1207 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
1208 MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
1209 MODULE_LICENSE("GPL v2");