1 // SPDX-License-Identifier: GPL-2.0-only
3 * Secure Digital Host Controller Interface ACPI driver.
5 * Copyright (c) 2012, Intel Corporation.
8 #include <linux/bitfield.h>
9 #include <linux/init.h>
10 #include <linux/export.h>
11 #include <linux/module.h>
12 #include <linux/device.h>
13 #include <linux/platform_device.h>
14 #include <linux/ioport.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/compiler.h>
18 #include <linux/stddef.h>
19 #include <linux/bitops.h>
20 #include <linux/types.h>
21 #include <linux/err.h>
22 #include <linux/interrupt.h>
23 #include <linux/acpi.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/delay.h>
27 #include <linux/dmi.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/pm.h>
31 #include <linux/mmc/slot-gpio.h>
34 #include <linux/platform_data/x86/soc.h>
35 #include <asm/iosf_mbi.h>
41 SDHCI_ACPI_SD_CD = BIT(0),
42 SDHCI_ACPI_RUNTIME_PM = BIT(1),
43 SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL = BIT(2),
46 struct sdhci_acpi_chip {
47 const struct sdhci_ops *ops;
52 mmc_pm_flag_t pm_caps;
55 struct sdhci_acpi_slot {
56 const struct sdhci_acpi_chip *chip;
61 mmc_pm_flag_t pm_caps;
64 int (*probe_slot)(struct platform_device *, struct acpi_device *);
65 int (*remove_slot)(struct platform_device *);
66 int (*free_slot)(struct platform_device *pdev);
67 int (*setup_host)(struct platform_device *pdev);
70 struct sdhci_acpi_host {
71 struct sdhci_host *host;
72 const struct sdhci_acpi_slot *slot;
73 struct platform_device *pdev;
76 bool reset_signal_volt_on_suspend;
77 unsigned long private[] ____cacheline_aligned;
81 DMI_QUIRK_RESET_SD_SIGNAL_VOLT_ON_SUSP = BIT(0),
82 DMI_QUIRK_SD_NO_WRITE_PROTECT = BIT(1),
85 static inline void *sdhci_acpi_priv(struct sdhci_acpi_host *c)
87 return (void *)c->private;
90 static inline bool sdhci_acpi_flag(struct sdhci_acpi_host *c, unsigned int flag)
92 return c->slot && (c->slot->flags & flag);
95 #define INTEL_DSM_HS_CAPS_SDR25 BIT(0)
96 #define INTEL_DSM_HS_CAPS_DDR50 BIT(1)
97 #define INTEL_DSM_HS_CAPS_SDR50 BIT(2)
98 #define INTEL_DSM_HS_CAPS_SDR104 BIT(3)
102 INTEL_DSM_V18_SWITCH = 3,
103 INTEL_DSM_V33_SWITCH = 4,
104 INTEL_DSM_HS_CAPS = 8,
112 static const guid_t intel_dsm_guid =
113 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F,
114 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61);
116 static int __intel_dsm(struct intel_host *intel_host, struct device *dev,
117 unsigned int fn, u32 *result)
119 union acpi_object *obj;
122 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL);
126 if (obj->type == ACPI_TYPE_INTEGER) {
127 *result = obj->integer.value;
128 } else if (obj->type == ACPI_TYPE_BUFFER && obj->buffer.length > 0) {
129 size_t len = min_t(size_t, obj->buffer.length, 4);
132 memcpy(result, obj->buffer.pointer, len);
134 dev_err(dev, "%s DSM fn %u obj->type %d obj->buffer.length %d\n",
135 __func__, fn, obj->type, obj->buffer.length);
144 static int intel_dsm(struct intel_host *intel_host, struct device *dev,
145 unsigned int fn, u32 *result)
147 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn)))
150 return __intel_dsm(intel_host, dev, fn, result);
153 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev,
154 struct mmc_host *mmc)
158 intel_host->hs_caps = ~0;
160 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns);
162 pr_debug("%s: DSM not supported, error %d\n",
163 mmc_hostname(mmc), err);
167 pr_debug("%s: DSM function mask %#x\n",
168 mmc_hostname(mmc), intel_host->dsm_fns);
170 intel_dsm(intel_host, dev, INTEL_DSM_HS_CAPS, &intel_host->hs_caps);
173 static int intel_start_signal_voltage_switch(struct mmc_host *mmc,
176 struct device *dev = mmc_dev(mmc);
177 struct sdhci_acpi_host *c = dev_get_drvdata(dev);
178 struct intel_host *intel_host = sdhci_acpi_priv(c);
183 err = sdhci_start_signal_voltage_switch(mmc, ios);
187 switch (ios->signal_voltage) {
188 case MMC_SIGNAL_VOLTAGE_330:
189 fn = INTEL_DSM_V33_SWITCH;
191 case MMC_SIGNAL_VOLTAGE_180:
192 fn = INTEL_DSM_V18_SWITCH;
198 err = intel_dsm(intel_host, dev, fn, &result);
199 pr_debug("%s: %s DSM fn %u error %d result %u\n",
200 mmc_hostname(mmc), __func__, fn, err, result);
205 static void sdhci_acpi_int_hw_reset(struct sdhci_host *host)
209 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
211 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
212 /* For eMMC, minimum is 1us but give it 9us for good measure */
215 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
216 /* For eMMC, minimum is 200us but give it 300us for good measure */
217 usleep_range(300, 1000);
220 static const struct sdhci_ops sdhci_acpi_ops_dflt = {
221 .set_clock = sdhci_set_clock,
222 .set_bus_width = sdhci_set_bus_width,
223 .reset = sdhci_reset,
224 .set_uhs_signaling = sdhci_set_uhs_signaling,
227 static const struct sdhci_ops sdhci_acpi_ops_int = {
228 .set_clock = sdhci_set_clock,
229 .set_bus_width = sdhci_set_bus_width,
230 .reset = sdhci_reset,
231 .set_uhs_signaling = sdhci_set_uhs_signaling,
232 .hw_reset = sdhci_acpi_int_hw_reset,
235 static const struct sdhci_acpi_chip sdhci_acpi_chip_int = {
236 .ops = &sdhci_acpi_ops_int,
241 #define BYT_IOSF_SCCEP 0x63
242 #define BYT_IOSF_OCP_NETCTRL0 0x1078
243 #define BYT_IOSF_OCP_TIMEOUT_BASE GENMASK(10, 8)
245 static void sdhci_acpi_byt_setting(struct device *dev)
249 if (!soc_intel_is_byt())
252 if (iosf_mbi_read(BYT_IOSF_SCCEP, MBI_CR_READ, BYT_IOSF_OCP_NETCTRL0,
254 dev_err(dev, "%s read error\n", __func__);
258 if (!(val & BYT_IOSF_OCP_TIMEOUT_BASE))
261 val &= ~BYT_IOSF_OCP_TIMEOUT_BASE;
263 if (iosf_mbi_write(BYT_IOSF_SCCEP, MBI_CR_WRITE, BYT_IOSF_OCP_NETCTRL0,
265 dev_err(dev, "%s write error\n", __func__);
269 dev_dbg(dev, "%s completed\n", __func__);
272 static bool sdhci_acpi_byt_defer(struct device *dev)
274 if (!soc_intel_is_byt())
277 if (!iosf_mbi_available())
280 sdhci_acpi_byt_setting(dev);
287 static inline void sdhci_acpi_byt_setting(struct device *dev)
291 static inline bool sdhci_acpi_byt_defer(struct device *dev)
298 static int bxt_get_cd(struct mmc_host *mmc)
300 int gpio_cd = mmc_gpio_get_cd(mmc);
305 return sdhci_get_cd_nogpio(mmc);
308 static int intel_probe_slot(struct platform_device *pdev, struct acpi_device *adev)
310 struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
311 struct intel_host *intel_host = sdhci_acpi_priv(c);
312 struct sdhci_host *host = c->host;
314 if (acpi_dev_hid_uid_match(adev, "80860F14", "1") &&
315 sdhci_readl(host, SDHCI_CAPABILITIES) == 0x446cc8b2 &&
316 sdhci_readl(host, SDHCI_CAPABILITIES_1) == 0x00000807)
317 host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
319 if (acpi_dev_hid_uid_match(adev, "80865ACA", NULL))
320 host->mmc_host_ops.get_cd = bxt_get_cd;
322 intel_dsm_init(intel_host, &pdev->dev, host->mmc);
324 host->mmc_host_ops.start_signal_voltage_switch =
325 intel_start_signal_voltage_switch;
332 static int intel_setup_host(struct platform_device *pdev)
334 struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
335 struct intel_host *intel_host = sdhci_acpi_priv(c);
337 if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR25))
338 c->host->mmc->caps &= ~MMC_CAP_UHS_SDR25;
340 if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR50))
341 c->host->mmc->caps &= ~MMC_CAP_UHS_SDR50;
343 if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_DDR50))
344 c->host->mmc->caps &= ~MMC_CAP_UHS_DDR50;
346 if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR104))
347 c->host->mmc->caps &= ~MMC_CAP_UHS_SDR104;
352 static const struct sdhci_acpi_slot sdhci_acpi_slot_int_emmc = {
353 .chip = &sdhci_acpi_chip_int,
354 .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
355 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
356 MMC_CAP_CMD_DURING_TFR | MMC_CAP_WAIT_WHILE_BUSY,
357 .flags = SDHCI_ACPI_RUNTIME_PM,
358 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
360 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
361 SDHCI_QUIRK2_STOP_WITH_TC |
362 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400,
363 .probe_slot = intel_probe_slot,
364 .setup_host = intel_setup_host,
365 .priv_size = sizeof(struct intel_host),
368 static const struct sdhci_acpi_slot sdhci_acpi_slot_int_sdio = {
369 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
371 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
372 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
373 .caps = MMC_CAP_NONREMOVABLE | MMC_CAP_POWER_OFF_CARD |
374 MMC_CAP_WAIT_WHILE_BUSY,
375 .flags = SDHCI_ACPI_RUNTIME_PM,
376 .pm_caps = MMC_PM_KEEP_POWER,
377 .probe_slot = intel_probe_slot,
378 .setup_host = intel_setup_host,
379 .priv_size = sizeof(struct intel_host),
382 static const struct sdhci_acpi_slot sdhci_acpi_slot_int_sd = {
383 .flags = SDHCI_ACPI_SD_CD | SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL |
384 SDHCI_ACPI_RUNTIME_PM,
385 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
387 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
388 SDHCI_QUIRK2_STOP_WITH_TC,
389 .caps = MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_AGGRESSIVE_PM,
390 .probe_slot = intel_probe_slot,
391 .setup_host = intel_setup_host,
392 .priv_size = sizeof(struct intel_host),
395 #define VENDOR_SPECIFIC_PWRCTL_CLEAR_REG 0x1a8
396 #define VENDOR_SPECIFIC_PWRCTL_CTL_REG 0x1ac
397 static irqreturn_t sdhci_acpi_qcom_handler(int irq, void *ptr)
399 struct sdhci_host *host = ptr;
401 sdhci_writel(host, 0x3, VENDOR_SPECIFIC_PWRCTL_CLEAR_REG);
402 sdhci_writel(host, 0x1, VENDOR_SPECIFIC_PWRCTL_CTL_REG);
407 static int qcom_probe_slot(struct platform_device *pdev, struct acpi_device *adev)
409 struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
410 struct sdhci_host *host = c->host;
411 int *irq = sdhci_acpi_priv(c);
415 if (!acpi_dev_hid_uid_match(adev, "QCOM8051", NULL))
418 *irq = platform_get_irq(pdev, 1);
422 return request_threaded_irq(*irq, NULL, sdhci_acpi_qcom_handler,
423 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
427 static int qcom_free_slot(struct platform_device *pdev)
429 struct device *dev = &pdev->dev;
430 struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
431 struct sdhci_host *host = c->host;
432 struct acpi_device *adev;
433 int *irq = sdhci_acpi_priv(c);
435 adev = ACPI_COMPANION(dev);
439 if (!acpi_dev_hid_uid_match(adev, "QCOM8051", NULL))
445 free_irq(*irq, host);
449 static const struct sdhci_acpi_slot sdhci_acpi_slot_qcom_sd_3v = {
450 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION,
451 .quirks2 = SDHCI_QUIRK2_NO_1_8_V,
452 .caps = MMC_CAP_NONREMOVABLE,
453 .priv_size = sizeof(int),
454 .probe_slot = qcom_probe_slot,
455 .free_slot = qcom_free_slot,
458 static const struct sdhci_acpi_slot sdhci_acpi_slot_qcom_sd = {
459 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION,
460 .caps = MMC_CAP_NONREMOVABLE,
463 struct amd_sdhci_host {
468 /* AMD sdhci reset dll register. */
469 #define SDHCI_AMD_RESET_DLL_REGISTER 0x908
471 static int amd_select_drive_strength(struct mmc_card *card,
472 unsigned int max_dtr, int host_drv,
473 int card_drv, int *host_driver_strength)
475 struct sdhci_host *host = mmc_priv(card->host);
476 u16 preset, preset_driver_strength;
479 * This method is only called by mmc_select_hs200 so we only need to
480 * read from the HS200 (SDR104) preset register.
482 * Firmware that has "invalid/default" presets return a driver strength
483 * of A. This matches the previously hard coded value.
485 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
486 preset_driver_strength = FIELD_GET(SDHCI_PRESET_DRV_MASK, preset);
489 * We want the controller driver strength to match the card's driver
490 * strength so they have similar rise/fall times.
492 * The controller driver strength set by this method is sticky for all
493 * timings after this method is called. This unfortunately means that
494 * while HS400 tuning is in progress we end up with mismatched driver
495 * strengths between the controller and the card. HS400 tuning requires
496 * switching from HS400->DDR52->HS->HS200->HS400. So the driver mismatch
497 * happens while in DDR52 and HS modes. This has not been observed to
498 * cause problems. Enabling presets would fix this issue.
500 *host_driver_strength = preset_driver_strength;
503 * The resulting card driver strength is only set when switching the
504 * card's timing to HS200 or HS400. The card will use the default driver
505 * strength (B) for any other mode.
507 return preset_driver_strength;
510 static void sdhci_acpi_amd_hs400_dll(struct sdhci_host *host, bool enable)
512 struct sdhci_acpi_host *acpi_host = sdhci_priv(host);
513 struct amd_sdhci_host *amd_host = sdhci_acpi_priv(acpi_host);
515 /* AMD Platform requires dll setting */
516 sdhci_writel(host, 0x40003210, SDHCI_AMD_RESET_DLL_REGISTER);
517 usleep_range(10, 20);
519 sdhci_writel(host, 0x40033210, SDHCI_AMD_RESET_DLL_REGISTER);
521 amd_host->dll_enabled = enable;
525 * The initialization sequence for HS400 is:
526 * HS->HS200->Perform Tuning->HS->HS400
528 * The re-tuning sequence is:
529 * HS400->DDR52->HS->HS200->Perform Tuning->HS->HS400
531 * The AMD eMMC Controller can only use the tuned clock while in HS200 and HS400
532 * mode. If we switch to a different mode, we need to disable the tuned clock.
533 * If we have previously performed tuning and switch back to HS200 or
534 * HS400, we can re-enable the tuned clock.
537 static void amd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
539 struct sdhci_host *host = mmc_priv(mmc);
540 struct sdhci_acpi_host *acpi_host = sdhci_priv(host);
541 struct amd_sdhci_host *amd_host = sdhci_acpi_priv(acpi_host);
542 unsigned int old_timing = host->timing;
545 sdhci_set_ios(mmc, ios);
547 if (old_timing != host->timing && amd_host->tuned_clock) {
548 if (host->timing == MMC_TIMING_MMC_HS400 ||
549 host->timing == MMC_TIMING_MMC_HS200) {
550 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
551 val |= SDHCI_CTRL_TUNED_CLK;
552 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
554 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
555 val &= ~SDHCI_CTRL_TUNED_CLK;
556 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
559 /* DLL is only required for HS400 */
560 if (host->timing == MMC_TIMING_MMC_HS400 &&
561 !amd_host->dll_enabled)
562 sdhci_acpi_amd_hs400_dll(host, true);
566 static int amd_sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
569 struct sdhci_host *host = mmc_priv(mmc);
570 struct sdhci_acpi_host *acpi_host = sdhci_priv(host);
571 struct amd_sdhci_host *amd_host = sdhci_acpi_priv(acpi_host);
573 amd_host->tuned_clock = false;
575 err = sdhci_execute_tuning(mmc, opcode);
577 if (!err && !host->tuning_err)
578 amd_host->tuned_clock = true;
583 static void amd_sdhci_reset(struct sdhci_host *host, u8 mask)
585 struct sdhci_acpi_host *acpi_host = sdhci_priv(host);
586 struct amd_sdhci_host *amd_host = sdhci_acpi_priv(acpi_host);
588 if (mask & SDHCI_RESET_ALL) {
589 amd_host->tuned_clock = false;
590 sdhci_acpi_amd_hs400_dll(host, false);
593 sdhci_reset(host, mask);
596 static const struct sdhci_ops sdhci_acpi_ops_amd = {
597 .set_clock = sdhci_set_clock,
598 .set_bus_width = sdhci_set_bus_width,
599 .reset = amd_sdhci_reset,
600 .set_uhs_signaling = sdhci_set_uhs_signaling,
603 static const struct sdhci_acpi_chip sdhci_acpi_chip_amd = {
604 .ops = &sdhci_acpi_ops_amd,
607 static int sdhci_acpi_emmc_amd_probe_slot(struct platform_device *pdev,
608 struct acpi_device *adev)
610 struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
611 struct sdhci_host *host = c->host;
613 sdhci_read_caps(host);
614 if (host->caps1 & SDHCI_SUPPORT_DDR50)
615 host->mmc->caps = MMC_CAP_1_8V_DDR;
617 if ((host->caps1 & SDHCI_SUPPORT_SDR104) &&
618 (host->mmc->caps & MMC_CAP_1_8V_DDR))
619 host->mmc->caps2 = MMC_CAP2_HS400_1_8V;
622 * There are two types of presets out in the wild:
623 * 1) Default/broken presets.
624 * These presets have two sets of problems:
625 * a) The clock divisor for SDR12, SDR25, and SDR50 is too small.
626 * This results in clock frequencies that are 2x higher than
627 * acceptable. i.e., SDR12 = 25 MHz, SDR25 = 50 MHz, SDR50 =
629 * b) The HS200 and HS400 driver strengths don't match.
630 * By default, the SDR104 preset register has a driver strength of
631 * A, but the (internal) HS400 preset register has a driver
632 * strength of B. As part of initializing HS400, HS200 tuning
633 * needs to be performed. Having different driver strengths
634 * between tuning and operation is wrong. It results in different
635 * rise/fall times that lead to incorrect sampling.
636 * 2) Firmware with properly initialized presets.
637 * These presets have proper clock divisors. i.e., SDR12 => 12MHz,
638 * SDR25 => 25 MHz, SDR50 => 50 MHz. Additionally the HS200 and
639 * HS400 preset driver strengths match.
641 * Enabling presets for HS400 doesn't work for the following reasons:
642 * 1) sdhci_set_ios has a hard coded list of timings that are used
643 * to determine if presets should be enabled.
644 * 2) sdhci_get_preset_value is using a non-standard register to
645 * read out HS400 presets. The AMD controller doesn't support this
646 * non-standard register. In fact, it doesn't expose the HS400
647 * preset register anywhere in the SDHCI memory map. This results
648 * in reading a garbage value and using the wrong presets.
650 * Since HS400 and HS200 presets must be identical, we could
651 * instead use the SDR104 preset register.
653 * If the above issues are resolved we could remove this quirk for
654 * firmware that has valid presets (i.e., SDR12 <= 12 MHz).
656 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
658 host->mmc_host_ops.select_drive_strength = amd_select_drive_strength;
659 host->mmc_host_ops.set_ios = amd_set_ios;
660 host->mmc_host_ops.execute_tuning = amd_sdhci_execute_tuning;
664 static const struct sdhci_acpi_slot sdhci_acpi_slot_amd_emmc = {
665 .chip = &sdhci_acpi_chip_amd,
666 .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
667 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
668 SDHCI_QUIRK_32BIT_DMA_SIZE |
669 SDHCI_QUIRK_32BIT_ADMA_SIZE,
670 .quirks2 = SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
671 .probe_slot = sdhci_acpi_emmc_amd_probe_slot,
672 .priv_size = sizeof(struct amd_sdhci_host),
675 struct sdhci_acpi_uid_slot {
678 const struct sdhci_acpi_slot *slot;
681 static const struct sdhci_acpi_uid_slot sdhci_acpi_uids[] = {
682 { "80865ACA", NULL, &sdhci_acpi_slot_int_sd },
683 { "80865ACC", NULL, &sdhci_acpi_slot_int_emmc },
684 { "80865AD0", NULL, &sdhci_acpi_slot_int_sdio },
685 { "80860F14" , "1" , &sdhci_acpi_slot_int_emmc },
686 { "80860F14" , "2" , &sdhci_acpi_slot_int_sdio },
687 { "80860F14" , "3" , &sdhci_acpi_slot_int_sd },
688 { "80860F16" , NULL, &sdhci_acpi_slot_int_sd },
689 { "INT33BB" , "2" , &sdhci_acpi_slot_int_sdio },
690 { "INT33BB" , "3" , &sdhci_acpi_slot_int_sd },
691 { "INT33C6" , NULL, &sdhci_acpi_slot_int_sdio },
692 { "INT3436" , NULL, &sdhci_acpi_slot_int_sdio },
693 { "INT344D" , NULL, &sdhci_acpi_slot_int_sdio },
694 { "PNP0FFF" , "3" , &sdhci_acpi_slot_int_sd },
696 { "QCOM8051", NULL, &sdhci_acpi_slot_qcom_sd_3v },
697 { "QCOM8052", NULL, &sdhci_acpi_slot_qcom_sd },
698 { "AMDI0040", NULL, &sdhci_acpi_slot_amd_emmc },
699 { "AMDI0041", NULL, &sdhci_acpi_slot_amd_emmc },
703 static const struct acpi_device_id sdhci_acpi_ids[] = {
720 MODULE_DEVICE_TABLE(acpi, sdhci_acpi_ids);
722 static const struct dmi_system_id sdhci_acpi_quirks[] = {
725 * The Lenovo Miix 320-10ICR has a bug in the _PS0 method of
726 * the SHC1 ACPI device, this bug causes it to reprogram the
727 * wrong LDO (DLDO3) to 1.8V if 1.8V modes are used and the
728 * card is (runtime) suspended + resumed. DLDO3 is used for
729 * the LCD and setting it to 1.8V causes the LCD to go black.
732 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
733 DMI_MATCH(DMI_PRODUCT_VERSION, "Lenovo MIIX 320-10ICR"),
735 .driver_data = (void *)DMI_QUIRK_RESET_SD_SIGNAL_VOLT_ON_SUSP,
739 * The Acer Aspire Switch 10 (SW5-012) microSD slot always
740 * reports the card being write-protected even though microSD
741 * cards do not have a write-protect switch at all.
744 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
745 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire SW5-012"),
747 .driver_data = (void *)DMI_QUIRK_SD_NO_WRITE_PROTECT,
751 * The Toshiba WT8-B's microSD slot always reports the card being
755 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
756 DMI_MATCH(DMI_PRODUCT_NAME, "TOSHIBA ENCORE 2 WT8-B"),
758 .driver_data = (void *)DMI_QUIRK_SD_NO_WRITE_PROTECT,
760 {} /* Terminating entry */
763 static const struct sdhci_acpi_slot *sdhci_acpi_get_slot(struct acpi_device *adev)
765 const struct sdhci_acpi_uid_slot *u;
767 for (u = sdhci_acpi_uids; u->hid; u++) {
768 if (acpi_dev_hid_uid_match(adev, u->hid, u->uid))
774 static int sdhci_acpi_probe(struct platform_device *pdev)
776 struct device *dev = &pdev->dev;
777 const struct sdhci_acpi_slot *slot;
778 const struct dmi_system_id *id;
779 struct acpi_device *device;
780 struct sdhci_acpi_host *c;
781 struct sdhci_host *host;
782 struct resource *iomem;
788 device = ACPI_COMPANION(dev);
792 id = dmi_first_match(sdhci_acpi_quirks);
794 quirks = (long)id->driver_data;
796 slot = sdhci_acpi_get_slot(device);
798 /* Power on the SDHCI controller and its children */
799 acpi_device_fix_up_power_extended(device);
801 if (sdhci_acpi_byt_defer(dev))
802 return -EPROBE_DEFER;
804 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
808 len = resource_size(iomem);
810 dev_err(dev, "Invalid iomem size!\n");
812 if (!devm_request_mem_region(dev, iomem->start, len, dev_name(dev)))
815 priv_size = slot ? slot->priv_size : 0;
816 host = sdhci_alloc_host(dev, sizeof(struct sdhci_acpi_host) + priv_size);
818 return PTR_ERR(host);
820 c = sdhci_priv(host);
824 c->use_runtime_pm = sdhci_acpi_flag(c, SDHCI_ACPI_RUNTIME_PM);
826 platform_set_drvdata(pdev, c);
828 host->hw_name = "ACPI";
829 host->ops = &sdhci_acpi_ops_dflt;
830 host->irq = platform_get_irq(pdev, 0);
836 host->ioaddr = devm_ioremap(dev, iomem->start,
837 resource_size(iomem));
838 if (host->ioaddr == NULL) {
844 if (c->slot->probe_slot) {
845 err = c->slot->probe_slot(pdev, device);
850 host->ops = c->slot->chip->ops;
851 host->quirks |= c->slot->chip->quirks;
852 host->quirks2 |= c->slot->chip->quirks2;
853 host->mmc->caps |= c->slot->chip->caps;
854 host->mmc->caps2 |= c->slot->chip->caps2;
855 host->mmc->pm_caps |= c->slot->chip->pm_caps;
857 host->quirks |= c->slot->quirks;
858 host->quirks2 |= c->slot->quirks2;
859 host->mmc->caps |= c->slot->caps;
860 host->mmc->caps2 |= c->slot->caps2;
861 host->mmc->pm_caps |= c->slot->pm_caps;
864 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
866 if (sdhci_acpi_flag(c, SDHCI_ACPI_SD_CD)) {
867 bool v = sdhci_acpi_flag(c, SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL);
869 err = mmc_gpiod_request_cd(host->mmc, NULL, 0, v, 0);
871 if (err == -EPROBE_DEFER)
873 dev_warn(dev, "failed to setup card detect gpio\n");
874 c->use_runtime_pm = false;
877 if (quirks & DMI_QUIRK_RESET_SD_SIGNAL_VOLT_ON_SUSP)
878 c->reset_signal_volt_on_suspend = true;
880 if (quirks & DMI_QUIRK_SD_NO_WRITE_PROTECT)
881 host->mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT;
884 err = sdhci_setup_host(host);
888 if (c->slot && c->slot->setup_host) {
889 err = c->slot->setup_host(pdev);
894 err = __sdhci_add_host(host);
898 if (c->use_runtime_pm) {
899 pm_runtime_set_active(dev);
900 pm_suspend_ignore_children(dev, 1);
901 pm_runtime_set_autosuspend_delay(dev, 50);
902 pm_runtime_use_autosuspend(dev);
903 pm_runtime_enable(dev);
906 device_enable_async_suspend(dev);
911 sdhci_cleanup_host(c->host);
913 if (c->slot && c->slot->free_slot)
914 c->slot->free_slot(pdev);
916 sdhci_free_host(c->host);
920 static int sdhci_acpi_remove(struct platform_device *pdev)
922 struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
923 struct device *dev = &pdev->dev;
926 if (c->use_runtime_pm) {
927 pm_runtime_get_sync(dev);
928 pm_runtime_disable(dev);
929 pm_runtime_put_noidle(dev);
932 if (c->slot && c->slot->remove_slot)
933 c->slot->remove_slot(pdev);
935 dead = (sdhci_readl(c->host, SDHCI_INT_STATUS) == ~0);
936 sdhci_remove_host(c->host, dead);
938 if (c->slot && c->slot->free_slot)
939 c->slot->free_slot(pdev);
941 sdhci_free_host(c->host);
946 static void __maybe_unused sdhci_acpi_reset_signal_voltage_if_needed(
949 struct sdhci_acpi_host *c = dev_get_drvdata(dev);
950 struct sdhci_host *host = c->host;
952 if (c->is_intel && c->reset_signal_volt_on_suspend &&
953 host->mmc->ios.signal_voltage != MMC_SIGNAL_VOLTAGE_330) {
954 struct intel_host *intel_host = sdhci_acpi_priv(c);
955 unsigned int fn = INTEL_DSM_V33_SWITCH;
958 intel_dsm(intel_host, dev, fn, &result);
962 #ifdef CONFIG_PM_SLEEP
964 static int sdhci_acpi_suspend(struct device *dev)
966 struct sdhci_acpi_host *c = dev_get_drvdata(dev);
967 struct sdhci_host *host = c->host;
970 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
971 mmc_retune_needed(host->mmc);
973 ret = sdhci_suspend_host(host);
977 sdhci_acpi_reset_signal_voltage_if_needed(dev);
981 static int sdhci_acpi_resume(struct device *dev)
983 struct sdhci_acpi_host *c = dev_get_drvdata(dev);
985 sdhci_acpi_byt_setting(&c->pdev->dev);
987 return sdhci_resume_host(c->host);
994 static int sdhci_acpi_runtime_suspend(struct device *dev)
996 struct sdhci_acpi_host *c = dev_get_drvdata(dev);
997 struct sdhci_host *host = c->host;
1000 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1001 mmc_retune_needed(host->mmc);
1003 ret = sdhci_runtime_suspend_host(host);
1007 sdhci_acpi_reset_signal_voltage_if_needed(dev);
1011 static int sdhci_acpi_runtime_resume(struct device *dev)
1013 struct sdhci_acpi_host *c = dev_get_drvdata(dev);
1015 sdhci_acpi_byt_setting(&c->pdev->dev);
1017 return sdhci_runtime_resume_host(c->host, 0);
1022 static const struct dev_pm_ops sdhci_acpi_pm_ops = {
1023 SET_SYSTEM_SLEEP_PM_OPS(sdhci_acpi_suspend, sdhci_acpi_resume)
1024 SET_RUNTIME_PM_OPS(sdhci_acpi_runtime_suspend,
1025 sdhci_acpi_runtime_resume, NULL)
1028 static struct platform_driver sdhci_acpi_driver = {
1030 .name = "sdhci-acpi",
1031 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1032 .acpi_match_table = sdhci_acpi_ids,
1033 .pm = &sdhci_acpi_pm_ops,
1035 .probe = sdhci_acpi_probe,
1036 .remove = sdhci_acpi_remove,
1039 module_platform_driver(sdhci_acpi_driver);
1041 MODULE_DESCRIPTION("Secure Digital Host Controller Interface ACPI driver");
1042 MODULE_AUTHOR("Adrian Hunter");
1043 MODULE_LICENSE("GPL v2");