drivers/mmc/host/s3cmci.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *  linux/drivers/mmc/s3cmci.h - Samsung S3C MCI driver
   4  *
   5  *  Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel <tk@maintech.de>
   6  *
   7  * Current driver maintained by Ben Dooks and Simtec Electronics
   8  *  Copyright (C) 2008 Simtec Electronics <ben-linux@fluff.org>
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/dmaengine.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/clk.h>
  15 #include <linux/mmc/host.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/cpufreq.h>
  18 #include <linux/debugfs.h>
  19 #include <linux/seq_file.h>
  20 #include <linux/gpio.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/irq.h>
  23 #include <linux/io.h>
  24 #include <linux/of.h>
  25 #include <linux/of_device.h>
  26 #include <linux/mmc/slot-gpio.h>
  27
  28 #include <plat/gpio-cfg.h>
  29 #include <mach/dma.h>
  30 #include <mach/gpio-samsung.h>
  31
  32 #include <linux/platform_data/mmc-s3cmci.h>
  33
  34 #include "s3cmci.h"
  35
  36 #define DRIVER_NAME "s3c-mci"
  37
  38 #define S3C2410_SDICON                  (0x00)
  39 #define S3C2410_SDIPRE                  (0x04)
  40 #define S3C2410_SDICMDARG               (0x08)
  41 #define S3C2410_SDICMDCON               (0x0C)
  42 #define S3C2410_SDICMDSTAT              (0x10)
  43 #define S3C2410_SDIRSP0                 (0x14)
  44 #define S3C2410_SDIRSP1                 (0x18)
  45 #define S3C2410_SDIRSP2                 (0x1C)
  46 #define S3C2410_SDIRSP3                 (0x20)
  47 #define S3C2410_SDITIMER                (0x24)
  48 #define S3C2410_SDIBSIZE                (0x28)
  49 #define S3C2410_SDIDCON                 (0x2C)
  50 #define S3C2410_SDIDCNT                 (0x30)
  51 #define S3C2410_SDIDSTA                 (0x34)
  52 #define S3C2410_SDIFSTA                 (0x38)
  53
  54 #define S3C2410_SDIDATA                 (0x3C)
  55 #define S3C2410_SDIIMSK                 (0x40)
  56
  57 #define S3C2440_SDIDATA                 (0x40)
  58 #define S3C2440_SDIIMSK                 (0x3C)
  59
  60 #define S3C2440_SDICON_SDRESET          (1 << 8)
  61 #define S3C2410_SDICON_SDIOIRQ          (1 << 3)
  62 #define S3C2410_SDICON_FIFORESET        (1 << 1)
  63 #define S3C2410_SDICON_CLOCKTYPE        (1 << 0)
  64
  65 #define S3C2410_SDICMDCON_LONGRSP       (1 << 10)
  66 #define S3C2410_SDICMDCON_WAITRSP       (1 << 9)
  67 #define S3C2410_SDICMDCON_CMDSTART      (1 << 8)
  68 #define S3C2410_SDICMDCON_SENDERHOST    (1 << 6)
  69 #define S3C2410_SDICMDCON_INDEX         (0x3f)
  70
  71 #define S3C2410_SDICMDSTAT_CRCFAIL      (1 << 12)
  72 #define S3C2410_SDICMDSTAT_CMDSENT      (1 << 11)
  73 #define S3C2410_SDICMDSTAT_CMDTIMEOUT   (1 << 10)
  74 #define S3C2410_SDICMDSTAT_RSPFIN       (1 << 9)
  75
  76 #define S3C2440_SDIDCON_DS_WORD         (2 << 22)
  77 #define S3C2410_SDIDCON_TXAFTERRESP     (1 << 20)
  78 #define S3C2410_SDIDCON_RXAFTERCMD      (1 << 19)
  79 #define S3C2410_SDIDCON_BLOCKMODE       (1 << 17)
  80 #define S3C2410_SDIDCON_WIDEBUS         (1 << 16)
  81 #define S3C2410_SDIDCON_DMAEN           (1 << 15)
  82 #define S3C2410_SDIDCON_STOP            (1 << 14)
  83 #define S3C2440_SDIDCON_DATSTART        (1 << 14)
  84
  85 #define S3C2410_SDIDCON_XFER_RXSTART    (2 << 12)
  86 #define S3C2410_SDIDCON_XFER_TXSTART    (3 << 12)
  87
  88 #define S3C2410_SDIDCON_BLKNUM_MASK     (0xFFF)
  89
  90 #define S3C2410_SDIDSTA_SDIOIRQDETECT   (1 << 9)
  91 #define S3C2410_SDIDSTA_FIFOFAIL        (1 << 8)
  92 #define S3C2410_SDIDSTA_CRCFAIL         (1 << 7)
  93 #define S3C2410_SDIDSTA_RXCRCFAIL       (1 << 6)
  94 #define S3C2410_SDIDSTA_DATATIMEOUT     (1 << 5)
  95 #define S3C2410_SDIDSTA_XFERFINISH      (1 << 4)
  96 #define S3C2410_SDIDSTA_TXDATAON        (1 << 1)
  97 #define S3C2410_SDIDSTA_RXDATAON        (1 << 0)
  98
  99 #define S3C2440_SDIFSTA_FIFORESET       (1 << 16)
 100 #define S3C2440_SDIFSTA_FIFOFAIL        (3 << 14)
 101 #define S3C2410_SDIFSTA_TFDET           (1 << 13)
 102 #define S3C2410_SDIFSTA_RFDET           (1 << 12)
 103 #define S3C2410_SDIFSTA_COUNTMASK       (0x7f)
 104
 105 #define S3C2410_SDIIMSK_RESPONSECRC     (1 << 17)
 106 #define S3C2410_SDIIMSK_CMDSENT         (1 << 16)
 107 #define S3C2410_SDIIMSK_CMDTIMEOUT      (1 << 15)
 108 #define S3C2410_SDIIMSK_RESPONSEND      (1 << 14)
 109 #define S3C2410_SDIIMSK_SDIOIRQ         (1 << 12)
 110 #define S3C2410_SDIIMSK_FIFOFAIL        (1 << 11)
 111 #define S3C2410_SDIIMSK_CRCSTATUS       (1 << 10)
 112 #define S3C2410_SDIIMSK_DATACRC         (1 << 9)
 113 #define S3C2410_SDIIMSK_DATATIMEOUT     (1 << 8)
 114 #define S3C2410_SDIIMSK_DATAFINISH      (1 << 7)
 115 #define S3C2410_SDIIMSK_TXFIFOHALF      (1 << 4)
 116 #define S3C2410_SDIIMSK_RXFIFOLAST      (1 << 2)
 117 #define S3C2410_SDIIMSK_RXFIFOHALF      (1 << 0)
 118
 119 enum dbg_channels {
 120         dbg_err   = (1 << 0),
 121         dbg_debug = (1 << 1),
 122         dbg_info  = (1 << 2),
 123         dbg_irq   = (1 << 3),
 124         dbg_sg    = (1 << 4),
 125         dbg_dma   = (1 << 5),
 126         dbg_pio   = (1 << 6),
 127         dbg_fail  = (1 << 7),
 128         dbg_conf  = (1 << 8),
 129 };
 130
 131 static const int dbgmap_err   = dbg_fail;
 132 static const int dbgmap_info  = dbg_info | dbg_conf;
 133 static const int dbgmap_debug = dbg_err | dbg_debug;
 134
 135 #define dbg(host, channels, args...)              \
 136         do {                                      \
 137         if (dbgmap_err & channels)                \
 138                 dev_err(&host->pdev->dev, args);  \
 139         else if (dbgmap_info & channels)          \
 140                 dev_info(&host->pdev->dev, args); \
 141         else if (dbgmap_debug & channels)         \
 142                 dev_dbg(&host->pdev->dev, args);  \
 143         } while (0)
 144
 145 static void finalize_request(struct s3cmci_host *host);
 146 static void s3cmci_send_request(struct mmc_host *mmc);
 147 static void s3cmci_reset(struct s3cmci_host *host);
 148
 149 #ifdef CONFIG_MMC_DEBUG
 150
 151 static void dbg_dumpregs(struct s3cmci_host *host, char *prefix)
 152 {
 153         u32 con, pre, cmdarg, cmdcon, cmdsta, r0, r1, r2, r3, timer;
 154         u32 datcon, datcnt, datsta, fsta;
 155
 156         con     = readl(host->base + S3C2410_SDICON);
 157         pre     = readl(host->base + S3C2410_SDIPRE);
 158         cmdarg  = readl(host->base + S3C2410_SDICMDARG);
 159         cmdcon  = readl(host->base + S3C2410_SDICMDCON);
 160         cmdsta  = readl(host->base + S3C2410_SDICMDSTAT);
 161         r0      = readl(host->base + S3C2410_SDIRSP0);
 162         r1      = readl(host->base + S3C2410_SDIRSP1);
 163         r2      = readl(host->base + S3C2410_SDIRSP2);
 164         r3      = readl(host->base + S3C2410_SDIRSP3);
 165         timer   = readl(host->base + S3C2410_SDITIMER);
 166         datcon  = readl(host->base + S3C2410_SDIDCON);
 167         datcnt  = readl(host->base + S3C2410_SDIDCNT);
 168         datsta  = readl(host->base + S3C2410_SDIDSTA);
 169         fsta    = readl(host->base + S3C2410_SDIFSTA);
 170
 171         dbg(host, dbg_debug, "%s  CON:[%08x]  PRE:[%08x]  TMR:[%08x]\n",
 172                                 prefix, con, pre, timer);
 173
 174         dbg(host, dbg_debug, "%s CCON:[%08x] CARG:[%08x] CSTA:[%08x]\n",
 175                                 prefix, cmdcon, cmdarg, cmdsta);
 176
 177         dbg(host, dbg_debug, "%s DCON:[%08x] FSTA:[%08x]"
 178                                " DSTA:[%08x] DCNT:[%08x]\n",
 179                                 prefix, datcon, fsta, datsta, datcnt);
 180
 181         dbg(host, dbg_debug, "%s   R0:[%08x]   R1:[%08x]"
 182                                "   R2:[%08x]   R3:[%08x]\n",
 183                                 prefix, r0, r1, r2, r3);
 184 }
 185
 186 static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
 187                            int stop)
 188 {
 189         snprintf(host->dbgmsg_cmd, 300,
 190                  "#%u%s op:%i arg:0x%08x flags:0x08%x retries:%u",
 191                  host->ccnt, (stop ? " (STOP)" : ""),
 192                  cmd->opcode, cmd->arg, cmd->flags, cmd->retries);
 193
 194         if (cmd->data) {
 195                 snprintf(host->dbgmsg_dat, 300,
 196                          "#%u bsize:%u blocks:%u bytes:%u",
 197                          host->dcnt, cmd->data->blksz,
 198                          cmd->data->blocks,
 199                          cmd->data->blocks * cmd->data->blksz);
 200         } else {
 201                 host->dbgmsg_dat[0] = '\0';
 202         }
 203 }
 204
 205 static void dbg_dumpcmd(struct s3cmci_host *host, struct mmc_command *cmd,
 206                         int fail)
 207 {
 208         unsigned int dbglvl = fail ? dbg_fail : dbg_debug;
 209
 210         if (!cmd)
 211                 return;
 212
 213         if (cmd->error == 0) {
 214                 dbg(host, dbglvl, "CMD[OK] %s R0:0x%08x\n",
 215                         host->dbgmsg_cmd, cmd->resp[0]);
 216         } else {
 217                 dbg(host, dbglvl, "CMD[ERR %i] %s Status:%s\n",
 218                         cmd->error, host->dbgmsg_cmd, host->status);
 219         }
 220
 221         if (!cmd->data)
 222                 return;
 223
 224         if (cmd->data->error == 0) {
 225                 dbg(host, dbglvl, "DAT[OK] %s\n", host->dbgmsg_dat);
 226         } else {
 227                 dbg(host, dbglvl, "DAT[ERR %i] %s DCNT:0x%08x\n",
 228                         cmd->data->error, host->dbgmsg_dat,
 229                         readl(host->base + S3C2410_SDIDCNT));
 230         }
 231 }
 232 #else
 233 static void dbg_dumpcmd(struct s3cmci_host *host,
 234                         struct mmc_command *cmd, int fail) { }
 235
 236 static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
 237                            int stop) { }
 238
 239 static void dbg_dumpregs(struct s3cmci_host *host, char *prefix) { }
 240
 241 #endif /* CONFIG_MMC_DEBUG */
 242
 243 /**
 244  * s3cmci_host_usedma - return whether the host is using dma or pio
 245  * @host: The host state
 246  *
 247  * Return true if the host is using DMA to transfer data, else false
 248  * to use PIO mode. Will return static data depending on the driver
 249  * configuration.
 250  */
 251 static inline bool s3cmci_host_usedma(struct s3cmci_host *host)
 252 {
 253 #ifdef CONFIG_MMC_S3C_PIO
 254         return false;
 255 #else /* CONFIG_MMC_S3C_DMA */
 256         return true;
 257 #endif
 258 }
 259
 260 static inline u32 enable_imask(struct s3cmci_host *host, u32 imask)
 261 {
 262         u32 newmask;
 263
 264         newmask = readl(host->base + host->sdiimsk);
 265         newmask |= imask;
 266
 267         writel(newmask, host->base + host->sdiimsk);
 268
 269         return newmask;
 270 }
 271
 272 static inline u32 disable_imask(struct s3cmci_host *host, u32 imask)
 273 {
 274         u32 newmask;
 275
 276         newmask = readl(host->base + host->sdiimsk);
 277         newmask &= ~imask;
 278
 279         writel(newmask, host->base + host->sdiimsk);
 280
 281         return newmask;
 282 }
 283
 284 static inline void clear_imask(struct s3cmci_host *host)
 285 {
 286         u32 mask = readl(host->base + host->sdiimsk);
 287
 288         /* preserve the SDIO IRQ mask state */
 289         mask &= S3C2410_SDIIMSK_SDIOIRQ;
 290         writel(mask, host->base + host->sdiimsk);
 291 }
 292
 293 /**
 294  * s3cmci_check_sdio_irq - test whether the SDIO IRQ is being signalled
 295  * @host: The host to check.
 296  *
 297  * Test to see if the SDIO interrupt is being signalled in case the
 298  * controller has failed to re-detect a card interrupt. Read GPE8 and
 299  * see if it is low and if so, signal a SDIO interrupt.
 300  *
 301  * This is currently called if a request is finished (we assume that the
 302  * bus is now idle) and when the SDIO IRQ is enabled in case the IRQ is
 303  * already being indicated.
 304 */
 305 static void s3cmci_check_sdio_irq(struct s3cmci_host *host)
 306 {
 307         if (host->sdio_irqen) {
 308                 if (gpio_get_value(S3C2410_GPE(8)) == 0) {
 309                         pr_debug("%s: signalling irq\n", __func__);
 310                         mmc_signal_sdio_irq(host->mmc);
 311                 }
 312         }
 313 }
 314
 315 static inline int get_data_buffer(struct s3cmci_host *host,
 316                                   u32 *bytes, u32 **pointer)
 317 {
 318         struct scatterlist *sg;
 319
 320         if (host->pio_active == XFER_NONE)
 321                 return -EINVAL;
 322
 323         if ((!host->mrq) || (!host->mrq->data))
 324                 return -EINVAL;
 325
 326         if (host->pio_sgptr >= host->mrq->data->sg_len) {
 327                 dbg(host, dbg_debug, "no more buffers (%i/%i)\n",
 328                       host->pio_sgptr, host->mrq->data->sg_len);
 329                 return -EBUSY;
 330         }
 331         sg = &host->mrq->data->sg[host->pio_sgptr];
 332
 333         *bytes = sg->length;
 334         *pointer = sg_virt(sg);
 335
 336         host->pio_sgptr++;
 337
 338         dbg(host, dbg_sg, "new buffer (%i/%i)\n",
 339             host->pio_sgptr, host->mrq->data->sg_len);
 340
 341         return 0;
 342 }
 343
 344 static inline u32 fifo_count(struct s3cmci_host *host)
 345 {
 346         u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
 347
 348         fifostat &= S3C2410_SDIFSTA_COUNTMASK;
 349         return fifostat;
 350 }
 351
 352 static inline u32 fifo_free(struct s3cmci_host *host)
 353 {
 354         u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
 355
 356         fifostat &= S3C2410_SDIFSTA_COUNTMASK;
 357         return 63 - fifostat;
 358 }
 359
 360 /**
 361  * s3cmci_enable_irq - enable IRQ, after having disabled it.
 362  * @host: The device state.
 363  * @more: True if more IRQs are expected from transfer.
 364  *
 365  * Enable the main IRQ if needed after it has been disabled.
 366  *
 367  * The IRQ can be one of the following states:
 368  *      - disabled during IDLE
 369  *      - disabled whilst processing data
 370  *      - enabled during transfer
 371  *      - enabled whilst awaiting SDIO interrupt detection
 372  */
 373 static void s3cmci_enable_irq(struct s3cmci_host *host, bool more)
 374 {
 375         unsigned long flags;
 376         bool enable = false;
 377
 378         local_irq_save(flags);
 379
 380         host->irq_enabled = more;
 381         host->irq_disabled = false;
 382
 383         enable = more | host->sdio_irqen;
 384
 385         if (host->irq_state != enable) {
 386                 host->irq_state = enable;
 387
 388                 if (enable)
 389                         enable_irq(host->irq);
 390                 else
 391                         disable_irq(host->irq);
 392         }
 393
 394         local_irq_restore(flags);
 395 }
 396
 397 static void s3cmci_disable_irq(struct s3cmci_host *host, bool transfer)
 398 {
 399         unsigned long flags;
 400
 401         local_irq_save(flags);
 402
 403         /* pr_debug("%s: transfer %d\n", __func__, transfer); */
 404
 405         host->irq_disabled = transfer;
 406
 407         if (transfer && host->irq_state) {
 408                 host->irq_state = false;
 409                 disable_irq(host->irq);
 410         }
 411
 412         local_irq_restore(flags);
 413 }
 414
 415 static void do_pio_read(struct s3cmci_host *host)
 416 {
 417         int res;
 418         u32 fifo;
 419         u32 *ptr;
 420         u32 fifo_words;
 421         void __iomem *from_ptr;
 422
 423         /* write real prescaler to host, it might be set slow to fix */
 424         writel(host->prescaler, host->base + S3C2410_SDIPRE);
 425
 426         from_ptr = host->base + host->sdidata;
 427
 428         while ((fifo = fifo_count(host))) {
 429                 if (!host->pio_bytes) {
 430                         res = get_data_buffer(host, &host->pio_bytes,
 431                                               &host->pio_ptr);
 432                         if (res) {
 433                                 host->pio_active = XFER_NONE;
 434                                 host->complete_what = COMPLETION_FINALIZE;
 435
 436                                 dbg(host, dbg_pio, "pio_read(): "
 437                                     "complete (no more data).\n");
 438                                 return;
 439                         }
 440
 441                         dbg(host, dbg_pio,
 442                             "pio_read(): new target: [%i]@[%p]\n",
 443                             host->pio_bytes, host->pio_ptr);
 444                 }
 445
 446                 dbg(host, dbg_pio,
 447                     "pio_read(): fifo:[%02i] buffer:[%03i] dcnt:[%08X]\n",
 448                     fifo, host->pio_bytes,
 449                     readl(host->base + S3C2410_SDIDCNT));
 450
 451                 /* If we have reached the end of the block, we can
 452                  * read a word and get 1 to 3 bytes.  If we in the
 453                  * middle of the block, we have to read full words,
 454                  * otherwise we will write garbage, so round down to
 455                  * an even multiple of 4. */
 456                 if (fifo >= host->pio_bytes)
 457                         fifo = host->pio_bytes;
 458                 else
 459                         fifo -= fifo & 3;
 460
 461                 host->pio_bytes -= fifo;
 462                 host->pio_count += fifo;
 463
 464                 fifo_words = fifo >> 2;
 465                 ptr = host->pio_ptr;
 466                 while (fifo_words--)
 467                         *ptr++ = readl(from_ptr);
 468                 host->pio_ptr = ptr;
 469
 470                 if (fifo & 3) {
 471                         u32 n = fifo & 3;
 472                         u32 data = readl(from_ptr);
 473                         u8 *p = (u8 *)host->pio_ptr;
 474
 475                         while (n--) {
 476                                 *p++ = data;
 477                                 data >>= 8;
 478                         }
 479                 }
 480         }
 481
 482         if (!host->pio_bytes) {
 483                 res = get_data_buffer(host, &host->pio_bytes, &host->pio_ptr);
 484                 if (res) {
 485                         dbg(host, dbg_pio,
 486                             "pio_read(): complete (no more buffers).\n");
 487                         host->pio_active = XFER_NONE;
 488                         host->complete_what = COMPLETION_FINALIZE;
 489
 490                         return;
 491                 }
 492         }
 493
 494         enable_imask(host,
 495                      S3C2410_SDIIMSK_RXFIFOHALF | S3C2410_SDIIMSK_RXFIFOLAST);
 496 }
 497
 498 static void do_pio_write(struct s3cmci_host *host)
 499 {
 500         void __iomem *to_ptr;
 501         int res;
 502         u32 fifo;
 503         u32 *ptr;
 504
 505         to_ptr = host->base + host->sdidata;
 506
 507         while ((fifo = fifo_free(host)) > 3) {
 508                 if (!host->pio_bytes) {
 509                         res = get_data_buffer(host, &host->pio_bytes,
 510                                                         &host->pio_ptr);
 511                         if (res) {
 512                                 dbg(host, dbg_pio,
 513                                     "pio_write(): complete (no more data).\n");
 514                                 host->pio_active = XFER_NONE;
 515
 516                                 return;
 517                         }
 518
 519                         dbg(host, dbg_pio,
 520                             "pio_write(): new source: [%i]@[%p]\n",
 521                             host->pio_bytes, host->pio_ptr);
 522
 523                 }
 524
 525                 /* If we have reached the end of the block, we have to
 526                  * write exactly the remaining number of bytes.  If we
 527                  * in the middle of the block, we have to write full
 528                  * words, so round down to an even multiple of 4. */
 529                 if (fifo >= host->pio_bytes)
 530                         fifo = host->pio_bytes;
 531                 else
 532                         fifo -= fifo & 3;
 533
 534                 host->pio_bytes -= fifo;
 535                 host->pio_count += fifo;
 536
 537                 fifo = (fifo + 3) >> 2;
 538                 ptr = host->pio_ptr;
 539                 while (fifo--)
 540                         writel(*ptr++, to_ptr);
 541                 host->pio_ptr = ptr;
 542         }
 543
 544         enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
 545 }
 546
 547 static void pio_tasklet(unsigned long data)
 548 {
 549         struct s3cmci_host *host = (struct s3cmci_host *) data;
 550
 551         s3cmci_disable_irq(host, true);
 552
 553         if (host->pio_active == XFER_WRITE)
 554                 do_pio_write(host);
 555
 556         if (host->pio_active == XFER_READ)
 557                 do_pio_read(host);
 558
 559         if (host->complete_what == COMPLETION_FINALIZE) {
 560                 clear_imask(host);
 561                 if (host->pio_active != XFER_NONE) {
 562                         dbg(host, dbg_err, "unfinished %s "
 563                             "- pio_count:[%u] pio_bytes:[%u]\n",
 564                             (host->pio_active == XFER_READ) ? "read" : "write",
 565                             host->pio_count, host->pio_bytes);
 566
 567                         if (host->mrq->data)
 568                                 host->mrq->data->error = -EINVAL;
 569                 }
 570
 571                 s3cmci_enable_irq(host, false);
 572                 finalize_request(host);
 573         } else
 574                 s3cmci_enable_irq(host, true);
 575 }
 576
 577 /*
 578  * ISR for SDI Interface IRQ
 579  * Communication between driver and ISR works as follows:
 580  *   host->mrq                  points to current request
 581  *   host->complete_what        Indicates when the request is considered done
 582  *     COMPLETION_CMDSENT         when the command was sent
 583  *     COMPLETION_RSPFIN          when a response was received
 584  *     COMPLETION_XFERFINISH      when the data transfer is finished
 585  *     COMPLETION_XFERFINISH_RSPFIN both of the above.
 586  *   host->complete_request     is the completion-object the driver waits for
 587  *
 588  * 1) Driver sets up host->mrq and host->complete_what
 589  * 2) Driver prepares the transfer
 590  * 3) Driver enables interrupts
 591  * 4) Driver starts transfer
 592  * 5) Driver waits for host->complete_rquest
 593  * 6) ISR checks for request status (errors and success)
 594  * 6) ISR sets host->mrq->cmd->error and host->mrq->data->error
 595  * 7) ISR completes host->complete_request
 596  * 8) ISR disables interrupts
 597  * 9) Driver wakes up and takes care of the request
 598  *
 599  * Note: "->error"-fields are expected to be set to 0 before the request
 600  *       was issued by mmc.c - therefore they are only set, when an error
 601  *       contition comes up
 602  */
 603
 604 static irqreturn_t s3cmci_irq(int irq, void *dev_id)
 605 {
 606         struct s3cmci_host *host = dev_id;
 607         struct mmc_command *cmd;
 608         u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt, mci_imsk;
 609         u32 mci_cclear = 0, mci_dclear;
 610         unsigned long iflags;
 611
 612         mci_dsta = readl(host->base + S3C2410_SDIDSTA);
 613         mci_imsk = readl(host->base + host->sdiimsk);
 614
 615         if (mci_dsta & S3C2410_SDIDSTA_SDIOIRQDETECT) {
 616                 if (mci_imsk & S3C2410_SDIIMSK_SDIOIRQ) {
 617                         mci_dclear = S3C2410_SDIDSTA_SDIOIRQDETECT;
 618                         writel(mci_dclear, host->base + S3C2410_SDIDSTA);
 619
 620                         mmc_signal_sdio_irq(host->mmc);
 621                         return IRQ_HANDLED;
 622                 }
 623         }
 624
 625         spin_lock_irqsave(&host->complete_lock, iflags);
 626
 627         mci_csta = readl(host->base + S3C2410_SDICMDSTAT);
 628         mci_dcnt = readl(host->base + S3C2410_SDIDCNT);
 629         mci_fsta = readl(host->base + S3C2410_SDIFSTA);
 630         mci_dclear = 0;
 631
 632         if ((host->complete_what == COMPLETION_NONE) ||
 633             (host->complete_what == COMPLETION_FINALIZE)) {
 634                 host->status = "nothing to complete";
 635                 clear_imask(host);
 636                 goto irq_out;
 637         }
 638
 639         if (!host->mrq) {
 640                 host->status = "no active mrq";
 641                 clear_imask(host);
 642                 goto irq_out;
 643         }
 644
 645         cmd = host->cmd_is_stop ? host->mrq->stop : host->mrq->cmd;
 646
 647         if (!cmd) {
 648                 host->status = "no active cmd";
 649                 clear_imask(host);
 650                 goto irq_out;
 651         }
 652
 653         if (!s3cmci_host_usedma(host)) {
 654                 if ((host->pio_active == XFER_WRITE) &&
 655                     (mci_fsta & S3C2410_SDIFSTA_TFDET)) {
 656
 657                         disable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
 658                         tasklet_schedule(&host->pio_tasklet);
 659                         host->status = "pio tx";
 660                 }
 661
 662                 if ((host->pio_active == XFER_READ) &&
 663                     (mci_fsta & S3C2410_SDIFSTA_RFDET)) {
 664
 665                         disable_imask(host,
 666                                       S3C2410_SDIIMSK_RXFIFOHALF |
 667                                       S3C2410_SDIIMSK_RXFIFOLAST);
 668
 669                         tasklet_schedule(&host->pio_tasklet);
 670                         host->status = "pio rx";
 671                 }
 672         }
 673
 674         if (mci_csta & S3C2410_SDICMDSTAT_CMDTIMEOUT) {
 675                 dbg(host, dbg_err, "CMDSTAT: error CMDTIMEOUT\n");
 676                 cmd->error = -ETIMEDOUT;
 677                 host->status = "error: command timeout";
 678                 goto fail_transfer;
 679         }
 680
 681         if (mci_csta & S3C2410_SDICMDSTAT_CMDSENT) {
 682                 if (host->complete_what == COMPLETION_CMDSENT) {
 683                         host->status = "ok: command sent";
 684                         goto close_transfer;
 685                 }
 686
 687                 mci_cclear |= S3C2410_SDICMDSTAT_CMDSENT;
 688         }
 689
 690         if (mci_csta & S3C2410_SDICMDSTAT_CRCFAIL) {
 691                 if (cmd->flags & MMC_RSP_CRC) {
 692                         if (host->mrq->cmd->flags & MMC_RSP_136) {
 693                                 dbg(host, dbg_irq,
 694                                     "fixup: ignore CRC fail with long rsp\n");
 695                         } else {
 696                                 /* note, we used to fail the transfer
 697                                  * here, but it seems that this is just
 698                                  * the hardware getting it wrong.
 699                                  *
 700                                  * cmd->error = -EILSEQ;
 701                                  * host->status = "error: bad command crc";
 702                                  * goto fail_transfer;
 703                                 */
 704                         }
 705                 }
 706
 707                 mci_cclear |= S3C2410_SDICMDSTAT_CRCFAIL;
 708         }
 709
 710         if (mci_csta & S3C2410_SDICMDSTAT_RSPFIN) {
 711                 if (host->complete_what == COMPLETION_RSPFIN) {
 712                         host->status = "ok: command response received";
 713                         goto close_transfer;
 714                 }
 715
 716                 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
 717                         host->complete_what = COMPLETION_XFERFINISH;
 718
 719                 mci_cclear |= S3C2410_SDICMDSTAT_RSPFIN;
 720         }
 721
 722         /* errors handled after this point are only relevant
 723            when a data transfer is in progress */
 724
 725         if (!cmd->data)
 726                 goto clear_status_bits;
 727
 728         /* Check for FIFO failure */
 729         if (host->is2440) {
 730                 if (mci_fsta & S3C2440_SDIFSTA_FIFOFAIL) {
 731                         dbg(host, dbg_err, "FIFO failure\n");
 732                         host->mrq->data->error = -EILSEQ;
 733                         host->status = "error: 2440 fifo failure";
 734                         goto fail_transfer;
 735                 }
 736         } else {
 737                 if (mci_dsta & S3C2410_SDIDSTA_FIFOFAIL) {
 738                         dbg(host, dbg_err, "FIFO failure\n");
 739                         cmd->data->error = -EILSEQ;
 740                         host->status = "error:  fifo failure";
 741                         goto fail_transfer;
 742                 }
 743         }
 744
 745         if (mci_dsta & S3C2410_SDIDSTA_RXCRCFAIL) {
 746                 dbg(host, dbg_err, "bad data crc (outgoing)\n");
 747                 cmd->data->error = -EILSEQ;
 748                 host->status = "error: bad data crc (outgoing)";
 749                 goto fail_transfer;
 750         }
 751
 752         if (mci_dsta & S3C2410_SDIDSTA_CRCFAIL) {
 753                 dbg(host, dbg_err, "bad data crc (incoming)\n");
 754                 cmd->data->error = -EILSEQ;
 755                 host->status = "error: bad data crc (incoming)";
 756                 goto fail_transfer;
 757         }
 758
 759         if (mci_dsta & S3C2410_SDIDSTA_DATATIMEOUT) {
 760                 dbg(host, dbg_err, "data timeout\n");
 761                 cmd->data->error = -ETIMEDOUT;
 762                 host->status = "error: data timeout";
 763                 goto fail_transfer;
 764         }
 765
 766         if (mci_dsta & S3C2410_SDIDSTA_XFERFINISH) {
 767                 if (host->complete_what == COMPLETION_XFERFINISH) {
 768                         host->status = "ok: data transfer completed";
 769                         goto close_transfer;
 770                 }
 771
 772                 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
 773                         host->complete_what = COMPLETION_RSPFIN;
 774
 775                 mci_dclear |= S3C2410_SDIDSTA_XFERFINISH;
 776         }
 777
 778 clear_status_bits:
 779         writel(mci_cclear, host->base + S3C2410_SDICMDSTAT);
 780         writel(mci_dclear, host->base + S3C2410_SDIDSTA);
 781
 782         goto irq_out;
 783
 784 fail_transfer:
 785         host->pio_active = XFER_NONE;
 786
 787 close_transfer:
 788         host->complete_what = COMPLETION_FINALIZE;
 789
 790         clear_imask(host);
 791         tasklet_schedule(&host->pio_tasklet);
 792
 793         goto irq_out;
 794
 795 irq_out:
 796         dbg(host, dbg_irq,
 797             "csta:0x%08x dsta:0x%08x fsta:0x%08x dcnt:0x%08x status:%s.\n",
 798             mci_csta, mci_dsta, mci_fsta, mci_dcnt, host->status);
 799
 800         spin_unlock_irqrestore(&host->complete_lock, iflags);
 801         return IRQ_HANDLED;
 802
 803 }
 804
 805 static void s3cmci_dma_done_callback(void *arg)
 806 {
 807         struct s3cmci_host *host = arg;
 808         unsigned long iflags;
 809
 810         BUG_ON(!host->mrq);
 811         BUG_ON(!host->mrq->data);
 812
 813         spin_lock_irqsave(&host->complete_lock, iflags);
 814
 815         dbg(host, dbg_dma, "DMA FINISHED\n");
 816
 817         host->dma_complete = 1;
 818         host->complete_what = COMPLETION_FINALIZE;
 819
 820         tasklet_schedule(&host->pio_tasklet);
 821         spin_unlock_irqrestore(&host->complete_lock, iflags);
 822
 823 }
 824
 825 static void finalize_request(struct s3cmci_host *host)
 826 {
 827         struct mmc_request *mrq = host->mrq;
 828         struct mmc_command *cmd;
 829         int debug_as_failure = 0;
 830
 831         if (host->complete_what != COMPLETION_FINALIZE)
 832                 return;
 833
 834         if (!mrq)
 835                 return;
 836         cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
 837
 838         if (cmd->data && (cmd->error == 0) &&
 839             (cmd->data->error == 0)) {
 840                 if (s3cmci_host_usedma(host) && (!host->dma_complete)) {
 841                         dbg(host, dbg_dma, "DMA Missing (%d)!\n",
 842                             host->dma_complete);
 843                         return;
 844                 }
 845         }
 846
 847         /* Read response from controller. */
 848         cmd->resp[0] = readl(host->base + S3C2410_SDIRSP0);
 849         cmd->resp[1] = readl(host->base + S3C2410_SDIRSP1);
 850         cmd->resp[2] = readl(host->base + S3C2410_SDIRSP2);
 851         cmd->resp[3] = readl(host->base + S3C2410_SDIRSP3);
 852
 853         writel(host->prescaler, host->base + S3C2410_SDIPRE);
 854
 855         if (cmd->error)
 856                 debug_as_failure = 1;
 857
 858         if (cmd->data && cmd->data->error)
 859                 debug_as_failure = 1;
 860
 861         dbg_dumpcmd(host, cmd, debug_as_failure);
 862
 863         /* Cleanup controller */
 864         writel(0, host->base + S3C2410_SDICMDARG);
 865         writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
 866         writel(0, host->base + S3C2410_SDICMDCON);
 867         clear_imask(host);
 868
 869         if (cmd->data && cmd->error)
 870                 cmd->data->error = cmd->error;
 871
 872         if (cmd->data && cmd->data->stop && (!host->cmd_is_stop)) {
 873                 host->cmd_is_stop = 1;
 874                 s3cmci_send_request(host->mmc);
 875                 return;
 876         }
 877
 878         /* If we have no data transfer we are finished here */
 879         if (!mrq->data)
 880                 goto request_done;
 881
 882         /* Calculate the amout of bytes transfer if there was no error */
 883         if (mrq->data->error == 0) {
 884                 mrq->data->bytes_xfered =
 885                         (mrq->data->blocks * mrq->data->blksz);
 886         } else {
 887                 mrq->data->bytes_xfered = 0;
 888         }
 889
 890         /* If we had an error while transferring data we flush the
 891          * DMA channel and the fifo to clear out any garbage. */
 892         if (mrq->data->error != 0) {
 893                 if (s3cmci_host_usedma(host))
 894                         dmaengine_terminate_all(host->dma);
 895
 896                 if (host->is2440) {
 897                         /* Clear failure register and reset fifo. */
 898                         writel(S3C2440_SDIFSTA_FIFORESET |
 899                                S3C2440_SDIFSTA_FIFOFAIL,
 900                                host->base + S3C2410_SDIFSTA);
 901                 } else {
 902                         u32 mci_con;
 903
 904                         /* reset fifo */
 905                         mci_con = readl(host->base + S3C2410_SDICON);
 906                         mci_con |= S3C2410_SDICON_FIFORESET;
 907
 908                         writel(mci_con, host->base + S3C2410_SDICON);
 909                 }
 910         }
 911
 912 request_done:
 913         host->complete_what = COMPLETION_NONE;
 914         host->mrq = NULL;
 915
 916         s3cmci_check_sdio_irq(host);
 917         mmc_request_done(host->mmc, mrq);
 918 }
 919
 920 static void s3cmci_send_command(struct s3cmci_host *host,
 921                                         struct mmc_command *cmd)
 922 {
 923         u32 ccon, imsk;
 924
 925         imsk  = S3C2410_SDIIMSK_CRCSTATUS | S3C2410_SDIIMSK_CMDTIMEOUT |
 926                 S3C2410_SDIIMSK_RESPONSEND | S3C2410_SDIIMSK_CMDSENT |
 927                 S3C2410_SDIIMSK_RESPONSECRC;
 928
 929         enable_imask(host, imsk);
 930
 931         if (cmd->data)
 932                 host->complete_what = COMPLETION_XFERFINISH_RSPFIN;
 933         else if (cmd->flags & MMC_RSP_PRESENT)
 934                 host->complete_what = COMPLETION_RSPFIN;
 935         else
 936                 host->complete_what = COMPLETION_CMDSENT;
 937
 938         writel(cmd->arg, host->base + S3C2410_SDICMDARG);
 939
 940         ccon  = cmd->opcode & S3C2410_SDICMDCON_INDEX;
 941         ccon |= S3C2410_SDICMDCON_SENDERHOST | S3C2410_SDICMDCON_CMDSTART;
 942
 943         if (cmd->flags & MMC_RSP_PRESENT)
 944                 ccon |= S3C2410_SDICMDCON_WAITRSP;
 945
 946         if (cmd->flags & MMC_RSP_136)
 947                 ccon |= S3C2410_SDICMDCON_LONGRSP;
 948
 949         writel(ccon, host->base + S3C2410_SDICMDCON);
 950 }
 951
 952 static int s3cmci_setup_data(struct s3cmci_host *host, struct mmc_data *data)
 953 {
 954         u32 dcon, imsk, stoptries = 3;
 955
 956         if ((data->blksz & 3) != 0) {
 957                 /* We cannot deal with unaligned blocks with more than
 958                  * one block being transferred. */
 959
 960                 if (data->blocks > 1) {
 961                         pr_warn("%s: can't do non-word sized block transfers (blksz %d)\n",
 962                                 __func__, data->blksz);
 963                         return -EINVAL;
 964                 }
 965         }
 966
 967         while (readl(host->base + S3C2410_SDIDSTA) &
 968                (S3C2410_SDIDSTA_TXDATAON | S3C2410_SDIDSTA_RXDATAON)) {
 969
 970                 dbg(host, dbg_err,
 971                     "mci_setup_data() transfer stillin progress.\n");
 972
 973                 writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
 974                 s3cmci_reset(host);
 975
 976                 if ((stoptries--) == 0) {
 977                         dbg_dumpregs(host, "DRF");
 978                         return -EINVAL;
 979                 }
 980         }
 981
 982         dcon  = data->blocks & S3C2410_SDIDCON_BLKNUM_MASK;
 983
 984         if (s3cmci_host_usedma(host))
 985                 dcon |= S3C2410_SDIDCON_DMAEN;
 986
 987         if (host->bus_width == MMC_BUS_WIDTH_4)
 988                 dcon |= S3C2410_SDIDCON_WIDEBUS;
 989
 990         dcon |= S3C2410_SDIDCON_BLOCKMODE;
 991
 992         if (data->flags & MMC_DATA_WRITE) {
 993                 dcon |= S3C2410_SDIDCON_TXAFTERRESP;
 994                 dcon |= S3C2410_SDIDCON_XFER_TXSTART;
 995         }
 996
 997         if (data->flags & MMC_DATA_READ) {
 998                 dcon |= S3C2410_SDIDCON_RXAFTERCMD;
 999                 dcon |= S3C2410_SDIDCON_XFER_RXSTART;
1000         }
1001
1002         if (host->is2440) {
1003                 dcon |= S3C2440_SDIDCON_DS_WORD;
1004                 dcon |= S3C2440_SDIDCON_DATSTART;
1005         }
1006
1007         writel(dcon, host->base + S3C2410_SDIDCON);
1008
1009         /* write BSIZE register */
1010
1011         writel(data->blksz, host->base + S3C2410_SDIBSIZE);
1012
1013         /* add to IMASK register */
1014         imsk = S3C2410_SDIIMSK_FIFOFAIL | S3C2410_SDIIMSK_DATACRC |
1015                S3C2410_SDIIMSK_DATATIMEOUT | S3C2410_SDIIMSK_DATAFINISH;
1016
1017         enable_imask(host, imsk);
1018
1019         /* write TIMER register */
1020
1021         if (host->is2440) {
1022                 writel(0x007FFFFF, host->base + S3C2410_SDITIMER);
1023         } else {
1024                 writel(0x0000FFFF, host->base + S3C2410_SDITIMER);
1025
1026                 /* FIX: set slow clock to prevent timeouts on read */
1027                 if (data->flags & MMC_DATA_READ)
1028                         writel(0xFF, host->base + S3C2410_SDIPRE);
1029         }
1030
1031         return 0;
1032 }
1033
1034 #define BOTH_DIR (MMC_DATA_WRITE | MMC_DATA_READ)
1035
1036 static int s3cmci_prepare_pio(struct s3cmci_host *host, struct mmc_data *data)
1037 {
1038         int rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0;
1039
1040         BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
1041
1042         host->pio_sgptr = 0;
1043         host->pio_bytes = 0;
1044         host->pio_count = 0;
1045         host->pio_active = rw ? XFER_WRITE : XFER_READ;
1046
1047         if (rw) {
1048                 do_pio_write(host);
1049                 enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
1050         } else {
1051                 enable_imask(host, S3C2410_SDIIMSK_RXFIFOHALF
1052                              | S3C2410_SDIIMSK_RXFIFOLAST);
1053         }
1054
1055         return 0;
1056 }
1057
1058 static int s3cmci_prepare_dma(struct s3cmci_host *host, struct mmc_data *data)
1059 {
1060         int rw = data->flags & MMC_DATA_WRITE;
1061         struct dma_async_tx_descriptor *desc;
1062         struct dma_slave_config conf = {
1063                 .src_addr = host->mem->start + host->sdidata,
1064                 .dst_addr = host->mem->start + host->sdidata,
1065                 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1066                 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1067         };
1068
1069         BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
1070
1071         /* Restore prescaler value */
1072         writel(host->prescaler, host->base + S3C2410_SDIPRE);
1073
1074         if (!rw)
1075                 conf.direction = DMA_DEV_TO_MEM;
1076         else
1077                 conf.direction = DMA_MEM_TO_DEV;
1078
1079         dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1080                    mmc_get_dma_dir(data));
1081
1082         dmaengine_slave_config(host->dma, &conf);
1083         desc = dmaengine_prep_slave_sg(host->dma, data->sg, data->sg_len,
1084                 conf.direction,
1085                 DMA_CTRL_ACK | DMA_PREP_INTERRUPT);
1086         if (!desc)
1087                 goto unmap_exit;
1088         desc->callback = s3cmci_dma_done_callback;
1089         desc->callback_param = host;
1090         dmaengine_submit(desc);
1091         dma_async_issue_pending(host->dma);
1092
1093         return 0;
1094
1095 unmap_exit:
1096         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1097                      mmc_get_dma_dir(data));
1098         return -ENOMEM;
1099 }
1100
1101 static void s3cmci_send_request(struct mmc_host *mmc)
1102 {
1103         struct s3cmci_host *host = mmc_priv(mmc);
1104         struct mmc_request *mrq = host->mrq;
1105         struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
1106
1107         host->ccnt++;
1108         prepare_dbgmsg(host, cmd, host->cmd_is_stop);
1109
1110         /* Clear command, data and fifo status registers
1111            Fifo clear only necessary on 2440, but doesn't hurt on 2410
1112         */
1113         writel(0xFFFFFFFF, host->base + S3C2410_SDICMDSTAT);
1114         writel(0xFFFFFFFF, host->base + S3C2410_SDIDSTA);
1115         writel(0xFFFFFFFF, host->base + S3C2410_SDIFSTA);
1116
1117         if (cmd->data) {
1118                 int res = s3cmci_setup_data(host, cmd->data);
1119
1120                 host->dcnt++;
1121
1122                 if (res) {
1123                         dbg(host, dbg_err, "setup data error %d\n", res);
1124                         cmd->error = res;
1125                         cmd->data->error = res;
1126
1127                         mmc_request_done(mmc, mrq);
1128                         return;
1129                 }
1130
1131                 if (s3cmci_host_usedma(host))
1132                         res = s3cmci_prepare_dma(host, cmd->data);
1133                 else
1134                         res = s3cmci_prepare_pio(host, cmd->data);
1135
1136                 if (res) {
1137                         dbg(host, dbg_err, "data prepare error %d\n", res);
1138                         cmd->error = res;
1139                         cmd->data->error = res;
1140
1141                         mmc_request_done(mmc, mrq);
1142                         return;
1143                 }
1144         }
1145
1146         /* Send command */
1147         s3cmci_send_command(host, cmd);
1148
1149         /* Enable Interrupt */
1150         s3cmci_enable_irq(host, true);
1151 }
1152
1153 static void s3cmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1154 {
1155         struct s3cmci_host *host = mmc_priv(mmc);
1156
1157         host->status = "mmc request";
1158         host->cmd_is_stop = 0;
1159         host->mrq = mrq;
1160
1161         if (mmc_gpio_get_cd(mmc) == 0) {
1162                 dbg(host, dbg_err, "%s: no medium present\n", __func__);
1163                 host->mrq->cmd->error = -ENOMEDIUM;
1164                 mmc_request_done(mmc, mrq);
1165         } else
1166                 s3cmci_send_request(mmc);
1167 }
1168
1169 static void s3cmci_set_clk(struct s3cmci_host *host, struct mmc_ios *ios)
1170 {
1171         u32 mci_psc;
1172
1173         /* Set clock */
1174         for (mci_psc = 0; mci_psc < 255; mci_psc++) {
1175                 host->real_rate = host->clk_rate / (host->clk_div*(mci_psc+1));
1176
1177                 if (host->real_rate <= ios->clock)
1178                         break;
1179         }
1180
1181         if (mci_psc > 255)
1182                 mci_psc = 255;
1183
1184         host->prescaler = mci_psc;
1185         writel(host->prescaler, host->base + S3C2410_SDIPRE);
1186
1187         /* If requested clock is 0, real_rate will be 0, too */
1188         if (ios->clock == 0)
1189                 host->real_rate = 0;
1190 }
1191
1192 static void s3cmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1193 {
1194         struct s3cmci_host *host = mmc_priv(mmc);
1195         u32 mci_con;
1196
1197         /* Set the power state */
1198
1199         mci_con = readl(host->base + S3C2410_SDICON);
1200
1201         switch (ios->power_mode) {
1202         case MMC_POWER_ON:
1203         case MMC_POWER_UP:
1204                 /* Configure GPE5...GPE10 pins in SD mode */
1205                 if (!host->pdev->dev.of_node)
1206                         s3c_gpio_cfgall_range(S3C2410_GPE(5), 6, S3C_GPIO_SFN(2),
1207                                               S3C_GPIO_PULL_NONE);
1208
1209                 if (host->pdata->set_power)
1210                         host->pdata->set_power(ios->power_mode, ios->vdd);
1211
1212                 if (!host->is2440)
1213                         mci_con |= S3C2410_SDICON_FIFORESET;
1214
1215                 break;
1216
1217         case MMC_POWER_OFF:
1218         default:
1219                 if (!host->pdev->dev.of_node)
1220                         gpio_direction_output(S3C2410_GPE(5), 0);
1221
1222                 if (host->is2440)
1223                         mci_con |= S3C2440_SDICON_SDRESET;
1224
1225                 if (host->pdata->set_power)
1226                         host->pdata->set_power(ios->power_mode, ios->vdd);
1227
1228                 break;
1229         }
1230
1231         s3cmci_set_clk(host, ios);
1232
1233         /* Set CLOCK_ENABLE */
1234         if (ios->clock)
1235                 mci_con |= S3C2410_SDICON_CLOCKTYPE;
1236         else
1237                 mci_con &= ~S3C2410_SDICON_CLOCKTYPE;
1238
1239         writel(mci_con, host->base + S3C2410_SDICON);
1240
1241         if ((ios->power_mode == MMC_POWER_ON) ||
1242             (ios->power_mode == MMC_POWER_UP)) {
1243                 dbg(host, dbg_conf, "running at %lukHz (requested: %ukHz).\n",
1244                         host->real_rate/1000, ios->clock/1000);
1245         } else {
1246                 dbg(host, dbg_conf, "powered down.\n");
1247         }
1248
1249         host->bus_width = ios->bus_width;
1250 }
1251
1252 static void s3cmci_reset(struct s3cmci_host *host)
1253 {
1254         u32 con = readl(host->base + S3C2410_SDICON);
1255
1256         con |= S3C2440_SDICON_SDRESET;
1257         writel(con, host->base + S3C2410_SDICON);
1258 }
1259
1260 static void s3cmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1261 {
1262         struct s3cmci_host *host = mmc_priv(mmc);
1263         unsigned long flags;
1264         u32 con;
1265
1266         local_irq_save(flags);
1267
1268         con = readl(host->base + S3C2410_SDICON);
1269         host->sdio_irqen = enable;
1270
1271         if (enable == host->sdio_irqen)
1272                 goto same_state;
1273
1274         if (enable) {
1275                 con |= S3C2410_SDICON_SDIOIRQ;
1276                 enable_imask(host, S3C2410_SDIIMSK_SDIOIRQ);
1277
1278                 if (!host->irq_state && !host->irq_disabled) {
1279                         host->irq_state = true;
1280                         enable_irq(host->irq);
1281                 }
1282         } else {
1283                 disable_imask(host, S3C2410_SDIIMSK_SDIOIRQ);
1284                 con &= ~S3C2410_SDICON_SDIOIRQ;
1285
1286                 if (!host->irq_enabled && host->irq_state) {
1287                         disable_irq_nosync(host->irq);
1288                         host->irq_state = false;
1289                 }
1290         }
1291
1292         writel(con, host->base + S3C2410_SDICON);
1293
1294  same_state:
1295         local_irq_restore(flags);
1296
1297         s3cmci_check_sdio_irq(host);
1298 }
1299
1300 static const struct mmc_host_ops s3cmci_ops = {
1301         .request        = s3cmci_request,
1302         .set_ios        = s3cmci_set_ios,
1303         .get_ro         = mmc_gpio_get_ro,
1304         .get_cd         = mmc_gpio_get_cd,
1305         .enable_sdio_irq = s3cmci_enable_sdio_irq,
1306 };
1307
1308 static struct s3c24xx_mci_pdata s3cmci_def_pdata = {
1309         /* This is currently here to avoid a number of if (host->pdata)
1310          * checks. Any zero fields to ensure reasonable defaults are picked. */
1311          .no_wprotect = 1,
1312          .no_detect = 1,
1313 };
1314
1315 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
1316
1317 static int s3cmci_cpufreq_transition(struct notifier_block *nb,
1318                                      unsigned long val, void *data)
1319 {
1320         struct s3cmci_host *host;
1321         struct mmc_host *mmc;
1322         unsigned long newclk;
1323         unsigned long flags;
1324
1325         host = container_of(nb, struct s3cmci_host, freq_transition);
1326         newclk = clk_get_rate(host->clk);
1327         mmc = host->mmc;
1328
1329         if ((val == CPUFREQ_PRECHANGE && newclk > host->clk_rate) ||
1330             (val == CPUFREQ_POSTCHANGE && newclk < host->clk_rate)) {
1331                 spin_lock_irqsave(&mmc->lock, flags);
1332
1333                 host->clk_rate = newclk;
1334
1335                 if (mmc->ios.power_mode != MMC_POWER_OFF &&
1336                     mmc->ios.clock != 0)
1337                         s3cmci_set_clk(host, &mmc->ios);
1338
1339                 spin_unlock_irqrestore(&mmc->lock, flags);
1340         }
1341
1342         return 0;
1343 }
1344
1345 static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
1346 {
1347         host->freq_transition.notifier_call = s3cmci_cpufreq_transition;
1348
1349         return cpufreq_register_notifier(&host->freq_transition,
1350                                          CPUFREQ_TRANSITION_NOTIFIER);
1351 }
1352
1353 static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
1354 {
1355         cpufreq_unregister_notifier(&host->freq_transition,
1356                                     CPUFREQ_TRANSITION_NOTIFIER);
1357 }
1358
1359 #else
1360 static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
1361 {
1362         return 0;
1363 }
1364
1365 static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
1366 {
1367 }
1368 #endif
1369
1370
1371 #ifdef CONFIG_DEBUG_FS
1372
1373 static int s3cmci_state_show(struct seq_file *seq, void *v)
1374 {
1375         struct s3cmci_host *host = seq->private;
1376
1377         seq_printf(seq, "Register base = 0x%p\n", host->base);
1378         seq_printf(seq, "Clock rate = %ld\n", host->clk_rate);
1379         seq_printf(seq, "Prescale = %d\n", host->prescaler);
1380         seq_printf(seq, "is2440 = %d\n", host->is2440);
1381         seq_printf(seq, "IRQ = %d\n", host->irq);
1382         seq_printf(seq, "IRQ enabled = %d\n", host->irq_enabled);
1383         seq_printf(seq, "IRQ disabled = %d\n", host->irq_disabled);
1384         seq_printf(seq, "IRQ state = %d\n", host->irq_state);
1385         seq_printf(seq, "CD IRQ = %d\n", host->irq_cd);
1386         seq_printf(seq, "Do DMA = %d\n", s3cmci_host_usedma(host));
1387         seq_printf(seq, "SDIIMSK at %d\n", host->sdiimsk);
1388         seq_printf(seq, "SDIDATA at %d\n", host->sdidata);
1389
1390         return 0;
1391 }
1392
1393 DEFINE_SHOW_ATTRIBUTE(s3cmci_state);
1394
1395 #define DBG_REG(_r) { .addr = S3C2410_SDI##_r, .name = #_r }
1396
1397 struct s3cmci_reg {
1398         unsigned short  addr;
1399         unsigned char   *name;
1400 };
1401
1402 static const struct s3cmci_reg debug_regs[] = {
1403         DBG_REG(CON),
1404         DBG_REG(PRE),
1405         DBG_REG(CMDARG),
1406         DBG_REG(CMDCON),
1407         DBG_REG(CMDSTAT),
1408         DBG_REG(RSP0),
1409         DBG_REG(RSP1),
1410         DBG_REG(RSP2),
1411         DBG_REG(RSP3),
1412         DBG_REG(TIMER),
1413         DBG_REG(BSIZE),
1414         DBG_REG(DCON),
1415         DBG_REG(DCNT),
1416         DBG_REG(DSTA),
1417         DBG_REG(FSTA),
1418         {}
1419 };
1420
1421 static int s3cmci_regs_show(struct seq_file *seq, void *v)
1422 {
1423         struct s3cmci_host *host = seq->private;
1424         const struct s3cmci_reg *rptr = debug_regs;
1425
1426         for (; rptr->name; rptr++)
1427                 seq_printf(seq, "SDI%s\t=0x%08x\n", rptr->name,
1428                            readl(host->base + rptr->addr));
1429
1430         seq_printf(seq, "SDIIMSK\t=0x%08x\n", readl(host->base + host->sdiimsk));
1431
1432         return 0;
1433 }
1434
1435 DEFINE_SHOW_ATTRIBUTE(s3cmci_regs);
1436
1437 static void s3cmci_debugfs_attach(struct s3cmci_host *host)
1438 {
1439         struct device *dev = &host->pdev->dev;
1440         struct dentry *root;
1441
1442         root = debugfs_create_dir(dev_name(dev), NULL);
1443         host->debug_root = root;
1444
1445         debugfs_create_file("state", 0444, root, host, &s3cmci_state_fops);
1446         debugfs_create_file("regs", 0444, root, host, &s3cmci_regs_fops);
1447 }
1448
1449 static void s3cmci_debugfs_remove(struct s3cmci_host *host)
1450 {
1451         debugfs_remove_recursive(host->debug_root);
1452 }
1453
1454 #else
1455 static inline void s3cmci_debugfs_attach(struct s3cmci_host *host) { }
1456 static inline void s3cmci_debugfs_remove(struct s3cmci_host *host) { }
1457
1458 #endif /* CONFIG_DEBUG_FS */
1459
1460 static int s3cmci_probe_pdata(struct s3cmci_host *host)
1461 {
1462         struct platform_device *pdev = host->pdev;
1463         struct mmc_host *mmc = host->mmc;
1464         struct s3c24xx_mci_pdata *pdata;
1465         int i, ret;
1466
1467         host->is2440 = platform_get_device_id(pdev)->driver_data;
1468
1469         for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++) {
1470                 ret = gpio_request(i, dev_name(&pdev->dev));
1471                 if (ret) {
1472                         dev_err(&pdev->dev, "failed to get gpio %d\n", i);
1473
1474                         for (i--; i >= S3C2410_GPE(5); i--)
1475                                 gpio_free(i);
1476
1477                         return ret;
1478                 }
1479         }
1480
1481         if (!pdev->dev.platform_data)
1482                 pdev->dev.platform_data = &s3cmci_def_pdata;
1483
1484         pdata = pdev->dev.platform_data;
1485
1486         if (pdata->no_wprotect)
1487                 mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT;
1488
1489         if (pdata->no_detect)
1490                 mmc->caps |= MMC_CAP_NEEDS_POLL;
1491
1492         if (pdata->wprotect_invert)
1493                 mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
1494
1495         /* If we get -ENOENT we have no card detect GPIO line */
1496         ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0);
1497         if (ret != -ENOENT) {
1498                 dev_err(&pdev->dev, "error requesting GPIO for CD %d\n",
1499                         ret);
1500                 return ret;
1501         }
1502
1503         ret = mmc_gpiod_request_ro(host->mmc, "wp", 0, 0);
1504         if (ret != -ENOENT) {
1505                 dev_err(&pdev->dev, "error requesting GPIO for WP %d\n",
1506                         ret);
1507                 return ret;
1508         }
1509
1510         return 0;
1511 }
1512
1513 static int s3cmci_probe_dt(struct s3cmci_host *host)
1514 {
1515         struct platform_device *pdev = host->pdev;
1516         struct s3c24xx_mci_pdata *pdata;
1517         struct mmc_host *mmc = host->mmc;
1518         int ret;
1519
1520         host->is2440 = (long) of_device_get_match_data(&pdev->dev);
1521
1522         ret = mmc_of_parse(mmc);
1523         if (ret)
1524                 return ret;
1525
1526         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1527         if (!pdata)
1528                 return -ENOMEM;
1529
1530         pdev->dev.platform_data = pdata;
1531
1532         return 0;
1533 }
1534
1535 static int s3cmci_probe(struct platform_device *pdev)
1536 {
1537         struct s3cmci_host *host;
1538         struct mmc_host *mmc;
1539         int ret;
1540         int i;
1541
1542         mmc = mmc_alloc_host(sizeof(struct s3cmci_host), &pdev->dev);
1543         if (!mmc) {
1544                 ret = -ENOMEM;
1545                 goto probe_out;
1546         }
1547
1548         host = mmc_priv(mmc);
1549         host->mmc       = mmc;
1550         host->pdev      = pdev;
1551
1552         if (pdev->dev.of_node)
1553                 ret = s3cmci_probe_dt(host);
1554         else
1555                 ret = s3cmci_probe_pdata(host);
1556
1557         if (ret)
1558                 goto probe_free_host;
1559
1560         host->pdata = pdev->dev.platform_data;
1561
1562         spin_lock_init(&host->complete_lock);
1563         tasklet_init(&host->pio_tasklet, pio_tasklet, (unsigned long) host);
1564
1565         if (host->is2440) {
1566                 host->sdiimsk   = S3C2440_SDIIMSK;
1567                 host->sdidata   = S3C2440_SDIDATA;
1568                 host->clk_div   = 1;
1569         } else {
1570                 host->sdiimsk   = S3C2410_SDIIMSK;
1571                 host->sdidata   = S3C2410_SDIDATA;
1572                 host->clk_div   = 2;
1573         }
1574
1575         host->complete_what     = COMPLETION_NONE;
1576         host->pio_active        = XFER_NONE;
1577
1578         host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1579         if (!host->mem) {
1580                 dev_err(&pdev->dev,
1581                         "failed to get io memory region resource.\n");
1582
1583                 ret = -ENOENT;
1584                 goto probe_free_gpio;
1585         }
1586
1587         host->mem = request_mem_region(host->mem->start,
1588                                        resource_size(host->mem), pdev->name);
1589
1590         if (!host->mem) {
1591                 dev_err(&pdev->dev, "failed to request io memory region.\n");
1592                 ret = -ENOENT;
1593                 goto probe_free_gpio;
1594         }
1595
1596         host->base = ioremap(host->mem->start, resource_size(host->mem));
1597         if (!host->base) {
1598                 dev_err(&pdev->dev, "failed to ioremap() io memory region.\n");
1599                 ret = -EINVAL;
1600                 goto probe_free_mem_region;
1601         }
1602
1603         host->irq = platform_get_irq(pdev, 0);
1604         if (host->irq <= 0) {
1605                 ret = -EINVAL;
1606                 goto probe_iounmap;
1607         }
1608
1609         if (request_irq(host->irq, s3cmci_irq, 0, DRIVER_NAME, host)) {
1610                 dev_err(&pdev->dev, "failed to request mci interrupt.\n");
1611                 ret = -ENOENT;
1612                 goto probe_iounmap;
1613         }
1614
1615         /* We get spurious interrupts even when we have set the IMSK
1616          * register to ignore everything, so use disable_irq() to make
1617          * ensure we don't lock the system with un-serviceable requests. */
1618
1619         disable_irq(host->irq);
1620         host->irq_state = false;
1621
1622         /* Depending on the dma state, get a DMA channel to use. */
1623
1624         if (s3cmci_host_usedma(host)) {
1625                 host->dma = dma_request_chan(&pdev->dev, "rx-tx");
1626                 ret = PTR_ERR_OR_ZERO(host->dma);
1627                 if (ret) {
1628                         dev_err(&pdev->dev, "cannot get DMA channel.\n");
1629                         goto probe_free_irq;
1630                 }
1631         }
1632
1633         host->clk = clk_get(&pdev->dev, "sdi");
1634         if (IS_ERR(host->clk)) {
1635                 dev_err(&pdev->dev, "failed to find clock source.\n");
1636                 ret = PTR_ERR(host->clk);
1637                 host->clk = NULL;
1638                 goto probe_free_dma;
1639         }
1640
1641         ret = clk_prepare_enable(host->clk);
1642         if (ret) {
1643                 dev_err(&pdev->dev, "failed to enable clock source.\n");
1644                 goto clk_free;
1645         }
1646
1647         host->clk_rate = clk_get_rate(host->clk);
1648
1649         mmc->ops        = &s3cmci_ops;
1650         mmc->ocr_avail  = MMC_VDD_32_33 | MMC_VDD_33_34;
1651 #ifdef CONFIG_MMC_S3C_HW_SDIO_IRQ
1652         mmc->caps       = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1653 #else
1654         mmc->caps       = MMC_CAP_4_BIT_DATA;
1655 #endif
1656         mmc->f_min      = host->clk_rate / (host->clk_div * 256);
1657         mmc->f_max      = host->clk_rate / host->clk_div;
1658
1659         if (host->pdata->ocr_avail)
1660                 mmc->ocr_avail = host->pdata->ocr_avail;
1661
1662         mmc->max_blk_count      = 4095;
1663         mmc->max_blk_size       = 4095;
1664         mmc->max_req_size       = 4095 * 512;
1665         mmc->max_seg_size       = mmc->max_req_size;
1666
1667         mmc->max_segs           = 128;
1668
1669         dbg(host, dbg_debug,
1670             "probe: mode:%s mapped mci_base:%p irq:%u irq_cd:%u dma:%p.\n",
1671             (host->is2440?"2440":""),
1672             host->base, host->irq, host->irq_cd, host->dma);
1673
1674         ret = s3cmci_cpufreq_register(host);
1675         if (ret) {
1676                 dev_err(&pdev->dev, "failed to register cpufreq\n");
1677                 goto free_dmabuf;
1678         }
1679
1680         ret = mmc_add_host(mmc);
1681         if (ret) {
1682                 dev_err(&pdev->dev, "failed to add mmc host.\n");
1683                 goto free_cpufreq;
1684         }
1685
1686         s3cmci_debugfs_attach(host);
1687
1688         platform_set_drvdata(pdev, mmc);
1689         dev_info(&pdev->dev, "%s - using %s, %s SDIO IRQ\n", mmc_hostname(mmc),
1690                  s3cmci_host_usedma(host) ? "dma" : "pio",
1691                  mmc->caps & MMC_CAP_SDIO_IRQ ? "hw" : "sw");
1692
1693         return 0;
1694
1695  free_cpufreq:
1696         s3cmci_cpufreq_deregister(host);
1697
1698  free_dmabuf:
1699         clk_disable_unprepare(host->clk);
1700
1701  clk_free:
1702         clk_put(host->clk);
1703
1704  probe_free_dma:
1705         if (s3cmci_host_usedma(host))
1706                 dma_release_channel(host->dma);
1707
1708  probe_free_irq:
1709         free_irq(host->irq, host);
1710
1711  probe_iounmap:
1712         iounmap(host->base);
1713
1714  probe_free_mem_region:
1715         release_mem_region(host->mem->start, resource_size(host->mem));
1716
1717  probe_free_gpio:
1718         if (!pdev->dev.of_node)
1719                 for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++)
1720                         gpio_free(i);
1721
1722  probe_free_host:
1723         mmc_free_host(mmc);
1724
1725  probe_out:
1726         return ret;
1727 }
1728
1729 static void s3cmci_shutdown(struct platform_device *pdev)
1730 {
1731         struct mmc_host *mmc = platform_get_drvdata(pdev);
1732         struct s3cmci_host *host = mmc_priv(mmc);
1733
1734         if (host->irq_cd >= 0)
1735                 free_irq(host->irq_cd, host);
1736
1737         s3cmci_debugfs_remove(host);
1738         s3cmci_cpufreq_deregister(host);
1739         mmc_remove_host(mmc);
1740         clk_disable_unprepare(host->clk);
1741 }
1742
1743 static int s3cmci_remove(struct platform_device *pdev)
1744 {
1745         struct mmc_host         *mmc  = platform_get_drvdata(pdev);
1746         struct s3cmci_host      *host = mmc_priv(mmc);
1747         int i;
1748
1749         s3cmci_shutdown(pdev);
1750
1751         clk_put(host->clk);
1752
1753         tasklet_disable(&host->pio_tasklet);
1754
1755         if (s3cmci_host_usedma(host))
1756                 dma_release_channel(host->dma);
1757
1758         free_irq(host->irq, host);
1759
1760         if (!pdev->dev.of_node)
1761                 for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++)
1762                         gpio_free(i);
1763
1764         iounmap(host->base);
1765         release_mem_region(host->mem->start, resource_size(host->mem));
1766
1767         mmc_free_host(mmc);
1768         return 0;
1769 }
1770
1771 static const struct of_device_id s3cmci_dt_match[] = {
1772         {
1773                 .compatible = "samsung,s3c2410-sdi",
1774                 .data = (void *)0,
1775         },
1776         {
1777                 .compatible = "samsung,s3c2412-sdi",
1778                 .data = (void *)1,
1779         },
1780         {
1781                 .compatible = "samsung,s3c2440-sdi",
1782                 .data = (void *)1,
1783         },
1784         { /* sentinel */ },
1785 };
1786 MODULE_DEVICE_TABLE(of, s3cmci_dt_match);
1787
1788 static const struct platform_device_id s3cmci_driver_ids[] = {
1789         {
1790                 .name   = "s3c2410-sdi",
1791                 .driver_data    = 0,
1792         }, {
1793                 .name   = "s3c2412-sdi",
1794                 .driver_data    = 1,
1795         }, {
1796                 .name   = "s3c2440-sdi",
1797                 .driver_data    = 1,
1798         },
1799         { }
1800 };
1801
1802 MODULE_DEVICE_TABLE(platform, s3cmci_driver_ids);
1803
1804 static struct platform_driver s3cmci_driver = {
1805         .driver = {
1806                 .name   = "s3c-sdi",
1807                 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1808                 .of_match_table = s3cmci_dt_match,
1809         },
1810         .id_table       = s3cmci_driver_ids,
1811         .probe          = s3cmci_probe,
1812         .remove         = s3cmci_remove,
1813         .shutdown       = s3cmci_shutdown,
1814 };
1815
1816 module_platform_driver(s3cmci_driver);
1817
1818 MODULE_DESCRIPTION("Samsung S3C MMC/SD Card Interface driver");
1819 MODULE_LICENSE("GPL v2");
1820 MODULE_AUTHOR("Thomas Kleffel <tk@maintech.de>, Ben Dooks <ben-linux@fluff.org>");