drivers/mmc/host/rtsx_pci_sdmmc.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /* Realtek PCI-Express SD/MMC Card Interface driver
   3  *
   4  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
   5  *
   6  * Author:
   7  *   Wei WANG <wei_wang@realsil.com.cn>
   8  */
   9
  10 #include <linux/module.h>
  11 #include <linux/slab.h>
  12 #include <linux/highmem.h>
  13 #include <linux/delay.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/workqueue.h>
  16 #include <linux/mmc/host.h>
  17 #include <linux/mmc/mmc.h>
  18 #include <linux/mmc/sd.h>
  19 #include <linux/mmc/sdio.h>
  20 #include <linux/mmc/card.h>
  21 #include <linux/rtsx_pci.h>
  22 #include <asm/unaligned.h>
  23
  24 struct realtek_pci_sdmmc {
  25         struct platform_device  *pdev;
  26         struct rtsx_pcr         *pcr;
  27         struct mmc_host         *mmc;
  28         struct mmc_request      *mrq;
  29 #define SDMMC_WORKQ_NAME        "rtsx_pci_sdmmc_workq"
  30
  31         struct work_struct      work;
  32         struct mutex            host_mutex;
  33
  34         u8                      ssc_depth;
  35         unsigned int            clock;
  36         bool                    vpclk;
  37         bool                    double_clk;
  38         bool                    eject;
  39         bool                    initial_mode;
  40         int                     power_state;
  41 #define SDMMC_POWER_ON          1
  42 #define SDMMC_POWER_OFF         0
  43
  44         int                     sg_count;
  45         s32                     cookie;
  46         int                     cookie_sg_count;
  47         bool                    using_cookie;
  48 };
  49
  50 static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host)
  51 {
  52         return &(host->pdev->dev);
  53 }
  54
  55 static inline void sd_clear_error(struct realtek_pci_sdmmc *host)
  56 {
  57         rtsx_pci_write_register(host->pcr, CARD_STOP,
  58                         SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR);
  59 }
  60
  61 #ifdef DEBUG
  62 static void dump_reg_range(struct realtek_pci_sdmmc *host, u16 start, u16 end)
  63 {
  64         u16 len = end - start + 1;
  65         int i;
  66         u8 data[8];
  67
  68         for (i = 0; i < len; i += 8) {
  69                 int j;
  70                 int n = min(8, len - i);
  71
  72                 memset(&data, 0, sizeof(data));
  73                 for (j = 0; j < n; j++)
  74                         rtsx_pci_read_register(host->pcr, start + i + j,
  75                                 data + j);
  76                 dev_dbg(sdmmc_dev(host), "0x%04X(%d): %8ph\n",
  77                         start + i, n, data);
  78         }
  79 }
  80
  81 static void sd_print_debug_regs(struct realtek_pci_sdmmc *host)
  82 {
  83         dump_reg_range(host, 0xFDA0, 0xFDB3);
  84         dump_reg_range(host, 0xFD52, 0xFD69);
  85 }
  86 #else
  87 #define sd_print_debug_regs(host)
  88 #endif /* DEBUG */
  89
  90 static inline int sd_get_cd_int(struct realtek_pci_sdmmc *host)
  91 {
  92         return rtsx_pci_readl(host->pcr, RTSX_BIPR) & SD_EXIST;
  93 }
  94
  95 static void sd_cmd_set_sd_cmd(struct rtsx_pcr *pcr, struct mmc_command *cmd)
  96 {
  97         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF,
  98                 SD_CMD_START | cmd->opcode);
  99         rtsx_pci_write_be32(pcr, SD_CMD1, cmd->arg);
 100 }
 101
 102 static void sd_cmd_set_data_len(struct rtsx_pcr *pcr, u16 blocks, u16 blksz)
 103 {
 104         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, blocks);
 105         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, blocks >> 8);
 106         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, blksz);
 107         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, blksz >> 8);
 108 }
 109
 110 static int sd_response_type(struct mmc_command *cmd)
 111 {
 112         switch (mmc_resp_type(cmd)) {
 113         case MMC_RSP_NONE:
 114                 return SD_RSP_TYPE_R0;
 115         case MMC_RSP_R1:
 116                 return SD_RSP_TYPE_R1;
 117         case MMC_RSP_R1_NO_CRC:
 118                 return SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7;
 119         case MMC_RSP_R1B:
 120                 return SD_RSP_TYPE_R1b;
 121         case MMC_RSP_R2:
 122                 return SD_RSP_TYPE_R2;
 123         case MMC_RSP_R3:
 124                 return SD_RSP_TYPE_R3;
 125         default:
 126                 return -EINVAL;
 127         }
 128 }
 129
 130 static int sd_status_index(int resp_type)
 131 {
 132         if (resp_type == SD_RSP_TYPE_R0)
 133                 return 0;
 134         else if (resp_type == SD_RSP_TYPE_R2)
 135                 return 16;
 136
 137         return 5;
 138 }
 139 /*
 140  * sd_pre_dma_transfer - do dma_map_sg() or using cookie
 141  *
 142  * @pre: if called in pre_req()
 143  * return:
 144  *      0 - do dma_map_sg()
 145  *      1 - using cookie
 146  */
 147 static int sd_pre_dma_transfer(struct realtek_pci_sdmmc *host,
 148                 struct mmc_data *data, bool pre)
 149 {
 150         struct rtsx_pcr *pcr = host->pcr;
 151         int read = data->flags & MMC_DATA_READ;
 152         int count = 0;
 153         int using_cookie = 0;
 154
 155         if (!pre && data->host_cookie && data->host_cookie != host->cookie) {
 156                 dev_err(sdmmc_dev(host),
 157                         "error: data->host_cookie = %d, host->cookie = %d\n",
 158                         data->host_cookie, host->cookie);
 159                 data->host_cookie = 0;
 160         }
 161
 162         if (pre || data->host_cookie != host->cookie) {
 163                 count = rtsx_pci_dma_map_sg(pcr, data->sg, data->sg_len, read);
 164         } else {
 165                 count = host->cookie_sg_count;
 166                 using_cookie = 1;
 167         }
 168
 169         if (pre) {
 170                 host->cookie_sg_count = count;
 171                 if (++host->cookie < 0)
 172                         host->cookie = 1;
 173                 data->host_cookie = host->cookie;
 174         } else {
 175                 host->sg_count = count;
 176         }
 177
 178         return using_cookie;
 179 }
 180
 181 static void sdmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
 182 {
 183         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
 184         struct mmc_data *data = mrq->data;
 185
 186         if (data->host_cookie) {
 187                 dev_err(sdmmc_dev(host),
 188                         "error: reset data->host_cookie = %d\n",
 189                         data->host_cookie);
 190                 data->host_cookie = 0;
 191         }
 192
 193         sd_pre_dma_transfer(host, data, true);
 194         dev_dbg(sdmmc_dev(host), "pre dma sg: %d\n", host->cookie_sg_count);
 195 }
 196
 197 static void sdmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
 198                 int err)
 199 {
 200         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
 201         struct rtsx_pcr *pcr = host->pcr;
 202         struct mmc_data *data = mrq->data;
 203         int read = data->flags & MMC_DATA_READ;
 204
 205         rtsx_pci_dma_unmap_sg(pcr, data->sg, data->sg_len, read);
 206         data->host_cookie = 0;
 207 }
 208
 209 static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host,
 210                 struct mmc_command *cmd)
 211 {
 212         struct rtsx_pcr *pcr = host->pcr;
 213         u8 cmd_idx = (u8)cmd->opcode;
 214         u32 arg = cmd->arg;
 215         int err = 0;
 216         int timeout = 100;
 217         int i;
 218         u8 *ptr;
 219         int rsp_type;
 220         int stat_idx;
 221         bool clock_toggled = false;
 222
 223         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 224                         __func__, cmd_idx, arg);
 225
 226         rsp_type = sd_response_type(cmd);
 227         if (rsp_type < 0)
 228                 goto out;
 229
 230         stat_idx = sd_status_index(rsp_type);
 231
 232         if (rsp_type == SD_RSP_TYPE_R1b)
 233                 timeout = cmd->busy_timeout ? cmd->busy_timeout : 3000;
 234
 235         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
 236                 err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
 237                                 0xFF, SD_CLK_TOGGLE_EN);
 238                 if (err < 0)
 239                         goto out;
 240
 241                 clock_toggled = true;
 242         }
 243
 244         rtsx_pci_init_cmd(pcr);
 245         sd_cmd_set_sd_cmd(pcr, cmd);
 246         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type);
 247         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
 248                         0x01, PINGPONG_BUFFER);
 249         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
 250                         0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
 251         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 252                      SD_TRANSFER_END | SD_STAT_IDLE,
 253                      SD_TRANSFER_END | SD_STAT_IDLE);
 254
 255         if (rsp_type == SD_RSP_TYPE_R2) {
 256                 /* Read data from ping-pong buffer */
 257                 for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++)
 258                         rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
 259         } else if (rsp_type != SD_RSP_TYPE_R0) {
 260                 /* Read data from SD_CMDx registers */
 261                 for (i = SD_CMD0; i <= SD_CMD4; i++)
 262                         rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0);
 263         }
 264
 265         rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0);
 266
 267         err = rtsx_pci_send_cmd(pcr, timeout);
 268         if (err < 0) {
 269                 sd_print_debug_regs(host);
 270                 sd_clear_error(host);
 271                 dev_dbg(sdmmc_dev(host),
 272                         "rtsx_pci_send_cmd error (err = %d)\n", err);
 273                 goto out;
 274         }
 275
 276         if (rsp_type == SD_RSP_TYPE_R0) {
 277                 err = 0;
 278                 goto out;
 279         }
 280
 281         /* Eliminate returned value of CHECK_REG_CMD */
 282         ptr = rtsx_pci_get_cmd_data(pcr) + 1;
 283
 284         /* Check (Start,Transmission) bit of Response */
 285         if ((ptr[0] & 0xC0) != 0) {
 286                 err = -EILSEQ;
 287                 dev_dbg(sdmmc_dev(host), "Invalid response bit\n");
 288                 goto out;
 289         }
 290
 291         /* Check CRC7 */
 292         if (!(rsp_type & SD_NO_CHECK_CRC7)) {
 293                 if (ptr[stat_idx] & SD_CRC7_ERR) {
 294                         err = -EILSEQ;
 295                         dev_dbg(sdmmc_dev(host), "CRC7 error\n");
 296                         goto out;
 297                 }
 298         }
 299
 300         if (rsp_type == SD_RSP_TYPE_R2) {
 301                 /*
 302                  * The controller offloads the last byte {CRC-7, end bit 1'b1}
 303                  * of response type R2. Assign dummy CRC, 0, and end bit to the
 304                  * byte(ptr[16], goes into the LSB of resp[3] later).
 305                  */
 306                 ptr[16] = 1;
 307
 308                 for (i = 0; i < 4; i++) {
 309                         cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4);
 310                         dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n",
 311                                         i, cmd->resp[i]);
 312                 }
 313         } else {
 314                 cmd->resp[0] = get_unaligned_be32(ptr + 1);
 315                 dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n",
 316                                 cmd->resp[0]);
 317         }
 318
 319 out:
 320         cmd->error = err;
 321
 322         if (err && clock_toggled)
 323                 rtsx_pci_write_register(pcr, SD_BUS_STAT,
 324                                 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
 325 }
 326
 327 static int sd_read_data(struct realtek_pci_sdmmc *host, struct mmc_command *cmd,
 328         u16 byte_cnt, u8 *buf, int buf_len, int timeout)
 329 {
 330         struct rtsx_pcr *pcr = host->pcr;
 331         int err;
 332         u8 trans_mode;
 333
 334         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 335                 __func__, cmd->opcode, cmd->arg);
 336
 337         if (!buf)
 338                 buf_len = 0;
 339
 340         if (cmd->opcode == MMC_SEND_TUNING_BLOCK)
 341                 trans_mode = SD_TM_AUTO_TUNING;
 342         else
 343                 trans_mode = SD_TM_NORMAL_READ;
 344
 345         rtsx_pci_init_cmd(pcr);
 346         sd_cmd_set_sd_cmd(pcr, cmd);
 347         sd_cmd_set_data_len(pcr, 1, byte_cnt);
 348         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
 349                         SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
 350                         SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6);
 351         if (trans_mode != SD_TM_AUTO_TUNING)
 352                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
 353                                 CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
 354
 355         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER,
 356                         0xFF, trans_mode | SD_TRANSFER_START);
 357         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 358                         SD_TRANSFER_END, SD_TRANSFER_END);
 359
 360         err = rtsx_pci_send_cmd(pcr, timeout);
 361         if (err < 0) {
 362                 sd_print_debug_regs(host);
 363                 dev_dbg(sdmmc_dev(host),
 364                         "rtsx_pci_send_cmd fail (err = %d)\n", err);
 365                 return err;
 366         }
 367
 368         if (buf && buf_len) {
 369                 err = rtsx_pci_read_ppbuf(pcr, buf, buf_len);
 370                 if (err < 0) {
 371                         dev_dbg(sdmmc_dev(host),
 372                                 "rtsx_pci_read_ppbuf fail (err = %d)\n", err);
 373                         return err;
 374                 }
 375         }
 376
 377         return 0;
 378 }
 379
 380 static int sd_write_data(struct realtek_pci_sdmmc *host,
 381         struct mmc_command *cmd, u16 byte_cnt, u8 *buf, int buf_len,
 382         int timeout)
 383 {
 384         struct rtsx_pcr *pcr = host->pcr;
 385         int err;
 386
 387         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 388                 __func__, cmd->opcode, cmd->arg);
 389
 390         if (!buf)
 391                 buf_len = 0;
 392
 393         sd_send_cmd_get_rsp(host, cmd);
 394         if (cmd->error)
 395                 return cmd->error;
 396
 397         if (buf && buf_len) {
 398                 err = rtsx_pci_write_ppbuf(pcr, buf, buf_len);
 399                 if (err < 0) {
 400                         dev_dbg(sdmmc_dev(host),
 401                                 "rtsx_pci_write_ppbuf fail (err = %d)\n", err);
 402                         return err;
 403                 }
 404         }
 405
 406         rtsx_pci_init_cmd(pcr);
 407         sd_cmd_set_data_len(pcr, 1, byte_cnt);
 408         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF,
 409                 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
 410                 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0);
 411         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
 412                         SD_TRANSFER_START | SD_TM_AUTO_WRITE_3);
 413         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 414                         SD_TRANSFER_END, SD_TRANSFER_END);
 415
 416         err = rtsx_pci_send_cmd(pcr, timeout);
 417         if (err < 0) {
 418                 sd_print_debug_regs(host);
 419                 dev_dbg(sdmmc_dev(host),
 420                         "rtsx_pci_send_cmd fail (err = %d)\n", err);
 421                 return err;
 422         }
 423
 424         return 0;
 425 }
 426
 427 static int sd_read_long_data(struct realtek_pci_sdmmc *host,
 428         struct mmc_request *mrq)
 429 {
 430         struct rtsx_pcr *pcr = host->pcr;
 431         struct mmc_host *mmc = host->mmc;
 432         struct mmc_card *card = mmc->card;
 433         struct mmc_command *cmd = mrq->cmd;
 434         struct mmc_data *data = mrq->data;
 435         int uhs = mmc_card_uhs(card);
 436         u8 cfg2 = 0;
 437         int err;
 438         int resp_type;
 439         size_t data_len = data->blksz * data->blocks;
 440
 441         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 442                 __func__, cmd->opcode, cmd->arg);
 443
 444         resp_type = sd_response_type(cmd);
 445         if (resp_type < 0)
 446                 return resp_type;
 447
 448         if (!uhs)
 449                 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
 450
 451         rtsx_pci_init_cmd(pcr);
 452         sd_cmd_set_sd_cmd(pcr, cmd);
 453         sd_cmd_set_data_len(pcr, data->blocks, data->blksz);
 454         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
 455                         DMA_DONE_INT, DMA_DONE_INT);
 456         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
 457                 0xFF, (u8)(data_len >> 24));
 458         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
 459                 0xFF, (u8)(data_len >> 16));
 460         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
 461                 0xFF, (u8)(data_len >> 8));
 462         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
 463         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
 464                 0x03 | DMA_PACK_SIZE_MASK,
 465                 DMA_DIR_FROM_CARD | DMA_EN | DMA_512);
 466         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
 467                         0x01, RING_BUFFER);
 468         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2 | resp_type);
 469         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
 470                         SD_TRANSFER_START | SD_TM_AUTO_READ_2);
 471         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 472                         SD_TRANSFER_END, SD_TRANSFER_END);
 473         rtsx_pci_send_cmd_no_wait(pcr);
 474
 475         err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 1, 10000);
 476         if (err < 0) {
 477                 sd_print_debug_regs(host);
 478                 sd_clear_error(host);
 479                 return err;
 480         }
 481
 482         return 0;
 483 }
 484
 485 static int sd_write_long_data(struct realtek_pci_sdmmc *host,
 486         struct mmc_request *mrq)
 487 {
 488         struct rtsx_pcr *pcr = host->pcr;
 489         struct mmc_host *mmc = host->mmc;
 490         struct mmc_card *card = mmc->card;
 491         struct mmc_command *cmd = mrq->cmd;
 492         struct mmc_data *data = mrq->data;
 493         int uhs = mmc_card_uhs(card);
 494         u8 cfg2;
 495         int err;
 496         size_t data_len = data->blksz * data->blocks;
 497
 498         sd_send_cmd_get_rsp(host, cmd);
 499         if (cmd->error)
 500                 return cmd->error;
 501
 502         dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n",
 503                 __func__, cmd->opcode, cmd->arg);
 504
 505         cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
 506                 SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
 507
 508         if (!uhs)
 509                 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
 510
 511         rtsx_pci_init_cmd(pcr);
 512         sd_cmd_set_data_len(pcr, data->blocks, data->blksz);
 513         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
 514                         DMA_DONE_INT, DMA_DONE_INT);
 515         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3,
 516                 0xFF, (u8)(data_len >> 24));
 517         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2,
 518                 0xFF, (u8)(data_len >> 16));
 519         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1,
 520                 0xFF, (u8)(data_len >> 8));
 521         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len);
 522         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
 523                 0x03 | DMA_PACK_SIZE_MASK,
 524                 DMA_DIR_TO_CARD | DMA_EN | DMA_512);
 525         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
 526                         0x01, RING_BUFFER);
 527         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2);
 528         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
 529                         SD_TRANSFER_START | SD_TM_AUTO_WRITE_3);
 530         rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,
 531                         SD_TRANSFER_END, SD_TRANSFER_END);
 532         rtsx_pci_send_cmd_no_wait(pcr);
 533         err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 0, 10000);
 534         if (err < 0) {
 535                 sd_clear_error(host);
 536                 return err;
 537         }
 538
 539         return 0;
 540 }
 541
 542 static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq)
 543 {
 544         struct mmc_data *data = mrq->data;
 545
 546         if (host->sg_count < 0) {
 547                 data->error = host->sg_count;
 548                 dev_dbg(sdmmc_dev(host), "%s: sg_count = %d is invalid\n",
 549                         __func__, host->sg_count);
 550                 return data->error;
 551         }
 552
 553         if (data->flags & MMC_DATA_READ)
 554                 return sd_read_long_data(host, mrq);
 555
 556         return sd_write_long_data(host, mrq);
 557 }
 558
 559 static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host)
 560 {
 561         rtsx_pci_write_register(host->pcr, SD_CFG1,
 562                         SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128);
 563 }
 564
 565 static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host)
 566 {
 567         rtsx_pci_write_register(host->pcr, SD_CFG1,
 568                         SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0);
 569 }
 570
 571 static void sd_normal_rw(struct realtek_pci_sdmmc *host,
 572                 struct mmc_request *mrq)
 573 {
 574         struct mmc_command *cmd = mrq->cmd;
 575         struct mmc_data *data = mrq->data;
 576         u8 *buf;
 577
 578         buf = kzalloc(data->blksz, GFP_NOIO);
 579         if (!buf) {
 580                 cmd->error = -ENOMEM;
 581                 return;
 582         }
 583
 584         if (data->flags & MMC_DATA_READ) {
 585                 if (host->initial_mode)
 586                         sd_disable_initial_mode(host);
 587
 588                 cmd->error = sd_read_data(host, cmd, (u16)data->blksz, buf,
 589                                 data->blksz, 200);
 590
 591                 if (host->initial_mode)
 592                         sd_enable_initial_mode(host);
 593
 594                 sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz);
 595         } else {
 596                 sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz);
 597
 598                 cmd->error = sd_write_data(host, cmd, (u16)data->blksz, buf,
 599                                 data->blksz, 200);
 600         }
 601
 602         kfree(buf);
 603 }
 604
 605 static int sd_change_phase(struct realtek_pci_sdmmc *host,
 606                 u8 sample_point, bool rx)
 607 {
 608         struct rtsx_pcr *pcr = host->pcr;
 609         u16 SD_VP_CTL = 0;
 610         dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n",
 611                         __func__, rx ? "RX" : "TX", sample_point);
 612
 613         rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
 614         if (rx) {
 615                 SD_VP_CTL = SD_VPRX_CTL;
 616                 rtsx_pci_write_register(pcr, SD_VPRX_CTL,
 617                         PHASE_SELECT_MASK, sample_point);
 618         } else {
 619                 SD_VP_CTL = SD_VPTX_CTL;
 620                 rtsx_pci_write_register(pcr, SD_VPTX_CTL,
 621                         PHASE_SELECT_MASK, sample_point);
 622         }
 623         rtsx_pci_write_register(pcr, SD_VP_CTL, PHASE_NOT_RESET, 0);
 624         rtsx_pci_write_register(pcr, SD_VP_CTL, PHASE_NOT_RESET,
 625                                 PHASE_NOT_RESET);
 626         rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, 0);
 627         rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
 628
 629         return 0;
 630 }
 631
 632 static inline u32 test_phase_bit(u32 phase_map, unsigned int bit)
 633 {
 634         bit %= RTSX_PHASE_MAX;
 635         return phase_map & (1 << bit);
 636 }
 637
 638 static int sd_get_phase_len(u32 phase_map, unsigned int start_bit)
 639 {
 640         int i;
 641
 642         for (i = 0; i < RTSX_PHASE_MAX; i++) {
 643                 if (test_phase_bit(phase_map, start_bit + i) == 0)
 644                         return i;
 645         }
 646         return RTSX_PHASE_MAX;
 647 }
 648
 649 static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map)
 650 {
 651         int start = 0, len = 0;
 652         int start_final = 0, len_final = 0;
 653         u8 final_phase = 0xFF;
 654
 655         if (phase_map == 0) {
 656                 dev_err(sdmmc_dev(host), "phase error: [map:%x]\n", phase_map);
 657                 return final_phase;
 658         }
 659
 660         while (start < RTSX_PHASE_MAX) {
 661                 len = sd_get_phase_len(phase_map, start);
 662                 if (len_final < len) {
 663                         start_final = start;
 664                         len_final = len;
 665                 }
 666                 start += len ? len : 1;
 667         }
 668
 669         final_phase = (start_final + len_final / 2) % RTSX_PHASE_MAX;
 670         dev_dbg(sdmmc_dev(host), "phase: [map:%x] [maxlen:%d] [final:%d]\n",
 671                 phase_map, len_final, final_phase);
 672
 673         return final_phase;
 674 }
 675
 676 static void sd_wait_data_idle(struct realtek_pci_sdmmc *host)
 677 {
 678         int err, i;
 679         u8 val = 0;
 680
 681         for (i = 0; i < 100; i++) {
 682                 err = rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val);
 683                 if (val & SD_DATA_IDLE)
 684                         return;
 685
 686                 udelay(100);
 687         }
 688 }
 689
 690 static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host,
 691                 u8 opcode, u8 sample_point)
 692 {
 693         int err;
 694         struct mmc_command cmd = {};
 695         struct rtsx_pcr *pcr = host->pcr;
 696
 697         sd_change_phase(host, sample_point, true);
 698
 699         rtsx_pci_write_register(pcr, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
 700                 SD_RSP_80CLK_TIMEOUT_EN);
 701
 702         cmd.opcode = opcode;
 703         err = sd_read_data(host, &cmd, 0x40, NULL, 0, 100);
 704         if (err < 0) {
 705                 /* Wait till SD DATA IDLE */
 706                 sd_wait_data_idle(host);
 707                 sd_clear_error(host);
 708                 rtsx_pci_write_register(pcr, SD_CFG3,
 709                         SD_RSP_80CLK_TIMEOUT_EN, 0);
 710                 return err;
 711         }
 712
 713         rtsx_pci_write_register(pcr, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
 714         return 0;
 715 }
 716
 717 static int sd_tuning_phase(struct realtek_pci_sdmmc *host,
 718                 u8 opcode, u32 *phase_map)
 719 {
 720         int err, i;
 721         u32 raw_phase_map = 0;
 722
 723         for (i = 0; i < RTSX_PHASE_MAX; i++) {
 724                 err = sd_tuning_rx_cmd(host, opcode, (u8)i);
 725                 if (err == 0)
 726                         raw_phase_map |= 1 << i;
 727         }
 728
 729         if (phase_map)
 730                 *phase_map = raw_phase_map;
 731
 732         return 0;
 733 }
 734
 735 static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode)
 736 {
 737         int err, i;
 738         u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map;
 739         u8 final_phase;
 740
 741         for (i = 0; i < RX_TUNING_CNT; i++) {
 742                 err = sd_tuning_phase(host, opcode, &(raw_phase_map[i]));
 743                 if (err < 0)
 744                         return err;
 745
 746                 if (raw_phase_map[i] == 0)
 747                         break;
 748         }
 749
 750         phase_map = 0xFFFFFFFF;
 751         for (i = 0; i < RX_TUNING_CNT; i++) {
 752                 dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n",
 753                                 i, raw_phase_map[i]);
 754                 phase_map &= raw_phase_map[i];
 755         }
 756         dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map);
 757
 758         if (phase_map) {
 759                 final_phase = sd_search_final_phase(host, phase_map);
 760                 if (final_phase == 0xFF)
 761                         return -EINVAL;
 762
 763                 err = sd_change_phase(host, final_phase, true);
 764                 if (err < 0)
 765                         return err;
 766         } else {
 767                 return -EINVAL;
 768         }
 769
 770         return 0;
 771 }
 772
 773 static inline int sdio_extblock_cmd(struct mmc_command *cmd,
 774         struct mmc_data *data)
 775 {
 776         return (cmd->opcode == SD_IO_RW_EXTENDED) && (data->blksz == 512);
 777 }
 778
 779 static inline int sd_rw_cmd(struct mmc_command *cmd)
 780 {
 781         return mmc_op_multi(cmd->opcode) ||
 782                 (cmd->opcode == MMC_READ_SINGLE_BLOCK) ||
 783                 (cmd->opcode == MMC_WRITE_BLOCK);
 784 }
 785
 786 static void sd_request(struct work_struct *work)
 787 {
 788         struct realtek_pci_sdmmc *host = container_of(work,
 789                         struct realtek_pci_sdmmc, work);
 790         struct rtsx_pcr *pcr = host->pcr;
 791
 792         struct mmc_host *mmc = host->mmc;
 793         struct mmc_request *mrq = host->mrq;
 794         struct mmc_command *cmd = mrq->cmd;
 795         struct mmc_data *data = mrq->data;
 796
 797         unsigned int data_size = 0;
 798         int err;
 799
 800         if (host->eject || !sd_get_cd_int(host)) {
 801                 cmd->error = -ENOMEDIUM;
 802                 goto finish;
 803         }
 804
 805         err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
 806         if (err) {
 807                 cmd->error = err;
 808                 goto finish;
 809         }
 810
 811         mutex_lock(&pcr->pcr_mutex);
 812
 813         rtsx_pci_start_run(pcr);
 814
 815         rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth,
 816                         host->initial_mode, host->double_clk, host->vpclk);
 817         rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL);
 818         rtsx_pci_write_register(pcr, CARD_SHARE_MODE,
 819                         CARD_SHARE_MASK, CARD_SHARE_48_SD);
 820
 821         mutex_lock(&host->host_mutex);
 822         host->mrq = mrq;
 823         mutex_unlock(&host->host_mutex);
 824
 825         if (mrq->data)
 826                 data_size = data->blocks * data->blksz;
 827
 828         if (!data_size) {
 829                 sd_send_cmd_get_rsp(host, cmd);
 830         } else if (sd_rw_cmd(cmd) || sdio_extblock_cmd(cmd, data)) {
 831                 cmd->error = sd_rw_multi(host, mrq);
 832                 if (!host->using_cookie)
 833                         sdmmc_post_req(host->mmc, host->mrq, 0);
 834
 835                 if (mmc_op_multi(cmd->opcode) && mrq->stop)
 836                         sd_send_cmd_get_rsp(host, mrq->stop);
 837         } else {
 838                 sd_normal_rw(host, mrq);
 839         }
 840
 841         if (mrq->data) {
 842                 if (cmd->error || data->error)
 843                         data->bytes_xfered = 0;
 844                 else
 845                         data->bytes_xfered = data->blocks * data->blksz;
 846         }
 847
 848         mutex_unlock(&pcr->pcr_mutex);
 849
 850 finish:
 851         if (cmd->error) {
 852                 dev_dbg(sdmmc_dev(host), "CMD %d 0x%08x error(%d)\n",
 853                         cmd->opcode, cmd->arg, cmd->error);
 854         }
 855
 856         mutex_lock(&host->host_mutex);
 857         host->mrq = NULL;
 858         mutex_unlock(&host->host_mutex);
 859
 860         mmc_request_done(mmc, mrq);
 861 }
 862
 863 static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
 864 {
 865         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
 866         struct mmc_data *data = mrq->data;
 867
 868         mutex_lock(&host->host_mutex);
 869         host->mrq = mrq;
 870         mutex_unlock(&host->host_mutex);
 871
 872         if (sd_rw_cmd(mrq->cmd) || sdio_extblock_cmd(mrq->cmd, data))
 873                 host->using_cookie = sd_pre_dma_transfer(host, data, false);
 874
 875         schedule_work(&host->work);
 876 }
 877
 878 static int sd_set_bus_width(struct realtek_pci_sdmmc *host,
 879                 unsigned char bus_width)
 880 {
 881         int err = 0;
 882         u8 width[] = {
 883                 [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT,
 884                 [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT,
 885                 [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT,
 886         };
 887
 888         if (bus_width <= MMC_BUS_WIDTH_8)
 889                 err = rtsx_pci_write_register(host->pcr, SD_CFG1,
 890                                 0x03, width[bus_width]);
 891
 892         return err;
 893 }
 894
 895 static int sd_power_on(struct realtek_pci_sdmmc *host)
 896 {
 897         struct rtsx_pcr *pcr = host->pcr;
 898         int err;
 899
 900         if (host->power_state == SDMMC_POWER_ON)
 901                 return 0;
 902
 903         rtsx_pci_init_cmd(pcr);
 904         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL);
 905         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE,
 906                         CARD_SHARE_MASK, CARD_SHARE_48_SD);
 907         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN,
 908                         SD_CLK_EN, SD_CLK_EN);
 909         err = rtsx_pci_send_cmd(pcr, 100);
 910         if (err < 0)
 911                 return err;
 912
 913         err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD);
 914         if (err < 0)
 915                 return err;
 916
 917         err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD);
 918         if (err < 0)
 919                 return err;
 920
 921         err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
 922         if (err < 0)
 923                 return err;
 924
 925         host->power_state = SDMMC_POWER_ON;
 926         return 0;
 927 }
 928
 929 static int sd_power_off(struct realtek_pci_sdmmc *host)
 930 {
 931         struct rtsx_pcr *pcr = host->pcr;
 932         int err;
 933
 934         host->power_state = SDMMC_POWER_OFF;
 935
 936         rtsx_pci_init_cmd(pcr);
 937
 938         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0);
 939         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
 940
 941         err = rtsx_pci_send_cmd(pcr, 100);
 942         if (err < 0)
 943                 return err;
 944
 945         err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
 946         if (err < 0)
 947                 return err;
 948
 949         return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
 950 }
 951
 952 static int sd_set_power_mode(struct realtek_pci_sdmmc *host,
 953                 unsigned char power_mode)
 954 {
 955         int err;
 956
 957         if (power_mode == MMC_POWER_OFF)
 958                 err = sd_power_off(host);
 959         else
 960                 err = sd_power_on(host);
 961
 962         return err;
 963 }
 964
 965 static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing)
 966 {
 967         struct rtsx_pcr *pcr = host->pcr;
 968         int err = 0;
 969
 970         rtsx_pci_init_cmd(pcr);
 971
 972         switch (timing) {
 973         case MMC_TIMING_UHS_SDR104:
 974         case MMC_TIMING_UHS_SDR50:
 975                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
 976                                 0x0C | SD_ASYNC_FIFO_NOT_RST,
 977                                 SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
 978                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
 979                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
 980                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
 981                                 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
 982                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
 983                 break;
 984
 985         case MMC_TIMING_MMC_DDR52:
 986         case MMC_TIMING_UHS_DDR50:
 987                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
 988                                 0x0C | SD_ASYNC_FIFO_NOT_RST,
 989                                 SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST);
 990                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
 991                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
 992                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
 993                                 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
 994                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
 995                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
 996                                 DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT);
 997                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
 998                                 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD,
 999                                 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD);
1000                 break;
1001
1002         case MMC_TIMING_MMC_HS:
1003         case MMC_TIMING_SD_HS:
1004                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
1005                                 0x0C, SD_20_MODE);
1006                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1007                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
1008                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1009                                 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
1010                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1011                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL,
1012                                 SD20_TX_SEL_MASK, SD20_TX_14_AHEAD);
1013                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1014                                 SD20_RX_SEL_MASK, SD20_RX_14_DELAY);
1015                 break;
1016
1017         default:
1018                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
1019                                 SD_CFG1, 0x0C, SD_20_MODE);
1020                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
1021                                 CLK_LOW_FREQ, CLK_LOW_FREQ);
1022                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF,
1023                                 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
1024                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
1025                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
1026                                 SD_PUSH_POINT_CTL, 0xFF, 0);
1027                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL,
1028                                 SD20_RX_SEL_MASK, SD20_RX_POS_EDGE);
1029                 break;
1030         }
1031
1032         err = rtsx_pci_send_cmd(pcr, 100);
1033
1034         return err;
1035 }
1036
1037 static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1038 {
1039         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1040         struct rtsx_pcr *pcr = host->pcr;
1041
1042         if (host->eject)
1043                 return;
1044
1045         if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD))
1046                 return;
1047
1048         mutex_lock(&pcr->pcr_mutex);
1049
1050         rtsx_pci_start_run(pcr);
1051
1052         sd_set_bus_width(host, ios->bus_width);
1053         sd_set_power_mode(host, ios->power_mode);
1054         sd_set_timing(host, ios->timing);
1055
1056         host->vpclk = false;
1057         host->double_clk = true;
1058
1059         switch (ios->timing) {
1060         case MMC_TIMING_UHS_SDR104:
1061         case MMC_TIMING_UHS_SDR50:
1062                 host->ssc_depth = RTSX_SSC_DEPTH_2M;
1063                 host->vpclk = true;
1064                 host->double_clk = false;
1065                 break;
1066         case MMC_TIMING_MMC_DDR52:
1067         case MMC_TIMING_UHS_DDR50:
1068         case MMC_TIMING_UHS_SDR25:
1069                 host->ssc_depth = RTSX_SSC_DEPTH_1M;
1070                 break;
1071         default:
1072                 host->ssc_depth = RTSX_SSC_DEPTH_500K;
1073                 break;
1074         }
1075
1076         host->initial_mode = (ios->clock <= 1000000) ? true : false;
1077
1078         host->clock = ios->clock;
1079         rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth,
1080                         host->initial_mode, host->double_clk, host->vpclk);
1081
1082         mutex_unlock(&pcr->pcr_mutex);
1083 }
1084
1085 static int sdmmc_get_ro(struct mmc_host *mmc)
1086 {
1087         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1088         struct rtsx_pcr *pcr = host->pcr;
1089         int ro = 0;
1090         u32 val;
1091
1092         if (host->eject)
1093                 return -ENOMEDIUM;
1094
1095         mutex_lock(&pcr->pcr_mutex);
1096
1097         rtsx_pci_start_run(pcr);
1098
1099         /* Check SD mechanical write-protect switch */
1100         val = rtsx_pci_readl(pcr, RTSX_BIPR);
1101         dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1102         if (val & SD_WRITE_PROTECT)
1103                 ro = 1;
1104
1105         mutex_unlock(&pcr->pcr_mutex);
1106
1107         return ro;
1108 }
1109
1110 static int sdmmc_get_cd(struct mmc_host *mmc)
1111 {
1112         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1113         struct rtsx_pcr *pcr = host->pcr;
1114         int cd = 0;
1115         u32 val;
1116
1117         if (host->eject)
1118                 return cd;
1119
1120         mutex_lock(&pcr->pcr_mutex);
1121
1122         rtsx_pci_start_run(pcr);
1123
1124         /* Check SD card detect */
1125         val = rtsx_pci_card_exist(pcr);
1126         dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val);
1127         if (val & SD_EXIST)
1128                 cd = 1;
1129
1130         mutex_unlock(&pcr->pcr_mutex);
1131
1132         return cd;
1133 }
1134
1135 static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host)
1136 {
1137         struct rtsx_pcr *pcr = host->pcr;
1138         int err;
1139         u8 stat;
1140
1141         /* Reference to Signal Voltage Switch Sequence in SD spec.
1142          * Wait for a period of time so that the card can drive SD_CMD and
1143          * SD_DAT[3:0] to low after sending back CMD11 response.
1144          */
1145         mdelay(1);
1146
1147         /* SD_CMD, SD_DAT[3:0] should be driven to low by card;
1148          * If either one of SD_CMD,SD_DAT[3:0] is not low,
1149          * abort the voltage switch sequence;
1150          */
1151         err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1152         if (err < 0)
1153                 return err;
1154
1155         if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1156                                 SD_DAT1_STATUS | SD_DAT0_STATUS))
1157                 return -EINVAL;
1158
1159         /* Stop toggle SD clock */
1160         err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1161                         0xFF, SD_CLK_FORCE_STOP);
1162         if (err < 0)
1163                 return err;
1164
1165         return 0;
1166 }
1167
1168 static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host)
1169 {
1170         struct rtsx_pcr *pcr = host->pcr;
1171         int err;
1172         u8 stat, mask, val;
1173
1174         /* Wait 1.8V output of voltage regulator in card stable */
1175         msleep(50);
1176
1177         /* Toggle SD clock again */
1178         err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
1179         if (err < 0)
1180                 return err;
1181
1182         /* Wait for a period of time so that the card can drive
1183          * SD_DAT[3:0] to high at 1.8V
1184          */
1185         msleep(20);
1186
1187         /* SD_CMD, SD_DAT[3:0] should be pulled high by host */
1188         err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat);
1189         if (err < 0)
1190                 return err;
1191
1192         mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1193                 SD_DAT1_STATUS | SD_DAT0_STATUS;
1194         val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
1195                 SD_DAT1_STATUS | SD_DAT0_STATUS;
1196         if ((stat & mask) != val) {
1197                 dev_dbg(sdmmc_dev(host),
1198                         "%s: SD_BUS_STAT = 0x%x\n", __func__, stat);
1199                 rtsx_pci_write_register(pcr, SD_BUS_STAT,
1200                                 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1201                 rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0);
1202                 return -EINVAL;
1203         }
1204
1205         return 0;
1206 }
1207
1208 static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1209 {
1210         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1211         struct rtsx_pcr *pcr = host->pcr;
1212         int err = 0;
1213         u8 voltage;
1214
1215         dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n",
1216                         __func__, ios->signal_voltage);
1217
1218         if (host->eject)
1219                 return -ENOMEDIUM;
1220
1221         err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1222         if (err)
1223                 return err;
1224
1225         mutex_lock(&pcr->pcr_mutex);
1226
1227         rtsx_pci_start_run(pcr);
1228
1229         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1230                 voltage = OUTPUT_3V3;
1231         else
1232                 voltage = OUTPUT_1V8;
1233
1234         if (voltage == OUTPUT_1V8) {
1235                 err = sd_wait_voltage_stable_1(host);
1236                 if (err < 0)
1237                         goto out;
1238         }
1239
1240         err = rtsx_pci_switch_output_voltage(pcr, voltage);
1241         if (err < 0)
1242                 goto out;
1243
1244         if (voltage == OUTPUT_1V8) {
1245                 err = sd_wait_voltage_stable_2(host);
1246                 if (err < 0)
1247                         goto out;
1248         }
1249
1250 out:
1251         /* Stop toggle SD clock in idle */
1252         err = rtsx_pci_write_register(pcr, SD_BUS_STAT,
1253                         SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
1254
1255         mutex_unlock(&pcr->pcr_mutex);
1256
1257         return err;
1258 }
1259
1260 static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1261 {
1262         struct realtek_pci_sdmmc *host = mmc_priv(mmc);
1263         struct rtsx_pcr *pcr = host->pcr;
1264         int err = 0;
1265
1266         if (host->eject)
1267                 return -ENOMEDIUM;
1268
1269         err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD);
1270         if (err)
1271                 return err;
1272
1273         mutex_lock(&pcr->pcr_mutex);
1274
1275         rtsx_pci_start_run(pcr);
1276
1277         /* Set initial TX phase */
1278         switch (mmc->ios.timing) {
1279         case MMC_TIMING_UHS_SDR104:
1280                 err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false);
1281                 break;
1282
1283         case MMC_TIMING_UHS_SDR50:
1284                 err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false);
1285                 break;
1286
1287         case MMC_TIMING_UHS_DDR50:
1288                 err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false);
1289                 break;
1290
1291         default:
1292                 err = 0;
1293         }
1294
1295         if (err)
1296                 goto out;
1297
1298         /* Tuning RX phase */
1299         if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) ||
1300                         (mmc->ios.timing == MMC_TIMING_UHS_SDR50))
1301                 err = sd_tuning_rx(host, opcode);
1302         else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50)
1303                 err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true);
1304
1305 out:
1306         mutex_unlock(&pcr->pcr_mutex);
1307
1308         return err;
1309 }
1310
1311 static const struct mmc_host_ops realtek_pci_sdmmc_ops = {
1312         .pre_req = sdmmc_pre_req,
1313         .post_req = sdmmc_post_req,
1314         .request = sdmmc_request,
1315         .set_ios = sdmmc_set_ios,
1316         .get_ro = sdmmc_get_ro,
1317         .get_cd = sdmmc_get_cd,
1318         .start_signal_voltage_switch = sdmmc_switch_voltage,
1319         .execute_tuning = sdmmc_execute_tuning,
1320 };
1321
1322 static void init_extra_caps(struct realtek_pci_sdmmc *host)
1323 {
1324         struct mmc_host *mmc = host->mmc;
1325         struct rtsx_pcr *pcr = host->pcr;
1326
1327         dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps);
1328
1329         if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50)
1330                 mmc->caps |= MMC_CAP_UHS_SDR50;
1331         if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
1332                 mmc->caps |= MMC_CAP_UHS_SDR104;
1333         if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50)
1334                 mmc->caps |= MMC_CAP_UHS_DDR50;
1335         if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR)
1336                 mmc->caps |= MMC_CAP_1_8V_DDR;
1337         if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT)
1338                 mmc->caps |= MMC_CAP_8_BIT_DATA;
1339 }
1340
1341 static void realtek_init_host(struct realtek_pci_sdmmc *host)
1342 {
1343         struct mmc_host *mmc = host->mmc;
1344
1345         mmc->f_min = 250000;
1346         mmc->f_max = 208000000;
1347         mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1348         mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED |
1349                 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST |
1350                 MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_ERASE;
1351         mmc->caps2 = MMC_CAP2_NO_PRESCAN_POWERUP | MMC_CAP2_FULL_PWR_CYCLE;
1352         mmc->max_current_330 = 400;
1353         mmc->max_current_180 = 800;
1354         mmc->ops = &realtek_pci_sdmmc_ops;
1355
1356         init_extra_caps(host);
1357
1358         mmc->max_segs = 256;
1359         mmc->max_seg_size = 65536;
1360         mmc->max_blk_size = 512;
1361         mmc->max_blk_count = 65535;
1362         mmc->max_req_size = 524288;
1363 }
1364
1365 static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev)
1366 {
1367         struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1368
1369         host->cookie = -1;
1370         mmc_detect_change(host->mmc, 0);
1371 }
1372
1373 static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev)
1374 {
1375         struct mmc_host *mmc;
1376         struct realtek_pci_sdmmc *host;
1377         struct rtsx_pcr *pcr;
1378         struct pcr_handle *handle = pdev->dev.platform_data;
1379
1380         if (!handle)
1381                 return -ENXIO;
1382
1383         pcr = handle->pcr;
1384         if (!pcr)
1385                 return -ENXIO;
1386
1387         dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n");
1388
1389         mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
1390         if (!mmc)
1391                 return -ENOMEM;
1392
1393         host = mmc_priv(mmc);
1394         host->pcr = pcr;
1395         host->mmc = mmc;
1396         host->pdev = pdev;
1397         host->cookie = -1;
1398         host->power_state = SDMMC_POWER_OFF;
1399         INIT_WORK(&host->work, sd_request);
1400         platform_set_drvdata(pdev, host);
1401         pcr->slots[RTSX_SD_CARD].p_dev = pdev;
1402         pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event;
1403
1404         mutex_init(&host->host_mutex);
1405
1406         realtek_init_host(host);
1407
1408         mmc_add_host(mmc);
1409
1410         return 0;
1411 }
1412
1413 static int rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev)
1414 {
1415         struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev);
1416         struct rtsx_pcr *pcr;
1417         struct mmc_host *mmc;
1418
1419         if (!host)
1420                 return 0;
1421
1422         pcr = host->pcr;
1423         pcr->slots[RTSX_SD_CARD].p_dev = NULL;
1424         pcr->slots[RTSX_SD_CARD].card_event = NULL;
1425         mmc = host->mmc;
1426
1427         cancel_work_sync(&host->work);
1428
1429         mutex_lock(&host->host_mutex);
1430         if (host->mrq) {
1431                 dev_dbg(&(pdev->dev),
1432                         "%s: Controller removed during transfer\n",
1433                         mmc_hostname(mmc));
1434
1435                 rtsx_pci_complete_unfinished_transfer(pcr);
1436
1437                 host->mrq->cmd->error = -ENOMEDIUM;
1438                 if (host->mrq->stop)
1439                         host->mrq->stop->error = -ENOMEDIUM;
1440                 mmc_request_done(mmc, host->mrq);
1441         }
1442         mutex_unlock(&host->host_mutex);
1443
1444         mmc_remove_host(mmc);
1445         host->eject = true;
1446
1447         flush_work(&host->work);
1448
1449         mmc_free_host(mmc);
1450
1451         dev_dbg(&(pdev->dev),
1452                 ": Realtek PCI-E SDMMC controller has been removed\n");
1453
1454         return 0;
1455 }
1456
1457 static const struct platform_device_id rtsx_pci_sdmmc_ids[] = {
1458         {
1459                 .name = DRV_NAME_RTSX_PCI_SDMMC,
1460         }, {
1461                 /* sentinel */
1462         }
1463 };
1464 MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids);
1465
1466 static struct platform_driver rtsx_pci_sdmmc_driver = {
1467         .probe          = rtsx_pci_sdmmc_drv_probe,
1468         .remove         = rtsx_pci_sdmmc_drv_remove,
1469         .id_table       = rtsx_pci_sdmmc_ids,
1470         .driver         = {
1471                 .name   = DRV_NAME_RTSX_PCI_SDMMC,
1472         },
1473 };
1474 module_platform_driver(rtsx_pci_sdmmc_driver);
1475
1476 MODULE_LICENSE("GPL");
1477 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1478 MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver");