2 * drivers/mmc/host/omap_hsmmc.c
4 * Driver for OMAP2430/3430 MMC controller.
6 * Copyright (C) 2007 Texas Instruments.
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/debugfs.h>
22 #include <linux/dmaengine.h>
23 #include <linux/seq_file.h>
24 #include <linux/sizes.h>
25 #include <linux/interrupt.h>
26 #include <linux/delay.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/platform_device.h>
29 #include <linux/timer.h>
30 #include <linux/clk.h>
32 #include <linux/of_gpio.h>
33 #include <linux/of_device.h>
34 #include <linux/omap-dma.h>
35 #include <linux/mmc/host.h>
36 #include <linux/mmc/core.h>
37 #include <linux/mmc/mmc.h>
39 #include <linux/gpio.h>
40 #include <linux/regulator/consumer.h>
41 #include <linux/pinctrl/consumer.h>
42 #include <linux/pm_runtime.h>
43 #include <linux/platform_data/mmc-omap.h>
45 /* OMAP HSMMC Host Controller Registers */
46 #define OMAP_HSMMC_SYSSTATUS 0x0014
47 #define OMAP_HSMMC_CON 0x002C
48 #define OMAP_HSMMC_SDMASA 0x0100
49 #define OMAP_HSMMC_BLK 0x0104
50 #define OMAP_HSMMC_ARG 0x0108
51 #define OMAP_HSMMC_CMD 0x010C
52 #define OMAP_HSMMC_RSP10 0x0110
53 #define OMAP_HSMMC_RSP32 0x0114
54 #define OMAP_HSMMC_RSP54 0x0118
55 #define OMAP_HSMMC_RSP76 0x011C
56 #define OMAP_HSMMC_DATA 0x0120
57 #define OMAP_HSMMC_HCTL 0x0128
58 #define OMAP_HSMMC_SYSCTL 0x012C
59 #define OMAP_HSMMC_STAT 0x0130
60 #define OMAP_HSMMC_IE 0x0134
61 #define OMAP_HSMMC_ISE 0x0138
62 #define OMAP_HSMMC_AC12 0x013C
63 #define OMAP_HSMMC_CAPA 0x0140
65 #define VS18 (1 << 26)
66 #define VS30 (1 << 25)
68 #define SDVS18 (0x5 << 9)
69 #define SDVS30 (0x6 << 9)
70 #define SDVS33 (0x7 << 9)
71 #define SDVS_MASK 0x00000E00
72 #define SDVSCLR 0xFFFFF1FF
73 #define SDVSDET 0x00000400
80 #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */
81 #define CLKD_MASK 0x0000FFC0
83 #define DTO_MASK 0x000F0000
85 #define INIT_STREAM (1 << 1)
86 #define ACEN_ACMD23 (2 << 2)
87 #define DP_SELECT (1 << 21)
92 #define FOUR_BIT (1 << 1)
97 #define STAT_CLEAR 0xFFFFFFFF
98 #define INIT_STREAM_CMD 0x00000000
99 #define DUAL_VOLT_OCR_BIT 7
100 #define SRC (1 << 25)
101 #define SRD (1 << 26)
102 #define SOFTRESET (1 << 1)
104 /* Interrupt masks for IE and ISE register */
105 #define CC_EN (1 << 0)
106 #define TC_EN (1 << 1)
107 #define BWR_EN (1 << 4)
108 #define BRR_EN (1 << 5)
109 #define ERR_EN (1 << 15)
110 #define CTO_EN (1 << 16)
111 #define CCRC_EN (1 << 17)
112 #define CEB_EN (1 << 18)
113 #define CIE_EN (1 << 19)
114 #define DTO_EN (1 << 20)
115 #define DCRC_EN (1 << 21)
116 #define DEB_EN (1 << 22)
117 #define ACE_EN (1 << 24)
118 #define CERR_EN (1 << 28)
119 #define BADA_EN (1 << 29)
121 #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\
122 DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \
123 BRR_EN | BWR_EN | TC_EN | CC_EN)
126 #define ACIE (1 << 4)
127 #define ACEB (1 << 3)
128 #define ACCE (1 << 2)
129 #define ACTO (1 << 1)
130 #define ACNE (1 << 0)
132 #define MMC_AUTOSUSPEND_DELAY 100
133 #define MMC_TIMEOUT_MS 20 /* 20 mSec */
134 #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */
135 #define OMAP_MMC_MIN_CLOCK 400000
136 #define OMAP_MMC_MAX_CLOCK 52000000
137 #define DRIVER_NAME "omap_hsmmc"
139 #define VDD_1V8 1800000 /* 180000 uV */
140 #define VDD_3V0 3000000 /* 300000 uV */
141 #define VDD_165_195 (ffs(MMC_VDD_165_195) - 1)
143 #define AUTO_CMD23 (1 << 1) /* Auto CMD23 support */
145 * One controller can have multiple slots, like on some omap boards using
146 * omap.c controller driver. Luckily this is not currently done on any known
147 * omap_hsmmc.c device.
149 #define mmc_slot(host) (host->pdata->slots[host->slot_id])
152 * MMC Host controller read/write API's
154 #define OMAP_HSMMC_READ(base, reg) \
155 __raw_readl((base) + OMAP_HSMMC_##reg)
157 #define OMAP_HSMMC_WRITE(base, reg, val) \
158 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
160 struct omap_hsmmc_next {
161 unsigned int dma_len;
165 struct omap_hsmmc_host {
167 struct mmc_host *mmc;
168 struct mmc_request *mrq;
169 struct mmc_command *cmd;
170 struct mmc_data *data;
174 * vcc == configured supply
175 * vcc_aux == optional
176 * - MMC1, supply for DAT4..DAT7
177 * - MMC2/MMC2, external level shifter voltage supply, for
178 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
180 struct regulator *vcc;
181 struct regulator *vcc_aux;
182 struct regulator *pbias;
185 resource_size_t mapbase;
186 spinlock_t irq_lock; /* Prevent races with irq handler */
187 unsigned int dma_len;
188 unsigned int dma_sg_idx;
189 unsigned char bus_mode;
190 unsigned char power_mode;
198 struct dma_chan *tx_chan;
199 struct dma_chan *rx_chan;
207 unsigned long clk_rate;
209 struct omap_hsmmc_next next_data;
210 struct omap_mmc_platform_data *pdata;
213 struct omap_mmc_of_data {
218 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host);
220 static int omap_hsmmc_card_detect(struct device *dev, int slot)
222 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
223 struct omap_mmc_platform_data *mmc = host->pdata;
225 /* NOTE: assumes card detect signal is active-low */
226 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
229 static int omap_hsmmc_get_wp(struct device *dev, int slot)
231 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
232 struct omap_mmc_platform_data *mmc = host->pdata;
234 /* NOTE: assumes write protect signal is active-high */
235 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
238 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
240 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
241 struct omap_mmc_platform_data *mmc = host->pdata;
243 /* NOTE: assumes card detect signal is active-low */
244 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
249 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
251 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
252 struct omap_mmc_platform_data *mmc = host->pdata;
254 disable_irq(mmc->slots[0].card_detect_irq);
258 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
260 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
261 struct omap_mmc_platform_data *mmc = host->pdata;
263 enable_irq(mmc->slots[0].card_detect_irq);
269 #define omap_hsmmc_suspend_cdirq NULL
270 #define omap_hsmmc_resume_cdirq NULL
274 #ifdef CONFIG_REGULATOR
276 static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on,
279 struct omap_hsmmc_host *host =
280 platform_get_drvdata(to_platform_device(dev));
284 * If we don't see a Vcc regulator, assume it's a fixed
285 * voltage always-on regulator.
290 if (mmc_slot(host).before_set_reg)
291 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
294 if (host->pbias_enabled == 1) {
295 ret = regulator_disable(host->pbias);
297 host->pbias_enabled = 0;
299 regulator_set_voltage(host->pbias, VDD_3V0, VDD_3V0);
303 * Assume Vcc regulator is used only to power the card ... OMAP
304 * VDDS is used to power the pins, optionally with a transceiver to
305 * support cards using voltages other than VDDS (1.8V nominal). When a
306 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
308 * In some cases this regulator won't support enable/disable;
309 * e.g. it's a fixed rail for a WLAN chip.
311 * In other cases vcc_aux switches interface power. Example, for
312 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
313 * chips/cards need an interface voltage rail too.
317 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
318 /* Enable interface voltage rail, if needed */
319 if (ret == 0 && host->vcc_aux) {
320 ret = regulator_enable(host->vcc_aux);
321 if (ret < 0 && host->vcc)
322 ret = mmc_regulator_set_ocr(host->mmc,
326 /* Shut down the rail */
328 ret = regulator_disable(host->vcc_aux);
330 /* Then proceed to shut down the local regulator */
331 ret = mmc_regulator_set_ocr(host->mmc,
337 if (vdd <= VDD_165_195)
338 ret = regulator_set_voltage(host->pbias, VDD_1V8,
341 ret = regulator_set_voltage(host->pbias, VDD_3V0,
344 goto error_set_power;
346 if (host->pbias_enabled == 0) {
347 ret = regulator_enable(host->pbias);
349 host->pbias_enabled = 1;
353 if (mmc_slot(host).after_set_reg)
354 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
360 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
362 struct regulator *reg;
365 reg = devm_regulator_get(host->dev, "vmmc");
367 dev_err(host->dev, "unable to get vmmc regulator %ld\n",
372 ocr_value = mmc_regulator_get_ocrmask(reg);
373 if (!mmc_slot(host).ocr_mask) {
374 mmc_slot(host).ocr_mask = ocr_value;
376 if (!(mmc_slot(host).ocr_mask & ocr_value)) {
377 dev_err(host->dev, "ocrmask %x is not supported\n",
378 mmc_slot(host).ocr_mask);
379 mmc_slot(host).ocr_mask = 0;
384 mmc_slot(host).set_power = omap_hsmmc_set_power;
386 /* Allow an aux regulator */
387 reg = devm_regulator_get_optional(host->dev, "vmmc_aux");
388 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
390 reg = devm_regulator_get_optional(host->dev, "pbias");
391 host->pbias = IS_ERR(reg) ? NULL : reg;
393 /* For eMMC do not power off when not in sleep state */
394 if (mmc_slot(host).no_regulator_off_init)
397 * To disable boot_on regulator, enable regulator
398 * to increase usecount and then disable it.
400 if ((host->vcc && regulator_is_enabled(host->vcc) > 0) ||
401 (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
402 int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
404 mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
405 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
411 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
413 mmc_slot(host).set_power = NULL;
416 static inline int omap_hsmmc_have_reg(void)
423 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
428 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
432 static inline int omap_hsmmc_have_reg(void)
439 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
443 if (gpio_is_valid(pdata->slots[0].switch_pin)) {
444 if (pdata->slots[0].cover)
445 pdata->slots[0].get_cover_state =
446 omap_hsmmc_get_cover_state;
448 pdata->slots[0].card_detect = omap_hsmmc_card_detect;
449 pdata->slots[0].card_detect_irq =
450 gpio_to_irq(pdata->slots[0].switch_pin);
451 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
454 ret = gpio_direction_input(pdata->slots[0].switch_pin);
458 pdata->slots[0].switch_pin = -EINVAL;
460 if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
461 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
462 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
465 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
469 pdata->slots[0].gpio_wp = -EINVAL;
474 gpio_free(pdata->slots[0].gpio_wp);
476 if (gpio_is_valid(pdata->slots[0].switch_pin))
478 gpio_free(pdata->slots[0].switch_pin);
482 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
484 if (gpio_is_valid(pdata->slots[0].gpio_wp))
485 gpio_free(pdata->slots[0].gpio_wp);
486 if (gpio_is_valid(pdata->slots[0].switch_pin))
487 gpio_free(pdata->slots[0].switch_pin);
491 * Start clock to the card
493 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
495 OMAP_HSMMC_WRITE(host->base, SYSCTL,
496 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
500 * Stop clock to the card
502 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
504 OMAP_HSMMC_WRITE(host->base, SYSCTL,
505 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
506 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
507 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
510 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
511 struct mmc_command *cmd)
513 unsigned int irq_mask;
516 irq_mask = INT_EN_MASK & ~(BRR_EN | BWR_EN);
518 irq_mask = INT_EN_MASK;
520 /* Disable timeout for erases */
521 if (cmd->opcode == MMC_ERASE)
524 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
525 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
526 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
529 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
531 OMAP_HSMMC_WRITE(host->base, ISE, 0);
532 OMAP_HSMMC_WRITE(host->base, IE, 0);
533 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
536 /* Calculate divisor for the given clock frequency */
537 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
542 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
550 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
552 struct mmc_ios *ios = &host->mmc->ios;
553 unsigned long regval;
554 unsigned long timeout;
555 unsigned long clkdiv;
557 dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
559 omap_hsmmc_stop_clock(host);
561 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
562 regval = regval & ~(CLKD_MASK | DTO_MASK);
563 clkdiv = calc_divisor(host, ios);
564 regval = regval | (clkdiv << 6) | (DTO << 16);
565 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
566 OMAP_HSMMC_WRITE(host->base, SYSCTL,
567 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
569 /* Wait till the ICS bit is set */
570 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
571 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
572 && time_before(jiffies, timeout))
576 * Enable High-Speed Support
578 * - Controller should support High-Speed-Enable Bit
579 * - Controller should not be using DDR Mode
580 * - Controller should advertise that it supports High Speed
581 * in capabilities register
582 * - MMC/SD clock coming out of controller > 25MHz
584 if ((mmc_slot(host).features & HSMMC_HAS_HSPE_SUPPORT) &&
585 (ios->timing != MMC_TIMING_MMC_DDR52) &&
586 ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
587 regval = OMAP_HSMMC_READ(host->base, HCTL);
588 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
593 OMAP_HSMMC_WRITE(host->base, HCTL, regval);
596 omap_hsmmc_start_clock(host);
599 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
601 struct mmc_ios *ios = &host->mmc->ios;
604 con = OMAP_HSMMC_READ(host->base, CON);
605 if (ios->timing == MMC_TIMING_MMC_DDR52)
606 con |= DDR; /* configure in DDR mode */
609 switch (ios->bus_width) {
610 case MMC_BUS_WIDTH_8:
611 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
613 case MMC_BUS_WIDTH_4:
614 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
615 OMAP_HSMMC_WRITE(host->base, HCTL,
616 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
618 case MMC_BUS_WIDTH_1:
619 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
620 OMAP_HSMMC_WRITE(host->base, HCTL,
621 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
626 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
628 struct mmc_ios *ios = &host->mmc->ios;
631 con = OMAP_HSMMC_READ(host->base, CON);
632 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
633 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
635 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
641 * Restore the MMC host context, if it was lost as result of a
642 * power state change.
644 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
646 struct mmc_ios *ios = &host->mmc->ios;
648 unsigned long timeout;
650 if (host->con == OMAP_HSMMC_READ(host->base, CON) &&
651 host->hctl == OMAP_HSMMC_READ(host->base, HCTL) &&
652 host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) &&
653 host->capa == OMAP_HSMMC_READ(host->base, CAPA))
656 host->context_loss++;
658 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
659 if (host->power_mode != MMC_POWER_OFF &&
660 (1 << ios->vdd) <= MMC_VDD_23_24)
670 OMAP_HSMMC_WRITE(host->base, HCTL,
671 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
673 OMAP_HSMMC_WRITE(host->base, CAPA,
674 OMAP_HSMMC_READ(host->base, CAPA) | capa);
676 OMAP_HSMMC_WRITE(host->base, HCTL,
677 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
679 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
680 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
681 && time_before(jiffies, timeout))
684 omap_hsmmc_disable_irq(host);
686 /* Do not initialize card-specific things if the power is off */
687 if (host->power_mode == MMC_POWER_OFF)
690 omap_hsmmc_set_bus_width(host);
692 omap_hsmmc_set_clock(host);
694 omap_hsmmc_set_bus_mode(host);
697 dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n",
703 * Save the MMC host context (store the number of power state changes so far).
705 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
707 host->con = OMAP_HSMMC_READ(host->base, CON);
708 host->hctl = OMAP_HSMMC_READ(host->base, HCTL);
709 host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL);
710 host->capa = OMAP_HSMMC_READ(host->base, CAPA);
715 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
720 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
727 * Send init stream sequence to card
728 * before sending IDLE command
730 static void send_init_stream(struct omap_hsmmc_host *host)
733 unsigned long timeout;
735 if (host->protect_card)
738 disable_irq(host->irq);
740 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
741 OMAP_HSMMC_WRITE(host->base, CON,
742 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
743 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
745 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
746 while ((reg != CC_EN) && time_before(jiffies, timeout))
747 reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN;
749 OMAP_HSMMC_WRITE(host->base, CON,
750 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
752 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
753 OMAP_HSMMC_READ(host->base, STAT);
755 enable_irq(host->irq);
759 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
763 if (mmc_slot(host).get_cover_state)
764 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
769 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
772 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
773 struct omap_hsmmc_host *host = mmc_priv(mmc);
775 return sprintf(buf, "%s\n",
776 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
779 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
782 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
785 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
786 struct omap_hsmmc_host *host = mmc_priv(mmc);
788 return sprintf(buf, "%s\n", mmc_slot(host).name);
791 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
794 * Configure the response type and send the cmd.
797 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
798 struct mmc_data *data)
800 int cmdreg = 0, resptype = 0, cmdtype = 0;
802 dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
803 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
806 omap_hsmmc_enable_irq(host, cmd);
808 host->response_busy = 0;
809 if (cmd->flags & MMC_RSP_PRESENT) {
810 if (cmd->flags & MMC_RSP_136)
812 else if (cmd->flags & MMC_RSP_BUSY) {
814 host->response_busy = 1;
820 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
821 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
822 * a val of 0x3, rest 0x0.
824 if (cmd == host->mrq->stop)
827 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
829 if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) &&
831 cmdreg |= ACEN_ACMD23;
832 OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg);
835 cmdreg |= DP_SELECT | MSBS | BCE;
836 if (data->flags & MMC_DATA_READ)
845 host->req_in_progress = 1;
847 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
848 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
852 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
854 if (data->flags & MMC_DATA_WRITE)
855 return DMA_TO_DEVICE;
857 return DMA_FROM_DEVICE;
860 static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
861 struct mmc_data *data)
863 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
866 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
871 spin_lock_irqsave(&host->irq_lock, flags);
872 host->req_in_progress = 0;
873 dma_ch = host->dma_ch;
874 spin_unlock_irqrestore(&host->irq_lock, flags);
876 omap_hsmmc_disable_irq(host);
877 /* Do not complete the request if DMA is still in progress */
878 if (mrq->data && host->use_dma && dma_ch != -1)
881 mmc_request_done(host->mmc, mrq);
885 * Notify the transfer complete to MMC core
888 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
891 struct mmc_request *mrq = host->mrq;
893 /* TC before CC from CMD6 - don't know why, but it happens */
894 if (host->cmd && host->cmd->opcode == 6 &&
895 host->response_busy) {
896 host->response_busy = 0;
900 omap_hsmmc_request_done(host, mrq);
907 data->bytes_xfered += data->blocks * (data->blksz);
909 data->bytes_xfered = 0;
911 if (data->stop && (data->error || !host->mrq->sbc))
912 omap_hsmmc_start_command(host, data->stop, NULL);
914 omap_hsmmc_request_done(host, data->mrq);
918 * Notify the core about command completion
921 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
923 if (host->mrq->sbc && (host->cmd == host->mrq->sbc) &&
924 !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) {
926 omap_hsmmc_start_dma_transfer(host);
927 omap_hsmmc_start_command(host, host->mrq->cmd,
934 if (cmd->flags & MMC_RSP_PRESENT) {
935 if (cmd->flags & MMC_RSP_136) {
936 /* response type 2 */
937 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
938 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
939 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
940 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
942 /* response types 1, 1b, 3, 4, 5, 6 */
943 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
946 if ((host->data == NULL && !host->response_busy) || cmd->error)
947 omap_hsmmc_request_done(host, host->mrq);
951 * DMA clean up for command errors
953 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
958 host->data->error = errno;
960 spin_lock_irqsave(&host->irq_lock, flags);
961 dma_ch = host->dma_ch;
963 spin_unlock_irqrestore(&host->irq_lock, flags);
965 if (host->use_dma && dma_ch != -1) {
966 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
968 dmaengine_terminate_all(chan);
969 dma_unmap_sg(chan->device->dev,
970 host->data->sg, host->data->sg_len,
971 omap_hsmmc_get_dma_dir(host, host->data));
973 host->data->host_cookie = 0;
979 * Readable error output
981 #ifdef CONFIG_MMC_DEBUG
982 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
984 /* --- means reserved bit without definition at documentation */
985 static const char *omap_hsmmc_status_bits[] = {
986 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
987 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
988 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
989 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
995 len = sprintf(buf, "MMC IRQ 0x%x :", status);
998 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
999 if (status & (1 << i)) {
1000 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
1004 dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
1007 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
1011 #endif /* CONFIG_MMC_DEBUG */
1014 * MMC controller internal state machines reset
1016 * Used to reset command or data internal state machines, using respectively
1017 * SRC or SRD bit of SYSCTL register
1018 * Can be called from interrupt context
1020 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1023 unsigned long i = 0;
1024 unsigned long limit = MMC_TIMEOUT_US;
1026 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1027 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1030 * OMAP4 ES2 and greater has an updated reset logic.
1031 * Monitor a 0->1 transition first
1033 if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
1034 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
1040 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1044 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1045 dev_err(mmc_dev(host->mmc),
1046 "Timeout waiting on controller reset in %s\n",
1050 static void hsmmc_command_incomplete(struct omap_hsmmc_host *host,
1051 int err, int end_cmd)
1054 omap_hsmmc_reset_controller_fsm(host, SRC);
1056 host->cmd->error = err;
1060 omap_hsmmc_reset_controller_fsm(host, SRD);
1061 omap_hsmmc_dma_cleanup(host, err);
1062 } else if (host->mrq && host->mrq->cmd)
1063 host->mrq->cmd->error = err;
1066 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1068 struct mmc_data *data;
1069 int end_cmd = 0, end_trans = 0;
1073 dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1075 if (status & ERR_EN) {
1076 omap_hsmmc_dbg_report_irq(host, status);
1078 if (status & (CTO_EN | CCRC_EN))
1080 if (status & (CTO_EN | DTO_EN))
1081 hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
1082 else if (status & (CCRC_EN | DCRC_EN))
1083 hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
1085 if (status & ACE_EN) {
1087 ac12 = OMAP_HSMMC_READ(host->base, AC12);
1088 if (!(ac12 & ACNE) && host->mrq->sbc) {
1092 else if (ac12 & (ACCE | ACEB | ACIE))
1094 host->mrq->sbc->error = error;
1095 hsmmc_command_incomplete(host, error, end_cmd);
1097 dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12);
1099 if (host->data || host->response_busy) {
1100 end_trans = !end_cmd;
1101 host->response_busy = 0;
1105 OMAP_HSMMC_WRITE(host->base, STAT, status);
1106 if (end_cmd || ((status & CC_EN) && host->cmd))
1107 omap_hsmmc_cmd_done(host, host->cmd);
1108 if ((end_trans || (status & TC_EN)) && host->mrq)
1109 omap_hsmmc_xfer_done(host, data);
1113 * MMC controller IRQ handler
1115 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1117 struct omap_hsmmc_host *host = dev_id;
1120 status = OMAP_HSMMC_READ(host->base, STAT);
1121 while (status & INT_EN_MASK && host->req_in_progress) {
1122 omap_hsmmc_do_irq(host, status);
1124 /* Flush posted write */
1125 status = OMAP_HSMMC_READ(host->base, STAT);
1131 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1135 OMAP_HSMMC_WRITE(host->base, HCTL,
1136 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1137 for (i = 0; i < loops_per_jiffy; i++) {
1138 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1145 * Switch MMC interface voltage ... only relevant for MMC1.
1147 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1148 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1149 * Some chips, like eMMC ones, use internal transceivers.
1151 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1156 /* Disable the clocks */
1157 pm_runtime_put_sync(host->dev);
1159 clk_disable_unprepare(host->dbclk);
1161 /* Turn the power off */
1162 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1164 /* Turn the power ON with given VDD 1.8 or 3.0v */
1166 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1168 pm_runtime_get_sync(host->dev);
1170 clk_prepare_enable(host->dbclk);
1175 OMAP_HSMMC_WRITE(host->base, HCTL,
1176 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1177 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1180 * If a MMC dual voltage card is detected, the set_ios fn calls
1181 * this fn with VDD bit set for 1.8V. Upon card removal from the
1182 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1184 * Cope with a bit of slop in the range ... per data sheets:
1185 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1186 * but recommended values are 1.71V to 1.89V
1187 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1188 * but recommended values are 2.7V to 3.3V
1190 * Board setup code shouldn't permit anything very out-of-range.
1191 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1192 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1194 if ((1 << vdd) <= MMC_VDD_23_24)
1199 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1200 set_sd_bus_power(host);
1204 dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1208 /* Protect the card while the cover is open */
1209 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1211 if (!mmc_slot(host).get_cover_state)
1214 host->reqs_blocked = 0;
1215 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1216 if (host->protect_card) {
1217 dev_info(host->dev, "%s: cover is closed, "
1218 "card is now accessible\n",
1219 mmc_hostname(host->mmc));
1220 host->protect_card = 0;
1223 if (!host->protect_card) {
1224 dev_info(host->dev, "%s: cover is open, "
1225 "card is now inaccessible\n",
1226 mmc_hostname(host->mmc));
1227 host->protect_card = 1;
1233 * irq handler to notify the core about card insertion/removal
1235 static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
1237 struct omap_hsmmc_host *host = dev_id;
1238 struct omap_mmc_slot_data *slot = &mmc_slot(host);
1241 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1243 if (slot->card_detect)
1244 carddetect = slot->card_detect(host->dev, host->slot_id);
1246 omap_hsmmc_protect_card(host);
1247 carddetect = -ENOSYS;
1251 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1253 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1257 static void omap_hsmmc_dma_callback(void *param)
1259 struct omap_hsmmc_host *host = param;
1260 struct dma_chan *chan;
1261 struct mmc_data *data;
1262 int req_in_progress;
1264 spin_lock_irq(&host->irq_lock);
1265 if (host->dma_ch < 0) {
1266 spin_unlock_irq(&host->irq_lock);
1270 data = host->mrq->data;
1271 chan = omap_hsmmc_get_dma_chan(host, data);
1272 if (!data->host_cookie)
1273 dma_unmap_sg(chan->device->dev,
1274 data->sg, data->sg_len,
1275 omap_hsmmc_get_dma_dir(host, data));
1277 req_in_progress = host->req_in_progress;
1279 spin_unlock_irq(&host->irq_lock);
1281 /* If DMA has finished after TC, complete the request */
1282 if (!req_in_progress) {
1283 struct mmc_request *mrq = host->mrq;
1286 mmc_request_done(host->mmc, mrq);
1290 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1291 struct mmc_data *data,
1292 struct omap_hsmmc_next *next,
1293 struct dma_chan *chan)
1297 if (!next && data->host_cookie &&
1298 data->host_cookie != host->next_data.cookie) {
1299 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
1300 " host->next_data.cookie %d\n",
1301 __func__, data->host_cookie, host->next_data.cookie);
1302 data->host_cookie = 0;
1305 /* Check if next job is already prepared */
1306 if (next || data->host_cookie != host->next_data.cookie) {
1307 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
1308 omap_hsmmc_get_dma_dir(host, data));
1311 dma_len = host->next_data.dma_len;
1312 host->next_data.dma_len = 0;
1320 next->dma_len = dma_len;
1321 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1323 host->dma_len = dma_len;
1329 * Routine to configure and start DMA for the MMC card
1331 static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host,
1332 struct mmc_request *req)
1334 struct dma_slave_config cfg;
1335 struct dma_async_tx_descriptor *tx;
1337 struct mmc_data *data = req->data;
1338 struct dma_chan *chan;
1340 /* Sanity check: all the SG entries must be aligned by block size. */
1341 for (i = 0; i < data->sg_len; i++) {
1342 struct scatterlist *sgl;
1345 if (sgl->length % data->blksz)
1348 if ((data->blksz % 4) != 0)
1349 /* REVISIT: The MMC buffer increments only when MSB is written.
1350 * Return error for blksz which is non multiple of four.
1354 BUG_ON(host->dma_ch != -1);
1356 chan = omap_hsmmc_get_dma_chan(host, data);
1358 cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA;
1359 cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA;
1360 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1361 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1362 cfg.src_maxburst = data->blksz / 4;
1363 cfg.dst_maxburst = data->blksz / 4;
1365 ret = dmaengine_slave_config(chan, &cfg);
1369 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
1373 tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
1374 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1375 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1377 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
1378 /* FIXME: cleanup */
1382 tx->callback = omap_hsmmc_dma_callback;
1383 tx->callback_param = host;
1386 dmaengine_submit(tx);
1393 static void set_data_timeout(struct omap_hsmmc_host *host,
1394 unsigned int timeout_ns,
1395 unsigned int timeout_clks)
1397 unsigned int timeout, cycle_ns;
1398 uint32_t reg, clkd, dto = 0;
1400 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1401 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1405 cycle_ns = 1000000000 / (host->clk_rate / clkd);
1406 timeout = timeout_ns / cycle_ns;
1407 timeout += timeout_clks;
1409 while ((timeout & 0x80000000) == 0) {
1426 reg |= dto << DTO_SHIFT;
1427 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1430 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host)
1432 struct mmc_request *req = host->mrq;
1433 struct dma_chan *chan;
1437 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1438 | (req->data->blocks << 16));
1439 set_data_timeout(host, req->data->timeout_ns,
1440 req->data->timeout_clks);
1441 chan = omap_hsmmc_get_dma_chan(host, req->data);
1442 dma_async_issue_pending(chan);
1446 * Configure block length for MMC/SD cards and initiate the transfer.
1449 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1452 host->data = req->data;
1454 if (req->data == NULL) {
1455 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1457 * Set an arbitrary 100ms data timeout for commands with
1460 if (req->cmd->flags & MMC_RSP_BUSY)
1461 set_data_timeout(host, 100000000U, 0);
1465 if (host->use_dma) {
1466 ret = omap_hsmmc_setup_dma_transfer(host, req);
1468 dev_err(mmc_dev(host->mmc), "MMC start dma failure\n");
1475 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1478 struct omap_hsmmc_host *host = mmc_priv(mmc);
1479 struct mmc_data *data = mrq->data;
1481 if (host->use_dma && data->host_cookie) {
1482 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
1484 dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
1485 omap_hsmmc_get_dma_dir(host, data));
1486 data->host_cookie = 0;
1490 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1493 struct omap_hsmmc_host *host = mmc_priv(mmc);
1495 if (mrq->data->host_cookie) {
1496 mrq->data->host_cookie = 0;
1500 if (host->use_dma) {
1501 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
1503 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1504 &host->next_data, c))
1505 mrq->data->host_cookie = 0;
1510 * Request function. for read/write operation
1512 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1514 struct omap_hsmmc_host *host = mmc_priv(mmc);
1517 BUG_ON(host->req_in_progress);
1518 BUG_ON(host->dma_ch != -1);
1519 if (host->protect_card) {
1520 if (host->reqs_blocked < 3) {
1522 * Ensure the controller is left in a consistent
1523 * state by resetting the command and data state
1526 omap_hsmmc_reset_controller_fsm(host, SRD);
1527 omap_hsmmc_reset_controller_fsm(host, SRC);
1528 host->reqs_blocked += 1;
1530 req->cmd->error = -EBADF;
1532 req->data->error = -EBADF;
1533 req->cmd->retries = 0;
1534 mmc_request_done(mmc, req);
1536 } else if (host->reqs_blocked)
1537 host->reqs_blocked = 0;
1538 WARN_ON(host->mrq != NULL);
1540 host->clk_rate = clk_get_rate(host->fclk);
1541 err = omap_hsmmc_prepare_data(host, req);
1543 req->cmd->error = err;
1545 req->data->error = err;
1547 mmc_request_done(mmc, req);
1550 if (req->sbc && !(host->flags & AUTO_CMD23)) {
1551 omap_hsmmc_start_command(host, req->sbc, NULL);
1555 omap_hsmmc_start_dma_transfer(host);
1556 omap_hsmmc_start_command(host, req->cmd, req->data);
1559 /* Routine to configure clock values. Exposed API to core */
1560 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1562 struct omap_hsmmc_host *host = mmc_priv(mmc);
1563 int do_send_init_stream = 0;
1565 pm_runtime_get_sync(host->dev);
1567 if (ios->power_mode != host->power_mode) {
1568 switch (ios->power_mode) {
1570 mmc_slot(host).set_power(host->dev, host->slot_id,
1574 mmc_slot(host).set_power(host->dev, host->slot_id,
1578 do_send_init_stream = 1;
1581 host->power_mode = ios->power_mode;
1584 /* FIXME: set registers based only on changes to ios */
1586 omap_hsmmc_set_bus_width(host);
1588 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1589 /* Only MMC1 can interface at 3V without some flavor
1590 * of external transceiver; but they all handle 1.8V.
1592 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1593 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1595 * The mmc_select_voltage fn of the core does
1596 * not seem to set the power_mode to
1597 * MMC_POWER_UP upon recalculating the voltage.
1600 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1601 dev_dbg(mmc_dev(host->mmc),
1602 "Switch operation failed\n");
1606 omap_hsmmc_set_clock(host);
1608 if (do_send_init_stream)
1609 send_init_stream(host);
1611 omap_hsmmc_set_bus_mode(host);
1613 pm_runtime_put_autosuspend(host->dev);
1616 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1618 struct omap_hsmmc_host *host = mmc_priv(mmc);
1620 if (!mmc_slot(host).card_detect)
1622 return mmc_slot(host).card_detect(host->dev, host->slot_id);
1625 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1627 struct omap_hsmmc_host *host = mmc_priv(mmc);
1629 if (!mmc_slot(host).get_ro)
1631 return mmc_slot(host).get_ro(host->dev, 0);
1634 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1636 struct omap_hsmmc_host *host = mmc_priv(mmc);
1638 if (mmc_slot(host).init_card)
1639 mmc_slot(host).init_card(card);
1642 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1644 u32 hctl, capa, value;
1646 /* Only MMC1 supports 3.0V */
1647 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1655 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1656 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1658 value = OMAP_HSMMC_READ(host->base, CAPA);
1659 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1661 /* Set SD bus power bit */
1662 set_sd_bus_power(host);
1665 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1667 struct omap_hsmmc_host *host = mmc_priv(mmc);
1669 pm_runtime_get_sync(host->dev);
1674 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc)
1676 struct omap_hsmmc_host *host = mmc_priv(mmc);
1678 pm_runtime_mark_last_busy(host->dev);
1679 pm_runtime_put_autosuspend(host->dev);
1684 static const struct mmc_host_ops omap_hsmmc_ops = {
1685 .enable = omap_hsmmc_enable_fclk,
1686 .disable = omap_hsmmc_disable_fclk,
1687 .post_req = omap_hsmmc_post_req,
1688 .pre_req = omap_hsmmc_pre_req,
1689 .request = omap_hsmmc_request,
1690 .set_ios = omap_hsmmc_set_ios,
1691 .get_cd = omap_hsmmc_get_cd,
1692 .get_ro = omap_hsmmc_get_ro,
1693 .init_card = omap_hsmmc_init_card,
1694 /* NYET -- enable_sdio_irq */
1697 #ifdef CONFIG_DEBUG_FS
1699 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1701 struct mmc_host *mmc = s->private;
1702 struct omap_hsmmc_host *host = mmc_priv(mmc);
1704 seq_printf(s, "mmc%d:\n ctx_loss:\t%d\n\nregs:\n",
1705 mmc->index, host->context_loss);
1707 pm_runtime_get_sync(host->dev);
1709 seq_printf(s, "CON:\t\t0x%08x\n",
1710 OMAP_HSMMC_READ(host->base, CON));
1711 seq_printf(s, "HCTL:\t\t0x%08x\n",
1712 OMAP_HSMMC_READ(host->base, HCTL));
1713 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1714 OMAP_HSMMC_READ(host->base, SYSCTL));
1715 seq_printf(s, "IE:\t\t0x%08x\n",
1716 OMAP_HSMMC_READ(host->base, IE));
1717 seq_printf(s, "ISE:\t\t0x%08x\n",
1718 OMAP_HSMMC_READ(host->base, ISE));
1719 seq_printf(s, "CAPA:\t\t0x%08x\n",
1720 OMAP_HSMMC_READ(host->base, CAPA));
1722 pm_runtime_mark_last_busy(host->dev);
1723 pm_runtime_put_autosuspend(host->dev);
1728 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1730 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1733 static const struct file_operations mmc_regs_fops = {
1734 .open = omap_hsmmc_regs_open,
1736 .llseek = seq_lseek,
1737 .release = single_release,
1740 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1742 if (mmc->debugfs_root)
1743 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1744 mmc, &mmc_regs_fops);
1749 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1756 static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = {
1757 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1758 .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1761 static const struct omap_mmc_of_data omap4_mmc_of_data = {
1762 .reg_offset = 0x100,
1765 static const struct of_device_id omap_mmc_of_match[] = {
1767 .compatible = "ti,omap2-hsmmc",
1770 .compatible = "ti,omap3-pre-es3-hsmmc",
1771 .data = &omap3_pre_es3_mmc_of_data,
1774 .compatible = "ti,omap3-hsmmc",
1777 .compatible = "ti,omap4-hsmmc",
1778 .data = &omap4_mmc_of_data,
1782 MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1784 static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1786 struct omap_mmc_platform_data *pdata;
1787 struct device_node *np = dev->of_node;
1788 u32 bus_width, max_freq;
1789 int cd_gpio, wp_gpio;
1791 cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
1792 wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
1793 if (cd_gpio == -EPROBE_DEFER || wp_gpio == -EPROBE_DEFER)
1794 return ERR_PTR(-EPROBE_DEFER);
1796 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1798 return ERR_PTR(-ENOMEM); /* out of memory */
1800 if (of_find_property(np, "ti,dual-volt", NULL))
1801 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1803 /* This driver only supports 1 slot */
1804 pdata->nr_slots = 1;
1805 pdata->slots[0].switch_pin = cd_gpio;
1806 pdata->slots[0].gpio_wp = wp_gpio;
1808 if (of_find_property(np, "ti,non-removable", NULL)) {
1809 pdata->slots[0].nonremovable = true;
1810 pdata->slots[0].no_regulator_off_init = true;
1812 of_property_read_u32(np, "bus-width", &bus_width);
1814 pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA;
1815 else if (bus_width == 8)
1816 pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA;
1818 if (of_find_property(np, "ti,needs-special-reset", NULL))
1819 pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
1821 if (!of_property_read_u32(np, "max-frequency", &max_freq))
1822 pdata->max_freq = max_freq;
1824 if (of_find_property(np, "ti,needs-special-hs-handling", NULL))
1825 pdata->slots[0].features |= HSMMC_HAS_HSPE_SUPPORT;
1827 if (of_find_property(np, "keep-power-in-suspend", NULL))
1828 pdata->slots[0].pm_caps |= MMC_PM_KEEP_POWER;
1830 if (of_find_property(np, "enable-sdio-wakeup", NULL))
1831 pdata->slots[0].pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
1836 static inline struct omap_mmc_platform_data
1837 *of_get_hsmmc_pdata(struct device *dev)
1839 return ERR_PTR(-EINVAL);
1843 static int omap_hsmmc_probe(struct platform_device *pdev)
1845 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1846 struct mmc_host *mmc;
1847 struct omap_hsmmc_host *host = NULL;
1848 struct resource *res;
1850 const struct of_device_id *match;
1851 dma_cap_mask_t mask;
1852 unsigned tx_req, rx_req;
1853 struct pinctrl *pinctrl;
1854 const struct omap_mmc_of_data *data;
1857 match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
1859 pdata = of_get_hsmmc_pdata(&pdev->dev);
1862 return PTR_ERR(pdata);
1866 pdata->reg_offset = data->reg_offset;
1867 pdata->controller_flags |= data->controller_flags;
1871 if (pdata == NULL) {
1872 dev_err(&pdev->dev, "Platform Data is missing\n");
1876 if (pdata->nr_slots == 0) {
1877 dev_err(&pdev->dev, "No Slots\n");
1881 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1882 irq = platform_get_irq(pdev, 0);
1883 if (res == NULL || irq < 0)
1886 base = devm_ioremap_resource(&pdev->dev, res);
1888 return PTR_ERR(base);
1890 ret = omap_hsmmc_gpio_init(pdata);
1894 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1900 host = mmc_priv(mmc);
1902 host->pdata = pdata;
1903 host->dev = &pdev->dev;
1908 host->mapbase = res->start + pdata->reg_offset;
1909 host->base = base + pdata->reg_offset;
1910 host->power_mode = MMC_POWER_OFF;
1911 host->next_data.cookie = 1;
1912 host->pbias_enabled = 0;
1914 platform_set_drvdata(pdev, host);
1916 mmc->ops = &omap_hsmmc_ops;
1918 mmc->f_min = OMAP_MMC_MIN_CLOCK;
1920 if (pdata->max_freq > 0)
1921 mmc->f_max = pdata->max_freq;
1923 mmc->f_max = OMAP_MMC_MAX_CLOCK;
1925 spin_lock_init(&host->irq_lock);
1927 host->fclk = devm_clk_get(&pdev->dev, "fck");
1928 if (IS_ERR(host->fclk)) {
1929 ret = PTR_ERR(host->fclk);
1934 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
1935 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
1936 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
1939 pm_runtime_enable(host->dev);
1940 pm_runtime_get_sync(host->dev);
1941 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1942 pm_runtime_use_autosuspend(host->dev);
1944 omap_hsmmc_context_save(host);
1946 host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck");
1948 * MMC can still work without debounce clock.
1950 if (IS_ERR(host->dbclk)) {
1952 } else if (clk_prepare_enable(host->dbclk) != 0) {
1953 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
1957 /* Since we do only SG emulation, we can have as many segs
1959 mmc->max_segs = 1024;
1961 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1962 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1963 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1964 mmc->max_seg_size = mmc->max_req_size;
1966 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1967 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
1969 mmc->caps |= mmc_slot(host).caps;
1970 if (mmc->caps & MMC_CAP_8_BIT_DATA)
1971 mmc->caps |= MMC_CAP_4_BIT_DATA;
1973 if (mmc_slot(host).nonremovable)
1974 mmc->caps |= MMC_CAP_NONREMOVABLE;
1976 mmc->pm_caps = mmc_slot(host).pm_caps;
1978 omap_hsmmc_conf_bus_power(host);
1980 if (!pdev->dev.of_node) {
1981 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1983 dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
1987 tx_req = res->start;
1989 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1991 dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
1995 rx_req = res->start;
1999 dma_cap_set(DMA_SLAVE, mask);
2002 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
2003 &rx_req, &pdev->dev, "rx");
2005 if (!host->rx_chan) {
2006 dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req);
2012 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
2013 &tx_req, &pdev->dev, "tx");
2015 if (!host->tx_chan) {
2016 dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req);
2021 /* Request IRQ for MMC operations */
2022 ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0,
2023 mmc_hostname(mmc), host);
2025 dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2029 if (pdata->init != NULL) {
2030 if (pdata->init(&pdev->dev) != 0) {
2031 dev_err(mmc_dev(host->mmc),
2032 "Unable to configure MMC IRQs\n");
2037 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
2038 ret = omap_hsmmc_reg_get(host);
2044 mmc->ocr_avail = mmc_slot(host).ocr_mask;
2046 /* Request IRQ for card detect */
2047 if ((mmc_slot(host).card_detect_irq)) {
2048 ret = devm_request_threaded_irq(&pdev->dev,
2049 mmc_slot(host).card_detect_irq,
2050 NULL, omap_hsmmc_detect,
2051 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
2052 mmc_hostname(mmc), host);
2054 dev_err(mmc_dev(host->mmc),
2055 "Unable to grab MMC CD IRQ\n");
2058 pdata->suspend = omap_hsmmc_suspend_cdirq;
2059 pdata->resume = omap_hsmmc_resume_cdirq;
2062 omap_hsmmc_disable_irq(host);
2064 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
2065 if (IS_ERR(pinctrl))
2066 dev_warn(&pdev->dev,
2067 "pins are not configured from the driver\n");
2069 omap_hsmmc_protect_card(host);
2073 if (mmc_slot(host).name != NULL) {
2074 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2078 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
2079 ret = device_create_file(&mmc->class_dev,
2080 &dev_attr_cover_switch);
2085 omap_hsmmc_debugfs(mmc);
2086 pm_runtime_mark_last_busy(host->dev);
2087 pm_runtime_put_autosuspend(host->dev);
2092 mmc_remove_host(mmc);
2095 omap_hsmmc_reg_put(host);
2097 if (host->pdata->cleanup)
2098 host->pdata->cleanup(&pdev->dev);
2101 dma_release_channel(host->tx_chan);
2103 dma_release_channel(host->rx_chan);
2104 pm_runtime_put_sync(host->dev);
2105 pm_runtime_disable(host->dev);
2107 clk_disable_unprepare(host->dbclk);
2111 omap_hsmmc_gpio_free(pdata);
2116 static int omap_hsmmc_remove(struct platform_device *pdev)
2118 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2120 pm_runtime_get_sync(host->dev);
2121 mmc_remove_host(host->mmc);
2123 omap_hsmmc_reg_put(host);
2124 if (host->pdata->cleanup)
2125 host->pdata->cleanup(&pdev->dev);
2128 dma_release_channel(host->tx_chan);
2130 dma_release_channel(host->rx_chan);
2132 pm_runtime_put_sync(host->dev);
2133 pm_runtime_disable(host->dev);
2135 clk_disable_unprepare(host->dbclk);
2137 omap_hsmmc_gpio_free(host->pdata);
2138 mmc_free_host(host->mmc);
2144 static int omap_hsmmc_prepare(struct device *dev)
2146 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2148 if (host->pdata->suspend)
2149 return host->pdata->suspend(dev, host->slot_id);
2154 static void omap_hsmmc_complete(struct device *dev)
2156 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2158 if (host->pdata->resume)
2159 host->pdata->resume(dev, host->slot_id);
2163 static int omap_hsmmc_suspend(struct device *dev)
2165 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2170 pm_runtime_get_sync(host->dev);
2172 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2173 omap_hsmmc_disable_irq(host);
2174 OMAP_HSMMC_WRITE(host->base, HCTL,
2175 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2179 clk_disable_unprepare(host->dbclk);
2181 pm_runtime_put_sync(host->dev);
2185 /* Routine to resume the MMC device */
2186 static int omap_hsmmc_resume(struct device *dev)
2188 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2193 pm_runtime_get_sync(host->dev);
2196 clk_prepare_enable(host->dbclk);
2198 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2199 omap_hsmmc_conf_bus_power(host);
2201 omap_hsmmc_protect_card(host);
2203 pm_runtime_mark_last_busy(host->dev);
2204 pm_runtime_put_autosuspend(host->dev);
2209 #define omap_hsmmc_prepare NULL
2210 #define omap_hsmmc_complete NULL
2211 #define omap_hsmmc_suspend NULL
2212 #define omap_hsmmc_resume NULL
2215 static int omap_hsmmc_runtime_suspend(struct device *dev)
2217 struct omap_hsmmc_host *host;
2219 host = platform_get_drvdata(to_platform_device(dev));
2220 omap_hsmmc_context_save(host);
2221 dev_dbg(dev, "disabled\n");
2226 static int omap_hsmmc_runtime_resume(struct device *dev)
2228 struct omap_hsmmc_host *host;
2230 host = platform_get_drvdata(to_platform_device(dev));
2231 omap_hsmmc_context_restore(host);
2232 dev_dbg(dev, "enabled\n");
2237 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2238 .suspend = omap_hsmmc_suspend,
2239 .resume = omap_hsmmc_resume,
2240 .prepare = omap_hsmmc_prepare,
2241 .complete = omap_hsmmc_complete,
2242 .runtime_suspend = omap_hsmmc_runtime_suspend,
2243 .runtime_resume = omap_hsmmc_runtime_resume,
2246 static struct platform_driver omap_hsmmc_driver = {
2247 .probe = omap_hsmmc_probe,
2248 .remove = omap_hsmmc_remove,
2250 .name = DRIVER_NAME,
2251 .owner = THIS_MODULE,
2252 .pm = &omap_hsmmc_dev_pm_ops,
2253 .of_match_table = of_match_ptr(omap_mmc_of_match),
2257 module_platform_driver(omap_hsmmc_driver);
2258 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2259 MODULE_LICENSE("GPL");
2260 MODULE_ALIAS("platform:" DRIVER_NAME);
2261 MODULE_AUTHOR("Texas Instruments Inc");