drivers/mmc/host/omap_hsmmc.c

   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/kernel.h>
  21 #include <linux/debugfs.h>
  22 #include <linux/dmaengine.h>
  23 #include <linux/seq_file.h>
  24 #include <linux/sizes.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/delay.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/timer.h>
  30 #include <linux/clk.h>
  31 #include <linux/of.h>
  32 #include <linux/of_irq.h>
  33 #include <linux/of_gpio.h>
  34 #include <linux/of_device.h>
  35 #include <linux/omap-dmaengine.h>
  36 #include <linux/mmc/host.h>
  37 #include <linux/mmc/core.h>
  38 #include <linux/mmc/mmc.h>
  39 #include <linux/mmc/slot-gpio.h>
  40 #include <linux/io.h>
  41 #include <linux/irq.h>
  42 #include <linux/gpio.h>
  43 #include <linux/regulator/consumer.h>
  44 #include <linux/pinctrl/consumer.h>
  45 #include <linux/pm_runtime.h>
  46 #include <linux/pm_wakeirq.h>
  47 #include <linux/platform_data/hsmmc-omap.h>
  48
  49 /* OMAP HSMMC Host Controller Registers */
  50 #define OMAP_HSMMC_SYSSTATUS    0x0014
  51 #define OMAP_HSMMC_CON          0x002C
  52 #define OMAP_HSMMC_SDMASA       0x0100
  53 #define OMAP_HSMMC_BLK          0x0104
  54 #define OMAP_HSMMC_ARG          0x0108
  55 #define OMAP_HSMMC_CMD          0x010C
  56 #define OMAP_HSMMC_RSP10        0x0110
  57 #define OMAP_HSMMC_RSP32        0x0114
  58 #define OMAP_HSMMC_RSP54        0x0118
  59 #define OMAP_HSMMC_RSP76        0x011C
  60 #define OMAP_HSMMC_DATA         0x0120
  61 #define OMAP_HSMMC_PSTATE       0x0124
  62 #define OMAP_HSMMC_HCTL         0x0128
  63 #define OMAP_HSMMC_SYSCTL       0x012C
  64 #define OMAP_HSMMC_STAT         0x0130
  65 #define OMAP_HSMMC_IE           0x0134
  66 #define OMAP_HSMMC_ISE          0x0138
  67 #define OMAP_HSMMC_AC12         0x013C
  68 #define OMAP_HSMMC_CAPA         0x0140
  69
  70 #define VS18                    (1 << 26)
  71 #define VS30                    (1 << 25)
  72 #define HSS                     (1 << 21)
  73 #define SDVS18                  (0x5 << 9)
  74 #define SDVS30                  (0x6 << 9)
  75 #define SDVS33                  (0x7 << 9)
  76 #define SDVS_MASK               0x00000E00
  77 #define SDVSCLR                 0xFFFFF1FF
  78 #define SDVSDET                 0x00000400
  79 #define AUTOIDLE                0x1
  80 #define SDBP                    (1 << 8)
  81 #define DTO                     0xe
  82 #define ICE                     0x1
  83 #define ICS                     0x2
  84 #define CEN                     (1 << 2)
  85 #define CLKD_MAX                0x3FF           /* max clock divisor: 1023 */
  86 #define CLKD_MASK               0x0000FFC0
  87 #define CLKD_SHIFT              6
  88 #define DTO_MASK                0x000F0000
  89 #define DTO_SHIFT               16
  90 #define INIT_STREAM             (1 << 1)
  91 #define ACEN_ACMD23             (2 << 2)
  92 #define DP_SELECT               (1 << 21)
  93 #define DDIR                    (1 << 4)
  94 #define DMAE                    0x1
  95 #define MSBS                    (1 << 5)
  96 #define BCE                     (1 << 1)
  97 #define FOUR_BIT                (1 << 1)
  98 #define HSPE                    (1 << 2)
  99 #define IWE                     (1 << 24)
 100 #define DDR                     (1 << 19)
 101 #define CLKEXTFREE              (1 << 16)
 102 #define CTPL                    (1 << 11)
 103 #define DW8                     (1 << 5)
 104 #define OD                      0x1
 105 #define STAT_CLEAR              0xFFFFFFFF
 106 #define INIT_STREAM_CMD         0x00000000
 107 #define DUAL_VOLT_OCR_BIT       7
 108 #define SRC                     (1 << 25)
 109 #define SRD                     (1 << 26)
 110 #define SOFTRESET               (1 << 1)
 111
 112 /* PSTATE */
 113 #define DLEV_DAT(x)             (1 << (20 + (x)))
 114
 115 /* Interrupt masks for IE and ISE register */
 116 #define CC_EN                   (1 << 0)
 117 #define TC_EN                   (1 << 1)
 118 #define BWR_EN                  (1 << 4)
 119 #define BRR_EN                  (1 << 5)
 120 #define CIRQ_EN                 (1 << 8)
 121 #define ERR_EN                  (1 << 15)
 122 #define CTO_EN                  (1 << 16)
 123 #define CCRC_EN                 (1 << 17)
 124 #define CEB_EN                  (1 << 18)
 125 #define CIE_EN                  (1 << 19)
 126 #define DTO_EN                  (1 << 20)
 127 #define DCRC_EN                 (1 << 21)
 128 #define DEB_EN                  (1 << 22)
 129 #define ACE_EN                  (1 << 24)
 130 #define CERR_EN                 (1 << 28)
 131 #define BADA_EN                 (1 << 29)
 132
 133 #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\
 134                 DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \
 135                 BRR_EN | BWR_EN | TC_EN | CC_EN)
 136
 137 #define CNI     (1 << 7)
 138 #define ACIE    (1 << 4)
 139 #define ACEB    (1 << 3)
 140 #define ACCE    (1 << 2)
 141 #define ACTO    (1 << 1)
 142 #define ACNE    (1 << 0)
 143
 144 #define MMC_AUTOSUSPEND_DELAY   100
 145 #define MMC_TIMEOUT_MS          20              /* 20 mSec */
 146 #define MMC_TIMEOUT_US          20000           /* 20000 micro Sec */
 147 #define OMAP_MMC_MIN_CLOCK      400000
 148 #define OMAP_MMC_MAX_CLOCK      52000000
 149 #define DRIVER_NAME             "omap_hsmmc"
 150
 151 #define VDD_1V8                 1800000         /* 180000 uV */
 152 #define VDD_3V0                 3000000         /* 300000 uV */
 153 #define VDD_165_195             (ffs(MMC_VDD_165_195) - 1)
 154
 155 /*
 156  * One controller can have multiple slots, like on some omap boards using
 157  * omap.c controller driver. Luckily this is not currently done on any known
 158  * omap_hsmmc.c device.
 159  */
 160 #define mmc_pdata(host)         host->pdata
 161
 162 /*
 163  * MMC Host controller read/write API's
 164  */
 165 #define OMAP_HSMMC_READ(base, reg)      \
 166         __raw_readl((base) + OMAP_HSMMC_##reg)
 167
 168 #define OMAP_HSMMC_WRITE(base, reg, val) \
 169         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 170
 171 struct omap_hsmmc_next {
 172         unsigned int    dma_len;
 173         s32             cookie;
 174 };
 175
 176 struct omap_hsmmc_host {
 177         struct  device          *dev;
 178         struct  mmc_host        *mmc;
 179         struct  mmc_request     *mrq;
 180         struct  mmc_command     *cmd;
 181         struct  mmc_data        *data;
 182         struct  clk             *fclk;
 183         struct  clk             *dbclk;
 184         /*
 185          * vcc == configured supply
 186          * vcc_aux == optional
 187          *   -  MMC1, supply for DAT4..DAT7
 188          *   -  MMC2/MMC2, external level shifter voltage supply, for
 189          *      chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
 190          */
 191         struct  regulator       *vcc;
 192         struct  regulator       *vcc_aux;
 193         struct  regulator       *pbias;
 194         bool                    pbias_enabled;
 195         void    __iomem         *base;
 196         resource_size_t         mapbase;
 197         spinlock_t              irq_lock; /* Prevent races with irq handler */
 198         unsigned int            dma_len;
 199         unsigned int            dma_sg_idx;
 200         unsigned char           bus_mode;
 201         unsigned char           power_mode;
 202         int                     suspended;
 203         u32                     con;
 204         u32                     hctl;
 205         u32                     sysctl;
 206         u32                     capa;
 207         int                     irq;
 208         int                     wake_irq;
 209         int                     use_dma, dma_ch;
 210         struct dma_chan         *tx_chan;
 211         struct dma_chan         *rx_chan;
 212         int                     response_busy;
 213         int                     context_loss;
 214         int                     protect_card;
 215         int                     reqs_blocked;
 216         int                     req_in_progress;
 217         unsigned long           clk_rate;
 218         unsigned int            flags;
 219 #define AUTO_CMD23              (1 << 0)        /* Auto CMD23 support */
 220 #define HSMMC_SDIO_IRQ_ENABLED  (1 << 1)        /* SDIO irq enabled */
 221         struct omap_hsmmc_next  next_data;
 222         struct  omap_hsmmc_platform_data        *pdata;
 223
 224         /* return MMC cover switch state, can be NULL if not supported.
 225          *
 226          * possible return values:
 227          *   0 - closed
 228          *   1 - open
 229          */
 230         int (*get_cover_state)(struct device *dev);
 231
 232         int (*card_detect)(struct device *dev);
 233 };
 234
 235 struct omap_mmc_of_data {
 236         u32 reg_offset;
 237         u8 controller_flags;
 238 };
 239
 240 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host);
 241
 242 static int omap_hsmmc_card_detect(struct device *dev)
 243 {
 244         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
 245
 246         return mmc_gpio_get_cd(host->mmc);
 247 }
 248
 249 static int omap_hsmmc_get_cover_state(struct device *dev)
 250 {
 251         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
 252
 253         return mmc_gpio_get_cd(host->mmc);
 254 }
 255
 256 #ifdef CONFIG_REGULATOR
 257
 258 static int omap_hsmmc_set_power(struct device *dev, int power_on, int vdd)
 259 {
 260         struct omap_hsmmc_host *host =
 261                 platform_get_drvdata(to_platform_device(dev));
 262         int ret = 0;
 263
 264         if (mmc_pdata(host)->set_power)
 265                 return mmc_pdata(host)->set_power(dev, power_on, vdd);
 266
 267         /*
 268          * If we don't see a Vcc regulator, assume it's a fixed
 269          * voltage always-on regulator.
 270          */
 271         if (!host->vcc)
 272                 return 0;
 273
 274         if (mmc_pdata(host)->before_set_reg)
 275                 mmc_pdata(host)->before_set_reg(dev, power_on, vdd);
 276
 277         if (host->pbias) {
 278                 if (host->pbias_enabled == 1) {
 279                         ret = regulator_disable(host->pbias);
 280                         if (!ret)
 281                                 host->pbias_enabled = 0;
 282                 }
 283                 regulator_set_voltage(host->pbias, VDD_3V0, VDD_3V0);
 284         }
 285
 286         /*
 287          * Assume Vcc regulator is used only to power the card ... OMAP
 288          * VDDS is used to power the pins, optionally with a transceiver to
 289          * support cards using voltages other than VDDS (1.8V nominal).  When a
 290          * transceiver is used, DAT3..7 are muxed as transceiver control pins.
 291          *
 292          * In some cases this regulator won't support enable/disable;
 293          * e.g. it's a fixed rail for a WLAN chip.
 294          *
 295          * In other cases vcc_aux switches interface power.  Example, for
 296          * eMMC cards it represents VccQ.  Sometimes transceivers or SDIO
 297          * chips/cards need an interface voltage rail too.
 298          */
 299         if (power_on) {
 300                 if (host->vcc)
 301                         ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
 302                 /* Enable interface voltage rail, if needed */
 303                 if (ret == 0 && host->vcc_aux) {
 304                         ret = regulator_enable(host->vcc_aux);
 305                         if (ret < 0 && host->vcc)
 306                                 ret = mmc_regulator_set_ocr(host->mmc,
 307                                                         host->vcc, 0);
 308                 }
 309         } else {
 310                 /* Shut down the rail */
 311                 if (host->vcc_aux)
 312                         ret = regulator_disable(host->vcc_aux);
 313                 if (host->vcc) {
 314                         /* Then proceed to shut down the local regulator */
 315                         ret = mmc_regulator_set_ocr(host->mmc,
 316                                                 host->vcc, 0);
 317                 }
 318         }
 319
 320         if (host->pbias) {
 321                 if (vdd <= VDD_165_195)
 322                         ret = regulator_set_voltage(host->pbias, VDD_1V8,
 323                                                                 VDD_1V8);
 324                 else
 325                         ret = regulator_set_voltage(host->pbias, VDD_3V0,
 326                                                                 VDD_3V0);
 327                 if (ret < 0)
 328                         goto error_set_power;
 329
 330                 if (host->pbias_enabled == 0) {
 331                         ret = regulator_enable(host->pbias);
 332                         if (!ret)
 333                                 host->pbias_enabled = 1;
 334                 }
 335         }
 336
 337         if (mmc_pdata(host)->after_set_reg)
 338                 mmc_pdata(host)->after_set_reg(dev, power_on, vdd);
 339
 340 error_set_power:
 341         return ret;
 342 }
 343
 344 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 345 {
 346         int ocr_value = 0;
 347         int ret;
 348
 349         if (mmc_pdata(host)->set_power)
 350                 return 0;
 351
 352         host->vcc = devm_regulator_get_optional(host->dev, "vmmc");
 353         if (IS_ERR(host->vcc)) {
 354                 ret = PTR_ERR(host->vcc);
 355                 if (ret != -ENODEV)
 356                         return ret;
 357                 dev_dbg(host->dev, "unable to get vmmc regulator %ld\n",
 358                         PTR_ERR(host->vcc));
 359                 host->vcc = NULL;
 360         } else {
 361                 ocr_value = mmc_regulator_get_ocrmask(host->vcc);
 362                 if (!mmc_pdata(host)->ocr_mask) {
 363                         mmc_pdata(host)->ocr_mask = ocr_value;
 364                 } else {
 365                         if (!(mmc_pdata(host)->ocr_mask & ocr_value)) {
 366                                 dev_err(host->dev, "ocrmask %x is not supported\n",
 367                                         mmc_pdata(host)->ocr_mask);
 368                                 mmc_pdata(host)->ocr_mask = 0;
 369                                 return -EINVAL;
 370                         }
 371                 }
 372         }
 373
 374         /* Allow an aux regulator */
 375         host->vcc_aux = devm_regulator_get_optional(host->dev, "vmmc_aux");
 376         if (IS_ERR(host->vcc_aux)) {
 377                 ret = PTR_ERR(host->vcc_aux);
 378                 if (ret != -ENODEV)
 379                         return ret;
 380                 dev_dbg(host->dev, "unable to get vmmc_aux regulator %ld\n",
 381                         PTR_ERR(host->vcc_aux));
 382                 host->vcc_aux = NULL;
 383         }
 384
 385         host->pbias = devm_regulator_get_optional(host->dev, "pbias");
 386         if (IS_ERR(host->pbias)) {
 387                 ret = PTR_ERR(host->pbias);
 388                 if (ret != -ENODEV)
 389                         return ret;
 390                 dev_dbg(host->dev, "unable to get pbias regulator %ld\n",
 391                         PTR_ERR(host->pbias));
 392                 host->pbias = NULL;
 393         }
 394
 395         /* For eMMC do not power off when not in sleep state */
 396         if (mmc_pdata(host)->no_regulator_off_init)
 397                 return 0;
 398         /*
 399          * To disable boot_on regulator, enable regulator
 400          * to increase usecount and then disable it.
 401          */
 402         if ((host->vcc && regulator_is_enabled(host->vcc) > 0) ||
 403             (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
 404                 int vdd = ffs(mmc_pdata(host)->ocr_mask) - 1;
 405
 406                 omap_hsmmc_set_power(host->dev, 1, vdd);
 407                 omap_hsmmc_set_power(host->dev, 0, 0);
 408         }
 409
 410         return 0;
 411 }
 412
 413 static inline int omap_hsmmc_have_reg(void)
 414 {
 415         return 1;
 416 }
 417
 418 #else
 419
 420 static int omap_hsmmc_set_power(struct device *dev, int power_on, int vdd)
 421 {
 422         return 0;
 423 }
 424
 425 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 426 {
 427         return -EINVAL;
 428 }
 429
 430 static inline int omap_hsmmc_have_reg(void)
 431 {
 432         return 0;
 433 }
 434
 435 #endif
 436
 437 static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id);
 438
 439 static int omap_hsmmc_gpio_init(struct mmc_host *mmc,
 440                                 struct omap_hsmmc_host *host,
 441                                 struct omap_hsmmc_platform_data *pdata)
 442 {
 443         int ret;
 444
 445         if (gpio_is_valid(pdata->gpio_cod)) {
 446                 ret = mmc_gpio_request_cd(mmc, pdata->gpio_cod, 0);
 447                 if (ret)
 448                         return ret;
 449
 450                 host->get_cover_state = omap_hsmmc_get_cover_state;
 451                 mmc_gpio_set_cd_isr(mmc, omap_hsmmc_cover_irq);
 452         } else if (gpio_is_valid(pdata->gpio_cd)) {
 453                 ret = mmc_gpio_request_cd(mmc, pdata->gpio_cd, 0);
 454                 if (ret)
 455                         return ret;
 456
 457                 host->card_detect = omap_hsmmc_card_detect;
 458         }
 459
 460         if (gpio_is_valid(pdata->gpio_wp)) {
 461                 ret = mmc_gpio_request_ro(mmc, pdata->gpio_wp);
 462                 if (ret)
 463                         return ret;
 464         }
 465
 466         return 0;
 467 }
 468
 469 /*
 470  * Start clock to the card
 471  */
 472 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
 473 {
 474         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 475                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 476 }
 477
 478 /*
 479  * Stop clock to the card
 480  */
 481 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
 482 {
 483         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 484                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 485         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 486                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
 487 }
 488
 489 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
 490                                   struct mmc_command *cmd)
 491 {
 492         u32 irq_mask = INT_EN_MASK;
 493         unsigned long flags;
 494
 495         if (host->use_dma)
 496                 irq_mask &= ~(BRR_EN | BWR_EN);
 497
 498         /* Disable timeout for erases */
 499         if (cmd->opcode == MMC_ERASE)
 500                 irq_mask &= ~DTO_EN;
 501
 502         spin_lock_irqsave(&host->irq_lock, flags);
 503         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 504         OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
 505
 506         /* latch pending CIRQ, but don't signal MMC core */
 507         if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
 508                 irq_mask |= CIRQ_EN;
 509         OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
 510         spin_unlock_irqrestore(&host->irq_lock, flags);
 511 }
 512
 513 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
 514 {
 515         u32 irq_mask = 0;
 516         unsigned long flags;
 517
 518         spin_lock_irqsave(&host->irq_lock, flags);
 519         /* no transfer running but need to keep cirq if enabled */
 520         if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
 521                 irq_mask |= CIRQ_EN;
 522         OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
 523         OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
 524         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 525         spin_unlock_irqrestore(&host->irq_lock, flags);
 526 }
 527
 528 /* Calculate divisor for the given clock frequency */
 529 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
 530 {
 531         u16 dsor = 0;
 532
 533         if (ios->clock) {
 534                 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
 535                 if (dsor > CLKD_MAX)
 536                         dsor = CLKD_MAX;
 537         }
 538
 539         return dsor;
 540 }
 541
 542 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
 543 {
 544         struct mmc_ios *ios = &host->mmc->ios;
 545         unsigned long regval;
 546         unsigned long timeout;
 547         unsigned long clkdiv;
 548
 549         dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
 550
 551         omap_hsmmc_stop_clock(host);
 552
 553         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
 554         regval = regval & ~(CLKD_MASK | DTO_MASK);
 555         clkdiv = calc_divisor(host, ios);
 556         regval = regval | (clkdiv << 6) | (DTO << 16);
 557         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
 558         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 559                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 560
 561         /* Wait till the ICS bit is set */
 562         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 563         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
 564                 && time_before(jiffies, timeout))
 565                 cpu_relax();
 566
 567         /*
 568          * Enable High-Speed Support
 569          * Pre-Requisites
 570          *      - Controller should support High-Speed-Enable Bit
 571          *      - Controller should not be using DDR Mode
 572          *      - Controller should advertise that it supports High Speed
 573          *        in capabilities register
 574          *      - MMC/SD clock coming out of controller > 25MHz
 575          */
 576         if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) &&
 577             (ios->timing != MMC_TIMING_MMC_DDR52) &&
 578             (ios->timing != MMC_TIMING_UHS_DDR50) &&
 579             ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
 580                 regval = OMAP_HSMMC_READ(host->base, HCTL);
 581                 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
 582                         regval |= HSPE;
 583                 else
 584                         regval &= ~HSPE;
 585
 586                 OMAP_HSMMC_WRITE(host->base, HCTL, regval);
 587         }
 588
 589         omap_hsmmc_start_clock(host);
 590 }
 591
 592 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
 593 {
 594         struct mmc_ios *ios = &host->mmc->ios;
 595         u32 con;
 596
 597         con = OMAP_HSMMC_READ(host->base, CON);
 598         if (ios->timing == MMC_TIMING_MMC_DDR52 ||
 599             ios->timing == MMC_TIMING_UHS_DDR50)
 600                 con |= DDR;     /* configure in DDR mode */
 601         else
 602                 con &= ~DDR;
 603         switch (ios->bus_width) {
 604         case MMC_BUS_WIDTH_8:
 605                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
 606                 break;
 607         case MMC_BUS_WIDTH_4:
 608                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 609                 OMAP_HSMMC_WRITE(host->base, HCTL,
 610                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 611                 break;
 612         case MMC_BUS_WIDTH_1:
 613                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 614                 OMAP_HSMMC_WRITE(host->base, HCTL,
 615                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 616                 break;
 617         }
 618 }
 619
 620 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
 621 {
 622         struct mmc_ios *ios = &host->mmc->ios;
 623         u32 con;
 624
 625         con = OMAP_HSMMC_READ(host->base, CON);
 626         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 627                 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
 628         else
 629                 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
 630 }
 631
 632 #ifdef CONFIG_PM
 633
 634 /*
 635  * Restore the MMC host context, if it was lost as result of a
 636  * power state change.
 637  */
 638 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 639 {
 640         struct mmc_ios *ios = &host->mmc->ios;
 641         u32 hctl, capa;
 642         unsigned long timeout;
 643
 644         if (host->con == OMAP_HSMMC_READ(host->base, CON) &&
 645             host->hctl == OMAP_HSMMC_READ(host->base, HCTL) &&
 646             host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) &&
 647             host->capa == OMAP_HSMMC_READ(host->base, CAPA))
 648                 return 0;
 649
 650         host->context_loss++;
 651
 652         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
 653                 if (host->power_mode != MMC_POWER_OFF &&
 654                     (1 << ios->vdd) <= MMC_VDD_23_24)
 655                         hctl = SDVS18;
 656                 else
 657                         hctl = SDVS30;
 658                 capa = VS30 | VS18;
 659         } else {
 660                 hctl = SDVS18;
 661                 capa = VS18;
 662         }
 663
 664         if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
 665                 hctl |= IWE;
 666
 667         OMAP_HSMMC_WRITE(host->base, HCTL,
 668                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
 669
 670         OMAP_HSMMC_WRITE(host->base, CAPA,
 671                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
 672
 673         OMAP_HSMMC_WRITE(host->base, HCTL,
 674                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 675
 676         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 677         while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
 678                 && time_before(jiffies, timeout))
 679                 ;
 680
 681         OMAP_HSMMC_WRITE(host->base, ISE, 0);
 682         OMAP_HSMMC_WRITE(host->base, IE, 0);
 683         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 684
 685         /* Do not initialize card-specific things if the power is off */
 686         if (host->power_mode == MMC_POWER_OFF)
 687                 goto out;
 688
 689         omap_hsmmc_set_bus_width(host);
 690
 691         omap_hsmmc_set_clock(host);
 692
 693         omap_hsmmc_set_bus_mode(host);
 694
 695 out:
 696         dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n",
 697                 host->context_loss);
 698         return 0;
 699 }
 700
 701 /*
 702  * Save the MMC host context (store the number of power state changes so far).
 703  */
 704 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 705 {
 706         host->con =  OMAP_HSMMC_READ(host->base, CON);
 707         host->hctl = OMAP_HSMMC_READ(host->base, HCTL);
 708         host->sysctl =  OMAP_HSMMC_READ(host->base, SYSCTL);
 709         host->capa = OMAP_HSMMC_READ(host->base, CAPA);
 710 }
 711
 712 #else
 713
 714 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 715 {
 716         return 0;
 717 }
 718
 719 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 720 {
 721 }
 722
 723 #endif
 724
 725 /*
 726  * Send init stream sequence to card
 727  * before sending IDLE command
 728  */
 729 static void send_init_stream(struct omap_hsmmc_host *host)
 730 {
 731         int reg = 0;
 732         unsigned long timeout;
 733
 734         if (host->protect_card)
 735                 return;
 736
 737         disable_irq(host->irq);
 738
 739         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 740         OMAP_HSMMC_WRITE(host->base, CON,
 741                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 742         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 743
 744         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 745         while ((reg != CC_EN) && time_before(jiffies, timeout))
 746                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN;
 747
 748         OMAP_HSMMC_WRITE(host->base, CON,
 749                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 750
 751         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 752         OMAP_HSMMC_READ(host->base, STAT);
 753
 754         enable_irq(host->irq);
 755 }
 756
 757 static inline
 758 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
 759 {
 760         int r = 1;
 761
 762         if (host->get_cover_state)
 763                 r = host->get_cover_state(host->dev);
 764         return r;
 765 }
 766
 767 static ssize_t
 768 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
 769                            char *buf)
 770 {
 771         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 772         struct omap_hsmmc_host *host = mmc_priv(mmc);
 773
 774         return sprintf(buf, "%s\n",
 775                         omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
 776 }
 777
 778 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
 779
 780 static ssize_t
 781 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
 782                         char *buf)
 783 {
 784         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 785         struct omap_hsmmc_host *host = mmc_priv(mmc);
 786
 787         return sprintf(buf, "%s\n", mmc_pdata(host)->name);
 788 }
 789
 790 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
 791
 792 /*
 793  * Configure the response type and send the cmd.
 794  */
 795 static void
 796 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
 797         struct mmc_data *data)
 798 {
 799         int cmdreg = 0, resptype = 0, cmdtype = 0;
 800
 801         dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 802                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 803         host->cmd = cmd;
 804
 805         omap_hsmmc_enable_irq(host, cmd);
 806
 807         host->response_busy = 0;
 808         if (cmd->flags & MMC_RSP_PRESENT) {
 809                 if (cmd->flags & MMC_RSP_136)
 810                         resptype = 1;
 811                 else if (cmd->flags & MMC_RSP_BUSY) {
 812                         resptype = 3;
 813                         host->response_busy = 1;
 814                 } else
 815                         resptype = 2;
 816         }
 817
 818         /*
 819          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 820          * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
 821          * a val of 0x3, rest 0x0.
 822          */
 823         if (cmd == host->mrq->stop)
 824                 cmdtype = 0x3;
 825
 826         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 827
 828         if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) &&
 829             host->mrq->sbc) {
 830                 cmdreg |= ACEN_ACMD23;
 831                 OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg);
 832         }
 833         if (data) {
 834                 cmdreg |= DP_SELECT | MSBS | BCE;
 835                 if (data->flags & MMC_DATA_READ)
 836                         cmdreg |= DDIR;
 837                 else
 838                         cmdreg &= ~(DDIR);
 839         }
 840
 841         if (host->use_dma)
 842                 cmdreg |= DMAE;
 843
 844         host->req_in_progress = 1;
 845
 846         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 847         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 848 }
 849
 850 static int
 851 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
 852 {
 853         if (data->flags & MMC_DATA_WRITE)
 854                 return DMA_TO_DEVICE;
 855         else
 856                 return DMA_FROM_DEVICE;
 857 }
 858
 859 static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
 860         struct mmc_data *data)
 861 {
 862         return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
 863 }
 864
 865 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
 866 {
 867         int dma_ch;
 868         unsigned long flags;
 869
 870         spin_lock_irqsave(&host->irq_lock, flags);
 871         host->req_in_progress = 0;
 872         dma_ch = host->dma_ch;
 873         spin_unlock_irqrestore(&host->irq_lock, flags);
 874
 875         omap_hsmmc_disable_irq(host);
 876         /* Do not complete the request if DMA is still in progress */
 877         if (mrq->data && host->use_dma && dma_ch != -1)
 878                 return;
 879         host->mrq = NULL;
 880         mmc_request_done(host->mmc, mrq);
 881         pm_runtime_mark_last_busy(host->dev);
 882         pm_runtime_put_autosuspend(host->dev);
 883 }
 884
 885 /*
 886  * Notify the transfer complete to MMC core
 887  */
 888 static void
 889 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
 890 {
 891         if (!data) {
 892                 struct mmc_request *mrq = host->mrq;
 893
 894                 /* TC before CC from CMD6 - don't know why, but it happens */
 895                 if (host->cmd && host->cmd->opcode == 6 &&
 896                     host->response_busy) {
 897                         host->response_busy = 0;
 898                         return;
 899                 }
 900
 901                 omap_hsmmc_request_done(host, mrq);
 902                 return;
 903         }
 904
 905         host->data = NULL;
 906
 907         if (!data->error)
 908                 data->bytes_xfered += data->blocks * (data->blksz);
 909         else
 910                 data->bytes_xfered = 0;
 911
 912         if (data->stop && (data->error || !host->mrq->sbc))
 913                 omap_hsmmc_start_command(host, data->stop, NULL);
 914         else
 915                 omap_hsmmc_request_done(host, data->mrq);
 916 }
 917
 918 /*
 919  * Notify the core about command completion
 920  */
 921 static void
 922 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
 923 {
 924         if (host->mrq->sbc && (host->cmd == host->mrq->sbc) &&
 925             !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) {
 926                 host->cmd = NULL;
 927                 omap_hsmmc_start_dma_transfer(host);
 928                 omap_hsmmc_start_command(host, host->mrq->cmd,
 929                                                 host->mrq->data);
 930                 return;
 931         }
 932
 933         host->cmd = NULL;
 934
 935         if (cmd->flags & MMC_RSP_PRESENT) {
 936                 if (cmd->flags & MMC_RSP_136) {
 937                         /* response type 2 */
 938                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 939                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 940                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 941                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 942                 } else {
 943                         /* response types 1, 1b, 3, 4, 5, 6 */
 944                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 945                 }
 946         }
 947         if ((host->data == NULL && !host->response_busy) || cmd->error)
 948                 omap_hsmmc_request_done(host, host->mrq);
 949 }
 950
 951 /*
 952  * DMA clean up for command errors
 953  */
 954 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
 955 {
 956         int dma_ch;
 957         unsigned long flags;
 958
 959         host->data->error = errno;
 960
 961         spin_lock_irqsave(&host->irq_lock, flags);
 962         dma_ch = host->dma_ch;
 963         host->dma_ch = -1;
 964         spin_unlock_irqrestore(&host->irq_lock, flags);
 965
 966         if (host->use_dma && dma_ch != -1) {
 967                 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
 968
 969                 dmaengine_terminate_all(chan);
 970                 dma_unmap_sg(chan->device->dev,
 971                         host->data->sg, host->data->sg_len,
 972                         omap_hsmmc_get_dma_dir(host, host->data));
 973
 974                 host->data->host_cookie = 0;
 975         }
 976         host->data = NULL;
 977 }
 978
 979 /*
 980  * Readable error output
 981  */
 982 #ifdef CONFIG_MMC_DEBUG
 983 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
 984 {
 985         /* --- means reserved bit without definition at documentation */
 986         static const char *omap_hsmmc_status_bits[] = {
 987                 "CC"  , "TC"  , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
 988                 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
 989                 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
 990                 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
 991         };
 992         char res[256];
 993         char *buf = res;
 994         int len, i;
 995
 996         len = sprintf(buf, "MMC IRQ 0x%x :", status);
 997         buf += len;
 998
 999         for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
1000                 if (status & (1 << i)) {
1001                         len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
1002                         buf += len;
1003                 }
1004
1005         dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
1006 }
1007 #else
1008 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
1009                                              u32 status)
1010 {
1011 }
1012 #endif  /* CONFIG_MMC_DEBUG */
1013
1014 /*
1015  * MMC controller internal state machines reset
1016  *
1017  * Used to reset command or data internal state machines, using respectively
1018  *  SRC or SRD bit of SYSCTL register
1019  * Can be called from interrupt context
1020  */
1021 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1022                                                    unsigned long bit)
1023 {
1024         unsigned long i = 0;
1025         unsigned long limit = MMC_TIMEOUT_US;
1026
1027         OMAP_HSMMC_WRITE(host->base, SYSCTL,
1028                          OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1029
1030         /*
1031          * OMAP4 ES2 and greater has an updated reset logic.
1032          * Monitor a 0->1 transition first
1033          */
1034         if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) {
1035                 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
1036                                         && (i++ < limit))
1037                         udelay(1);
1038         }
1039         i = 0;
1040
1041         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1042                 (i++ < limit))
1043                 udelay(1);
1044
1045         if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1046                 dev_err(mmc_dev(host->mmc),
1047                         "Timeout waiting on controller reset in %s\n",
1048                         __func__);
1049 }
1050
1051 static void hsmmc_command_incomplete(struct omap_hsmmc_host *host,
1052                                         int err, int end_cmd)
1053 {
1054         if (end_cmd) {
1055                 omap_hsmmc_reset_controller_fsm(host, SRC);
1056                 if (host->cmd)
1057                         host->cmd->error = err;
1058         }
1059
1060         if (host->data) {
1061                 omap_hsmmc_reset_controller_fsm(host, SRD);
1062                 omap_hsmmc_dma_cleanup(host, err);
1063         } else if (host->mrq && host->mrq->cmd)
1064                 host->mrq->cmd->error = err;
1065 }
1066
1067 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1068 {
1069         struct mmc_data *data;
1070         int end_cmd = 0, end_trans = 0;
1071         int error = 0;
1072
1073         data = host->data;
1074         dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1075
1076         if (status & ERR_EN) {
1077                 omap_hsmmc_dbg_report_irq(host, status);
1078
1079                 if (status & (CTO_EN | CCRC_EN))
1080                         end_cmd = 1;
1081                 if (host->data || host->response_busy) {
1082                         end_trans = !end_cmd;
1083                         host->response_busy = 0;
1084                 }
1085                 if (status & (CTO_EN | DTO_EN))
1086                         hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
1087                 else if (status & (CCRC_EN | DCRC_EN | DEB_EN | CEB_EN |
1088                                    BADA_EN))
1089                         hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
1090
1091                 if (status & ACE_EN) {
1092                         u32 ac12;
1093                         ac12 = OMAP_HSMMC_READ(host->base, AC12);
1094                         if (!(ac12 & ACNE) && host->mrq->sbc) {
1095                                 end_cmd = 1;
1096                                 if (ac12 & ACTO)
1097                                         error =  -ETIMEDOUT;
1098                                 else if (ac12 & (ACCE | ACEB | ACIE))
1099                                         error = -EILSEQ;
1100                                 host->mrq->sbc->error = error;
1101                                 hsmmc_command_incomplete(host, error, end_cmd);
1102                         }
1103                         dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12);
1104                 }
1105         }
1106
1107         OMAP_HSMMC_WRITE(host->base, STAT, status);
1108         if (end_cmd || ((status & CC_EN) && host->cmd))
1109                 omap_hsmmc_cmd_done(host, host->cmd);
1110         if ((end_trans || (status & TC_EN)) && host->mrq)
1111                 omap_hsmmc_xfer_done(host, data);
1112 }
1113
1114 /*
1115  * MMC controller IRQ handler
1116  */
1117 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1118 {
1119         struct omap_hsmmc_host *host = dev_id;
1120         int status;
1121
1122         status = OMAP_HSMMC_READ(host->base, STAT);
1123         while (status & (INT_EN_MASK | CIRQ_EN)) {
1124                 if (host->req_in_progress)
1125                         omap_hsmmc_do_irq(host, status);
1126
1127                 if (status & CIRQ_EN)
1128                         mmc_signal_sdio_irq(host->mmc);
1129
1130                 /* Flush posted write */
1131                 status = OMAP_HSMMC_READ(host->base, STAT);
1132         }
1133
1134         return IRQ_HANDLED;
1135 }
1136
1137 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1138 {
1139         unsigned long i;
1140
1141         OMAP_HSMMC_WRITE(host->base, HCTL,
1142                          OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1143         for (i = 0; i < loops_per_jiffy; i++) {
1144                 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1145                         break;
1146                 cpu_relax();
1147         }
1148 }
1149
1150 /*
1151  * Switch MMC interface voltage ... only relevant for MMC1.
1152  *
1153  * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1154  * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1155  * Some chips, like eMMC ones, use internal transceivers.
1156  */
1157 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1158 {
1159         u32 reg_val = 0;
1160         int ret;
1161
1162         /* Disable the clocks */
1163         pm_runtime_put_sync(host->dev);
1164         if (host->dbclk)
1165                 clk_disable_unprepare(host->dbclk);
1166
1167         /* Turn the power off */
1168         ret = omap_hsmmc_set_power(host->dev, 0, 0);
1169
1170         /* Turn the power ON with given VDD 1.8 or 3.0v */
1171         if (!ret)
1172                 ret = omap_hsmmc_set_power(host->dev, 1, vdd);
1173         pm_runtime_get_sync(host->dev);
1174         if (host->dbclk)
1175                 clk_prepare_enable(host->dbclk);
1176
1177         if (ret != 0)
1178                 goto err;
1179
1180         OMAP_HSMMC_WRITE(host->base, HCTL,
1181                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1182         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1183
1184         /*
1185          * If a MMC dual voltage card is detected, the set_ios fn calls
1186          * this fn with VDD bit set for 1.8V. Upon card removal from the
1187          * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1188          *
1189          * Cope with a bit of slop in the range ... per data sheets:
1190          *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1191          *    but recommended values are 1.71V to 1.89V
1192          *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1193          *    but recommended values are 2.7V to 3.3V
1194          *
1195          * Board setup code shouldn't permit anything very out-of-range.
1196          * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1197          * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1198          */
1199         if ((1 << vdd) <= MMC_VDD_23_24)
1200                 reg_val |= SDVS18;
1201         else
1202                 reg_val |= SDVS30;
1203
1204         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1205         set_sd_bus_power(host);
1206
1207         return 0;
1208 err:
1209         dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1210         return ret;
1211 }
1212
1213 /* Protect the card while the cover is open */
1214 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1215 {
1216         if (!host->get_cover_state)
1217                 return;
1218
1219         host->reqs_blocked = 0;
1220         if (host->get_cover_state(host->dev)) {
1221                 if (host->protect_card) {
1222                         dev_info(host->dev, "%s: cover is closed, "
1223                                          "card is now accessible\n",
1224                                          mmc_hostname(host->mmc));
1225                         host->protect_card = 0;
1226                 }
1227         } else {
1228                 if (!host->protect_card) {
1229                         dev_info(host->dev, "%s: cover is open, "
1230                                          "card is now inaccessible\n",
1231                                          mmc_hostname(host->mmc));
1232                         host->protect_card = 1;
1233                 }
1234         }
1235 }
1236
1237 /*
1238  * irq handler when (cell-phone) cover is mounted/removed
1239  */
1240 static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id)
1241 {
1242         struct omap_hsmmc_host *host = dev_id;
1243
1244         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1245
1246         omap_hsmmc_protect_card(host);
1247         mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1248         return IRQ_HANDLED;
1249 }
1250
1251 static void omap_hsmmc_dma_callback(void *param)
1252 {
1253         struct omap_hsmmc_host *host = param;
1254         struct dma_chan *chan;
1255         struct mmc_data *data;
1256         int req_in_progress;
1257
1258         spin_lock_irq(&host->irq_lock);
1259         if (host->dma_ch < 0) {
1260                 spin_unlock_irq(&host->irq_lock);
1261                 return;
1262         }
1263
1264         data = host->mrq->data;
1265         chan = omap_hsmmc_get_dma_chan(host, data);
1266         if (!data->host_cookie)
1267                 dma_unmap_sg(chan->device->dev,
1268                              data->sg, data->sg_len,
1269                              omap_hsmmc_get_dma_dir(host, data));
1270
1271         req_in_progress = host->req_in_progress;
1272         host->dma_ch = -1;
1273         spin_unlock_irq(&host->irq_lock);
1274
1275         /* If DMA has finished after TC, complete the request */
1276         if (!req_in_progress) {
1277                 struct mmc_request *mrq = host->mrq;
1278
1279                 host->mrq = NULL;
1280                 mmc_request_done(host->mmc, mrq);
1281                 pm_runtime_mark_last_busy(host->dev);
1282                 pm_runtime_put_autosuspend(host->dev);
1283         }
1284 }
1285
1286 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1287                                        struct mmc_data *data,
1288                                        struct omap_hsmmc_next *next,
1289                                        struct dma_chan *chan)
1290 {
1291         int dma_len;
1292
1293         if (!next && data->host_cookie &&
1294             data->host_cookie != host->next_data.cookie) {
1295                 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
1296                        " host->next_data.cookie %d\n",
1297                        __func__, data->host_cookie, host->next_data.cookie);
1298                 data->host_cookie = 0;
1299         }
1300
1301         /* Check if next job is already prepared */
1302         if (next || data->host_cookie != host->next_data.cookie) {
1303                 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
1304                                      omap_hsmmc_get_dma_dir(host, data));
1305
1306         } else {
1307                 dma_len = host->next_data.dma_len;
1308                 host->next_data.dma_len = 0;
1309         }
1310
1311
1312         if (dma_len == 0)
1313                 return -EINVAL;
1314
1315         if (next) {
1316                 next->dma_len = dma_len;
1317                 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1318         } else
1319                 host->dma_len = dma_len;
1320
1321         return 0;
1322 }
1323
1324 /*
1325  * Routine to configure and start DMA for the MMC card
1326  */
1327 static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host,
1328                                         struct mmc_request *req)
1329 {
1330         struct dma_slave_config cfg;
1331         struct dma_async_tx_descriptor *tx;
1332         int ret = 0, i;
1333         struct mmc_data *data = req->data;
1334         struct dma_chan *chan;
1335
1336         /* Sanity check: all the SG entries must be aligned by block size. */
1337         for (i = 0; i < data->sg_len; i++) {
1338                 struct scatterlist *sgl;
1339
1340                 sgl = data->sg + i;
1341                 if (sgl->length % data->blksz)
1342                         return -EINVAL;
1343         }
1344         if ((data->blksz % 4) != 0)
1345                 /* REVISIT: The MMC buffer increments only when MSB is written.
1346                  * Return error for blksz which is non multiple of four.
1347                  */
1348                 return -EINVAL;
1349
1350         BUG_ON(host->dma_ch != -1);
1351
1352         chan = omap_hsmmc_get_dma_chan(host, data);
1353
1354         cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA;
1355         cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA;
1356         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1357         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1358         cfg.src_maxburst = data->blksz / 4;
1359         cfg.dst_maxburst = data->blksz / 4;
1360
1361         ret = dmaengine_slave_config(chan, &cfg);
1362         if (ret)
1363                 return ret;
1364
1365         ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
1366         if (ret)
1367                 return ret;
1368
1369         tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
1370                 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1371                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1372         if (!tx) {
1373                 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
1374                 /* FIXME: cleanup */
1375                 return -1;
1376         }
1377
1378         tx->callback = omap_hsmmc_dma_callback;
1379         tx->callback_param = host;
1380
1381         /* Does not fail */
1382         dmaengine_submit(tx);
1383
1384         host->dma_ch = 1;
1385
1386         return 0;
1387 }
1388
1389 static void set_data_timeout(struct omap_hsmmc_host *host,
1390                              unsigned int timeout_ns,
1391                              unsigned int timeout_clks)
1392 {
1393         unsigned int timeout, cycle_ns;
1394         uint32_t reg, clkd, dto = 0;
1395
1396         reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1397         clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1398         if (clkd == 0)
1399                 clkd = 1;
1400
1401         cycle_ns = 1000000000 / (host->clk_rate / clkd);
1402         timeout = timeout_ns / cycle_ns;
1403         timeout += timeout_clks;
1404         if (timeout) {
1405                 while ((timeout & 0x80000000) == 0) {
1406                         dto += 1;
1407                         timeout <<= 1;
1408                 }
1409                 dto = 31 - dto;
1410                 timeout <<= 1;
1411                 if (timeout && dto)
1412                         dto += 1;
1413                 if (dto >= 13)
1414                         dto -= 13;
1415                 else
1416                         dto = 0;
1417                 if (dto > 14)
1418                         dto = 14;
1419         }
1420
1421         reg &= ~DTO_MASK;
1422         reg |= dto << DTO_SHIFT;
1423         OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1424 }
1425
1426 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host)
1427 {
1428         struct mmc_request *req = host->mrq;
1429         struct dma_chan *chan;
1430
1431         if (!req->data)
1432                 return;
1433         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1434                                 | (req->data->blocks << 16));
1435         set_data_timeout(host, req->data->timeout_ns,
1436                                 req->data->timeout_clks);
1437         chan = omap_hsmmc_get_dma_chan(host, req->data);
1438         dma_async_issue_pending(chan);
1439 }
1440
1441 /*
1442  * Configure block length for MMC/SD cards and initiate the transfer.
1443  */
1444 static int
1445 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1446 {
1447         int ret;
1448         host->data = req->data;
1449
1450         if (req->data == NULL) {
1451                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1452                 /*
1453                  * Set an arbitrary 100ms data timeout for commands with
1454                  * busy signal.
1455                  */
1456                 if (req->cmd->flags & MMC_RSP_BUSY)
1457                         set_data_timeout(host, 100000000U, 0);
1458                 return 0;
1459         }
1460
1461         if (host->use_dma) {
1462                 ret = omap_hsmmc_setup_dma_transfer(host, req);
1463                 if (ret != 0) {
1464                         dev_err(mmc_dev(host->mmc), "MMC start dma failure\n");
1465                         return ret;
1466                 }
1467         }
1468         return 0;
1469 }
1470
1471 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1472                                 int err)
1473 {
1474         struct omap_hsmmc_host *host = mmc_priv(mmc);
1475         struct mmc_data *data = mrq->data;
1476
1477         if (host->use_dma && data->host_cookie) {
1478                 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
1479
1480                 dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
1481                              omap_hsmmc_get_dma_dir(host, data));
1482                 data->host_cookie = 0;
1483         }
1484 }
1485
1486 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1487                                bool is_first_req)
1488 {
1489         struct omap_hsmmc_host *host = mmc_priv(mmc);
1490
1491         if (mrq->data->host_cookie) {
1492                 mrq->data->host_cookie = 0;
1493                 return ;
1494         }
1495
1496         if (host->use_dma) {
1497                 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
1498
1499                 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1500                                                 &host->next_data, c))
1501                         mrq->data->host_cookie = 0;
1502         }
1503 }
1504
1505 /*
1506  * Request function. for read/write operation
1507  */
1508 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1509 {
1510         struct omap_hsmmc_host *host = mmc_priv(mmc);
1511         int err;
1512
1513         BUG_ON(host->req_in_progress);
1514         BUG_ON(host->dma_ch != -1);
1515         pm_runtime_get_sync(host->dev);
1516         if (host->protect_card) {
1517                 if (host->reqs_blocked < 3) {
1518                         /*
1519                          * Ensure the controller is left in a consistent
1520                          * state by resetting the command and data state
1521                          * machines.
1522                          */
1523                         omap_hsmmc_reset_controller_fsm(host, SRD);
1524                         omap_hsmmc_reset_controller_fsm(host, SRC);
1525                         host->reqs_blocked += 1;
1526                 }
1527                 req->cmd->error = -EBADF;
1528                 if (req->data)
1529                         req->data->error = -EBADF;
1530                 req->cmd->retries = 0;
1531                 mmc_request_done(mmc, req);
1532                 pm_runtime_mark_last_busy(host->dev);
1533                 pm_runtime_put_autosuspend(host->dev);
1534                 return;
1535         } else if (host->reqs_blocked)
1536                 host->reqs_blocked = 0;
1537         WARN_ON(host->mrq != NULL);
1538         host->mrq = req;
1539         host->clk_rate = clk_get_rate(host->fclk);
1540         err = omap_hsmmc_prepare_data(host, req);
1541         if (err) {
1542                 req->cmd->error = err;
1543                 if (req->data)
1544                         req->data->error = err;
1545                 host->mrq = NULL;
1546                 mmc_request_done(mmc, req);
1547                 pm_runtime_mark_last_busy(host->dev);
1548                 pm_runtime_put_autosuspend(host->dev);
1549                 return;
1550         }
1551         if (req->sbc && !(host->flags & AUTO_CMD23)) {
1552                 omap_hsmmc_start_command(host, req->sbc, NULL);
1553                 return;
1554         }
1555
1556         omap_hsmmc_start_dma_transfer(host);
1557         omap_hsmmc_start_command(host, req->cmd, req->data);
1558 }
1559
1560 /* Routine to configure clock values. Exposed API to core */
1561 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1562 {
1563         struct omap_hsmmc_host *host = mmc_priv(mmc);
1564         int do_send_init_stream = 0;
1565
1566         pm_runtime_get_sync(host->dev);
1567
1568         if (ios->power_mode != host->power_mode) {
1569                 switch (ios->power_mode) {
1570                 case MMC_POWER_OFF:
1571                         omap_hsmmc_set_power(host->dev, 0, 0);
1572                         break;
1573                 case MMC_POWER_UP:
1574                         omap_hsmmc_set_power(host->dev, 1, ios->vdd);
1575                         break;
1576                 case MMC_POWER_ON:
1577                         do_send_init_stream = 1;
1578                         break;
1579                 }
1580                 host->power_mode = ios->power_mode;
1581         }
1582
1583         /* FIXME: set registers based only on changes to ios */
1584
1585         omap_hsmmc_set_bus_width(host);
1586
1587         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1588                 /* Only MMC1 can interface at 3V without some flavor
1589                  * of external transceiver; but they all handle 1.8V.
1590                  */
1591                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1592                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1593                                 /*
1594                                  * The mmc_select_voltage fn of the core does
1595                                  * not seem to set the power_mode to
1596                                  * MMC_POWER_UP upon recalculating the voltage.
1597                                  * vdd 1.8v.
1598                                  */
1599                         if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1600                                 dev_dbg(mmc_dev(host->mmc),
1601                                                 "Switch operation failed\n");
1602                 }
1603         }
1604
1605         omap_hsmmc_set_clock(host);
1606
1607         if (do_send_init_stream)
1608                 send_init_stream(host);
1609
1610         omap_hsmmc_set_bus_mode(host);
1611
1612         pm_runtime_put_autosuspend(host->dev);
1613 }
1614
1615 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1616 {
1617         struct omap_hsmmc_host *host = mmc_priv(mmc);
1618
1619         if (!host->card_detect)
1620                 return -ENOSYS;
1621         return host->card_detect(host->dev);
1622 }
1623
1624 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1625 {
1626         struct omap_hsmmc_host *host = mmc_priv(mmc);
1627
1628         if (mmc_pdata(host)->init_card)
1629                 mmc_pdata(host)->init_card(card);
1630 }
1631
1632 static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
1633 {
1634         struct omap_hsmmc_host *host = mmc_priv(mmc);
1635         u32 irq_mask, con;
1636         unsigned long flags;
1637
1638         spin_lock_irqsave(&host->irq_lock, flags);
1639
1640         con = OMAP_HSMMC_READ(host->base, CON);
1641         irq_mask = OMAP_HSMMC_READ(host->base, ISE);
1642         if (enable) {
1643                 host->flags |= HSMMC_SDIO_IRQ_ENABLED;
1644                 irq_mask |= CIRQ_EN;
1645                 con |= CTPL | CLKEXTFREE;
1646         } else {
1647                 host->flags &= ~HSMMC_SDIO_IRQ_ENABLED;
1648                 irq_mask &= ~CIRQ_EN;
1649                 con &= ~(CTPL | CLKEXTFREE);
1650         }
1651         OMAP_HSMMC_WRITE(host->base, CON, con);
1652         OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
1653
1654         /*
1655          * if enable, piggy back detection on current request
1656          * but always disable immediately
1657          */
1658         if (!host->req_in_progress || !enable)
1659                 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
1660
1661         /* flush posted write */
1662         OMAP_HSMMC_READ(host->base, IE);
1663
1664         spin_unlock_irqrestore(&host->irq_lock, flags);
1665 }
1666
1667 static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host)
1668 {
1669         int ret;
1670
1671         /*
1672          * For omaps with wake-up path, wakeirq will be irq from pinctrl and
1673          * for other omaps, wakeirq will be from GPIO (dat line remuxed to
1674          * gpio). wakeirq is needed to detect sdio irq in runtime suspend state
1675          * with functional clock disabled.
1676          */
1677         if (!host->dev->of_node || !host->wake_irq)
1678                 return -ENODEV;
1679
1680         ret = dev_pm_set_dedicated_wake_irq(host->dev, host->wake_irq);
1681         if (ret) {
1682                 dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n");
1683                 goto err;
1684         }
1685
1686         /*
1687          * Some omaps don't have wake-up path from deeper idle states
1688          * and need to remux SDIO DAT1 to GPIO for wake-up from idle.
1689          */
1690         if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) {
1691                 struct pinctrl *p = devm_pinctrl_get(host->dev);
1692                 if (!p) {
1693                         ret = -ENODEV;
1694                         goto err_free_irq;
1695                 }
1696                 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_DEFAULT))) {
1697                         dev_info(host->dev, "missing default pinctrl state\n");
1698                         devm_pinctrl_put(p);
1699                         ret = -EINVAL;
1700                         goto err_free_irq;
1701                 }
1702
1703                 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) {
1704                         dev_info(host->dev, "missing idle pinctrl state\n");
1705                         devm_pinctrl_put(p);
1706                         ret = -EINVAL;
1707                         goto err_free_irq;
1708                 }
1709                 devm_pinctrl_put(p);
1710         }
1711
1712         OMAP_HSMMC_WRITE(host->base, HCTL,
1713                          OMAP_HSMMC_READ(host->base, HCTL) | IWE);
1714         return 0;
1715
1716 err_free_irq:
1717         dev_pm_clear_wake_irq(host->dev);
1718 err:
1719         dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n");
1720         host->wake_irq = 0;
1721         return ret;
1722 }
1723
1724 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1725 {
1726         u32 hctl, capa, value;
1727
1728         /* Only MMC1 supports 3.0V */
1729         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1730                 hctl = SDVS30;
1731                 capa = VS30 | VS18;
1732         } else {
1733                 hctl = SDVS18;
1734                 capa = VS18;
1735         }
1736
1737         value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1738         OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1739
1740         value = OMAP_HSMMC_READ(host->base, CAPA);
1741         OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1742
1743         /* Set SD bus power bit */
1744         set_sd_bus_power(host);
1745 }
1746
1747 static int omap_hsmmc_multi_io_quirk(struct mmc_card *card,
1748                                      unsigned int direction, int blk_size)
1749 {
1750         /* This controller can't do multiblock reads due to hw bugs */
1751         if (direction == MMC_DATA_READ)
1752                 return 1;
1753
1754         return blk_size;
1755 }
1756
1757 static struct mmc_host_ops omap_hsmmc_ops = {
1758         .post_req = omap_hsmmc_post_req,
1759         .pre_req = omap_hsmmc_pre_req,
1760         .request = omap_hsmmc_request,
1761         .set_ios = omap_hsmmc_set_ios,
1762         .get_cd = omap_hsmmc_get_cd,
1763         .get_ro = mmc_gpio_get_ro,
1764         .init_card = omap_hsmmc_init_card,
1765         .enable_sdio_irq = omap_hsmmc_enable_sdio_irq,
1766 };
1767
1768 #ifdef CONFIG_DEBUG_FS
1769
1770 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1771 {
1772         struct mmc_host *mmc = s->private;
1773         struct omap_hsmmc_host *host = mmc_priv(mmc);
1774
1775         seq_printf(s, "mmc%d:\n", mmc->index);
1776         seq_printf(s, "sdio irq mode\t%s\n",
1777                    (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling");
1778
1779         if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1780                 seq_printf(s, "sdio irq \t%s\n",
1781                            (host->flags & HSMMC_SDIO_IRQ_ENABLED) ?  "enabled"
1782                            : "disabled");
1783         }
1784         seq_printf(s, "ctx_loss:\t%d\n", host->context_loss);
1785
1786         pm_runtime_get_sync(host->dev);
1787         seq_puts(s, "\nregs:\n");
1788         seq_printf(s, "CON:\t\t0x%08x\n",
1789                         OMAP_HSMMC_READ(host->base, CON));
1790         seq_printf(s, "PSTATE:\t\t0x%08x\n",
1791                    OMAP_HSMMC_READ(host->base, PSTATE));
1792         seq_printf(s, "HCTL:\t\t0x%08x\n",
1793                         OMAP_HSMMC_READ(host->base, HCTL));
1794         seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1795                         OMAP_HSMMC_READ(host->base, SYSCTL));
1796         seq_printf(s, "IE:\t\t0x%08x\n",
1797                         OMAP_HSMMC_READ(host->base, IE));
1798         seq_printf(s, "ISE:\t\t0x%08x\n",
1799                         OMAP_HSMMC_READ(host->base, ISE));
1800         seq_printf(s, "CAPA:\t\t0x%08x\n",
1801                         OMAP_HSMMC_READ(host->base, CAPA));
1802
1803         pm_runtime_mark_last_busy(host->dev);
1804         pm_runtime_put_autosuspend(host->dev);
1805
1806         return 0;
1807 }
1808
1809 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1810 {
1811         return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1812 }
1813
1814 static const struct file_operations mmc_regs_fops = {
1815         .open           = omap_hsmmc_regs_open,
1816         .read           = seq_read,
1817         .llseek         = seq_lseek,
1818         .release        = single_release,
1819 };
1820
1821 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1822 {
1823         if (mmc->debugfs_root)
1824                 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1825                         mmc, &mmc_regs_fops);
1826 }
1827
1828 #else
1829
1830 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1831 {
1832 }
1833
1834 #endif
1835
1836 #ifdef CONFIG_OF
1837 static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = {
1838         /* See 35xx errata 2.1.1.128 in SPRZ278F */
1839         .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1840 };
1841
1842 static const struct omap_mmc_of_data omap4_mmc_of_data = {
1843         .reg_offset = 0x100,
1844 };
1845 static const struct omap_mmc_of_data am33xx_mmc_of_data = {
1846         .reg_offset = 0x100,
1847         .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING,
1848 };
1849
1850 static const struct of_device_id omap_mmc_of_match[] = {
1851         {
1852                 .compatible = "ti,omap2-hsmmc",
1853         },
1854         {
1855                 .compatible = "ti,omap3-pre-es3-hsmmc",
1856                 .data = &omap3_pre_es3_mmc_of_data,
1857         },
1858         {
1859                 .compatible = "ti,omap3-hsmmc",
1860         },
1861         {
1862                 .compatible = "ti,omap4-hsmmc",
1863                 .data = &omap4_mmc_of_data,
1864         },
1865         {
1866                 .compatible = "ti,am33xx-hsmmc",
1867                 .data = &am33xx_mmc_of_data,
1868         },
1869         {},
1870 };
1871 MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1872
1873 static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1874 {
1875         struct omap_hsmmc_platform_data *pdata;
1876         struct device_node *np = dev->of_node;
1877
1878         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1879         if (!pdata)
1880                 return ERR_PTR(-ENOMEM); /* out of memory */
1881
1882         if (of_find_property(np, "ti,dual-volt", NULL))
1883                 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1884
1885         pdata->gpio_cd = -EINVAL;
1886         pdata->gpio_cod = -EINVAL;
1887         pdata->gpio_wp = -EINVAL;
1888
1889         if (of_find_property(np, "ti,non-removable", NULL)) {
1890                 pdata->nonremovable = true;
1891                 pdata->no_regulator_off_init = true;
1892         }
1893
1894         if (of_find_property(np, "ti,needs-special-reset", NULL))
1895                 pdata->features |= HSMMC_HAS_UPDATED_RESET;
1896
1897         if (of_find_property(np, "ti,needs-special-hs-handling", NULL))
1898                 pdata->features |= HSMMC_HAS_HSPE_SUPPORT;
1899
1900         return pdata;
1901 }
1902 #else
1903 static inline struct omap_hsmmc_platform_data
1904                         *of_get_hsmmc_pdata(struct device *dev)
1905 {
1906         return ERR_PTR(-EINVAL);
1907 }
1908 #endif
1909
1910 static int omap_hsmmc_probe(struct platform_device *pdev)
1911 {
1912         struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data;
1913         struct mmc_host *mmc;
1914         struct omap_hsmmc_host *host = NULL;
1915         struct resource *res;
1916         int ret, irq;
1917         const struct of_device_id *match;
1918         dma_cap_mask_t mask;
1919         unsigned tx_req, rx_req;
1920         const struct omap_mmc_of_data *data;
1921         void __iomem *base;
1922
1923         match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
1924         if (match) {
1925                 pdata = of_get_hsmmc_pdata(&pdev->dev);
1926
1927                 if (IS_ERR(pdata))
1928                         return PTR_ERR(pdata);
1929
1930                 if (match->data) {
1931                         data = match->data;
1932                         pdata->reg_offset = data->reg_offset;
1933                         pdata->controller_flags |= data->controller_flags;
1934                 }
1935         }
1936
1937         if (pdata == NULL) {
1938                 dev_err(&pdev->dev, "Platform Data is missing\n");
1939                 return -ENXIO;
1940         }
1941
1942         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1943         irq = platform_get_irq(pdev, 0);
1944         if (res == NULL || irq < 0)
1945                 return -ENXIO;
1946
1947         base = devm_ioremap_resource(&pdev->dev, res);
1948         if (IS_ERR(base))
1949                 return PTR_ERR(base);
1950
1951         mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1952         if (!mmc) {
1953                 ret = -ENOMEM;
1954                 goto err;
1955         }
1956
1957         ret = mmc_of_parse(mmc);
1958         if (ret)
1959                 goto err1;
1960
1961         host            = mmc_priv(mmc);
1962         host->mmc       = mmc;
1963         host->pdata     = pdata;
1964         host->dev       = &pdev->dev;
1965         host->use_dma   = 1;
1966         host->dma_ch    = -1;
1967         host->irq       = irq;
1968         host->mapbase   = res->start + pdata->reg_offset;
1969         host->base      = base + pdata->reg_offset;
1970         host->power_mode = MMC_POWER_OFF;
1971         host->next_data.cookie = 1;
1972         host->pbias_enabled = 0;
1973
1974         ret = omap_hsmmc_gpio_init(mmc, host, pdata);
1975         if (ret)
1976                 goto err_gpio;
1977
1978         platform_set_drvdata(pdev, host);
1979
1980         if (pdev->dev.of_node)
1981                 host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1982
1983         mmc->ops        = &omap_hsmmc_ops;
1984
1985         mmc->f_min = OMAP_MMC_MIN_CLOCK;
1986
1987         if (pdata->max_freq > 0)
1988                 mmc->f_max = pdata->max_freq;
1989         else if (mmc->f_max == 0)
1990                 mmc->f_max = OMAP_MMC_MAX_CLOCK;
1991
1992         spin_lock_init(&host->irq_lock);
1993
1994         host->fclk = devm_clk_get(&pdev->dev, "fck");
1995         if (IS_ERR(host->fclk)) {
1996                 ret = PTR_ERR(host->fclk);
1997                 host->fclk = NULL;
1998                 goto err1;
1999         }
2000
2001         if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
2002                 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
2003                 omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk;
2004         }
2005
2006         device_init_wakeup(&pdev->dev, true);
2007         pm_runtime_enable(host->dev);
2008         pm_runtime_get_sync(host->dev);
2009         pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
2010         pm_runtime_use_autosuspend(host->dev);
2011
2012         omap_hsmmc_context_save(host);
2013
2014         host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck");
2015         /*
2016          * MMC can still work without debounce clock.
2017          */
2018         if (IS_ERR(host->dbclk)) {
2019                 host->dbclk = NULL;
2020         } else if (clk_prepare_enable(host->dbclk) != 0) {
2021                 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
2022                 host->dbclk = NULL;
2023         }
2024
2025         /* Since we do only SG emulation, we can have as many segs
2026          * as we want. */
2027         mmc->max_segs = 1024;
2028
2029         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
2030         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
2031         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2032         mmc->max_seg_size = mmc->max_req_size;
2033
2034         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
2035                      MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
2036
2037         mmc->caps |= mmc_pdata(host)->caps;
2038         if (mmc->caps & MMC_CAP_8_BIT_DATA)
2039                 mmc->caps |= MMC_CAP_4_BIT_DATA;
2040
2041         if (mmc_pdata(host)->nonremovable)
2042                 mmc->caps |= MMC_CAP_NONREMOVABLE;
2043
2044         mmc->pm_caps |= mmc_pdata(host)->pm_caps;
2045
2046         omap_hsmmc_conf_bus_power(host);
2047
2048         if (!pdev->dev.of_node) {
2049                 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
2050                 if (!res) {
2051                         dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
2052                         ret = -ENXIO;
2053                         goto err_irq;
2054                 }
2055                 tx_req = res->start;
2056
2057                 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
2058                 if (!res) {
2059                         dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
2060                         ret = -ENXIO;
2061                         goto err_irq;
2062                 }
2063                 rx_req = res->start;
2064         }
2065
2066         dma_cap_zero(mask);
2067         dma_cap_set(DMA_SLAVE, mask);
2068
2069         host->rx_chan =
2070                 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
2071                                                  &rx_req, &pdev->dev, "rx");
2072
2073         if (!host->rx_chan) {
2074                 dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req);
2075                 ret = -ENXIO;
2076                 goto err_irq;
2077         }
2078
2079         host->tx_chan =
2080                 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
2081                                                  &tx_req, &pdev->dev, "tx");
2082
2083         if (!host->tx_chan) {
2084                 dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req);
2085                 ret = -ENXIO;
2086                 goto err_irq;
2087         }
2088
2089         /* Request IRQ for MMC operations */
2090         ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0,
2091                         mmc_hostname(mmc), host);
2092         if (ret) {
2093                 dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2094                 goto err_irq;
2095         }
2096
2097         if (omap_hsmmc_have_reg()) {
2098                 ret = omap_hsmmc_reg_get(host);
2099                 if (ret)
2100                         goto err_irq;
2101         }
2102
2103         mmc->ocr_avail = mmc_pdata(host)->ocr_mask;
2104
2105         omap_hsmmc_disable_irq(host);
2106
2107         /*
2108          * For now, only support SDIO interrupt if we have a separate
2109          * wake-up interrupt configured from device tree. This is because
2110          * the wake-up interrupt is needed for idle state and some
2111          * platforms need special quirks. And we don't want to add new
2112          * legacy mux platform init code callbacks any longer as we
2113          * are moving to DT based booting anyways.
2114          */
2115         ret = omap_hsmmc_configure_wake_irq(host);
2116         if (!ret)
2117                 mmc->caps |= MMC_CAP_SDIO_IRQ;
2118
2119         omap_hsmmc_protect_card(host);
2120
2121         mmc_add_host(mmc);
2122
2123         if (mmc_pdata(host)->name != NULL) {
2124                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2125                 if (ret < 0)
2126                         goto err_slot_name;
2127         }
2128         if (host->get_cover_state) {
2129                 ret = device_create_file(&mmc->class_dev,
2130                                          &dev_attr_cover_switch);
2131                 if (ret < 0)
2132                         goto err_slot_name;
2133         }
2134
2135         omap_hsmmc_debugfs(mmc);
2136         pm_runtime_mark_last_busy(host->dev);
2137         pm_runtime_put_autosuspend(host->dev);
2138
2139         return 0;
2140
2141 err_slot_name:
2142         mmc_remove_host(mmc);
2143 err_irq:
2144         device_init_wakeup(&pdev->dev, false);
2145         if (host->tx_chan)
2146                 dma_release_channel(host->tx_chan);
2147         if (host->rx_chan)
2148                 dma_release_channel(host->rx_chan);
2149         pm_runtime_put_sync(host->dev);
2150         pm_runtime_disable(host->dev);
2151         if (host->dbclk)
2152                 clk_disable_unprepare(host->dbclk);
2153 err1:
2154 err_gpio:
2155         mmc_free_host(mmc);
2156 err:
2157         return ret;
2158 }
2159
2160 static int omap_hsmmc_remove(struct platform_device *pdev)
2161 {
2162         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2163
2164         pm_runtime_get_sync(host->dev);
2165         mmc_remove_host(host->mmc);
2166
2167         if (host->tx_chan)
2168                 dma_release_channel(host->tx_chan);
2169         if (host->rx_chan)
2170                 dma_release_channel(host->rx_chan);
2171
2172         pm_runtime_put_sync(host->dev);
2173         pm_runtime_disable(host->dev);
2174         device_init_wakeup(&pdev->dev, false);
2175         if (host->dbclk)
2176                 clk_disable_unprepare(host->dbclk);
2177
2178         mmc_free_host(host->mmc);
2179
2180         return 0;
2181 }
2182
2183 #ifdef CONFIG_PM_SLEEP
2184 static int omap_hsmmc_suspend(struct device *dev)
2185 {
2186         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2187
2188         if (!host)
2189                 return 0;
2190
2191         pm_runtime_get_sync(host->dev);
2192
2193         if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2194                 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2195                 OMAP_HSMMC_WRITE(host->base, IE, 0);
2196                 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2197                 OMAP_HSMMC_WRITE(host->base, HCTL,
2198                                 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2199         }
2200
2201         if (host->dbclk)
2202                 clk_disable_unprepare(host->dbclk);
2203
2204         pm_runtime_put_sync(host->dev);
2205         return 0;
2206 }
2207
2208 /* Routine to resume the MMC device */
2209 static int omap_hsmmc_resume(struct device *dev)
2210 {
2211         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2212
2213         if (!host)
2214                 return 0;
2215
2216         pm_runtime_get_sync(host->dev);
2217
2218         if (host->dbclk)
2219                 clk_prepare_enable(host->dbclk);
2220
2221         if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2222                 omap_hsmmc_conf_bus_power(host);
2223
2224         omap_hsmmc_protect_card(host);
2225         pm_runtime_mark_last_busy(host->dev);
2226         pm_runtime_put_autosuspend(host->dev);
2227         return 0;
2228 }
2229 #endif
2230
2231 static int omap_hsmmc_runtime_suspend(struct device *dev)
2232 {
2233         struct omap_hsmmc_host *host;
2234         unsigned long flags;
2235         int ret = 0;
2236
2237         host = platform_get_drvdata(to_platform_device(dev));
2238         omap_hsmmc_context_save(host);
2239         dev_dbg(dev, "disabled\n");
2240
2241         spin_lock_irqsave(&host->irq_lock, flags);
2242         if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2243             (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2244                 /* disable sdio irq handling to prevent race */
2245                 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2246                 OMAP_HSMMC_WRITE(host->base, IE, 0);
2247
2248                 if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) {
2249                         /*
2250                          * dat1 line low, pending sdio irq
2251                          * race condition: possible irq handler running on
2252                          * multi-core, abort
2253                          */
2254                         dev_dbg(dev, "pending sdio irq, abort suspend\n");
2255                         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2256                         OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2257                         OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2258                         pm_runtime_mark_last_busy(dev);
2259                         ret = -EBUSY;
2260                         goto abort;
2261                 }
2262
2263                 pinctrl_pm_select_idle_state(dev);
2264         } else {
2265                 pinctrl_pm_select_idle_state(dev);
2266         }
2267
2268 abort:
2269         spin_unlock_irqrestore(&host->irq_lock, flags);
2270         return ret;
2271 }
2272
2273 static int omap_hsmmc_runtime_resume(struct device *dev)
2274 {
2275         struct omap_hsmmc_host *host;
2276         unsigned long flags;
2277
2278         host = platform_get_drvdata(to_platform_device(dev));
2279         omap_hsmmc_context_restore(host);
2280         dev_dbg(dev, "enabled\n");
2281
2282         spin_lock_irqsave(&host->irq_lock, flags);
2283         if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2284             (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2285
2286                 pinctrl_pm_select_default_state(host->dev);
2287
2288                 /* irq lost, if pinmux incorrect */
2289                 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2290                 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2291                 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2292         } else {
2293                 pinctrl_pm_select_default_state(host->dev);
2294         }
2295         spin_unlock_irqrestore(&host->irq_lock, flags);
2296         return 0;
2297 }
2298
2299 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2300         SET_SYSTEM_SLEEP_PM_OPS(omap_hsmmc_suspend, omap_hsmmc_resume)
2301         .runtime_suspend = omap_hsmmc_runtime_suspend,
2302         .runtime_resume = omap_hsmmc_runtime_resume,
2303 };
2304
2305 static struct platform_driver omap_hsmmc_driver = {
2306         .probe          = omap_hsmmc_probe,
2307         .remove         = omap_hsmmc_remove,
2308         .driver         = {
2309                 .name = DRIVER_NAME,
2310                 .pm = &omap_hsmmc_dev_pm_ops,
2311                 .of_match_table = of_match_ptr(omap_mmc_of_match),
2312         },
2313 };
2314
2315 module_platform_driver(omap_hsmmc_driver);
2316 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2317 MODULE_LICENSE("GPL");
2318 MODULE_ALIAS("platform:" DRIVER_NAME);
2319 MODULE_AUTHOR("Texas Instruments Inc");