2 * drivers/mmc/host/omap_hsmmc.c
4 * Driver for OMAP2430/3430 MMC controller.
6 * Copyright (C) 2007 Texas Instruments.
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/debugfs.h>
22 #include <linux/dmaengine.h>
23 #include <linux/seq_file.h>
24 #include <linux/interrupt.h>
25 #include <linux/delay.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/platform_device.h>
28 #include <linux/timer.h>
29 #include <linux/clk.h>
31 #include <linux/of_gpio.h>
32 #include <linux/of_device.h>
33 #include <linux/omap-dma.h>
34 #include <linux/mmc/host.h>
35 #include <linux/mmc/core.h>
36 #include <linux/mmc/mmc.h>
38 #include <linux/gpio.h>
39 #include <linux/regulator/consumer.h>
40 #include <linux/pm_runtime.h>
41 #include <mach/hardware.h>
45 /* OMAP HSMMC Host Controller Registers */
46 #define OMAP_HSMMC_SYSSTATUS 0x0014
47 #define OMAP_HSMMC_CON 0x002C
48 #define OMAP_HSMMC_BLK 0x0104
49 #define OMAP_HSMMC_ARG 0x0108
50 #define OMAP_HSMMC_CMD 0x010C
51 #define OMAP_HSMMC_RSP10 0x0110
52 #define OMAP_HSMMC_RSP32 0x0114
53 #define OMAP_HSMMC_RSP54 0x0118
54 #define OMAP_HSMMC_RSP76 0x011C
55 #define OMAP_HSMMC_DATA 0x0120
56 #define OMAP_HSMMC_HCTL 0x0128
57 #define OMAP_HSMMC_SYSCTL 0x012C
58 #define OMAP_HSMMC_STAT 0x0130
59 #define OMAP_HSMMC_IE 0x0134
60 #define OMAP_HSMMC_ISE 0x0138
61 #define OMAP_HSMMC_CAPA 0x0140
63 #define VS18 (1 << 26)
64 #define VS30 (1 << 25)
65 #define SDVS18 (0x5 << 9)
66 #define SDVS30 (0x6 << 9)
67 #define SDVS33 (0x7 << 9)
68 #define SDVS_MASK 0x00000E00
69 #define SDVSCLR 0xFFFFF1FF
70 #define SDVSDET 0x00000400
77 #define CLKD_MASK 0x0000FFC0
79 #define DTO_MASK 0x000F0000
81 #define INT_EN_MASK 0x307F0033
82 #define BWR_ENABLE (1 << 4)
83 #define BRR_ENABLE (1 << 5)
84 #define DTO_ENABLE (1 << 20)
85 #define INIT_STREAM (1 << 1)
86 #define DP_SELECT (1 << 21)
91 #define FOUR_BIT (1 << 1)
98 #define CMD_TIMEOUT (1 << 16)
99 #define DATA_TIMEOUT (1 << 20)
100 #define CMD_CRC (1 << 17)
101 #define DATA_CRC (1 << 21)
102 #define CARD_ERR (1 << 28)
103 #define STAT_CLEAR 0xFFFFFFFF
104 #define INIT_STREAM_CMD 0x00000000
105 #define DUAL_VOLT_OCR_BIT 7
106 #define SRC (1 << 25)
107 #define SRD (1 << 26)
108 #define SOFTRESET (1 << 1)
109 #define RESETDONE (1 << 0)
111 #define MMC_AUTOSUSPEND_DELAY 100
112 #define MMC_TIMEOUT_MS 20
113 #define OMAP_MMC_MIN_CLOCK 400000
114 #define OMAP_MMC_MAX_CLOCK 52000000
115 #define DRIVER_NAME "omap_hsmmc"
118 * One controller can have multiple slots, like on some omap boards using
119 * omap.c controller driver. Luckily this is not currently done on any known
120 * omap_hsmmc.c device.
122 #define mmc_slot(host) (host->pdata->slots[host->slot_id])
125 * MMC Host controller read/write API's
127 #define OMAP_HSMMC_READ(base, reg) \
128 __raw_readl((base) + OMAP_HSMMC_##reg)
130 #define OMAP_HSMMC_WRITE(base, reg, val) \
131 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
133 struct omap_hsmmc_next {
134 unsigned int dma_len;
138 struct omap_hsmmc_host {
140 struct mmc_host *mmc;
141 struct mmc_request *mrq;
142 struct mmc_command *cmd;
143 struct mmc_data *data;
147 * vcc == configured supply
148 * vcc_aux == optional
149 * - MMC1, supply for DAT4..DAT7
150 * - MMC2/MMC2, external level shifter voltage supply, for
151 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
153 struct regulator *vcc;
154 struct regulator *vcc_aux;
156 resource_size_t mapbase;
157 spinlock_t irq_lock; /* Prevent races with irq handler */
158 unsigned int dma_len;
159 unsigned int dma_sg_idx;
160 unsigned char bus_mode;
161 unsigned char power_mode;
165 struct dma_chan *tx_chan;
166 struct dma_chan *rx_chan;
174 struct omap_hsmmc_next next_data;
176 struct omap_mmc_platform_data *pdata;
179 static int omap_hsmmc_card_detect(struct device *dev, int slot)
181 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
182 struct omap_mmc_platform_data *mmc = host->pdata;
184 /* NOTE: assumes card detect signal is active-low */
185 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
188 static int omap_hsmmc_get_wp(struct device *dev, int slot)
190 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
191 struct omap_mmc_platform_data *mmc = host->pdata;
193 /* NOTE: assumes write protect signal is active-high */
194 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
197 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
199 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
200 struct omap_mmc_platform_data *mmc = host->pdata;
202 /* NOTE: assumes card detect signal is active-low */
203 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
208 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
210 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
211 struct omap_mmc_platform_data *mmc = host->pdata;
213 disable_irq(mmc->slots[0].card_detect_irq);
217 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
219 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
220 struct omap_mmc_platform_data *mmc = host->pdata;
222 enable_irq(mmc->slots[0].card_detect_irq);
228 #define omap_hsmmc_suspend_cdirq NULL
229 #define omap_hsmmc_resume_cdirq NULL
233 #ifdef CONFIG_REGULATOR
235 static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on,
238 struct omap_hsmmc_host *host =
239 platform_get_drvdata(to_platform_device(dev));
243 * If we don't see a Vcc regulator, assume it's a fixed
244 * voltage always-on regulator.
249 * With DT, never turn OFF the regulator. This is because
250 * the pbias cell programming support is still missing when
251 * booting with Device tree
253 if (dev->of_node && !vdd)
256 if (mmc_slot(host).before_set_reg)
257 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
260 * Assume Vcc regulator is used only to power the card ... OMAP
261 * VDDS is used to power the pins, optionally with a transceiver to
262 * support cards using voltages other than VDDS (1.8V nominal). When a
263 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
265 * In some cases this regulator won't support enable/disable;
266 * e.g. it's a fixed rail for a WLAN chip.
268 * In other cases vcc_aux switches interface power. Example, for
269 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
270 * chips/cards need an interface voltage rail too.
273 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
274 /* Enable interface voltage rail, if needed */
275 if (ret == 0 && host->vcc_aux) {
276 ret = regulator_enable(host->vcc_aux);
278 ret = mmc_regulator_set_ocr(host->mmc,
282 /* Shut down the rail */
284 ret = regulator_disable(host->vcc_aux);
286 /* Then proceed to shut down the local regulator */
287 ret = mmc_regulator_set_ocr(host->mmc,
292 if (mmc_slot(host).after_set_reg)
293 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
298 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
300 struct regulator *reg;
303 reg = regulator_get(host->dev, "vmmc");
305 dev_dbg(host->dev, "vmmc regulator missing\n");
308 mmc_slot(host).set_power = omap_hsmmc_set_power;
310 ocr_value = mmc_regulator_get_ocrmask(reg);
311 if (!mmc_slot(host).ocr_mask) {
312 mmc_slot(host).ocr_mask = ocr_value;
314 if (!(mmc_slot(host).ocr_mask & ocr_value)) {
315 dev_err(host->dev, "ocrmask %x is not supported\n",
316 mmc_slot(host).ocr_mask);
317 mmc_slot(host).ocr_mask = 0;
322 /* Allow an aux regulator */
323 reg = regulator_get(host->dev, "vmmc_aux");
324 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
326 /* For eMMC do not power off when not in sleep state */
327 if (mmc_slot(host).no_regulator_off_init)
330 * UGLY HACK: workaround regulator framework bugs.
331 * When the bootloader leaves a supply active, it's
332 * initialized with zero usecount ... and we can't
333 * disable it without first enabling it. Until the
334 * framework is fixed, we need a workaround like this
335 * (which is safe for MMC, but not in general).
337 if (regulator_is_enabled(host->vcc) > 0 ||
338 (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
339 int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
341 mmc_slot(host).set_power(host->dev, host->slot_id,
343 mmc_slot(host).set_power(host->dev, host->slot_id,
351 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
353 regulator_put(host->vcc);
354 regulator_put(host->vcc_aux);
355 mmc_slot(host).set_power = NULL;
358 static inline int omap_hsmmc_have_reg(void)
365 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
370 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
374 static inline int omap_hsmmc_have_reg(void)
381 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
385 if (gpio_is_valid(pdata->slots[0].switch_pin)) {
386 if (pdata->slots[0].cover)
387 pdata->slots[0].get_cover_state =
388 omap_hsmmc_get_cover_state;
390 pdata->slots[0].card_detect = omap_hsmmc_card_detect;
391 pdata->slots[0].card_detect_irq =
392 gpio_to_irq(pdata->slots[0].switch_pin);
393 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
396 ret = gpio_direction_input(pdata->slots[0].switch_pin);
400 pdata->slots[0].switch_pin = -EINVAL;
402 if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
403 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
404 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
407 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
411 pdata->slots[0].gpio_wp = -EINVAL;
416 gpio_free(pdata->slots[0].gpio_wp);
418 if (gpio_is_valid(pdata->slots[0].switch_pin))
420 gpio_free(pdata->slots[0].switch_pin);
424 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
426 if (gpio_is_valid(pdata->slots[0].gpio_wp))
427 gpio_free(pdata->slots[0].gpio_wp);
428 if (gpio_is_valid(pdata->slots[0].switch_pin))
429 gpio_free(pdata->slots[0].switch_pin);
433 * Start clock to the card
435 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
437 OMAP_HSMMC_WRITE(host->base, SYSCTL,
438 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
442 * Stop clock to the card
444 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
446 OMAP_HSMMC_WRITE(host->base, SYSCTL,
447 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
448 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
449 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
452 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
453 struct mmc_command *cmd)
455 unsigned int irq_mask;
458 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
460 irq_mask = INT_EN_MASK;
462 /* Disable timeout for erases */
463 if (cmd->opcode == MMC_ERASE)
464 irq_mask &= ~DTO_ENABLE;
466 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
467 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
468 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
471 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
473 OMAP_HSMMC_WRITE(host->base, ISE, 0);
474 OMAP_HSMMC_WRITE(host->base, IE, 0);
475 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
478 /* Calculate divisor for the given clock frequency */
479 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
484 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
492 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
494 struct mmc_ios *ios = &host->mmc->ios;
495 unsigned long regval;
496 unsigned long timeout;
498 dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
500 omap_hsmmc_stop_clock(host);
502 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
503 regval = regval & ~(CLKD_MASK | DTO_MASK);
504 regval = regval | (calc_divisor(host, ios) << 6) | (DTO << 16);
505 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
506 OMAP_HSMMC_WRITE(host->base, SYSCTL,
507 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
509 /* Wait till the ICS bit is set */
510 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
511 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
512 && time_before(jiffies, timeout))
515 omap_hsmmc_start_clock(host);
518 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
520 struct mmc_ios *ios = &host->mmc->ios;
523 con = OMAP_HSMMC_READ(host->base, CON);
524 if (ios->timing == MMC_TIMING_UHS_DDR50)
525 con |= DDR; /* configure in DDR mode */
528 switch (ios->bus_width) {
529 case MMC_BUS_WIDTH_8:
530 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
532 case MMC_BUS_WIDTH_4:
533 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
534 OMAP_HSMMC_WRITE(host->base, HCTL,
535 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
537 case MMC_BUS_WIDTH_1:
538 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
539 OMAP_HSMMC_WRITE(host->base, HCTL,
540 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
545 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
547 struct mmc_ios *ios = &host->mmc->ios;
550 con = OMAP_HSMMC_READ(host->base, CON);
551 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
552 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
554 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
560 * Restore the MMC host context, if it was lost as result of a
561 * power state change.
563 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
565 struct mmc_ios *ios = &host->mmc->ios;
566 struct omap_mmc_platform_data *pdata = host->pdata;
567 int context_loss = 0;
569 unsigned long timeout;
571 if (pdata->get_context_loss_count) {
572 context_loss = pdata->get_context_loss_count(host->dev);
573 if (context_loss < 0)
577 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
578 context_loss == host->context_loss ? "not " : "");
579 if (host->context_loss == context_loss)
582 if (!OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE)
585 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
586 if (host->power_mode != MMC_POWER_OFF &&
587 (1 << ios->vdd) <= MMC_VDD_23_24)
597 OMAP_HSMMC_WRITE(host->base, HCTL,
598 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
600 OMAP_HSMMC_WRITE(host->base, CAPA,
601 OMAP_HSMMC_READ(host->base, CAPA) | capa);
603 OMAP_HSMMC_WRITE(host->base, HCTL,
604 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
606 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
607 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
608 && time_before(jiffies, timeout))
611 omap_hsmmc_disable_irq(host);
613 /* Do not initialize card-specific things if the power is off */
614 if (host->power_mode == MMC_POWER_OFF)
617 omap_hsmmc_set_bus_width(host);
619 omap_hsmmc_set_clock(host);
621 omap_hsmmc_set_bus_mode(host);
624 host->context_loss = context_loss;
626 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
631 * Save the MMC host context (store the number of power state changes so far).
633 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
635 struct omap_mmc_platform_data *pdata = host->pdata;
638 if (pdata->get_context_loss_count) {
639 context_loss = pdata->get_context_loss_count(host->dev);
640 if (context_loss < 0)
642 host->context_loss = context_loss;
648 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
653 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
660 * Send init stream sequence to card
661 * before sending IDLE command
663 static void send_init_stream(struct omap_hsmmc_host *host)
666 unsigned long timeout;
668 if (host->protect_card)
671 disable_irq(host->irq);
673 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
674 OMAP_HSMMC_WRITE(host->base, CON,
675 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
676 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
678 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
679 while ((reg != CC) && time_before(jiffies, timeout))
680 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
682 OMAP_HSMMC_WRITE(host->base, CON,
683 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
685 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
686 OMAP_HSMMC_READ(host->base, STAT);
688 enable_irq(host->irq);
692 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
696 if (mmc_slot(host).get_cover_state)
697 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
702 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
705 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
706 struct omap_hsmmc_host *host = mmc_priv(mmc);
708 return sprintf(buf, "%s\n",
709 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
712 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
715 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
718 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
719 struct omap_hsmmc_host *host = mmc_priv(mmc);
721 return sprintf(buf, "%s\n", mmc_slot(host).name);
724 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
727 * Configure the response type and send the cmd.
730 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
731 struct mmc_data *data)
733 int cmdreg = 0, resptype = 0, cmdtype = 0;
735 dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
736 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
739 omap_hsmmc_enable_irq(host, cmd);
741 host->response_busy = 0;
742 if (cmd->flags & MMC_RSP_PRESENT) {
743 if (cmd->flags & MMC_RSP_136)
745 else if (cmd->flags & MMC_RSP_BUSY) {
747 host->response_busy = 1;
753 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
754 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
755 * a val of 0x3, rest 0x0.
757 if (cmd == host->mrq->stop)
760 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
763 cmdreg |= DP_SELECT | MSBS | BCE;
764 if (data->flags & MMC_DATA_READ)
773 host->req_in_progress = 1;
775 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
776 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
780 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
782 if (data->flags & MMC_DATA_WRITE)
783 return DMA_TO_DEVICE;
785 return DMA_FROM_DEVICE;
788 static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
789 struct mmc_data *data)
791 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
794 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
799 spin_lock_irqsave(&host->irq_lock, flags);
800 host->req_in_progress = 0;
801 dma_ch = host->dma_ch;
802 spin_unlock_irqrestore(&host->irq_lock, flags);
804 omap_hsmmc_disable_irq(host);
805 /* Do not complete the request if DMA is still in progress */
806 if (mrq->data && host->use_dma && dma_ch != -1)
809 mmc_request_done(host->mmc, mrq);
813 * Notify the transfer complete to MMC core
816 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
819 struct mmc_request *mrq = host->mrq;
821 /* TC before CC from CMD6 - don't know why, but it happens */
822 if (host->cmd && host->cmd->opcode == 6 &&
823 host->response_busy) {
824 host->response_busy = 0;
828 omap_hsmmc_request_done(host, mrq);
835 data->bytes_xfered += data->blocks * (data->blksz);
837 data->bytes_xfered = 0;
840 omap_hsmmc_request_done(host, data->mrq);
843 omap_hsmmc_start_command(host, data->stop, NULL);
847 * Notify the core about command completion
850 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
854 if (cmd->flags & MMC_RSP_PRESENT) {
855 if (cmd->flags & MMC_RSP_136) {
856 /* response type 2 */
857 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
858 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
859 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
860 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
862 /* response types 1, 1b, 3, 4, 5, 6 */
863 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
866 if ((host->data == NULL && !host->response_busy) || cmd->error)
867 omap_hsmmc_request_done(host, cmd->mrq);
871 * DMA clean up for command errors
873 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
878 host->data->error = errno;
880 spin_lock_irqsave(&host->irq_lock, flags);
881 dma_ch = host->dma_ch;
883 spin_unlock_irqrestore(&host->irq_lock, flags);
885 if (host->use_dma && dma_ch != -1) {
886 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
888 dmaengine_terminate_all(chan);
889 dma_unmap_sg(chan->device->dev,
890 host->data->sg, host->data->sg_len,
891 omap_hsmmc_get_dma_dir(host, host->data));
893 host->data->host_cookie = 0;
899 * Readable error output
901 #ifdef CONFIG_MMC_DEBUG
902 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
904 /* --- means reserved bit without definition at documentation */
905 static const char *omap_hsmmc_status_bits[] = {
906 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
907 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
908 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
909 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
915 len = sprintf(buf, "MMC IRQ 0x%x :", status);
918 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
919 if (status & (1 << i)) {
920 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
924 dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
927 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
931 #endif /* CONFIG_MMC_DEBUG */
934 * MMC controller internal state machines reset
936 * Used to reset command or data internal state machines, using respectively
937 * SRC or SRD bit of SYSCTL register
938 * Can be called from interrupt context
940 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
944 unsigned long limit = (loops_per_jiffy *
945 msecs_to_jiffies(MMC_TIMEOUT_MS));
947 OMAP_HSMMC_WRITE(host->base, SYSCTL,
948 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
951 * OMAP4 ES2 and greater has an updated reset logic.
952 * Monitor a 0->1 transition first
954 if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
955 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
961 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
965 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
966 dev_err(mmc_dev(host->mmc),
967 "Timeout waiting on controller reset in %s\n",
971 static void hsmmc_command_incomplete(struct omap_hsmmc_host *host, int err)
973 omap_hsmmc_reset_controller_fsm(host, SRC);
974 host->cmd->error = err;
977 omap_hsmmc_reset_controller_fsm(host, SRD);
978 omap_hsmmc_dma_cleanup(host, err);
983 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
985 struct mmc_data *data;
986 int end_cmd = 0, end_trans = 0;
989 dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
992 omap_hsmmc_dbg_report_irq(host, status);
993 if (status & (CMD_TIMEOUT | DATA_TIMEOUT))
994 hsmmc_command_incomplete(host, -ETIMEDOUT);
995 else if (status & (CMD_CRC | DATA_CRC))
996 hsmmc_command_incomplete(host, -EILSEQ);
999 if (host->data || host->response_busy) {
1001 host->response_busy = 0;
1005 if (end_cmd || ((status & CC) && host->cmd))
1006 omap_hsmmc_cmd_done(host, host->cmd);
1007 if ((end_trans || (status & TC)) && host->mrq)
1008 omap_hsmmc_xfer_done(host, data);
1012 * MMC controller IRQ handler
1014 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1016 struct omap_hsmmc_host *host = dev_id;
1019 status = OMAP_HSMMC_READ(host->base, STAT);
1020 while (status & INT_EN_MASK && host->req_in_progress) {
1021 omap_hsmmc_do_irq(host, status);
1023 /* Flush posted write */
1024 OMAP_HSMMC_WRITE(host->base, STAT, status);
1025 status = OMAP_HSMMC_READ(host->base, STAT);
1031 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1035 OMAP_HSMMC_WRITE(host->base, HCTL,
1036 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1037 for (i = 0; i < loops_per_jiffy; i++) {
1038 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1045 * Switch MMC interface voltage ... only relevant for MMC1.
1047 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1048 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1049 * Some chips, like eMMC ones, use internal transceivers.
1051 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1056 /* Disable the clocks */
1057 pm_runtime_put_sync(host->dev);
1059 clk_disable_unprepare(host->dbclk);
1061 /* Turn the power off */
1062 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1064 /* Turn the power ON with given VDD 1.8 or 3.0v */
1066 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1068 pm_runtime_get_sync(host->dev);
1070 clk_prepare_enable(host->dbclk);
1075 OMAP_HSMMC_WRITE(host->base, HCTL,
1076 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1077 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1080 * If a MMC dual voltage card is detected, the set_ios fn calls
1081 * this fn with VDD bit set for 1.8V. Upon card removal from the
1082 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1084 * Cope with a bit of slop in the range ... per data sheets:
1085 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1086 * but recommended values are 1.71V to 1.89V
1087 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1088 * but recommended values are 2.7V to 3.3V
1090 * Board setup code shouldn't permit anything very out-of-range.
1091 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1092 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1094 if ((1 << vdd) <= MMC_VDD_23_24)
1099 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1100 set_sd_bus_power(host);
1104 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1108 /* Protect the card while the cover is open */
1109 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1111 if (!mmc_slot(host).get_cover_state)
1114 host->reqs_blocked = 0;
1115 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1116 if (host->protect_card) {
1117 dev_info(host->dev, "%s: cover is closed, "
1118 "card is now accessible\n",
1119 mmc_hostname(host->mmc));
1120 host->protect_card = 0;
1123 if (!host->protect_card) {
1124 dev_info(host->dev, "%s: cover is open, "
1125 "card is now inaccessible\n",
1126 mmc_hostname(host->mmc));
1127 host->protect_card = 1;
1133 * irq handler to notify the core about card insertion/removal
1135 static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
1137 struct omap_hsmmc_host *host = dev_id;
1138 struct omap_mmc_slot_data *slot = &mmc_slot(host);
1141 if (host->suspended)
1144 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1146 if (slot->card_detect)
1147 carddetect = slot->card_detect(host->dev, host->slot_id);
1149 omap_hsmmc_protect_card(host);
1150 carddetect = -ENOSYS;
1154 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1156 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1160 static void omap_hsmmc_dma_callback(void *param)
1162 struct omap_hsmmc_host *host = param;
1163 struct dma_chan *chan;
1164 struct mmc_data *data;
1165 int req_in_progress;
1167 spin_lock_irq(&host->irq_lock);
1168 if (host->dma_ch < 0) {
1169 spin_unlock_irq(&host->irq_lock);
1173 data = host->mrq->data;
1174 chan = omap_hsmmc_get_dma_chan(host, data);
1175 if (!data->host_cookie)
1176 dma_unmap_sg(chan->device->dev,
1177 data->sg, data->sg_len,
1178 omap_hsmmc_get_dma_dir(host, data));
1180 req_in_progress = host->req_in_progress;
1182 spin_unlock_irq(&host->irq_lock);
1184 /* If DMA has finished after TC, complete the request */
1185 if (!req_in_progress) {
1186 struct mmc_request *mrq = host->mrq;
1189 mmc_request_done(host->mmc, mrq);
1193 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1194 struct mmc_data *data,
1195 struct omap_hsmmc_next *next,
1196 struct dma_chan *chan)
1200 if (!next && data->host_cookie &&
1201 data->host_cookie != host->next_data.cookie) {
1202 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
1203 " host->next_data.cookie %d\n",
1204 __func__, data->host_cookie, host->next_data.cookie);
1205 data->host_cookie = 0;
1208 /* Check if next job is already prepared */
1210 (!next && data->host_cookie != host->next_data.cookie)) {
1211 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
1212 omap_hsmmc_get_dma_dir(host, data));
1215 dma_len = host->next_data.dma_len;
1216 host->next_data.dma_len = 0;
1224 next->dma_len = dma_len;
1225 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1227 host->dma_len = dma_len;
1233 * Routine to configure and start DMA for the MMC card
1235 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1236 struct mmc_request *req)
1238 struct dma_slave_config cfg;
1239 struct dma_async_tx_descriptor *tx;
1241 struct mmc_data *data = req->data;
1242 struct dma_chan *chan;
1244 /* Sanity check: all the SG entries must be aligned by block size. */
1245 for (i = 0; i < data->sg_len; i++) {
1246 struct scatterlist *sgl;
1249 if (sgl->length % data->blksz)
1252 if ((data->blksz % 4) != 0)
1253 /* REVISIT: The MMC buffer increments only when MSB is written.
1254 * Return error for blksz which is non multiple of four.
1258 BUG_ON(host->dma_ch != -1);
1260 chan = omap_hsmmc_get_dma_chan(host, data);
1262 cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA;
1263 cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA;
1264 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1265 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1266 cfg.src_maxburst = data->blksz / 4;
1267 cfg.dst_maxburst = data->blksz / 4;
1269 ret = dmaengine_slave_config(chan, &cfg);
1273 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
1277 tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
1278 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1279 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1281 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
1282 /* FIXME: cleanup */
1286 tx->callback = omap_hsmmc_dma_callback;
1287 tx->callback_param = host;
1290 dmaengine_submit(tx);
1294 dma_async_issue_pending(chan);
1299 static void set_data_timeout(struct omap_hsmmc_host *host,
1300 unsigned int timeout_ns,
1301 unsigned int timeout_clks)
1303 unsigned int timeout, cycle_ns;
1304 uint32_t reg, clkd, dto = 0;
1306 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1307 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1311 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
1312 timeout = timeout_ns / cycle_ns;
1313 timeout += timeout_clks;
1315 while ((timeout & 0x80000000) == 0) {
1332 reg |= dto << DTO_SHIFT;
1333 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1337 * Configure block length for MMC/SD cards and initiate the transfer.
1340 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1343 host->data = req->data;
1345 if (req->data == NULL) {
1346 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1348 * Set an arbitrary 100ms data timeout for commands with
1351 if (req->cmd->flags & MMC_RSP_BUSY)
1352 set_data_timeout(host, 100000000U, 0);
1356 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1357 | (req->data->blocks << 16));
1358 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
1360 if (host->use_dma) {
1361 ret = omap_hsmmc_start_dma_transfer(host, req);
1363 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1370 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1373 struct omap_hsmmc_host *host = mmc_priv(mmc);
1374 struct mmc_data *data = mrq->data;
1376 if (host->use_dma && data->host_cookie) {
1377 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
1379 dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
1380 omap_hsmmc_get_dma_dir(host, data));
1381 data->host_cookie = 0;
1385 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1388 struct omap_hsmmc_host *host = mmc_priv(mmc);
1390 if (mrq->data->host_cookie) {
1391 mrq->data->host_cookie = 0;
1395 if (host->use_dma) {
1396 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
1398 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1399 &host->next_data, c))
1400 mrq->data->host_cookie = 0;
1405 * Request function. for read/write operation
1407 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1409 struct omap_hsmmc_host *host = mmc_priv(mmc);
1412 BUG_ON(host->req_in_progress);
1413 BUG_ON(host->dma_ch != -1);
1414 if (host->protect_card) {
1415 if (host->reqs_blocked < 3) {
1417 * Ensure the controller is left in a consistent
1418 * state by resetting the command and data state
1421 omap_hsmmc_reset_controller_fsm(host, SRD);
1422 omap_hsmmc_reset_controller_fsm(host, SRC);
1423 host->reqs_blocked += 1;
1425 req->cmd->error = -EBADF;
1427 req->data->error = -EBADF;
1428 req->cmd->retries = 0;
1429 mmc_request_done(mmc, req);
1431 } else if (host->reqs_blocked)
1432 host->reqs_blocked = 0;
1433 WARN_ON(host->mrq != NULL);
1435 err = omap_hsmmc_prepare_data(host, req);
1437 req->cmd->error = err;
1439 req->data->error = err;
1441 mmc_request_done(mmc, req);
1445 omap_hsmmc_start_command(host, req->cmd, req->data);
1448 /* Routine to configure clock values. Exposed API to core */
1449 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1451 struct omap_hsmmc_host *host = mmc_priv(mmc);
1452 int do_send_init_stream = 0;
1454 pm_runtime_get_sync(host->dev);
1456 if (ios->power_mode != host->power_mode) {
1457 switch (ios->power_mode) {
1459 mmc_slot(host).set_power(host->dev, host->slot_id,
1463 mmc_slot(host).set_power(host->dev, host->slot_id,
1467 do_send_init_stream = 1;
1470 host->power_mode = ios->power_mode;
1473 /* FIXME: set registers based only on changes to ios */
1475 omap_hsmmc_set_bus_width(host);
1477 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1478 /* Only MMC1 can interface at 3V without some flavor
1479 * of external transceiver; but they all handle 1.8V.
1481 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1482 (ios->vdd == DUAL_VOLT_OCR_BIT) &&
1484 * With pbias cell programming missing, this
1485 * can't be allowed when booting with device
1488 !host->dev->of_node) {
1490 * The mmc_select_voltage fn of the core does
1491 * not seem to set the power_mode to
1492 * MMC_POWER_UP upon recalculating the voltage.
1495 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1496 dev_dbg(mmc_dev(host->mmc),
1497 "Switch operation failed\n");
1501 omap_hsmmc_set_clock(host);
1503 if (do_send_init_stream)
1504 send_init_stream(host);
1506 omap_hsmmc_set_bus_mode(host);
1508 pm_runtime_put_autosuspend(host->dev);
1511 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1513 struct omap_hsmmc_host *host = mmc_priv(mmc);
1515 if (!mmc_slot(host).card_detect)
1517 return mmc_slot(host).card_detect(host->dev, host->slot_id);
1520 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1522 struct omap_hsmmc_host *host = mmc_priv(mmc);
1524 if (!mmc_slot(host).get_ro)
1526 return mmc_slot(host).get_ro(host->dev, 0);
1529 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1531 struct omap_hsmmc_host *host = mmc_priv(mmc);
1533 if (mmc_slot(host).init_card)
1534 mmc_slot(host).init_card(card);
1537 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1539 u32 hctl, capa, value;
1541 /* Only MMC1 supports 3.0V */
1542 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1550 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1551 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1553 value = OMAP_HSMMC_READ(host->base, CAPA);
1554 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1556 /* Set SD bus power bit */
1557 set_sd_bus_power(host);
1560 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1562 struct omap_hsmmc_host *host = mmc_priv(mmc);
1564 pm_runtime_get_sync(host->dev);
1569 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc)
1571 struct omap_hsmmc_host *host = mmc_priv(mmc);
1573 pm_runtime_mark_last_busy(host->dev);
1574 pm_runtime_put_autosuspend(host->dev);
1579 static const struct mmc_host_ops omap_hsmmc_ops = {
1580 .enable = omap_hsmmc_enable_fclk,
1581 .disable = omap_hsmmc_disable_fclk,
1582 .post_req = omap_hsmmc_post_req,
1583 .pre_req = omap_hsmmc_pre_req,
1584 .request = omap_hsmmc_request,
1585 .set_ios = omap_hsmmc_set_ios,
1586 .get_cd = omap_hsmmc_get_cd,
1587 .get_ro = omap_hsmmc_get_ro,
1588 .init_card = omap_hsmmc_init_card,
1589 /* NYET -- enable_sdio_irq */
1592 #ifdef CONFIG_DEBUG_FS
1594 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1596 struct mmc_host *mmc = s->private;
1597 struct omap_hsmmc_host *host = mmc_priv(mmc);
1598 int context_loss = 0;
1600 if (host->pdata->get_context_loss_count)
1601 context_loss = host->pdata->get_context_loss_count(host->dev);
1603 seq_printf(s, "mmc%d:\n ctx_loss:\t%d:%d\n\nregs:\n",
1604 mmc->index, host->context_loss, context_loss);
1606 if (host->suspended) {
1607 seq_printf(s, "host suspended, can't read registers\n");
1611 pm_runtime_get_sync(host->dev);
1613 seq_printf(s, "CON:\t\t0x%08x\n",
1614 OMAP_HSMMC_READ(host->base, CON));
1615 seq_printf(s, "HCTL:\t\t0x%08x\n",
1616 OMAP_HSMMC_READ(host->base, HCTL));
1617 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1618 OMAP_HSMMC_READ(host->base, SYSCTL));
1619 seq_printf(s, "IE:\t\t0x%08x\n",
1620 OMAP_HSMMC_READ(host->base, IE));
1621 seq_printf(s, "ISE:\t\t0x%08x\n",
1622 OMAP_HSMMC_READ(host->base, ISE));
1623 seq_printf(s, "CAPA:\t\t0x%08x\n",
1624 OMAP_HSMMC_READ(host->base, CAPA));
1626 pm_runtime_mark_last_busy(host->dev);
1627 pm_runtime_put_autosuspend(host->dev);
1632 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1634 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1637 static const struct file_operations mmc_regs_fops = {
1638 .open = omap_hsmmc_regs_open,
1640 .llseek = seq_lseek,
1641 .release = single_release,
1644 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1646 if (mmc->debugfs_root)
1647 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1648 mmc, &mmc_regs_fops);
1653 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1660 static u16 omap4_reg_offset = 0x100;
1662 static const struct of_device_id omap_mmc_of_match[] = {
1664 .compatible = "ti,omap2-hsmmc",
1667 .compatible = "ti,omap3-hsmmc",
1670 .compatible = "ti,omap4-hsmmc",
1671 .data = &omap4_reg_offset,
1675 MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1677 static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1679 struct omap_mmc_platform_data *pdata;
1680 struct device_node *np = dev->of_node;
1683 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1685 return NULL; /* out of memory */
1687 if (of_find_property(np, "ti,dual-volt", NULL))
1688 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1690 /* This driver only supports 1 slot */
1691 pdata->nr_slots = 1;
1692 pdata->slots[0].switch_pin = of_get_named_gpio(np, "cd-gpios", 0);
1693 pdata->slots[0].gpio_wp = of_get_named_gpio(np, "wp-gpios", 0);
1695 if (of_find_property(np, "ti,non-removable", NULL)) {
1696 pdata->slots[0].nonremovable = true;
1697 pdata->slots[0].no_regulator_off_init = true;
1699 of_property_read_u32(np, "bus-width", &bus_width);
1701 pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA;
1702 else if (bus_width == 8)
1703 pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA;
1705 if (of_find_property(np, "ti,needs-special-reset", NULL))
1706 pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
1711 static inline struct omap_mmc_platform_data
1712 *of_get_hsmmc_pdata(struct device *dev)
1718 static int omap_hsmmc_probe(struct platform_device *pdev)
1720 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1721 struct mmc_host *mmc;
1722 struct omap_hsmmc_host *host = NULL;
1723 struct resource *res;
1725 const struct of_device_id *match;
1726 dma_cap_mask_t mask;
1727 unsigned tx_req, rx_req;
1729 match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
1731 pdata = of_get_hsmmc_pdata(&pdev->dev);
1733 const u16 *offsetp = match->data;
1734 pdata->reg_offset = *offsetp;
1738 if (pdata == NULL) {
1739 dev_err(&pdev->dev, "Platform Data is missing\n");
1743 if (pdata->nr_slots == 0) {
1744 dev_err(&pdev->dev, "No Slots\n");
1748 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1749 irq = platform_get_irq(pdev, 0);
1750 if (res == NULL || irq < 0)
1753 res = request_mem_region(res->start, resource_size(res), pdev->name);
1757 ret = omap_hsmmc_gpio_init(pdata);
1761 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1767 host = mmc_priv(mmc);
1769 host->pdata = pdata;
1770 host->dev = &pdev->dev;
1775 host->mapbase = res->start + pdata->reg_offset;
1776 host->base = ioremap(host->mapbase, SZ_4K);
1777 host->power_mode = MMC_POWER_OFF;
1778 host->next_data.cookie = 1;
1780 platform_set_drvdata(pdev, host);
1782 mmc->ops = &omap_hsmmc_ops;
1785 * If regulator_disable can only put vcc_aux to sleep then there is
1788 if (mmc_slot(host).vcc_aux_disable_is_sleep)
1789 mmc_slot(host).no_off = 1;
1791 mmc->f_min = OMAP_MMC_MIN_CLOCK;
1793 if (pdata->max_freq > 0)
1794 mmc->f_max = pdata->max_freq;
1796 mmc->f_max = OMAP_MMC_MAX_CLOCK;
1798 spin_lock_init(&host->irq_lock);
1800 host->fclk = clk_get(&pdev->dev, "fck");
1801 if (IS_ERR(host->fclk)) {
1802 ret = PTR_ERR(host->fclk);
1807 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
1808 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
1809 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
1812 pm_runtime_enable(host->dev);
1813 pm_runtime_get_sync(host->dev);
1814 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1815 pm_runtime_use_autosuspend(host->dev);
1817 omap_hsmmc_context_save(host);
1819 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1821 * MMC can still work without debounce clock.
1823 if (IS_ERR(host->dbclk)) {
1824 dev_warn(mmc_dev(host->mmc), "Failed to get debounce clk\n");
1826 } else if (clk_prepare_enable(host->dbclk) != 0) {
1827 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
1828 clk_put(host->dbclk);
1832 /* Since we do only SG emulation, we can have as many segs
1834 mmc->max_segs = 1024;
1836 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1837 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1838 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1839 mmc->max_seg_size = mmc->max_req_size;
1841 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1842 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
1844 mmc->caps |= mmc_slot(host).caps;
1845 if (mmc->caps & MMC_CAP_8_BIT_DATA)
1846 mmc->caps |= MMC_CAP_4_BIT_DATA;
1848 if (mmc_slot(host).nonremovable)
1849 mmc->caps |= MMC_CAP_NONREMOVABLE;
1851 mmc->pm_caps = mmc_slot(host).pm_caps;
1853 omap_hsmmc_conf_bus_power(host);
1855 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1857 dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
1861 tx_req = res->start;
1863 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1865 dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
1869 rx_req = res->start;
1872 dma_cap_set(DMA_SLAVE, mask);
1874 host->rx_chan = dma_request_channel(mask, omap_dma_filter_fn, &rx_req);
1875 if (!host->rx_chan) {
1876 dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req);
1881 host->tx_chan = dma_request_channel(mask, omap_dma_filter_fn, &tx_req);
1882 if (!host->tx_chan) {
1883 dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req);
1888 /* Request IRQ for MMC operations */
1889 ret = request_irq(host->irq, omap_hsmmc_irq, 0,
1890 mmc_hostname(mmc), host);
1892 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1896 if (pdata->init != NULL) {
1897 if (pdata->init(&pdev->dev) != 0) {
1898 dev_dbg(mmc_dev(host->mmc),
1899 "Unable to configure MMC IRQs\n");
1900 goto err_irq_cd_init;
1904 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
1905 ret = omap_hsmmc_reg_get(host);
1911 mmc->ocr_avail = mmc_slot(host).ocr_mask;
1913 /* Request IRQ for card detect */
1914 if ((mmc_slot(host).card_detect_irq)) {
1915 ret = request_threaded_irq(mmc_slot(host).card_detect_irq,
1918 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1919 mmc_hostname(mmc), host);
1921 dev_dbg(mmc_dev(host->mmc),
1922 "Unable to grab MMC CD IRQ\n");
1925 pdata->suspend = omap_hsmmc_suspend_cdirq;
1926 pdata->resume = omap_hsmmc_resume_cdirq;
1929 omap_hsmmc_disable_irq(host);
1931 omap_hsmmc_protect_card(host);
1935 if (mmc_slot(host).name != NULL) {
1936 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1940 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
1941 ret = device_create_file(&mmc->class_dev,
1942 &dev_attr_cover_switch);
1947 omap_hsmmc_debugfs(mmc);
1948 pm_runtime_mark_last_busy(host->dev);
1949 pm_runtime_put_autosuspend(host->dev);
1954 mmc_remove_host(mmc);
1955 free_irq(mmc_slot(host).card_detect_irq, host);
1958 omap_hsmmc_reg_put(host);
1960 if (host->pdata->cleanup)
1961 host->pdata->cleanup(&pdev->dev);
1963 free_irq(host->irq, host);
1966 dma_release_channel(host->tx_chan);
1968 dma_release_channel(host->rx_chan);
1969 pm_runtime_put_sync(host->dev);
1970 pm_runtime_disable(host->dev);
1971 clk_put(host->fclk);
1973 clk_disable_unprepare(host->dbclk);
1974 clk_put(host->dbclk);
1977 iounmap(host->base);
1978 platform_set_drvdata(pdev, NULL);
1981 omap_hsmmc_gpio_free(pdata);
1983 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1985 release_mem_region(res->start, resource_size(res));
1989 static int __devexit omap_hsmmc_remove(struct platform_device *pdev)
1991 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
1992 struct resource *res;
1994 pm_runtime_get_sync(host->dev);
1995 mmc_remove_host(host->mmc);
1997 omap_hsmmc_reg_put(host);
1998 if (host->pdata->cleanup)
1999 host->pdata->cleanup(&pdev->dev);
2000 free_irq(host->irq, host);
2001 if (mmc_slot(host).card_detect_irq)
2002 free_irq(mmc_slot(host).card_detect_irq, host);
2005 dma_release_channel(host->tx_chan);
2007 dma_release_channel(host->rx_chan);
2009 pm_runtime_put_sync(host->dev);
2010 pm_runtime_disable(host->dev);
2011 clk_put(host->fclk);
2013 clk_disable_unprepare(host->dbclk);
2014 clk_put(host->dbclk);
2017 omap_hsmmc_gpio_free(host->pdata);
2018 iounmap(host->base);
2019 mmc_free_host(host->mmc);
2021 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2023 release_mem_region(res->start, resource_size(res));
2024 platform_set_drvdata(pdev, NULL);
2030 static int omap_hsmmc_suspend(struct device *dev)
2033 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2038 if (host && host->suspended)
2041 pm_runtime_get_sync(host->dev);
2042 host->suspended = 1;
2043 if (host->pdata->suspend) {
2044 ret = host->pdata->suspend(dev, host->slot_id);
2046 dev_dbg(dev, "Unable to handle MMC board"
2047 " level suspend\n");
2048 host->suspended = 0;
2052 ret = mmc_suspend_host(host->mmc);
2055 host->suspended = 0;
2056 if (host->pdata->resume) {
2057 if (host->pdata->resume(dev, host->slot_id))
2058 dev_dbg(dev, "Unmask interrupt failed\n");
2063 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2064 omap_hsmmc_disable_irq(host);
2065 OMAP_HSMMC_WRITE(host->base, HCTL,
2066 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2070 clk_disable_unprepare(host->dbclk);
2072 pm_runtime_put_sync(host->dev);
2076 /* Routine to resume the MMC device */
2077 static int omap_hsmmc_resume(struct device *dev)
2080 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2085 if (host && !host->suspended)
2088 pm_runtime_get_sync(host->dev);
2091 clk_prepare_enable(host->dbclk);
2093 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2094 omap_hsmmc_conf_bus_power(host);
2096 if (host->pdata->resume) {
2097 ret = host->pdata->resume(dev, host->slot_id);
2099 dev_dbg(dev, "Unmask interrupt failed\n");
2102 omap_hsmmc_protect_card(host);
2104 /* Notify the core to resume the host */
2105 ret = mmc_resume_host(host->mmc);
2107 host->suspended = 0;
2109 pm_runtime_mark_last_busy(host->dev);
2110 pm_runtime_put_autosuspend(host->dev);
2117 #define omap_hsmmc_suspend NULL
2118 #define omap_hsmmc_resume NULL
2121 static int omap_hsmmc_runtime_suspend(struct device *dev)
2123 struct omap_hsmmc_host *host;
2125 host = platform_get_drvdata(to_platform_device(dev));
2126 omap_hsmmc_context_save(host);
2127 dev_dbg(dev, "disabled\n");
2132 static int omap_hsmmc_runtime_resume(struct device *dev)
2134 struct omap_hsmmc_host *host;
2136 host = platform_get_drvdata(to_platform_device(dev));
2137 omap_hsmmc_context_restore(host);
2138 dev_dbg(dev, "enabled\n");
2143 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2144 .suspend = omap_hsmmc_suspend,
2145 .resume = omap_hsmmc_resume,
2146 .runtime_suspend = omap_hsmmc_runtime_suspend,
2147 .runtime_resume = omap_hsmmc_runtime_resume,
2150 static struct platform_driver omap_hsmmc_driver = {
2151 .probe = omap_hsmmc_probe,
2152 .remove = omap_hsmmc_remove,
2154 .name = DRIVER_NAME,
2155 .owner = THIS_MODULE,
2156 .pm = &omap_hsmmc_dev_pm_ops,
2157 .of_match_table = of_match_ptr(omap_mmc_of_match),
2161 module_platform_driver(omap_hsmmc_driver);
2162 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2163 MODULE_LICENSE("GPL");
2164 MODULE_ALIAS("platform:" DRIVER_NAME);
2165 MODULE_AUTHOR("Texas Instruments Inc");