1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/mmc/host/omap.c
5 * Copyright (C) 2004 Nokia Corporation
6 * Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
7 * Misc hacks here and there by Tony Lindgren <tony@atomide.com>
8 * Other hacks (DMA, SD, etc) by David Brownell
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/platform_device.h>
16 #include <linux/interrupt.h>
17 #include <linux/dmaengine.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/delay.h>
20 #include <linux/spinlock.h>
21 #include <linux/timer.h>
23 #include <linux/mmc/host.h>
24 #include <linux/mmc/card.h>
25 #include <linux/mmc/mmc.h>
26 #include <linux/clk.h>
27 #include <linux/scatterlist.h>
28 #include <linux/slab.h>
29 #include <linux/gpio/consumer.h>
30 #include <linux/platform_data/mmc-omap.h>
33 #define OMAP_MMC_REG_CMD 0x00
34 #define OMAP_MMC_REG_ARGL 0x01
35 #define OMAP_MMC_REG_ARGH 0x02
36 #define OMAP_MMC_REG_CON 0x03
37 #define OMAP_MMC_REG_STAT 0x04
38 #define OMAP_MMC_REG_IE 0x05
39 #define OMAP_MMC_REG_CTO 0x06
40 #define OMAP_MMC_REG_DTO 0x07
41 #define OMAP_MMC_REG_DATA 0x08
42 #define OMAP_MMC_REG_BLEN 0x09
43 #define OMAP_MMC_REG_NBLK 0x0a
44 #define OMAP_MMC_REG_BUF 0x0b
45 #define OMAP_MMC_REG_SDIO 0x0d
46 #define OMAP_MMC_REG_REV 0x0f
47 #define OMAP_MMC_REG_RSP0 0x10
48 #define OMAP_MMC_REG_RSP1 0x11
49 #define OMAP_MMC_REG_RSP2 0x12
50 #define OMAP_MMC_REG_RSP3 0x13
51 #define OMAP_MMC_REG_RSP4 0x14
52 #define OMAP_MMC_REG_RSP5 0x15
53 #define OMAP_MMC_REG_RSP6 0x16
54 #define OMAP_MMC_REG_RSP7 0x17
55 #define OMAP_MMC_REG_IOSR 0x18
56 #define OMAP_MMC_REG_SYSC 0x19
57 #define OMAP_MMC_REG_SYSS 0x1a
59 #define OMAP_MMC_STAT_CARD_ERR (1 << 14)
60 #define OMAP_MMC_STAT_CARD_IRQ (1 << 13)
61 #define OMAP_MMC_STAT_OCR_BUSY (1 << 12)
62 #define OMAP_MMC_STAT_A_EMPTY (1 << 11)
63 #define OMAP_MMC_STAT_A_FULL (1 << 10)
64 #define OMAP_MMC_STAT_CMD_CRC (1 << 8)
65 #define OMAP_MMC_STAT_CMD_TOUT (1 << 7)
66 #define OMAP_MMC_STAT_DATA_CRC (1 << 6)
67 #define OMAP_MMC_STAT_DATA_TOUT (1 << 5)
68 #define OMAP_MMC_STAT_END_BUSY (1 << 4)
69 #define OMAP_MMC_STAT_END_OF_DATA (1 << 3)
70 #define OMAP_MMC_STAT_CARD_BUSY (1 << 2)
71 #define OMAP_MMC_STAT_END_OF_CMD (1 << 0)
73 #define mmc_omap7xx() (host->features & MMC_OMAP7XX)
74 #define mmc_omap15xx() (host->features & MMC_OMAP15XX)
75 #define mmc_omap16xx() (host->features & MMC_OMAP16XX)
76 #define MMC_OMAP1_MASK (MMC_OMAP7XX | MMC_OMAP15XX | MMC_OMAP16XX)
77 #define mmc_omap1() (host->features & MMC_OMAP1_MASK)
78 #define mmc_omap2() (!mmc_omap1())
80 #define OMAP_MMC_REG(host, reg) (OMAP_MMC_REG_##reg << (host)->reg_shift)
81 #define OMAP_MMC_READ(host, reg) __raw_readw((host)->virt_base + OMAP_MMC_REG(host, reg))
82 #define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG(host, reg))
87 #define OMAP_MMC_CMDTYPE_BC 0
88 #define OMAP_MMC_CMDTYPE_BCR 1
89 #define OMAP_MMC_CMDTYPE_AC 2
90 #define OMAP_MMC_CMDTYPE_ADTC 3
92 #define DRIVER_NAME "mmci-omap"
94 /* Specifies how often in millisecs to poll for card status changes
95 * when the cover switch is open */
96 #define OMAP_MMC_COVER_POLL_DELAY 500
100 struct mmc_omap_slot {
106 unsigned int fclk_freq;
108 struct tasklet_struct cover_tasklet;
109 struct timer_list cover_timer;
112 struct mmc_request *mrq;
113 struct mmc_omap_host *host;
114 struct mmc_host *mmc;
115 struct gpio_desc *vsd;
116 struct gpio_desc *vio;
117 struct gpio_desc *cover;
118 struct omap_mmc_slot_data *pdata;
121 struct mmc_omap_host {
123 struct mmc_request * mrq;
124 struct mmc_command * cmd;
125 struct mmc_data * data;
126 struct mmc_host * mmc;
128 unsigned char id; /* 16xx chips have 2 MMC blocks */
131 struct dma_chan *dma_rx;
133 struct dma_chan *dma_tx;
135 void __iomem *virt_base;
136 unsigned int phys_base;
138 unsigned char bus_mode;
139 unsigned int reg_shift;
140 struct gpio_desc *slot_switch;
142 struct work_struct cmd_abort_work;
144 struct timer_list cmd_abort_timer;
146 struct work_struct slot_release_work;
147 struct mmc_omap_slot *next_slot;
148 struct work_struct send_stop_work;
149 struct mmc_data *stop_data;
151 struct sg_mapping_iter sg_miter;
153 u32 total_bytes_left;
156 unsigned brs_received:1, dma_done:1;
157 unsigned dma_in_use:1;
160 struct mmc_omap_slot *slots[OMAP_MMC_MAX_SLOTS];
161 struct mmc_omap_slot *current_slot;
162 spinlock_t slot_lock;
163 wait_queue_head_t slot_wq;
166 struct timer_list clk_timer;
167 spinlock_t clk_lock; /* for changing enabled state */
168 unsigned int fclk_enabled:1;
169 struct workqueue_struct *mmc_omap_wq;
171 struct omap_mmc_platform_data *pdata;
175 static void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot)
177 unsigned long tick_ns;
179 if (slot != NULL && slot->host->fclk_enabled && slot->fclk_freq > 0) {
180 tick_ns = DIV_ROUND_UP(NSEC_PER_SEC, slot->fclk_freq);
185 static void mmc_omap_fclk_enable(struct mmc_omap_host *host, unsigned int enable)
189 spin_lock_irqsave(&host->clk_lock, flags);
190 if (host->fclk_enabled != enable) {
191 host->fclk_enabled = enable;
193 clk_enable(host->fclk);
195 clk_disable(host->fclk);
197 spin_unlock_irqrestore(&host->clk_lock, flags);
200 static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
202 struct mmc_omap_host *host = slot->host;
207 spin_lock_irqsave(&host->slot_lock, flags);
208 while (host->mmc != NULL) {
209 spin_unlock_irqrestore(&host->slot_lock, flags);
210 wait_event(host->slot_wq, host->mmc == NULL);
211 spin_lock_irqsave(&host->slot_lock, flags);
213 host->mmc = slot->mmc;
214 spin_unlock_irqrestore(&host->slot_lock, flags);
216 del_timer(&host->clk_timer);
217 if (host->current_slot != slot || !claimed)
218 mmc_omap_fclk_offdelay(host->current_slot);
220 if (host->current_slot != slot) {
221 OMAP_MMC_WRITE(host, CON, slot->saved_con & 0xFC00);
222 if (host->slot_switch)
224 * With two slots and a simple GPIO switch, setting
225 * the GPIO to 0 selects slot ID 0, setting it to 1
228 gpiod_set_value(host->slot_switch, slot->id);
229 host->current_slot = slot;
233 mmc_omap_fclk_enable(host, 1);
235 /* Doing the dummy read here seems to work around some bug
236 * at least in OMAP24xx silicon where the command would not
237 * start after writing the CMD register. Sigh. */
238 OMAP_MMC_READ(host, CON);
240 OMAP_MMC_WRITE(host, CON, slot->saved_con);
242 mmc_omap_fclk_enable(host, 0);
245 static void mmc_omap_start_request(struct mmc_omap_host *host,
246 struct mmc_request *req);
248 static void mmc_omap_slot_release_work(struct work_struct *work)
250 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
252 struct mmc_omap_slot *next_slot = host->next_slot;
253 struct mmc_request *rq;
255 host->next_slot = NULL;
256 mmc_omap_select_slot(next_slot, 1);
259 next_slot->mrq = NULL;
260 mmc_omap_start_request(host, rq);
263 static void mmc_omap_release_slot(struct mmc_omap_slot *slot, int clk_enabled)
265 struct mmc_omap_host *host = slot->host;
269 BUG_ON(slot == NULL || host->mmc == NULL);
272 /* Keeps clock running for at least 8 cycles on valid freq */
273 mod_timer(&host->clk_timer, jiffies + HZ/10);
275 del_timer(&host->clk_timer);
276 mmc_omap_fclk_offdelay(slot);
277 mmc_omap_fclk_enable(host, 0);
280 spin_lock_irqsave(&host->slot_lock, flags);
281 /* Check for any pending requests */
282 for (i = 0; i < host->nr_slots; i++) {
283 struct mmc_omap_slot *new_slot;
285 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
288 BUG_ON(host->next_slot != NULL);
289 new_slot = host->slots[i];
290 /* The current slot should not have a request in queue */
291 BUG_ON(new_slot == host->current_slot);
293 host->next_slot = new_slot;
294 host->mmc = new_slot->mmc;
295 spin_unlock_irqrestore(&host->slot_lock, flags);
296 queue_work(host->mmc_omap_wq, &host->slot_release_work);
301 wake_up(&host->slot_wq);
302 spin_unlock_irqrestore(&host->slot_lock, flags);
306 int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
308 /* If we have a GPIO then use that */
310 return gpiod_get_value(slot->cover);
311 if (slot->pdata->get_cover_state)
312 return slot->pdata->get_cover_state(mmc_dev(slot->mmc),
318 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
321 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
322 struct mmc_omap_slot *slot = mmc_priv(mmc);
324 return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
328 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
331 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
334 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
335 struct mmc_omap_slot *slot = mmc_priv(mmc);
337 return sprintf(buf, "%s\n", slot->pdata->name);
340 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
343 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
355 /* Our hardware needs to know exact type */
356 switch (mmc_resp_type(cmd)) {
361 /* resp 1, 1b, 6, 7 */
371 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
375 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
376 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
377 } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
378 cmdtype = OMAP_MMC_CMDTYPE_BC;
379 } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
380 cmdtype = OMAP_MMC_CMDTYPE_BCR;
382 cmdtype = OMAP_MMC_CMDTYPE_AC;
385 cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
387 if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
390 if (cmd->flags & MMC_RSP_BUSY)
393 if (host->data && !(host->data->flags & MMC_DATA_WRITE))
396 mod_timer(&host->cmd_abort_timer, jiffies + HZ/2);
398 OMAP_MMC_WRITE(host, CTO, 200);
399 OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
400 OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
401 irq_mask = OMAP_MMC_STAT_A_EMPTY | OMAP_MMC_STAT_A_FULL |
402 OMAP_MMC_STAT_CMD_CRC | OMAP_MMC_STAT_CMD_TOUT |
403 OMAP_MMC_STAT_DATA_CRC | OMAP_MMC_STAT_DATA_TOUT |
404 OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR |
405 OMAP_MMC_STAT_END_OF_DATA;
406 if (cmd->opcode == MMC_ERASE)
407 irq_mask &= ~OMAP_MMC_STAT_DATA_TOUT;
408 OMAP_MMC_WRITE(host, IE, irq_mask);
409 OMAP_MMC_WRITE(host, CMD, cmdreg);
413 mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,
416 enum dma_data_direction dma_data_dir;
417 struct device *dev = mmc_dev(host->mmc);
420 if (data->flags & MMC_DATA_WRITE) {
421 dma_data_dir = DMA_TO_DEVICE;
424 dma_data_dir = DMA_FROM_DEVICE;
429 dmaengine_terminate_all(c);
430 /* Claim nothing transferred on error... */
431 data->bytes_xfered = 0;
433 dev = c->device->dev;
435 dma_unmap_sg(dev, data->sg, host->sg_len, dma_data_dir);
438 static void mmc_omap_send_stop_work(struct work_struct *work)
440 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
442 struct mmc_omap_slot *slot = host->current_slot;
443 struct mmc_data *data = host->stop_data;
444 unsigned long tick_ns;
446 tick_ns = DIV_ROUND_UP(NSEC_PER_SEC, slot->fclk_freq);
449 mmc_omap_start_command(host, data->stop);
453 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
455 if (host->dma_in_use)
456 mmc_omap_release_dma(host, data, data->error);
458 sg_miter_stop(&host->sg_miter);
463 /* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing
464 * dozens of requests until the card finishes writing data.
465 * It'd be cheaper to just wait till an EOFB interrupt arrives...
469 struct mmc_host *mmc;
473 mmc_omap_release_slot(host->current_slot, 1);
474 mmc_request_done(mmc, data->mrq);
478 host->stop_data = data;
479 queue_work(host->mmc_omap_wq, &host->send_stop_work);
483 mmc_omap_send_abort(struct mmc_omap_host *host, int maxloops)
485 struct mmc_omap_slot *slot = host->current_slot;
486 unsigned int restarts, passes, timeout;
489 /* Sending abort takes 80 clocks. Have some extra and round up */
490 timeout = DIV_ROUND_UP(120 * USEC_PER_SEC, slot->fclk_freq);
492 while (restarts < maxloops) {
493 OMAP_MMC_WRITE(host, STAT, 0xFFFF);
494 OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7));
497 while (passes < timeout) {
498 stat = OMAP_MMC_READ(host, STAT);
499 if (stat & OMAP_MMC_STAT_END_OF_CMD)
508 OMAP_MMC_WRITE(host, STAT, stat);
512 mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)
514 if (host->dma_in_use)
515 mmc_omap_release_dma(host, data, 1);
520 mmc_omap_send_abort(host, 10000);
524 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
529 if (!host->dma_in_use) {
530 mmc_omap_xfer_done(host, data);
534 spin_lock_irqsave(&host->dma_lock, flags);
538 host->brs_received = 1;
539 spin_unlock_irqrestore(&host->dma_lock, flags);
541 mmc_omap_xfer_done(host, data);
545 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
551 spin_lock_irqsave(&host->dma_lock, flags);
552 if (host->brs_received)
556 spin_unlock_irqrestore(&host->dma_lock, flags);
558 mmc_omap_xfer_done(host, data);
562 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
566 del_timer(&host->cmd_abort_timer);
568 if (cmd->flags & MMC_RSP_PRESENT) {
569 if (cmd->flags & MMC_RSP_136) {
570 /* response type 2 */
572 OMAP_MMC_READ(host, RSP0) |
573 (OMAP_MMC_READ(host, RSP1) << 16);
575 OMAP_MMC_READ(host, RSP2) |
576 (OMAP_MMC_READ(host, RSP3) << 16);
578 OMAP_MMC_READ(host, RSP4) |
579 (OMAP_MMC_READ(host, RSP5) << 16);
581 OMAP_MMC_READ(host, RSP6) |
582 (OMAP_MMC_READ(host, RSP7) << 16);
584 /* response types 1, 1b, 3, 4, 5, 6 */
586 OMAP_MMC_READ(host, RSP6) |
587 (OMAP_MMC_READ(host, RSP7) << 16);
591 if (host->data == NULL || cmd->error) {
592 struct mmc_host *mmc;
594 if (host->data != NULL)
595 mmc_omap_abort_xfer(host, host->data);
598 mmc_omap_release_slot(host->current_slot, 1);
599 mmc_request_done(mmc, cmd->mrq);
604 * Abort stuck command. Can occur when card is removed while it is being
607 static void mmc_omap_abort_command(struct work_struct *work)
609 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
613 dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n",
616 if (host->cmd->error == 0)
617 host->cmd->error = -ETIMEDOUT;
619 if (host->data == NULL) {
620 struct mmc_command *cmd;
621 struct mmc_host *mmc;
625 mmc_omap_send_abort(host, 10000);
629 mmc_omap_release_slot(host->current_slot, 1);
630 mmc_request_done(mmc, cmd->mrq);
632 mmc_omap_cmd_done(host, host->cmd);
635 enable_irq(host->irq);
639 mmc_omap_cmd_timer(struct timer_list *t)
641 struct mmc_omap_host *host = from_timer(host, t, cmd_abort_timer);
644 spin_lock_irqsave(&host->slot_lock, flags);
645 if (host->cmd != NULL && !host->abort) {
646 OMAP_MMC_WRITE(host, IE, 0);
647 disable_irq(host->irq);
649 queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
651 spin_unlock_irqrestore(&host->slot_lock, flags);
655 mmc_omap_clk_timer(struct timer_list *t)
657 struct mmc_omap_host *host = from_timer(host, t, clk_timer);
659 mmc_omap_fclk_enable(host, 0);
664 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
666 struct sg_mapping_iter *sgm = &host->sg_miter;
670 if (!sg_miter_next(sgm)) {
671 /* This should not happen */
672 dev_err(mmc_dev(host->mmc), "ran out of scatterlist prematurely\n");
680 if (n > host->total_bytes_left)
681 n = host->total_bytes_left;
683 /* Round up to handle odd number of bytes to transfer */
684 nwords = DIV_ROUND_UP(n, 2);
687 host->total_bytes_left -= n;
688 host->data->bytes_xfered += n;
691 __raw_writesw(host->virt_base + OMAP_MMC_REG(host, DATA),
694 __raw_readsw(host->virt_base + OMAP_MMC_REG(host, DATA),
699 #ifdef CONFIG_MMC_DEBUG
700 static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status)
702 static const char *mmc_omap_status_bits[] = {
703 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
704 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
707 char res[64], *buf = res;
709 buf += sprintf(buf, "MMC IRQ 0x%x:", status);
711 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
712 if (status & (1 << i))
713 buf += sprintf(buf, " %s", mmc_omap_status_bits[i]);
714 dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
717 static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status)
723 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
725 struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
729 int transfer_error, cmd_error;
731 if (host->cmd == NULL && host->data == NULL) {
732 status = OMAP_MMC_READ(host, STAT);
733 dev_info(mmc_dev(host->slots[0]->mmc),
734 "Spurious IRQ 0x%04x\n", status);
736 OMAP_MMC_WRITE(host, STAT, status);
737 OMAP_MMC_WRITE(host, IE, 0);
747 while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
750 OMAP_MMC_WRITE(host, STAT, status);
751 if (host->cmd != NULL)
752 cmd = host->cmd->opcode;
755 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
757 mmc_omap_report_irq(host, status);
759 if (host->total_bytes_left) {
760 if ((status & OMAP_MMC_STAT_A_FULL) ||
761 (status & OMAP_MMC_STAT_END_OF_DATA))
762 mmc_omap_xfer_data(host, 0);
763 if (status & OMAP_MMC_STAT_A_EMPTY)
764 mmc_omap_xfer_data(host, 1);
767 if (status & OMAP_MMC_STAT_END_OF_DATA)
770 if (status & OMAP_MMC_STAT_DATA_TOUT) {
771 dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n",
774 host->data->error = -ETIMEDOUT;
779 if (status & OMAP_MMC_STAT_DATA_CRC) {
781 host->data->error = -EILSEQ;
782 dev_dbg(mmc_dev(host->mmc),
783 "data CRC error, bytes left %d\n",
784 host->total_bytes_left);
787 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
791 if (status & OMAP_MMC_STAT_CMD_TOUT) {
792 /* Timeouts are routine with some commands */
794 struct mmc_omap_slot *slot =
797 !mmc_omap_cover_is_open(slot))
798 dev_err(mmc_dev(host->mmc),
799 "command timeout (CMD%d)\n",
801 host->cmd->error = -ETIMEDOUT;
807 if (status & OMAP_MMC_STAT_CMD_CRC) {
809 dev_err(mmc_dev(host->mmc),
810 "command CRC error (CMD%d, arg 0x%08x)\n",
811 cmd, host->cmd->arg);
812 host->cmd->error = -EILSEQ;
816 dev_err(mmc_dev(host->mmc),
817 "command CRC error without cmd?\n");
820 if (status & OMAP_MMC_STAT_CARD_ERR) {
821 dev_dbg(mmc_dev(host->mmc),
822 "ignoring card status error (CMD%d)\n",
828 * NOTE: On 1610 the END_OF_CMD may come too early when
831 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
832 (!(status & OMAP_MMC_STAT_A_EMPTY))) {
837 if (cmd_error && host->data) {
838 del_timer(&host->cmd_abort_timer);
840 OMAP_MMC_WRITE(host, IE, 0);
841 disable_irq_nosync(host->irq);
842 queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
846 if (end_command && host->cmd)
847 mmc_omap_cmd_done(host, host->cmd);
848 if (host->data != NULL) {
850 mmc_omap_xfer_done(host, host->data);
851 else if (end_transfer)
852 mmc_omap_end_of_data(host, host->data);
858 void omap_mmc_notify_cover_event(struct device *dev, int num, int is_closed)
861 struct mmc_omap_host *host = dev_get_drvdata(dev);
862 struct mmc_omap_slot *slot = host->slots[num];
864 BUG_ON(num >= host->nr_slots);
866 /* Other subsystems can call in here before we're initialised. */
867 if (host->nr_slots == 0 || !host->slots[num])
870 cover_open = mmc_omap_cover_is_open(slot);
871 if (cover_open != slot->cover_open) {
872 slot->cover_open = cover_open;
873 sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
876 tasklet_hi_schedule(&slot->cover_tasklet);
879 static void mmc_omap_cover_timer(struct timer_list *t)
881 struct mmc_omap_slot *slot = from_timer(slot, t, cover_timer);
882 tasklet_schedule(&slot->cover_tasklet);
885 static void mmc_omap_cover_handler(struct tasklet_struct *t)
887 struct mmc_omap_slot *slot = from_tasklet(slot, t, cover_tasklet);
888 int cover_open = mmc_omap_cover_is_open(slot);
890 mmc_detect_change(slot->mmc, 0);
895 * If no card is inserted, we postpone polling until
896 * the cover has been closed.
898 if (slot->mmc->card == NULL)
901 mod_timer(&slot->cover_timer,
902 jiffies + msecs_to_jiffies(OMAP_MMC_COVER_POLL_DELAY));
905 static void mmc_omap_dma_callback(void *priv)
907 struct mmc_omap_host *host = priv;
908 struct mmc_data *data = host->data;
910 /* If we got to the end of DMA, assume everything went well */
911 data->bytes_xfered += data->blocks * data->blksz;
913 mmc_omap_dma_done(host, data);
916 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
920 reg = OMAP_MMC_READ(host, SDIO);
922 OMAP_MMC_WRITE(host, SDIO, reg);
923 /* Set maximum timeout */
924 OMAP_MMC_WRITE(host, CTO, 0xfd);
927 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
929 unsigned int timeout, cycle_ns;
932 cycle_ns = 1000000000 / host->current_slot->fclk_freq;
933 timeout = req->data->timeout_ns / cycle_ns;
934 timeout += req->data->timeout_clks;
936 /* Check if we need to use timeout multiplier register */
937 reg = OMAP_MMC_READ(host, SDIO);
938 if (timeout > 0xffff) {
943 OMAP_MMC_WRITE(host, SDIO, reg);
944 OMAP_MMC_WRITE(host, DTO, timeout);
948 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
950 unsigned int miter_flags = SG_MITER_ATOMIC; /* Used from IRQ */
951 struct mmc_data *data = req->data;
952 int i, use_dma = 1, block_size;
953 struct scatterlist *sg;
958 OMAP_MMC_WRITE(host, BLEN, 0);
959 OMAP_MMC_WRITE(host, NBLK, 0);
960 OMAP_MMC_WRITE(host, BUF, 0);
961 host->dma_in_use = 0;
962 set_cmd_timeout(host, req);
966 block_size = data->blksz;
968 OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
969 OMAP_MMC_WRITE(host, BLEN, block_size - 1);
970 set_data_timeout(host, req);
972 /* cope with calling layer confusion; it issues "single
973 * block" writes using multi-block scatterlists.
975 sg_len = (data->blocks == 1) ? 1 : data->sg_len;
977 /* Only do DMA for entire blocks */
978 for_each_sg(data->sg, sg, sg_len, i) {
979 if ((sg->length % block_size) != 0) {
986 enum dma_data_direction dma_data_dir;
987 struct dma_async_tx_descriptor *tx;
993 * FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx
994 * and 24xx. Use 16 or 32 word frames when the
995 * blocksize is at least that large. Blocksize is
996 * usually 512 bytes; but not for some SD reads.
998 burst = mmc_omap15xx() ? 32 : 64;
999 if (burst > data->blksz)
1000 burst = data->blksz;
1004 if (data->flags & MMC_DATA_WRITE) {
1006 bp = &host->dma_tx_burst;
1007 buf = 0x0f80 | (burst - 1) << 0;
1008 dma_data_dir = DMA_TO_DEVICE;
1011 bp = &host->dma_rx_burst;
1012 buf = 0x800f | (burst - 1) << 8;
1013 dma_data_dir = DMA_FROM_DEVICE;
1019 /* Only reconfigure if we have a different burst size */
1021 struct dma_slave_config cfg = {
1022 .src_addr = host->phys_base +
1023 OMAP_MMC_REG(host, DATA),
1024 .dst_addr = host->phys_base +
1025 OMAP_MMC_REG(host, DATA),
1026 .src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
1027 .dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
1028 .src_maxburst = burst,
1029 .dst_maxburst = burst,
1032 if (dmaengine_slave_config(c, &cfg))
1038 host->sg_len = dma_map_sg(c->device->dev, data->sg, sg_len,
1040 if (host->sg_len == 0)
1043 tx = dmaengine_prep_slave_sg(c, data->sg, host->sg_len,
1044 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1045 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1049 OMAP_MMC_WRITE(host, BUF, buf);
1051 tx->callback = mmc_omap_dma_callback;
1052 tx->callback_param = host;
1053 dmaengine_submit(tx);
1054 host->brs_received = 0;
1056 host->dma_in_use = 1;
1061 /* Revert to PIO? */
1062 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
1063 host->total_bytes_left = data->blocks * block_size;
1064 host->sg_len = sg_len;
1065 if (data->flags & MMC_DATA_READ)
1066 miter_flags |= SG_MITER_TO_SG;
1068 miter_flags |= SG_MITER_FROM_SG;
1069 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, miter_flags);
1070 host->dma_in_use = 0;
1073 static void mmc_omap_start_request(struct mmc_omap_host *host,
1074 struct mmc_request *req)
1076 BUG_ON(host->mrq != NULL);
1080 /* only touch fifo AFTER the controller readies it */
1081 mmc_omap_prepare_data(host, req);
1082 mmc_omap_start_command(host, req->cmd);
1083 if (host->dma_in_use) {
1084 struct dma_chan *c = host->data->flags & MMC_DATA_WRITE ?
1085 host->dma_tx : host->dma_rx;
1087 dma_async_issue_pending(c);
1091 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
1093 struct mmc_omap_slot *slot = mmc_priv(mmc);
1094 struct mmc_omap_host *host = slot->host;
1095 unsigned long flags;
1097 spin_lock_irqsave(&host->slot_lock, flags);
1098 if (host->mmc != NULL) {
1099 BUG_ON(slot->mrq != NULL);
1101 spin_unlock_irqrestore(&host->slot_lock, flags);
1105 spin_unlock_irqrestore(&host->slot_lock, flags);
1106 mmc_omap_select_slot(slot, 1);
1107 mmc_omap_start_request(host, req);
1110 static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on,
1113 struct mmc_omap_host *host;
1119 gpiod_set_value(slot->vsd, power_on);
1123 gpiod_set_value(slot->vio, power_on);
1128 gpiod_set_value(slot->vio, power_on);
1132 gpiod_set_value(slot->vsd, power_on);
1137 if (slot->pdata->set_power != NULL)
1138 slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on,
1144 w = OMAP_MMC_READ(host, CON);
1145 OMAP_MMC_WRITE(host, CON, w | (1 << 11));
1147 w = OMAP_MMC_READ(host, CON);
1148 OMAP_MMC_WRITE(host, CON, w & ~(1 << 11));
1153 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
1155 struct mmc_omap_slot *slot = mmc_priv(mmc);
1156 struct mmc_omap_host *host = slot->host;
1157 int func_clk_rate = clk_get_rate(host->fclk);
1160 if (ios->clock == 0)
1163 dsor = func_clk_rate / ios->clock;
1167 if (func_clk_rate / dsor > ios->clock)
1173 slot->fclk_freq = func_clk_rate / dsor;
1175 if (ios->bus_width == MMC_BUS_WIDTH_4)
1181 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1183 struct mmc_omap_slot *slot = mmc_priv(mmc);
1184 struct mmc_omap_host *host = slot->host;
1186 int clk_enabled, init_stream;
1188 mmc_omap_select_slot(slot, 0);
1190 dsor = mmc_omap_calc_divisor(mmc, ios);
1192 if (ios->vdd != slot->vdd)
1193 slot->vdd = ios->vdd;
1197 switch (ios->power_mode) {
1199 mmc_omap_set_power(slot, 0, ios->vdd);
1202 /* Cannot touch dsor yet, just power up MMC */
1203 mmc_omap_set_power(slot, 1, ios->vdd);
1204 slot->power_mode = ios->power_mode;
1207 mmc_omap_fclk_enable(host, 1);
1210 if (slot->power_mode != MMC_POWER_ON)
1214 slot->power_mode = ios->power_mode;
1216 if (slot->bus_mode != ios->bus_mode) {
1217 if (slot->pdata->set_bus_mode != NULL)
1218 slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id,
1220 slot->bus_mode = ios->bus_mode;
1223 /* On insanely high arm_per frequencies something sometimes
1224 * goes somehow out of sync, and the POW bit is not being set,
1225 * which results in the while loop below getting stuck.
1226 * Writing to the CON register twice seems to do the trick. */
1227 for (i = 0; i < 2; i++)
1228 OMAP_MMC_WRITE(host, CON, dsor);
1229 slot->saved_con = dsor;
1231 /* worst case at 400kHz, 80 cycles makes 200 microsecs */
1234 /* Send clock cycles, poll completion */
1235 OMAP_MMC_WRITE(host, IE, 0);
1236 OMAP_MMC_WRITE(host, STAT, 0xffff);
1237 OMAP_MMC_WRITE(host, CMD, 1 << 7);
1238 while (usecs > 0 && (OMAP_MMC_READ(host, STAT) & 1) == 0) {
1242 OMAP_MMC_WRITE(host, STAT, 1);
1246 mmc_omap_release_slot(slot, clk_enabled);
1249 static const struct mmc_host_ops mmc_omap_ops = {
1250 .request = mmc_omap_request,
1251 .set_ios = mmc_omap_set_ios,
1254 static int mmc_omap_new_slot(struct mmc_omap_host *host, int id)
1256 struct mmc_omap_slot *slot = NULL;
1257 struct mmc_host *mmc;
1260 mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
1264 slot = mmc_priv(mmc);
1268 slot->power_mode = MMC_POWER_UNDEFINED;
1269 slot->pdata = &host->pdata->slots[id];
1271 /* Check for some optional GPIO controls */
1272 slot->vsd = devm_gpiod_get_index_optional(host->dev, "vsd",
1274 if (IS_ERR(slot->vsd))
1275 return dev_err_probe(host->dev, PTR_ERR(slot->vsd),
1276 "error looking up VSD GPIO\n");
1277 slot->vio = devm_gpiod_get_index_optional(host->dev, "vio",
1279 if (IS_ERR(slot->vio))
1280 return dev_err_probe(host->dev, PTR_ERR(slot->vio),
1281 "error looking up VIO GPIO\n");
1282 slot->cover = devm_gpiod_get_index_optional(host->dev, "cover",
1284 if (IS_ERR(slot->cover))
1285 return dev_err_probe(host->dev, PTR_ERR(slot->cover),
1286 "error looking up cover switch GPIO\n");
1288 host->slots[id] = slot;
1291 if (host->pdata->slots[id].wires >= 4)
1292 mmc->caps |= MMC_CAP_4_BIT_DATA;
1294 mmc->ops = &mmc_omap_ops;
1295 mmc->f_min = 400000;
1298 mmc->f_max = 48000000;
1300 mmc->f_max = 24000000;
1301 if (host->pdata->max_freq)
1302 mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
1303 mmc->ocr_avail = slot->pdata->ocr_mask;
1305 /* Use scatterlist DMA to reduce per-transfer costs.
1306 * NOTE max_seg_size assumption that small blocks aren't
1307 * normally used (except e.g. for reading SD registers).
1310 mmc->max_blk_size = 2048; /* BLEN is 11 bits (+1) */
1311 mmc->max_blk_count = 2048; /* NBLK is 11 bits (+1) */
1312 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1313 mmc->max_seg_size = mmc->max_req_size;
1315 if (slot->pdata->get_cover_state != NULL) {
1316 timer_setup(&slot->cover_timer, mmc_omap_cover_timer, 0);
1317 tasklet_setup(&slot->cover_tasklet, mmc_omap_cover_handler);
1320 r = mmc_add_host(mmc);
1322 goto err_remove_host;
1324 if (slot->pdata->name != NULL) {
1325 r = device_create_file(&mmc->class_dev,
1326 &dev_attr_slot_name);
1328 goto err_remove_host;
1331 if (slot->pdata->get_cover_state != NULL) {
1332 r = device_create_file(&mmc->class_dev,
1333 &dev_attr_cover_switch);
1335 goto err_remove_slot_name;
1336 tasklet_schedule(&slot->cover_tasklet);
1341 err_remove_slot_name:
1342 if (slot->pdata->name != NULL)
1343 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1345 mmc_remove_host(mmc);
1350 static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
1352 struct mmc_host *mmc = slot->mmc;
1354 if (slot->pdata->name != NULL)
1355 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1356 if (slot->pdata->get_cover_state != NULL)
1357 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1359 tasklet_kill(&slot->cover_tasklet);
1360 del_timer_sync(&slot->cover_timer);
1361 flush_workqueue(slot->host->mmc_omap_wq);
1363 mmc_remove_host(mmc);
1367 static int mmc_omap_probe(struct platform_device *pdev)
1369 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1370 struct mmc_omap_host *host = NULL;
1371 struct resource *res;
1375 if (pdata == NULL) {
1376 dev_err(&pdev->dev, "platform data missing\n");
1379 if (pdata->nr_slots == 0) {
1380 dev_err(&pdev->dev, "no slots\n");
1381 return -EPROBE_DEFER;
1384 host = devm_kzalloc(&pdev->dev, sizeof(struct mmc_omap_host),
1389 irq = platform_get_irq(pdev, 0);
1393 host->virt_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1394 if (IS_ERR(host->virt_base))
1395 return PTR_ERR(host->virt_base);
1397 INIT_WORK(&host->slot_release_work, mmc_omap_slot_release_work);
1398 INIT_WORK(&host->send_stop_work, mmc_omap_send_stop_work);
1400 INIT_WORK(&host->cmd_abort_work, mmc_omap_abort_command);
1401 timer_setup(&host->cmd_abort_timer, mmc_omap_cmd_timer, 0);
1403 spin_lock_init(&host->clk_lock);
1404 timer_setup(&host->clk_timer, mmc_omap_clk_timer, 0);
1406 spin_lock_init(&host->dma_lock);
1407 spin_lock_init(&host->slot_lock);
1408 init_waitqueue_head(&host->slot_wq);
1410 host->pdata = pdata;
1411 host->features = host->pdata->slots[0].features;
1412 host->dev = &pdev->dev;
1413 platform_set_drvdata(pdev, host);
1415 host->slot_switch = devm_gpiod_get_optional(host->dev, "switch",
1417 if (IS_ERR(host->slot_switch))
1418 return dev_err_probe(host->dev, PTR_ERR(host->slot_switch),
1419 "error looking up slot switch GPIO\n");
1421 host->id = pdev->id;
1423 host->phys_base = res->start;
1424 host->iclk = clk_get(&pdev->dev, "ick");
1425 if (IS_ERR(host->iclk))
1426 return PTR_ERR(host->iclk);
1427 clk_prepare_enable(host->iclk);
1429 host->fclk = clk_get(&pdev->dev, "fck");
1430 if (IS_ERR(host->fclk)) {
1431 ret = PTR_ERR(host->fclk);
1435 ret = clk_prepare(host->fclk);
1439 host->dma_tx_burst = -1;
1440 host->dma_rx_burst = -1;
1442 host->dma_tx = dma_request_chan(&pdev->dev, "tx");
1443 if (IS_ERR(host->dma_tx)) {
1444 ret = PTR_ERR(host->dma_tx);
1445 if (ret == -EPROBE_DEFER)
1448 host->dma_tx = NULL;
1449 dev_warn(host->dev, "TX DMA channel request failed\n");
1452 host->dma_rx = dma_request_chan(&pdev->dev, "rx");
1453 if (IS_ERR(host->dma_rx)) {
1454 ret = PTR_ERR(host->dma_rx);
1455 if (ret == -EPROBE_DEFER) {
1457 dma_release_channel(host->dma_tx);
1461 host->dma_rx = NULL;
1462 dev_warn(host->dev, "RX DMA channel request failed\n");
1465 ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1469 if (pdata->init != NULL) {
1470 ret = pdata->init(&pdev->dev);
1475 host->nr_slots = pdata->nr_slots;
1476 host->reg_shift = (mmc_omap7xx() ? 1 : 2);
1478 host->mmc_omap_wq = alloc_workqueue("mmc_omap", 0, 0);
1479 if (!host->mmc_omap_wq) {
1481 goto err_plat_cleanup;
1484 for (i = 0; i < pdata->nr_slots; i++) {
1485 ret = mmc_omap_new_slot(host, i);
1488 mmc_omap_remove_slot(host->slots[i]);
1490 goto err_destroy_wq;
1497 destroy_workqueue(host->mmc_omap_wq);
1500 pdata->cleanup(&pdev->dev);
1502 free_irq(host->irq, host);
1505 dma_release_channel(host->dma_tx);
1507 dma_release_channel(host->dma_rx);
1509 clk_unprepare(host->fclk);
1511 clk_put(host->fclk);
1513 clk_disable_unprepare(host->iclk);
1514 clk_put(host->iclk);
1518 static void mmc_omap_remove(struct platform_device *pdev)
1520 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1523 BUG_ON(host == NULL);
1525 for (i = 0; i < host->nr_slots; i++)
1526 mmc_omap_remove_slot(host->slots[i]);
1528 if (host->pdata->cleanup)
1529 host->pdata->cleanup(&pdev->dev);
1531 mmc_omap_fclk_enable(host, 0);
1532 free_irq(host->irq, host);
1533 clk_unprepare(host->fclk);
1534 clk_put(host->fclk);
1535 clk_disable_unprepare(host->iclk);
1536 clk_put(host->iclk);
1539 dma_release_channel(host->dma_tx);
1541 dma_release_channel(host->dma_rx);
1543 destroy_workqueue(host->mmc_omap_wq);
1546 #if IS_BUILTIN(CONFIG_OF)
1547 static const struct of_device_id mmc_omap_match[] = {
1548 { .compatible = "ti,omap2420-mmc", },
1551 MODULE_DEVICE_TABLE(of, mmc_omap_match);
1554 static struct platform_driver mmc_omap_driver = {
1555 .probe = mmc_omap_probe,
1556 .remove_new = mmc_omap_remove,
1558 .name = DRIVER_NAME,
1559 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1560 .of_match_table = of_match_ptr(mmc_omap_match),
1564 module_platform_driver(mmc_omap_driver);
1565 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1566 MODULE_LICENSE("GPL");
1567 MODULE_ALIAS("platform:" DRIVER_NAME);
1568 MODULE_AUTHOR("Juha Yrjölä");