drivers/mmc/host/omap.c

   1 /*
   2  *  linux/drivers/mmc/host/omap.c
   3  *
   4  *  Copyright (C) 2004 Nokia Corporation
   5  *  Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
   6  *  Misc hacks here and there by Tony Lindgren <tony@atomide.com>
   7  *  Other hacks (DMA, SD, etc) by David Brownell
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/ioport.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/dmaengine.h>
  21 #include <linux/dma-mapping.h>
  22 #include <linux/delay.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/timer.h>
  25 #include <linux/omap-dma.h>
  26 #include <linux/mmc/host.h>
  27 #include <linux/mmc/card.h>
  28 #include <linux/clk.h>
  29 #include <linux/scatterlist.h>
  30 #include <linux/slab.h>
  31
  32 #include <plat/mmc.h>
  33 #include <plat/dma.h>
  34
  35 #define OMAP_MMC_REG_CMD        0x00
  36 #define OMAP_MMC_REG_ARGL       0x01
  37 #define OMAP_MMC_REG_ARGH       0x02
  38 #define OMAP_MMC_REG_CON        0x03
  39 #define OMAP_MMC_REG_STAT       0x04
  40 #define OMAP_MMC_REG_IE         0x05
  41 #define OMAP_MMC_REG_CTO        0x06
  42 #define OMAP_MMC_REG_DTO        0x07
  43 #define OMAP_MMC_REG_DATA       0x08
  44 #define OMAP_MMC_REG_BLEN       0x09
  45 #define OMAP_MMC_REG_NBLK       0x0a
  46 #define OMAP_MMC_REG_BUF        0x0b
  47 #define OMAP_MMC_REG_SDIO       0x0d
  48 #define OMAP_MMC_REG_REV        0x0f
  49 #define OMAP_MMC_REG_RSP0       0x10
  50 #define OMAP_MMC_REG_RSP1       0x11
  51 #define OMAP_MMC_REG_RSP2       0x12
  52 #define OMAP_MMC_REG_RSP3       0x13
  53 #define OMAP_MMC_REG_RSP4       0x14
  54 #define OMAP_MMC_REG_RSP5       0x15
  55 #define OMAP_MMC_REG_RSP6       0x16
  56 #define OMAP_MMC_REG_RSP7       0x17
  57 #define OMAP_MMC_REG_IOSR       0x18
  58 #define OMAP_MMC_REG_SYSC       0x19
  59 #define OMAP_MMC_REG_SYSS       0x1a
  60
  61 #define OMAP_MMC_STAT_CARD_ERR          (1 << 14)
  62 #define OMAP_MMC_STAT_CARD_IRQ          (1 << 13)
  63 #define OMAP_MMC_STAT_OCR_BUSY          (1 << 12)
  64 #define OMAP_MMC_STAT_A_EMPTY           (1 << 11)
  65 #define OMAP_MMC_STAT_A_FULL            (1 << 10)
  66 #define OMAP_MMC_STAT_CMD_CRC           (1 <<  8)
  67 #define OMAP_MMC_STAT_CMD_TOUT          (1 <<  7)
  68 #define OMAP_MMC_STAT_DATA_CRC          (1 <<  6)
  69 #define OMAP_MMC_STAT_DATA_TOUT         (1 <<  5)
  70 #define OMAP_MMC_STAT_END_BUSY          (1 <<  4)
  71 #define OMAP_MMC_STAT_END_OF_DATA       (1 <<  3)
  72 #define OMAP_MMC_STAT_CARD_BUSY         (1 <<  2)
  73 #define OMAP_MMC_STAT_END_OF_CMD        (1 <<  0)
  74
  75 #define OMAP_MMC_REG(host, reg)         (OMAP_MMC_REG_##reg << (host)->reg_shift)
  76 #define OMAP_MMC_READ(host, reg)        __raw_readw((host)->virt_base + OMAP_MMC_REG(host, reg))
  77 #define OMAP_MMC_WRITE(host, reg, val)  __raw_writew((val), (host)->virt_base + OMAP_MMC_REG(host, reg))
  78
  79 /*
  80  * Command types
  81  */
  82 #define OMAP_MMC_CMDTYPE_BC     0
  83 #define OMAP_MMC_CMDTYPE_BCR    1
  84 #define OMAP_MMC_CMDTYPE_AC     2
  85 #define OMAP_MMC_CMDTYPE_ADTC   3
  86
  87
  88 #define DRIVER_NAME "mmci-omap"
  89
  90 /* Specifies how often in millisecs to poll for card status changes
  91  * when the cover switch is open */
  92 #define OMAP_MMC_COVER_POLL_DELAY       500
  93
  94 struct mmc_omap_host;
  95
  96 struct mmc_omap_slot {
  97         int                     id;
  98         unsigned int            vdd;
  99         u16                     saved_con;
 100         u16                     bus_mode;
 101         unsigned int            fclk_freq;
 102
 103         struct tasklet_struct   cover_tasklet;
 104         struct timer_list       cover_timer;
 105         unsigned                cover_open;
 106
 107         struct mmc_request      *mrq;
 108         struct mmc_omap_host    *host;
 109         struct mmc_host         *mmc;
 110         struct omap_mmc_slot_data *pdata;
 111 };
 112
 113 struct mmc_omap_host {
 114         int                     initialized;
 115         int                     suspended;
 116         struct mmc_request *    mrq;
 117         struct mmc_command *    cmd;
 118         struct mmc_data *       data;
 119         struct mmc_host *       mmc;
 120         struct device *         dev;
 121         unsigned char           id; /* 16xx chips have 2 MMC blocks */
 122         struct clk *            iclk;
 123         struct clk *            fclk;
 124         struct dma_chan         *dma_rx;
 125         u32                     dma_rx_burst;
 126         struct dma_chan         *dma_tx;
 127         u32                     dma_tx_burst;
 128         struct resource         *mem_res;
 129         void __iomem            *virt_base;
 130         unsigned int            phys_base;
 131         int                     irq;
 132         unsigned char           bus_mode;
 133         unsigned int            reg_shift;
 134
 135         struct work_struct      cmd_abort_work;
 136         unsigned                abort:1;
 137         struct timer_list       cmd_abort_timer;
 138
 139         struct work_struct      slot_release_work;
 140         struct mmc_omap_slot    *next_slot;
 141         struct work_struct      send_stop_work;
 142         struct mmc_data         *stop_data;
 143
 144         unsigned int            sg_len;
 145         int                     sg_idx;
 146         u16 *                   buffer;
 147         u32                     buffer_bytes_left;
 148         u32                     total_bytes_left;
 149
 150         unsigned                use_dma:1;
 151         unsigned                brs_received:1, dma_done:1;
 152         unsigned                dma_in_use:1;
 153         spinlock_t              dma_lock;
 154
 155         struct mmc_omap_slot    *slots[OMAP_MMC_MAX_SLOTS];
 156         struct mmc_omap_slot    *current_slot;
 157         spinlock_t              slot_lock;
 158         wait_queue_head_t       slot_wq;
 159         int                     nr_slots;
 160
 161         struct timer_list       clk_timer;
 162         spinlock_t              clk_lock;     /* for changing enabled state */
 163         unsigned int            fclk_enabled:1;
 164         struct workqueue_struct *mmc_omap_wq;
 165
 166         struct omap_mmc_platform_data *pdata;
 167 };
 168
 169
 170 static void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot)
 171 {
 172         unsigned long tick_ns;
 173
 174         if (slot != NULL && slot->host->fclk_enabled && slot->fclk_freq > 0) {
 175                 tick_ns = (1000000000 + slot->fclk_freq - 1) / slot->fclk_freq;
 176                 ndelay(8 * tick_ns);
 177         }
 178 }
 179
 180 static void mmc_omap_fclk_enable(struct mmc_omap_host *host, unsigned int enable)
 181 {
 182         unsigned long flags;
 183
 184         spin_lock_irqsave(&host->clk_lock, flags);
 185         if (host->fclk_enabled != enable) {
 186                 host->fclk_enabled = enable;
 187                 if (enable)
 188                         clk_enable(host->fclk);
 189                 else
 190                         clk_disable(host->fclk);
 191         }
 192         spin_unlock_irqrestore(&host->clk_lock, flags);
 193 }
 194
 195 static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
 196 {
 197         struct mmc_omap_host *host = slot->host;
 198         unsigned long flags;
 199
 200         if (claimed)
 201                 goto no_claim;
 202         spin_lock_irqsave(&host->slot_lock, flags);
 203         while (host->mmc != NULL) {
 204                 spin_unlock_irqrestore(&host->slot_lock, flags);
 205                 wait_event(host->slot_wq, host->mmc == NULL);
 206                 spin_lock_irqsave(&host->slot_lock, flags);
 207         }
 208         host->mmc = slot->mmc;
 209         spin_unlock_irqrestore(&host->slot_lock, flags);
 210 no_claim:
 211         del_timer(&host->clk_timer);
 212         if (host->current_slot != slot || !claimed)
 213                 mmc_omap_fclk_offdelay(host->current_slot);
 214
 215         if (host->current_slot != slot) {
 216                 OMAP_MMC_WRITE(host, CON, slot->saved_con & 0xFC00);
 217                 if (host->pdata->switch_slot != NULL)
 218                         host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
 219                 host->current_slot = slot;
 220         }
 221
 222         if (claimed) {
 223                 mmc_omap_fclk_enable(host, 1);
 224
 225                 /* Doing the dummy read here seems to work around some bug
 226                  * at least in OMAP24xx silicon where the command would not
 227                  * start after writing the CMD register. Sigh. */
 228                 OMAP_MMC_READ(host, CON);
 229
 230                 OMAP_MMC_WRITE(host, CON, slot->saved_con);
 231         } else
 232                 mmc_omap_fclk_enable(host, 0);
 233 }
 234
 235 static void mmc_omap_start_request(struct mmc_omap_host *host,
 236                                    struct mmc_request *req);
 237
 238 static void mmc_omap_slot_release_work(struct work_struct *work)
 239 {
 240         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 241                                                   slot_release_work);
 242         struct mmc_omap_slot *next_slot = host->next_slot;
 243         struct mmc_request *rq;
 244
 245         host->next_slot = NULL;
 246         mmc_omap_select_slot(next_slot, 1);
 247
 248         rq = next_slot->mrq;
 249         next_slot->mrq = NULL;
 250         mmc_omap_start_request(host, rq);
 251 }
 252
 253 static void mmc_omap_release_slot(struct mmc_omap_slot *slot, int clk_enabled)
 254 {
 255         struct mmc_omap_host *host = slot->host;
 256         unsigned long flags;
 257         int i;
 258
 259         BUG_ON(slot == NULL || host->mmc == NULL);
 260
 261         if (clk_enabled)
 262                 /* Keeps clock running for at least 8 cycles on valid freq */
 263                 mod_timer(&host->clk_timer, jiffies  + HZ/10);
 264         else {
 265                 del_timer(&host->clk_timer);
 266                 mmc_omap_fclk_offdelay(slot);
 267                 mmc_omap_fclk_enable(host, 0);
 268         }
 269
 270         spin_lock_irqsave(&host->slot_lock, flags);
 271         /* Check for any pending requests */
 272         for (i = 0; i < host->nr_slots; i++) {
 273                 struct mmc_omap_slot *new_slot;
 274
 275                 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
 276                         continue;
 277
 278                 BUG_ON(host->next_slot != NULL);
 279                 new_slot = host->slots[i];
 280                 /* The current slot should not have a request in queue */
 281                 BUG_ON(new_slot == host->current_slot);
 282
 283                 host->next_slot = new_slot;
 284                 host->mmc = new_slot->mmc;
 285                 spin_unlock_irqrestore(&host->slot_lock, flags);
 286                 queue_work(host->mmc_omap_wq, &host->slot_release_work);
 287                 return;
 288         }
 289
 290         host->mmc = NULL;
 291         wake_up(&host->slot_wq);
 292         spin_unlock_irqrestore(&host->slot_lock, flags);
 293 }
 294
 295 static inline
 296 int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
 297 {
 298         if (slot->pdata->get_cover_state)
 299                 return slot->pdata->get_cover_state(mmc_dev(slot->mmc),
 300                                                     slot->id);
 301         return 0;
 302 }
 303
 304 static ssize_t
 305 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
 306                            char *buf)
 307 {
 308         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 309         struct mmc_omap_slot *slot = mmc_priv(mmc);
 310
 311         return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
 312                        "closed");
 313 }
 314
 315 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 316
 317 static ssize_t
 318 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
 319                         char *buf)
 320 {
 321         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 322         struct mmc_omap_slot *slot = mmc_priv(mmc);
 323
 324         return sprintf(buf, "%s\n", slot->pdata->name);
 325 }
 326
 327 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
 328
 329 static void
 330 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
 331 {
 332         u32 cmdreg;
 333         u32 resptype;
 334         u32 cmdtype;
 335
 336         host->cmd = cmd;
 337
 338         resptype = 0;
 339         cmdtype = 0;
 340
 341         /* Our hardware needs to know exact type */
 342         switch (mmc_resp_type(cmd)) {
 343         case MMC_RSP_NONE:
 344                 break;
 345         case MMC_RSP_R1:
 346         case MMC_RSP_R1B:
 347                 /* resp 1, 1b, 6, 7 */
 348                 resptype = 1;
 349                 break;
 350         case MMC_RSP_R2:
 351                 resptype = 2;
 352                 break;
 353         case MMC_RSP_R3:
 354                 resptype = 3;
 355                 break;
 356         default:
 357                 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
 358                 break;
 359         }
 360
 361         if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
 362                 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
 363         } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
 364                 cmdtype = OMAP_MMC_CMDTYPE_BC;
 365         } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
 366                 cmdtype = OMAP_MMC_CMDTYPE_BCR;
 367         } else {
 368                 cmdtype = OMAP_MMC_CMDTYPE_AC;
 369         }
 370
 371         cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
 372
 373         if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
 374                 cmdreg |= 1 << 6;
 375
 376         if (cmd->flags & MMC_RSP_BUSY)
 377                 cmdreg |= 1 << 11;
 378
 379         if (host->data && !(host->data->flags & MMC_DATA_WRITE))
 380                 cmdreg |= 1 << 15;
 381
 382         mod_timer(&host->cmd_abort_timer, jiffies + HZ/2);
 383
 384         OMAP_MMC_WRITE(host, CTO, 200);
 385         OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
 386         OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
 387         OMAP_MMC_WRITE(host, IE,
 388                        OMAP_MMC_STAT_A_EMPTY    | OMAP_MMC_STAT_A_FULL    |
 389                        OMAP_MMC_STAT_CMD_CRC    | OMAP_MMC_STAT_CMD_TOUT  |
 390                        OMAP_MMC_STAT_DATA_CRC   | OMAP_MMC_STAT_DATA_TOUT |
 391                        OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR  |
 392                        OMAP_MMC_STAT_END_OF_DATA);
 393         OMAP_MMC_WRITE(host, CMD, cmdreg);
 394 }
 395
 396 static void
 397 mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,
 398                      int abort)
 399 {
 400         enum dma_data_direction dma_data_dir;
 401         struct device *dev = mmc_dev(host->mmc);
 402         struct dma_chan *c;
 403
 404         if (data->flags & MMC_DATA_WRITE) {
 405                 dma_data_dir = DMA_TO_DEVICE;
 406                 c = host->dma_tx;
 407         } else {
 408                 dma_data_dir = DMA_FROM_DEVICE;
 409                 c = host->dma_rx;
 410         }
 411         if (c) {
 412                 if (data->error) {
 413                         dmaengine_terminate_all(c);
 414                         /* Claim nothing transferred on error... */
 415                         data->bytes_xfered = 0;
 416                 }
 417                 dev = c->device->dev;
 418         }
 419         dma_unmap_sg(dev, data->sg, host->sg_len, dma_data_dir);
 420 }
 421
 422 static void mmc_omap_send_stop_work(struct work_struct *work)
 423 {
 424         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 425                                                   send_stop_work);
 426         struct mmc_omap_slot *slot = host->current_slot;
 427         struct mmc_data *data = host->stop_data;
 428         unsigned long tick_ns;
 429
 430         tick_ns = (1000000000 + slot->fclk_freq - 1)/slot->fclk_freq;
 431         ndelay(8*tick_ns);
 432
 433         mmc_omap_start_command(host, data->stop);
 434 }
 435
 436 static void
 437 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 438 {
 439         if (host->dma_in_use)
 440                 mmc_omap_release_dma(host, data, data->error);
 441
 442         host->data = NULL;
 443         host->sg_len = 0;
 444
 445         /* NOTE:  MMC layer will sometimes poll-wait CMD13 next, issuing
 446          * dozens of requests until the card finishes writing data.
 447          * It'd be cheaper to just wait till an EOFB interrupt arrives...
 448          */
 449
 450         if (!data->stop) {
 451                 struct mmc_host *mmc;
 452
 453                 host->mrq = NULL;
 454                 mmc = host->mmc;
 455                 mmc_omap_release_slot(host->current_slot, 1);
 456                 mmc_request_done(mmc, data->mrq);
 457                 return;
 458         }
 459
 460         host->stop_data = data;
 461         queue_work(host->mmc_omap_wq, &host->send_stop_work);
 462 }
 463
 464 static void
 465 mmc_omap_send_abort(struct mmc_omap_host *host, int maxloops)
 466 {
 467         struct mmc_omap_slot *slot = host->current_slot;
 468         unsigned int restarts, passes, timeout;
 469         u16 stat = 0;
 470
 471         /* Sending abort takes 80 clocks. Have some extra and round up */
 472         timeout = (120*1000000 + slot->fclk_freq - 1)/slot->fclk_freq;
 473         restarts = 0;
 474         while (restarts < maxloops) {
 475                 OMAP_MMC_WRITE(host, STAT, 0xFFFF);
 476                 OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7));
 477
 478                 passes = 0;
 479                 while (passes < timeout) {
 480                         stat = OMAP_MMC_READ(host, STAT);
 481                         if (stat & OMAP_MMC_STAT_END_OF_CMD)
 482                                 goto out;
 483                         udelay(1);
 484                         passes++;
 485                 }
 486
 487                 restarts++;
 488         }
 489 out:
 490         OMAP_MMC_WRITE(host, STAT, stat);
 491 }
 492
 493 static void
 494 mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)
 495 {
 496         if (host->dma_in_use)
 497                 mmc_omap_release_dma(host, data, 1);
 498
 499         host->data = NULL;
 500         host->sg_len = 0;
 501
 502         mmc_omap_send_abort(host, 10000);
 503 }
 504
 505 static void
 506 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
 507 {
 508         unsigned long flags;
 509         int done;
 510
 511         if (!host->dma_in_use) {
 512                 mmc_omap_xfer_done(host, data);
 513                 return;
 514         }
 515         done = 0;
 516         spin_lock_irqsave(&host->dma_lock, flags);
 517         if (host->dma_done)
 518                 done = 1;
 519         else
 520                 host->brs_received = 1;
 521         spin_unlock_irqrestore(&host->dma_lock, flags);
 522         if (done)
 523                 mmc_omap_xfer_done(host, data);
 524 }
 525
 526 static void
 527 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
 528 {
 529         unsigned long flags;
 530         int done;
 531
 532         done = 0;
 533         spin_lock_irqsave(&host->dma_lock, flags);
 534         if (host->brs_received)
 535                 done = 1;
 536         else
 537                 host->dma_done = 1;
 538         spin_unlock_irqrestore(&host->dma_lock, flags);
 539         if (done)
 540                 mmc_omap_xfer_done(host, data);
 541 }
 542
 543 static void
 544 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 545 {
 546         host->cmd = NULL;
 547
 548         del_timer(&host->cmd_abort_timer);
 549
 550         if (cmd->flags & MMC_RSP_PRESENT) {
 551                 if (cmd->flags & MMC_RSP_136) {
 552                         /* response type 2 */
 553                         cmd->resp[3] =
 554                                 OMAP_MMC_READ(host, RSP0) |
 555                                 (OMAP_MMC_READ(host, RSP1) << 16);
 556                         cmd->resp[2] =
 557                                 OMAP_MMC_READ(host, RSP2) |
 558                                 (OMAP_MMC_READ(host, RSP3) << 16);
 559                         cmd->resp[1] =
 560                                 OMAP_MMC_READ(host, RSP4) |
 561                                 (OMAP_MMC_READ(host, RSP5) << 16);
 562                         cmd->resp[0] =
 563                                 OMAP_MMC_READ(host, RSP6) |
 564                                 (OMAP_MMC_READ(host, RSP7) << 16);
 565                 } else {
 566                         /* response types 1, 1b, 3, 4, 5, 6 */
 567                         cmd->resp[0] =
 568                                 OMAP_MMC_READ(host, RSP6) |
 569                                 (OMAP_MMC_READ(host, RSP7) << 16);
 570                 }
 571         }
 572
 573         if (host->data == NULL || cmd->error) {
 574                 struct mmc_host *mmc;
 575
 576                 if (host->data != NULL)
 577                         mmc_omap_abort_xfer(host, host->data);
 578                 host->mrq = NULL;
 579                 mmc = host->mmc;
 580                 mmc_omap_release_slot(host->current_slot, 1);
 581                 mmc_request_done(mmc, cmd->mrq);
 582         }
 583 }
 584
 585 /*
 586  * Abort stuck command. Can occur when card is removed while it is being
 587  * read.
 588  */
 589 static void mmc_omap_abort_command(struct work_struct *work)
 590 {
 591         struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 592                                                   cmd_abort_work);
 593         BUG_ON(!host->cmd);
 594
 595         dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n",
 596                 host->cmd->opcode);
 597
 598         if (host->cmd->error == 0)
 599                 host->cmd->error = -ETIMEDOUT;
 600
 601         if (host->data == NULL) {
 602                 struct mmc_command *cmd;
 603                 struct mmc_host    *mmc;
 604
 605                 cmd = host->cmd;
 606                 host->cmd = NULL;
 607                 mmc_omap_send_abort(host, 10000);
 608
 609                 host->mrq = NULL;
 610                 mmc = host->mmc;
 611                 mmc_omap_release_slot(host->current_slot, 1);
 612                 mmc_request_done(mmc, cmd->mrq);
 613         } else
 614                 mmc_omap_cmd_done(host, host->cmd);
 615
 616         host->abort = 0;
 617         enable_irq(host->irq);
 618 }
 619
 620 static void
 621 mmc_omap_cmd_timer(unsigned long data)
 622 {
 623         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 624         unsigned long flags;
 625
 626         spin_lock_irqsave(&host->slot_lock, flags);
 627         if (host->cmd != NULL && !host->abort) {
 628                 OMAP_MMC_WRITE(host, IE, 0);
 629                 disable_irq(host->irq);
 630                 host->abort = 1;
 631                 queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
 632         }
 633         spin_unlock_irqrestore(&host->slot_lock, flags);
 634 }
 635
 636 /* PIO only */
 637 static void
 638 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
 639 {
 640         struct scatterlist *sg;
 641
 642         sg = host->data->sg + host->sg_idx;
 643         host->buffer_bytes_left = sg->length;
 644         host->buffer = sg_virt(sg);
 645         if (host->buffer_bytes_left > host->total_bytes_left)
 646                 host->buffer_bytes_left = host->total_bytes_left;
 647 }
 648
 649 static void
 650 mmc_omap_clk_timer(unsigned long data)
 651 {
 652         struct mmc_omap_host *host = (struct mmc_omap_host *) data;
 653
 654         mmc_omap_fclk_enable(host, 0);
 655 }
 656
 657 /* PIO only */
 658 static void
 659 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
 660 {
 661         int n, nwords;
 662
 663         if (host->buffer_bytes_left == 0) {
 664                 host->sg_idx++;
 665                 BUG_ON(host->sg_idx == host->sg_len);
 666                 mmc_omap_sg_to_buf(host);
 667         }
 668         n = 64;
 669         if (n > host->buffer_bytes_left)
 670                 n = host->buffer_bytes_left;
 671
 672         nwords = n / 2;
 673         nwords += n & 1; /* handle odd number of bytes to transfer */
 674
 675         host->buffer_bytes_left -= n;
 676         host->total_bytes_left -= n;
 677         host->data->bytes_xfered += n;
 678
 679         if (write) {
 680                 __raw_writesw(host->virt_base + OMAP_MMC_REG(host, DATA),
 681                               host->buffer, nwords);
 682         } else {
 683                 __raw_readsw(host->virt_base + OMAP_MMC_REG(host, DATA),
 684                              host->buffer, nwords);
 685         }
 686
 687         host->buffer += nwords;
 688 }
 689
 690 #ifdef CONFIG_MMC_DEBUG
 691 static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status)
 692 {
 693         static const char *mmc_omap_status_bits[] = {
 694                 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
 695                 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
 696         };
 697         int i;
 698         char res[64], *buf = res;
 699
 700         buf += sprintf(buf, "MMC IRQ 0x%x:", status);
 701
 702         for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 703                 if (status & (1 << i))
 704                         buf += sprintf(buf, " %s", mmc_omap_status_bits[i]);
 705         dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
 706 }
 707 #else
 708 static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status)
 709 {
 710 }
 711 #endif
 712
 713
 714 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 715 {
 716         struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
 717         u16 status;
 718         int end_command;
 719         int end_transfer;
 720         int transfer_error, cmd_error;
 721
 722         if (host->cmd == NULL && host->data == NULL) {
 723                 status = OMAP_MMC_READ(host, STAT);
 724                 dev_info(mmc_dev(host->slots[0]->mmc),
 725                          "Spurious IRQ 0x%04x\n", status);
 726                 if (status != 0) {
 727                         OMAP_MMC_WRITE(host, STAT, status);
 728                         OMAP_MMC_WRITE(host, IE, 0);
 729                 }
 730                 return IRQ_HANDLED;
 731         }
 732
 733         end_command = 0;
 734         end_transfer = 0;
 735         transfer_error = 0;
 736         cmd_error = 0;
 737
 738         while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
 739                 int cmd;
 740
 741                 OMAP_MMC_WRITE(host, STAT, status);
 742                 if (host->cmd != NULL)
 743                         cmd = host->cmd->opcode;
 744                 else
 745                         cmd = -1;
 746                 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
 747                         status, cmd);
 748                 mmc_omap_report_irq(host, status);
 749
 750                 if (host->total_bytes_left) {
 751                         if ((status & OMAP_MMC_STAT_A_FULL) ||
 752                             (status & OMAP_MMC_STAT_END_OF_DATA))
 753                                 mmc_omap_xfer_data(host, 0);
 754                         if (status & OMAP_MMC_STAT_A_EMPTY)
 755                                 mmc_omap_xfer_data(host, 1);
 756                 }
 757
 758                 if (status & OMAP_MMC_STAT_END_OF_DATA)
 759                         end_transfer = 1;
 760
 761                 if (status & OMAP_MMC_STAT_DATA_TOUT) {
 762                         dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n",
 763                                 cmd);
 764                         if (host->data) {
 765                                 host->data->error = -ETIMEDOUT;
 766                                 transfer_error = 1;
 767                         }
 768                 }
 769
 770                 if (status & OMAP_MMC_STAT_DATA_CRC) {
 771                         if (host->data) {
 772                                 host->data->error = -EILSEQ;
 773                                 dev_dbg(mmc_dev(host->mmc),
 774                                          "data CRC error, bytes left %d\n",
 775                                         host->total_bytes_left);
 776                                 transfer_error = 1;
 777                         } else {
 778                                 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
 779                         }
 780                 }
 781
 782                 if (status & OMAP_MMC_STAT_CMD_TOUT) {
 783                         /* Timeouts are routine with some commands */
 784                         if (host->cmd) {
 785                                 struct mmc_omap_slot *slot =
 786                                         host->current_slot;
 787                                 if (slot == NULL ||
 788                                     !mmc_omap_cover_is_open(slot))
 789                                         dev_err(mmc_dev(host->mmc),
 790                                                 "command timeout (CMD%d)\n",
 791                                                 cmd);
 792                                 host->cmd->error = -ETIMEDOUT;
 793                                 end_command = 1;
 794                                 cmd_error = 1;
 795                         }
 796                 }
 797
 798                 if (status & OMAP_MMC_STAT_CMD_CRC) {
 799                         if (host->cmd) {
 800                                 dev_err(mmc_dev(host->mmc),
 801                                         "command CRC error (CMD%d, arg 0x%08x)\n",
 802                                         cmd, host->cmd->arg);
 803                                 host->cmd->error = -EILSEQ;
 804                                 end_command = 1;
 805                                 cmd_error = 1;
 806                         } else
 807                                 dev_err(mmc_dev(host->mmc),
 808                                         "command CRC error without cmd?\n");
 809                 }
 810
 811                 if (status & OMAP_MMC_STAT_CARD_ERR) {
 812                         dev_dbg(mmc_dev(host->mmc),
 813                                 "ignoring card status error (CMD%d)\n",
 814                                 cmd);
 815                         end_command = 1;
 816                 }
 817
 818                 /*
 819                  * NOTE: On 1610 the END_OF_CMD may come too early when
 820                  * starting a write
 821                  */
 822                 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
 823                     (!(status & OMAP_MMC_STAT_A_EMPTY))) {
 824                         end_command = 1;
 825                 }
 826         }
 827
 828         if (cmd_error && host->data) {
 829                 del_timer(&host->cmd_abort_timer);
 830                 host->abort = 1;
 831                 OMAP_MMC_WRITE(host, IE, 0);
 832                 disable_irq_nosync(host->irq);
 833                 queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
 834                 return IRQ_HANDLED;
 835         }
 836
 837         if (end_command && host->cmd)
 838                 mmc_omap_cmd_done(host, host->cmd);
 839         if (host->data != NULL) {
 840                 if (transfer_error)
 841                         mmc_omap_xfer_done(host, host->data);
 842                 else if (end_transfer)
 843                         mmc_omap_end_of_data(host, host->data);
 844         }
 845
 846         return IRQ_HANDLED;
 847 }
 848
 849 void omap_mmc_notify_cover_event(struct device *dev, int num, int is_closed)
 850 {
 851         int cover_open;
 852         struct mmc_omap_host *host = dev_get_drvdata(dev);
 853         struct mmc_omap_slot *slot = host->slots[num];
 854
 855         BUG_ON(num >= host->nr_slots);
 856
 857         /* Other subsystems can call in here before we're initialised. */
 858         if (host->nr_slots == 0 || !host->slots[num])
 859                 return;
 860
 861         cover_open = mmc_omap_cover_is_open(slot);
 862         if (cover_open != slot->cover_open) {
 863                 slot->cover_open = cover_open;
 864                 sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
 865         }
 866
 867         tasklet_hi_schedule(&slot->cover_tasklet);
 868 }
 869
 870 static void mmc_omap_cover_timer(unsigned long arg)
 871 {
 872         struct mmc_omap_slot *slot = (struct mmc_omap_slot *) arg;
 873         tasklet_schedule(&slot->cover_tasklet);
 874 }
 875
 876 static void mmc_omap_cover_handler(unsigned long param)
 877 {
 878         struct mmc_omap_slot *slot = (struct mmc_omap_slot *)param;
 879         int cover_open = mmc_omap_cover_is_open(slot);
 880
 881         mmc_detect_change(slot->mmc, 0);
 882         if (!cover_open)
 883                 return;
 884
 885         /*
 886          * If no card is inserted, we postpone polling until
 887          * the cover has been closed.
 888          */
 889         if (slot->mmc->card == NULL || !mmc_card_present(slot->mmc->card))
 890                 return;
 891
 892         mod_timer(&slot->cover_timer,
 893                   jiffies + msecs_to_jiffies(OMAP_MMC_COVER_POLL_DELAY));
 894 }
 895
 896 static void mmc_omap_dma_callback(void *priv)
 897 {
 898         struct mmc_omap_host *host = priv;
 899         struct mmc_data *data = host->data;
 900
 901         /* If we got to the end of DMA, assume everything went well */
 902         data->bytes_xfered += data->blocks * data->blksz;
 903
 904         mmc_omap_dma_done(host, data);
 905 }
 906
 907 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 908 {
 909         u16 reg;
 910
 911         reg = OMAP_MMC_READ(host, SDIO);
 912         reg &= ~(1 << 5);
 913         OMAP_MMC_WRITE(host, SDIO, reg);
 914         /* Set maximum timeout */
 915         OMAP_MMC_WRITE(host, CTO, 0xff);
 916 }
 917
 918 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 919 {
 920         unsigned int timeout, cycle_ns;
 921         u16 reg;
 922
 923         cycle_ns = 1000000000 / host->current_slot->fclk_freq;
 924         timeout = req->data->timeout_ns / cycle_ns;
 925         timeout += req->data->timeout_clks;
 926
 927         /* Check if we need to use timeout multiplier register */
 928         reg = OMAP_MMC_READ(host, SDIO);
 929         if (timeout > 0xffff) {
 930                 reg |= (1 << 5);
 931                 timeout /= 1024;
 932         } else
 933                 reg &= ~(1 << 5);
 934         OMAP_MMC_WRITE(host, SDIO, reg);
 935         OMAP_MMC_WRITE(host, DTO, timeout);
 936 }
 937
 938 static void
 939 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 940 {
 941         struct mmc_data *data = req->data;
 942         int i, use_dma, block_size;
 943         unsigned sg_len;
 944
 945         host->data = data;
 946         if (data == NULL) {
 947                 OMAP_MMC_WRITE(host, BLEN, 0);
 948                 OMAP_MMC_WRITE(host, NBLK, 0);
 949                 OMAP_MMC_WRITE(host, BUF, 0);
 950                 host->dma_in_use = 0;
 951                 set_cmd_timeout(host, req);
 952                 return;
 953         }
 954
 955         block_size = data->blksz;
 956
 957         OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
 958         OMAP_MMC_WRITE(host, BLEN, block_size - 1);
 959         set_data_timeout(host, req);
 960
 961         /* cope with calling layer confusion; it issues "single
 962          * block" writes using multi-block scatterlists.
 963          */
 964         sg_len = (data->blocks == 1) ? 1 : data->sg_len;
 965
 966         /* Only do DMA for entire blocks */
 967         use_dma = host->use_dma;
 968         if (use_dma) {
 969                 for (i = 0; i < sg_len; i++) {
 970                         if ((data->sg[i].length % block_size) != 0) {
 971                                 use_dma = 0;
 972                                 break;
 973                         }
 974                 }
 975         }
 976
 977         host->sg_idx = 0;
 978         if (use_dma) {
 979                 enum dma_data_direction dma_data_dir;
 980                 struct dma_async_tx_descriptor *tx;
 981                 struct dma_chan *c;
 982                 u32 burst, *bp;
 983                 u16 buf;
 984
 985                 /*
 986                  * FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx
 987                  * and 24xx. Use 16 or 32 word frames when the
 988                  * blocksize is at least that large. Blocksize is
 989                  * usually 512 bytes; but not for some SD reads.
 990                  */
 991                 burst = cpu_is_omap15xx() ? 32 : 64;
 992                 if (burst > data->blksz)
 993                         burst = data->blksz;
 994
 995                 burst >>= 1;
 996
 997                 if (data->flags & MMC_DATA_WRITE) {
 998                         c = host->dma_tx;
 999                         bp = &host->dma_tx_burst;
1000                         buf = 0x0f80 | (burst - 1) << 0;
1001                         dma_data_dir = DMA_TO_DEVICE;
1002                 } else {
1003                         c = host->dma_rx;
1004                         bp = &host->dma_rx_burst;
1005                         buf = 0x800f | (burst - 1) << 8;
1006                         dma_data_dir = DMA_FROM_DEVICE;
1007                 }
1008
1009                 if (!c)
1010                         goto use_pio;
1011
1012                 /* Only reconfigure if we have a different burst size */
1013                 if (*bp != burst) {
1014                         struct dma_slave_config cfg;
1015
1016                         cfg.src_addr = host->phys_base + OMAP_MMC_REG(host, DATA);
1017                         cfg.dst_addr = host->phys_base + OMAP_MMC_REG(host, DATA);
1018                         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1019                         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1020                         cfg.src_maxburst = burst;
1021                         cfg.dst_maxburst = burst;
1022
1023                         if (dmaengine_slave_config(c, &cfg))
1024                                 goto use_pio;
1025
1026                         *bp = burst;
1027                 }
1028
1029                 host->sg_len = dma_map_sg(c->device->dev, data->sg, sg_len,
1030                                           dma_data_dir);
1031                 if (host->sg_len == 0)
1032                         goto use_pio;
1033
1034                 tx = dmaengine_prep_slave_sg(c, data->sg, host->sg_len,
1035                         data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1036                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1037                 if (!tx)
1038                         goto use_pio;
1039
1040                 OMAP_MMC_WRITE(host, BUF, buf);
1041
1042                 tx->callback = mmc_omap_dma_callback;
1043                 tx->callback_param = host;
1044                 dmaengine_submit(tx);
1045                 host->brs_received = 0;
1046                 host->dma_done = 0;
1047                 host->dma_in_use = 1;
1048                 return;
1049         }
1050  use_pio:
1051
1052         /* Revert to PIO? */
1053         OMAP_MMC_WRITE(host, BUF, 0x1f1f);
1054         host->total_bytes_left = data->blocks * block_size;
1055         host->sg_len = sg_len;
1056         mmc_omap_sg_to_buf(host);
1057         host->dma_in_use = 0;
1058 }
1059
1060 static void mmc_omap_start_request(struct mmc_omap_host *host,
1061                                    struct mmc_request *req)
1062 {
1063         BUG_ON(host->mrq != NULL);
1064
1065         host->mrq = req;
1066
1067         /* only touch fifo AFTER the controller readies it */
1068         mmc_omap_prepare_data(host, req);
1069         mmc_omap_start_command(host, req->cmd);
1070         if (host->dma_in_use) {
1071                 struct dma_chan *c = host->data->flags & MMC_DATA_WRITE ?
1072                                 host->dma_tx : host->dma_rx;
1073
1074                 dma_async_issue_pending(c);
1075         }
1076 }
1077
1078 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
1079 {
1080         struct mmc_omap_slot *slot = mmc_priv(mmc);
1081         struct mmc_omap_host *host = slot->host;
1082         unsigned long flags;
1083
1084         spin_lock_irqsave(&host->slot_lock, flags);
1085         if (host->mmc != NULL) {
1086                 BUG_ON(slot->mrq != NULL);
1087                 slot->mrq = req;
1088                 spin_unlock_irqrestore(&host->slot_lock, flags);
1089                 return;
1090         } else
1091                 host->mmc = mmc;
1092         spin_unlock_irqrestore(&host->slot_lock, flags);
1093         mmc_omap_select_slot(slot, 1);
1094         mmc_omap_start_request(host, req);
1095 }
1096
1097 static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on,
1098                                 int vdd)
1099 {
1100         struct mmc_omap_host *host;
1101
1102         host = slot->host;
1103
1104         if (slot->pdata->set_power != NULL)
1105                 slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on,
1106                                         vdd);
1107
1108         if (cpu_is_omap24xx()) {
1109                 u16 w;
1110
1111                 if (power_on) {
1112                         w = OMAP_MMC_READ(host, CON);
1113                         OMAP_MMC_WRITE(host, CON, w | (1 << 11));
1114                 } else {
1115                         w = OMAP_MMC_READ(host, CON);
1116                         OMAP_MMC_WRITE(host, CON, w & ~(1 << 11));
1117                 }
1118         }
1119 }
1120
1121 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
1122 {
1123         struct mmc_omap_slot *slot = mmc_priv(mmc);
1124         struct mmc_omap_host *host = slot->host;
1125         int func_clk_rate = clk_get_rate(host->fclk);
1126         int dsor;
1127
1128         if (ios->clock == 0)
1129                 return 0;
1130
1131         dsor = func_clk_rate / ios->clock;
1132         if (dsor < 1)
1133                 dsor = 1;
1134
1135         if (func_clk_rate / dsor > ios->clock)
1136                 dsor++;
1137
1138         if (dsor > 250)
1139                 dsor = 250;
1140
1141         slot->fclk_freq = func_clk_rate / dsor;
1142
1143         if (ios->bus_width == MMC_BUS_WIDTH_4)
1144                 dsor |= 1 << 15;
1145
1146         return dsor;
1147 }
1148
1149 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1150 {
1151         struct mmc_omap_slot *slot = mmc_priv(mmc);
1152         struct mmc_omap_host *host = slot->host;
1153         int i, dsor;
1154         int clk_enabled;
1155
1156         mmc_omap_select_slot(slot, 0);
1157
1158         dsor = mmc_omap_calc_divisor(mmc, ios);
1159
1160         if (ios->vdd != slot->vdd)
1161                 slot->vdd = ios->vdd;
1162
1163         clk_enabled = 0;
1164         switch (ios->power_mode) {
1165         case MMC_POWER_OFF:
1166                 mmc_omap_set_power(slot, 0, ios->vdd);
1167                 break;
1168         case MMC_POWER_UP:
1169                 /* Cannot touch dsor yet, just power up MMC */
1170                 mmc_omap_set_power(slot, 1, ios->vdd);
1171                 goto exit;
1172         case MMC_POWER_ON:
1173                 mmc_omap_fclk_enable(host, 1);
1174                 clk_enabled = 1;
1175                 dsor |= 1 << 11;
1176                 break;
1177         }
1178
1179         if (slot->bus_mode != ios->bus_mode) {
1180                 if (slot->pdata->set_bus_mode != NULL)
1181                         slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id,
1182                                                   ios->bus_mode);
1183                 slot->bus_mode = ios->bus_mode;
1184         }
1185
1186         /* On insanely high arm_per frequencies something sometimes
1187          * goes somehow out of sync, and the POW bit is not being set,
1188          * which results in the while loop below getting stuck.
1189          * Writing to the CON register twice seems to do the trick. */
1190         for (i = 0; i < 2; i++)
1191                 OMAP_MMC_WRITE(host, CON, dsor);
1192         slot->saved_con = dsor;
1193         if (ios->power_mode == MMC_POWER_ON) {
1194                 /* worst case at 400kHz, 80 cycles makes 200 microsecs */
1195                 int usecs = 250;
1196
1197                 /* Send clock cycles, poll completion */
1198                 OMAP_MMC_WRITE(host, IE, 0);
1199                 OMAP_MMC_WRITE(host, STAT, 0xffff);
1200                 OMAP_MMC_WRITE(host, CMD, 1 << 7);
1201                 while (usecs > 0 && (OMAP_MMC_READ(host, STAT) & 1) == 0) {
1202                         udelay(1);
1203                         usecs--;
1204                 }
1205                 OMAP_MMC_WRITE(host, STAT, 1);
1206         }
1207
1208 exit:
1209         mmc_omap_release_slot(slot, clk_enabled);
1210 }
1211
1212 static const struct mmc_host_ops mmc_omap_ops = {
1213         .request        = mmc_omap_request,
1214         .set_ios        = mmc_omap_set_ios,
1215 };
1216
1217 static int mmc_omap_new_slot(struct mmc_omap_host *host, int id)
1218 {
1219         struct mmc_omap_slot *slot = NULL;
1220         struct mmc_host *mmc;
1221         int r;
1222
1223         mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
1224         if (mmc == NULL)
1225                 return -ENOMEM;
1226
1227         slot = mmc_priv(mmc);
1228         slot->host = host;
1229         slot->mmc = mmc;
1230         slot->id = id;
1231         slot->pdata = &host->pdata->slots[id];
1232
1233         host->slots[id] = slot;
1234
1235         mmc->caps = 0;
1236         if (host->pdata->slots[id].wires >= 4)
1237                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1238
1239         mmc->ops = &mmc_omap_ops;
1240         mmc->f_min = 400000;
1241
1242         if (cpu_class_is_omap2())
1243                 mmc->f_max = 48000000;
1244         else
1245                 mmc->f_max = 24000000;
1246         if (host->pdata->max_freq)
1247                 mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
1248         mmc->ocr_avail = slot->pdata->ocr_mask;
1249
1250         /* Use scatterlist DMA to reduce per-transfer costs.
1251          * NOTE max_seg_size assumption that small blocks aren't
1252          * normally used (except e.g. for reading SD registers).
1253          */
1254         mmc->max_segs = 32;
1255         mmc->max_blk_size = 2048;       /* BLEN is 11 bits (+1) */
1256         mmc->max_blk_count = 2048;      /* NBLK is 11 bits (+1) */
1257         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1258         mmc->max_seg_size = mmc->max_req_size;
1259
1260         r = mmc_add_host(mmc);
1261         if (r < 0)
1262                 goto err_remove_host;
1263
1264         if (slot->pdata->name != NULL) {
1265                 r = device_create_file(&mmc->class_dev,
1266                                         &dev_attr_slot_name);
1267                 if (r < 0)
1268                         goto err_remove_host;
1269         }
1270
1271         if (slot->pdata->get_cover_state != NULL) {
1272                 r = device_create_file(&mmc->class_dev,
1273                                         &dev_attr_cover_switch);
1274                 if (r < 0)
1275                         goto err_remove_slot_name;
1276
1277                 setup_timer(&slot->cover_timer, mmc_omap_cover_timer,
1278                             (unsigned long)slot);
1279                 tasklet_init(&slot->cover_tasklet, mmc_omap_cover_handler,
1280                              (unsigned long)slot);
1281                 tasklet_schedule(&slot->cover_tasklet);
1282         }
1283
1284         return 0;
1285
1286 err_remove_slot_name:
1287         if (slot->pdata->name != NULL)
1288                 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1289 err_remove_host:
1290         mmc_remove_host(mmc);
1291         mmc_free_host(mmc);
1292         return r;
1293 }
1294
1295 static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
1296 {
1297         struct mmc_host *mmc = slot->mmc;
1298
1299         if (slot->pdata->name != NULL)
1300                 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1301         if (slot->pdata->get_cover_state != NULL)
1302                 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1303
1304         tasklet_kill(&slot->cover_tasklet);
1305         del_timer_sync(&slot->cover_timer);
1306         flush_workqueue(slot->host->mmc_omap_wq);
1307
1308         mmc_remove_host(mmc);
1309         mmc_free_host(mmc);
1310 }
1311
1312 static int mmc_omap_probe(struct platform_device *pdev)
1313 {
1314         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1315         struct mmc_omap_host *host = NULL;
1316         struct resource *res;
1317         dma_cap_mask_t mask;
1318         unsigned sig;
1319         int i, ret = 0;
1320         int irq;
1321
1322         if (pdata == NULL) {
1323                 dev_err(&pdev->dev, "platform data missing\n");
1324                 return -ENXIO;
1325         }
1326         if (pdata->nr_slots == 0) {
1327                 dev_err(&pdev->dev, "no slots\n");
1328                 return -ENXIO;
1329         }
1330
1331         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1332         irq = platform_get_irq(pdev, 0);
1333         if (res == NULL || irq < 0)
1334                 return -ENXIO;
1335
1336         res = request_mem_region(res->start, resource_size(res),
1337                                  pdev->name);
1338         if (res == NULL)
1339                 return -EBUSY;
1340
1341         host = kzalloc(sizeof(struct mmc_omap_host), GFP_KERNEL);
1342         if (host == NULL) {
1343                 ret = -ENOMEM;
1344                 goto err_free_mem_region;
1345         }
1346
1347         INIT_WORK(&host->slot_release_work, mmc_omap_slot_release_work);
1348         INIT_WORK(&host->send_stop_work, mmc_omap_send_stop_work);
1349
1350         INIT_WORK(&host->cmd_abort_work, mmc_omap_abort_command);
1351         setup_timer(&host->cmd_abort_timer, mmc_omap_cmd_timer,
1352                     (unsigned long) host);
1353
1354         spin_lock_init(&host->clk_lock);
1355         setup_timer(&host->clk_timer, mmc_omap_clk_timer, (unsigned long) host);
1356
1357         spin_lock_init(&host->dma_lock);
1358         spin_lock_init(&host->slot_lock);
1359         init_waitqueue_head(&host->slot_wq);
1360
1361         host->pdata = pdata;
1362         host->dev = &pdev->dev;
1363         platform_set_drvdata(pdev, host);
1364
1365         host->id = pdev->id;
1366         host->mem_res = res;
1367         host->irq = irq;
1368         host->use_dma = 1;
1369         host->irq = irq;
1370         host->phys_base = host->mem_res->start;
1371         host->virt_base = ioremap(res->start, resource_size(res));
1372         if (!host->virt_base)
1373                 goto err_ioremap;
1374
1375         host->iclk = clk_get(&pdev->dev, "ick");
1376         if (IS_ERR(host->iclk)) {
1377                 ret = PTR_ERR(host->iclk);
1378                 goto err_free_mmc_host;
1379         }
1380         clk_enable(host->iclk);
1381
1382         host->fclk = clk_get(&pdev->dev, "fck");
1383         if (IS_ERR(host->fclk)) {
1384                 ret = PTR_ERR(host->fclk);
1385                 goto err_free_iclk;
1386         }
1387
1388         dma_cap_zero(mask);
1389         dma_cap_set(DMA_SLAVE, mask);
1390
1391         host->dma_tx_burst = -1;
1392         host->dma_rx_burst = -1;
1393
1394         if (cpu_is_omap24xx())
1395                 sig = host->id == 0 ? OMAP24XX_DMA_MMC1_TX : OMAP24XX_DMA_MMC2_TX;
1396         else
1397                 sig = host->id == 0 ? OMAP_DMA_MMC_TX : OMAP_DMA_MMC2_TX;
1398         host->dma_tx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
1399 #if 0
1400         if (!host->dma_tx) {
1401                 dev_err(host->dev, "unable to obtain TX DMA engine channel %u\n",
1402                         sig);
1403                 goto err_dma;
1404         }
1405 #else
1406         if (!host->dma_tx)
1407                 dev_warn(host->dev, "unable to obtain TX DMA engine channel %u\n",
1408                         sig);
1409 #endif
1410         if (cpu_is_omap24xx())
1411                 sig = host->id == 0 ? OMAP24XX_DMA_MMC1_RX : OMAP24XX_DMA_MMC2_RX;
1412         else
1413                 sig = host->id == 0 ? OMAP_DMA_MMC_RX : OMAP_DMA_MMC2_RX;
1414         host->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
1415 #if 0
1416         if (!host->dma_rx) {
1417                 dev_err(host->dev, "unable to obtain RX DMA engine channel %u\n",
1418                         sig);
1419                 goto err_dma;
1420         }
1421 #else
1422         if (!host->dma_rx)
1423                 dev_warn(host->dev, "unable to obtain RX DMA engine channel %u\n",
1424                         sig);
1425 #endif
1426
1427         ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1428         if (ret)
1429                 goto err_free_dma;
1430
1431         if (pdata->init != NULL) {
1432                 ret = pdata->init(&pdev->dev);
1433                 if (ret < 0)
1434                         goto err_free_irq;
1435         }
1436
1437         host->nr_slots = pdata->nr_slots;
1438         host->reg_shift = (cpu_is_omap7xx() ? 1 : 2);
1439
1440         host->mmc_omap_wq = alloc_workqueue("mmc_omap", 0, 0);
1441         if (!host->mmc_omap_wq)
1442                 goto err_plat_cleanup;
1443
1444         for (i = 0; i < pdata->nr_slots; i++) {
1445                 ret = mmc_omap_new_slot(host, i);
1446                 if (ret < 0) {
1447                         while (--i >= 0)
1448                                 mmc_omap_remove_slot(host->slots[i]);
1449
1450                         goto err_destroy_wq;
1451                 }
1452         }
1453
1454         return 0;
1455
1456 err_destroy_wq:
1457         destroy_workqueue(host->mmc_omap_wq);
1458 err_plat_cleanup:
1459         if (pdata->cleanup)
1460                 pdata->cleanup(&pdev->dev);
1461 err_free_irq:
1462         free_irq(host->irq, host);
1463 err_free_dma:
1464         if (host->dma_tx)
1465                 dma_release_channel(host->dma_tx);
1466         if (host->dma_rx)
1467                 dma_release_channel(host->dma_rx);
1468         clk_put(host->fclk);
1469 err_free_iclk:
1470         clk_disable(host->iclk);
1471         clk_put(host->iclk);
1472 err_free_mmc_host:
1473         iounmap(host->virt_base);
1474 err_ioremap:
1475         kfree(host);
1476 err_free_mem_region:
1477         release_mem_region(res->start, resource_size(res));
1478         return ret;
1479 }
1480
1481 static int mmc_omap_remove(struct platform_device *pdev)
1482 {
1483         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1484         int i;
1485
1486         platform_set_drvdata(pdev, NULL);
1487
1488         BUG_ON(host == NULL);
1489
1490         for (i = 0; i < host->nr_slots; i++)
1491                 mmc_omap_remove_slot(host->slots[i]);
1492
1493         if (host->pdata->cleanup)
1494                 host->pdata->cleanup(&pdev->dev);
1495
1496         mmc_omap_fclk_enable(host, 0);
1497         free_irq(host->irq, host);
1498         clk_put(host->fclk);
1499         clk_disable(host->iclk);
1500         clk_put(host->iclk);
1501
1502         if (host->dma_tx)
1503                 dma_release_channel(host->dma_tx);
1504         if (host->dma_rx)
1505                 dma_release_channel(host->dma_rx);
1506
1507         iounmap(host->virt_base);
1508         release_mem_region(pdev->resource[0].start,
1509                            pdev->resource[0].end - pdev->resource[0].start + 1);
1510         destroy_workqueue(host->mmc_omap_wq);
1511
1512         kfree(host);
1513
1514         return 0;
1515 }
1516
1517 #ifdef CONFIG_PM
1518 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1519 {
1520         int i, ret = 0;
1521         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1522
1523         if (host == NULL || host->suspended)
1524                 return 0;
1525
1526         for (i = 0; i < host->nr_slots; i++) {
1527                 struct mmc_omap_slot *slot;
1528
1529                 slot = host->slots[i];
1530                 ret = mmc_suspend_host(slot->mmc);
1531                 if (ret < 0) {
1532                         while (--i >= 0) {
1533                                 slot = host->slots[i];
1534                                 mmc_resume_host(slot->mmc);
1535                         }
1536                         return ret;
1537                 }
1538         }
1539         host->suspended = 1;
1540         return 0;
1541 }
1542
1543 static int mmc_omap_resume(struct platform_device *pdev)
1544 {
1545         int i, ret = 0;
1546         struct mmc_omap_host *host = platform_get_drvdata(pdev);
1547
1548         if (host == NULL || !host->suspended)
1549                 return 0;
1550
1551         for (i = 0; i < host->nr_slots; i++) {
1552                 struct mmc_omap_slot *slot;
1553                 slot = host->slots[i];
1554                 ret = mmc_resume_host(slot->mmc);
1555                 if (ret < 0)
1556                         return ret;
1557
1558                 host->suspended = 0;
1559         }
1560         return 0;
1561 }
1562 #else
1563 #define mmc_omap_suspend        NULL
1564 #define mmc_omap_resume         NULL
1565 #endif
1566
1567 static struct platform_driver mmc_omap_driver = {
1568         .probe          = mmc_omap_probe,
1569         .remove         = mmc_omap_remove,
1570         .suspend        = mmc_omap_suspend,
1571         .resume         = mmc_omap_resume,
1572         .driver         = {
1573                 .name   = DRIVER_NAME,
1574                 .owner  = THIS_MODULE,
1575         },
1576 };
1577
1578 module_platform_driver(mmc_omap_driver);
1579 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1580 MODULE_LICENSE("GPL");
1581 MODULE_ALIAS("platform:" DRIVER_NAME);
1582 MODULE_AUTHOR("Juha Yrjölä");