2 * linux/drivers/mmc/host/mxcmmc.c - Freescale i.MX MMCI driver
4 * This is a driver for the SDHC controller found in Freescale MX2/MX3
5 * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
6 * Unlike the hardware found on MX1, this hardware just works and does
7 * not need all the quirks found in imxmmc.c, hence the separate driver.
9 * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
10 * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
12 * derived from pxamci.c by Russell King
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/ioport.h>
23 #include <linux/platform_device.h>
24 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/blkdev.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/mmc/host.h>
29 #include <linux/mmc/card.h>
30 #include <linux/delay.h>
31 #include <linux/clk.h>
33 #include <linux/gpio.h>
34 #include <linux/regulator/consumer.h>
38 #include <asm/sizes.h>
41 #ifdef CONFIG_ARCH_MX2
42 #include <mach/dma-mx1-mx2.h>
46 #define DRIVER_NAME "mxc-mmc"
48 #define MMC_REG_STR_STP_CLK 0x00
49 #define MMC_REG_STATUS 0x04
50 #define MMC_REG_CLK_RATE 0x08
51 #define MMC_REG_CMD_DAT_CONT 0x0C
52 #define MMC_REG_RES_TO 0x10
53 #define MMC_REG_READ_TO 0x14
54 #define MMC_REG_BLK_LEN 0x18
55 #define MMC_REG_NOB 0x1C
56 #define MMC_REG_REV_NO 0x20
57 #define MMC_REG_INT_CNTR 0x24
58 #define MMC_REG_CMD 0x28
59 #define MMC_REG_ARG 0x2C
60 #define MMC_REG_RES_FIFO 0x34
61 #define MMC_REG_BUFFER_ACCESS 0x38
63 #define STR_STP_CLK_RESET (1 << 3)
64 #define STR_STP_CLK_START_CLK (1 << 1)
65 #define STR_STP_CLK_STOP_CLK (1 << 0)
67 #define STATUS_CARD_INSERTION (1 << 31)
68 #define STATUS_CARD_REMOVAL (1 << 30)
69 #define STATUS_YBUF_EMPTY (1 << 29)
70 #define STATUS_XBUF_EMPTY (1 << 28)
71 #define STATUS_YBUF_FULL (1 << 27)
72 #define STATUS_XBUF_FULL (1 << 26)
73 #define STATUS_BUF_UND_RUN (1 << 25)
74 #define STATUS_BUF_OVFL (1 << 24)
75 #define STATUS_SDIO_INT_ACTIVE (1 << 14)
76 #define STATUS_END_CMD_RESP (1 << 13)
77 #define STATUS_WRITE_OP_DONE (1 << 12)
78 #define STATUS_DATA_TRANS_DONE (1 << 11)
79 #define STATUS_READ_OP_DONE (1 << 11)
80 #define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10)
81 #define STATUS_CARD_BUS_CLK_RUN (1 << 8)
82 #define STATUS_BUF_READ_RDY (1 << 7)
83 #define STATUS_BUF_WRITE_RDY (1 << 6)
84 #define STATUS_RESP_CRC_ERR (1 << 5)
85 #define STATUS_CRC_READ_ERR (1 << 3)
86 #define STATUS_CRC_WRITE_ERR (1 << 2)
87 #define STATUS_TIME_OUT_RESP (1 << 1)
88 #define STATUS_TIME_OUT_READ (1 << 0)
89 #define STATUS_ERR_MASK 0x2f
91 #define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12)
92 #define CMD_DAT_CONT_STOP_READWAIT (1 << 11)
93 #define CMD_DAT_CONT_START_READWAIT (1 << 10)
94 #define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8)
95 #define CMD_DAT_CONT_INIT (1 << 7)
96 #define CMD_DAT_CONT_WRITE (1 << 4)
97 #define CMD_DAT_CONT_DATA_ENABLE (1 << 3)
98 #define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0)
99 #define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0)
100 #define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0)
102 #define INT_SDIO_INT_WKP_EN (1 << 18)
103 #define INT_CARD_INSERTION_WKP_EN (1 << 17)
104 #define INT_CARD_REMOVAL_WKP_EN (1 << 16)
105 #define INT_CARD_INSERTION_EN (1 << 15)
106 #define INT_CARD_REMOVAL_EN (1 << 14)
107 #define INT_SDIO_IRQ_EN (1 << 13)
108 #define INT_DAT0_EN (1 << 12)
109 #define INT_BUF_READ_EN (1 << 4)
110 #define INT_BUF_WRITE_EN (1 << 3)
111 #define INT_END_CMD_RES_EN (1 << 2)
112 #define INT_WRITE_OP_DONE_EN (1 << 1)
113 #define INT_READ_OP_EN (1 << 0)
116 struct mmc_host *mmc;
117 struct resource *res;
123 int default_irq_mask;
125 unsigned int power_mode;
126 struct imxmmc_platform_data *pdata;
128 struct mmc_request *req;
129 struct mmc_command *cmd;
130 struct mmc_data *data;
132 unsigned int dma_nents;
133 unsigned int datasize;
134 unsigned int dma_dir;
143 struct work_struct datawork;
146 struct regulator *vcc;
149 static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios);
151 static inline void mxcmci_init_ocr(struct mxcmci_host *host)
153 #ifdef CONFIG_REGULATOR
154 host->vcc = regulator_get(mmc_dev(host->mmc), "vmmc");
156 if (IS_ERR(host->vcc)) {
159 host->mmc->ocr_avail = mmc_regulator_get_ocrmask(host->vcc);
160 if (host->pdata && host->pdata->ocr_avail)
161 dev_warn(mmc_dev(host->mmc),
162 "pdata->ocr_avail will not be used\n");
165 if (host->vcc == NULL) {
166 /* fall-back to platform data */
167 if (host->pdata && host->pdata->ocr_avail)
168 host->mmc->ocr_avail = host->pdata->ocr_avail;
170 host->mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
174 static inline void mxcmci_set_power(struct mxcmci_host *host, unsigned int vdd)
176 #ifdef CONFIG_REGULATOR
178 mmc_regulator_set_ocr(host->vcc, vdd);
180 if (host->pdata && host->pdata->setpower)
181 host->pdata->setpower(mmc_dev(host->mmc), vdd);
184 static inline int mxcmci_use_dma(struct mxcmci_host *host)
189 static void mxcmci_softreset(struct mxcmci_host *host)
193 dev_dbg(mmc_dev(host->mmc), "mxcmci_softreset\n");
196 writew(STR_STP_CLK_RESET, host->base + MMC_REG_STR_STP_CLK);
197 writew(STR_STP_CLK_RESET | STR_STP_CLK_START_CLK,
198 host->base + MMC_REG_STR_STP_CLK);
200 for (i = 0; i < 8; i++)
201 writew(STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
203 writew(0xff, host->base + MMC_REG_RES_TO);
206 static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data)
208 unsigned int nob = data->blocks;
209 unsigned int blksz = data->blksz;
210 unsigned int datasize = nob * blksz;
212 struct scatterlist *sg;
216 if (data->flags & MMC_DATA_STREAM)
220 data->bytes_xfered = 0;
222 writew(nob, host->base + MMC_REG_NOB);
223 writew(blksz, host->base + MMC_REG_BLK_LEN);
224 host->datasize = datasize;
227 for_each_sg(data->sg, sg, data->sg_len, i) {
228 if (sg->offset & 3 || sg->length & 3) {
234 if (data->flags & MMC_DATA_READ) {
235 host->dma_dir = DMA_FROM_DEVICE;
236 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
237 data->sg_len, host->dma_dir);
239 ret = imx_dma_setup_sg(host->dma, data->sg, host->dma_nents,
241 host->res->start + MMC_REG_BUFFER_ACCESS,
244 host->dma_dir = DMA_TO_DEVICE;
245 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
246 data->sg_len, host->dma_dir);
248 ret = imx_dma_setup_sg(host->dma, data->sg, host->dma_nents,
250 host->res->start + MMC_REG_BUFFER_ACCESS,
255 dev_err(mmc_dev(host->mmc), "failed to setup DMA : %d\n", ret);
260 imx_dma_enable(host->dma);
265 static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd,
268 u32 int_cntr = host->default_irq_mask;
271 WARN_ON(host->cmd != NULL);
274 switch (mmc_resp_type(cmd)) {
275 case MMC_RSP_R1: /* short CRC, OPCODE */
276 case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */
277 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC;
279 case MMC_RSP_R2: /* long 136 bit + CRC */
280 cmdat |= CMD_DAT_CONT_RESPONSE_136BIT;
282 case MMC_RSP_R3: /* short */
283 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT;
288 dev_err(mmc_dev(host->mmc), "unhandled response type 0x%x\n",
290 cmd->error = -EINVAL;
294 int_cntr = INT_END_CMD_RES_EN;
296 if (mxcmci_use_dma(host))
297 int_cntr |= INT_READ_OP_EN | INT_WRITE_OP_DONE_EN;
299 spin_lock_irqsave(&host->lock, flags);
301 int_cntr |= INT_SDIO_IRQ_EN;
302 writel(int_cntr, host->base + MMC_REG_INT_CNTR);
303 spin_unlock_irqrestore(&host->lock, flags);
305 writew(cmd->opcode, host->base + MMC_REG_CMD);
306 writel(cmd->arg, host->base + MMC_REG_ARG);
307 writew(cmdat, host->base + MMC_REG_CMD_DAT_CONT);
312 static void mxcmci_finish_request(struct mxcmci_host *host,
313 struct mmc_request *req)
315 u32 int_cntr = host->default_irq_mask;
318 spin_lock_irqsave(&host->lock, flags);
320 int_cntr |= INT_SDIO_IRQ_EN;
321 writel(int_cntr, host->base + MMC_REG_INT_CNTR);
322 spin_unlock_irqrestore(&host->lock, flags);
328 mmc_request_done(host->mmc, req);
331 static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat)
333 struct mmc_data *data = host->data;
337 if (mxcmci_use_dma(host)) {
338 imx_dma_disable(host->dma);
339 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_nents,
344 if (stat & STATUS_ERR_MASK) {
345 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",
347 if (stat & STATUS_CRC_READ_ERR) {
348 dev_err(mmc_dev(host->mmc), "%s: -EILSEQ\n", __func__);
349 data->error = -EILSEQ;
350 } else if (stat & STATUS_CRC_WRITE_ERR) {
351 u32 err_code = (stat >> 9) & 0x3;
352 if (err_code == 2) { /* No CRC response */
353 dev_err(mmc_dev(host->mmc),
354 "%s: No CRC -ETIMEDOUT\n", __func__);
355 data->error = -ETIMEDOUT;
357 dev_err(mmc_dev(host->mmc),
358 "%s: -EILSEQ\n", __func__);
359 data->error = -EILSEQ;
361 } else if (stat & STATUS_TIME_OUT_READ) {
362 dev_err(mmc_dev(host->mmc),
363 "%s: read -ETIMEDOUT\n", __func__);
364 data->error = -ETIMEDOUT;
366 dev_err(mmc_dev(host->mmc), "%s: -EIO\n", __func__);
370 data->bytes_xfered = host->datasize;
373 data_error = data->error;
380 static void mxcmci_read_response(struct mxcmci_host *host, unsigned int stat)
382 struct mmc_command *cmd = host->cmd;
389 if (stat & STATUS_TIME_OUT_RESP) {
390 dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n");
391 cmd->error = -ETIMEDOUT;
392 } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
393 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n");
394 cmd->error = -EILSEQ;
397 if (cmd->flags & MMC_RSP_PRESENT) {
398 if (cmd->flags & MMC_RSP_136) {
399 for (i = 0; i < 4; i++) {
400 a = readw(host->base + MMC_REG_RES_FIFO);
401 b = readw(host->base + MMC_REG_RES_FIFO);
402 cmd->resp[i] = a << 16 | b;
405 a = readw(host->base + MMC_REG_RES_FIFO);
406 b = readw(host->base + MMC_REG_RES_FIFO);
407 c = readw(host->base + MMC_REG_RES_FIFO);
408 cmd->resp[0] = a << 24 | b << 8 | c >> 8;
413 static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask)
416 unsigned long timeout = jiffies + HZ;
419 stat = readl(host->base + MMC_REG_STATUS);
420 if (stat & STATUS_ERR_MASK)
422 if (time_after(jiffies, timeout)) {
423 mxcmci_softreset(host);
424 mxcmci_set_clk_rate(host, host->clock);
425 return STATUS_TIME_OUT_READ;
433 static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes)
439 stat = mxcmci_poll_status(host,
440 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
443 *buf++ = readl(host->base + MMC_REG_BUFFER_ACCESS);
451 stat = mxcmci_poll_status(host,
452 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
455 tmp = readl(host->base + MMC_REG_BUFFER_ACCESS);
456 memcpy(b, &tmp, bytes);
462 static int mxcmci_push(struct mxcmci_host *host, void *_buf, int bytes)
468 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
471 writel(*buf++, host->base + MMC_REG_BUFFER_ACCESS);
479 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
483 memcpy(&tmp, b, bytes);
484 writel(tmp, host->base + MMC_REG_BUFFER_ACCESS);
487 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
494 static int mxcmci_transfer_data(struct mxcmci_host *host)
496 struct mmc_data *data = host->req->data;
497 struct scatterlist *sg;
503 if (data->flags & MMC_DATA_READ) {
504 for_each_sg(data->sg, sg, data->sg_len, i) {
505 stat = mxcmci_pull(host, sg_virt(sg), sg->length);
508 host->datasize += sg->length;
511 for_each_sg(data->sg, sg, data->sg_len, i) {
512 stat = mxcmci_push(host, sg_virt(sg), sg->length);
515 host->datasize += sg->length;
517 stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE);
524 static void mxcmci_datawork(struct work_struct *work)
526 struct mxcmci_host *host = container_of(work, struct mxcmci_host,
528 int datastat = mxcmci_transfer_data(host);
530 writel(STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE,
531 host->base + MMC_REG_STATUS);
532 mxcmci_finish_data(host, datastat);
534 if (host->req->stop) {
535 if (mxcmci_start_cmd(host, host->req->stop, 0)) {
536 mxcmci_finish_request(host, host->req);
540 mxcmci_finish_request(host, host->req);
545 static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat)
547 struct mmc_data *data = host->data;
553 data_error = mxcmci_finish_data(host, stat);
555 mxcmci_read_response(host, stat);
558 if (host->req->stop) {
559 if (mxcmci_start_cmd(host, host->req->stop, 0)) {
560 mxcmci_finish_request(host, host->req);
564 mxcmci_finish_request(host, host->req);
569 static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat)
571 mxcmci_read_response(host, stat);
574 if (!host->data && host->req) {
575 mxcmci_finish_request(host, host->req);
579 /* For the DMA case the DMA engine handles the data transfer
580 * automatically. For non DMA we have to do it ourselves.
581 * Don't do it in interrupt context though.
583 if (!mxcmci_use_dma(host) && host->data)
584 schedule_work(&host->datawork);
588 static irqreturn_t mxcmci_irq(int irq, void *devid)
590 struct mxcmci_host *host = devid;
595 stat = readl(host->base + MMC_REG_STATUS);
596 writel(stat & ~(STATUS_SDIO_INT_ACTIVE | STATUS_DATA_TRANS_DONE |
597 STATUS_WRITE_OP_DONE), host->base + MMC_REG_STATUS);
599 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
601 spin_lock_irqsave(&host->lock, flags);
602 sdio_irq = (stat & STATUS_SDIO_INT_ACTIVE) && host->use_sdio;
603 spin_unlock_irqrestore(&host->lock, flags);
606 if (mxcmci_use_dma(host) &&
607 (stat & (STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE)))
608 writel(STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE,
609 host->base + MMC_REG_STATUS);
613 writel(STATUS_SDIO_INT_ACTIVE, host->base + MMC_REG_STATUS);
614 mmc_signal_sdio_irq(host->mmc);
617 if (stat & STATUS_END_CMD_RESP)
618 mxcmci_cmd_done(host, stat);
621 if (mxcmci_use_dma(host) &&
622 (stat & (STATUS_DATA_TRANS_DONE | STATUS_WRITE_OP_DONE)))
623 mxcmci_data_done(host, stat);
625 if (host->default_irq_mask &&
626 (stat & (STATUS_CARD_INSERTION | STATUS_CARD_REMOVAL)))
627 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
631 static void mxcmci_request(struct mmc_host *mmc, struct mmc_request *req)
633 struct mxcmci_host *host = mmc_priv(mmc);
634 unsigned int cmdat = host->cmdat;
637 WARN_ON(host->req != NULL);
640 host->cmdat &= ~CMD_DAT_CONT_INIT;
645 error = mxcmci_setup_data(host, req->data);
647 req->cmd->error = error;
652 cmdat |= CMD_DAT_CONT_DATA_ENABLE;
654 if (req->data->flags & MMC_DATA_WRITE)
655 cmdat |= CMD_DAT_CONT_WRITE;
658 error = mxcmci_start_cmd(host, req->cmd, cmdat);
661 mxcmci_finish_request(host, req);
664 static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios)
666 unsigned int divider;
668 unsigned int clk_in = clk_get_rate(host->clk);
670 while (prescaler <= 0x800) {
671 for (divider = 1; divider <= 0xF; divider++) {
674 x = (clk_in / (divider + 1));
677 x /= (prescaler * 2);
691 writew((prescaler << 4) | divider, host->base + MMC_REG_CLK_RATE);
693 dev_dbg(mmc_dev(host->mmc), "scaler: %d divider: %d in: %d out: %d\n",
694 prescaler, divider, clk_in, clk_ios);
697 static void mxcmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
699 struct mxcmci_host *host = mmc_priv(mmc);
703 * use burstlen of 64 in 4 bit mode (--> reg value 0)
704 * use burstlen of 16 in 1 bit mode (--> reg value 16)
706 if (ios->bus_width == MMC_BUS_WIDTH_4)
711 imx_dma_config_burstlen(host->dma, blen);
713 if (ios->bus_width == MMC_BUS_WIDTH_4)
714 host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
716 host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4;
718 if (host->power_mode != ios->power_mode) {
719 mxcmci_set_power(host, ios->vdd);
720 host->power_mode = ios->power_mode;
722 if (ios->power_mode == MMC_POWER_ON)
723 host->cmdat |= CMD_DAT_CONT_INIT;
727 mxcmci_set_clk_rate(host, ios->clock);
728 writew(STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
730 writew(STR_STP_CLK_STOP_CLK, host->base + MMC_REG_STR_STP_CLK);
733 host->clock = ios->clock;
736 static irqreturn_t mxcmci_detect_irq(int irq, void *data)
738 struct mmc_host *mmc = data;
740 dev_dbg(mmc_dev(mmc), "%s\n", __func__);
742 mmc_detect_change(mmc, msecs_to_jiffies(250));
746 static int mxcmci_get_ro(struct mmc_host *mmc)
748 struct mxcmci_host *host = mmc_priv(mmc);
750 if (host->pdata && host->pdata->get_ro)
751 return !!host->pdata->get_ro(mmc_dev(mmc));
753 * Board doesn't support read only detection; let the mmc core
759 static void mxcmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
761 struct mxcmci_host *host = mmc_priv(mmc);
765 spin_lock_irqsave(&host->lock, flags);
766 host->use_sdio = enable;
767 int_cntr = readl(host->base + MMC_REG_INT_CNTR);
770 int_cntr |= INT_SDIO_IRQ_EN;
772 int_cntr &= ~INT_SDIO_IRQ_EN;
774 writel(int_cntr, host->base + MMC_REG_INT_CNTR);
775 spin_unlock_irqrestore(&host->lock, flags);
778 static void mxcmci_init_card(struct mmc_host *host, struct mmc_card *card)
781 * MX3 SoCs have a silicon bug which corrupts CRC calculation of
782 * multi-block transfers when connected SDIO peripheral doesn't
783 * drive the BUSY line as required by the specs.
784 * One way to prevent this is to only allow 1-bit transfers.
787 if (cpu_is_mx3() && card->type == MMC_TYPE_SDIO)
788 host->caps &= ~MMC_CAP_4_BIT_DATA;
790 host->caps |= MMC_CAP_4_BIT_DATA;
793 static const struct mmc_host_ops mxcmci_ops = {
794 .request = mxcmci_request,
795 .set_ios = mxcmci_set_ios,
796 .get_ro = mxcmci_get_ro,
797 .enable_sdio_irq = mxcmci_enable_sdio_irq,
798 .init_card = mxcmci_init_card,
801 static int mxcmci_probe(struct platform_device *pdev)
803 struct mmc_host *mmc;
804 struct mxcmci_host *host = NULL;
805 struct resource *iores, *r;
808 printk(KERN_INFO "i.MX SDHC driver\n");
810 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
811 irq = platform_get_irq(pdev, 0);
812 if (!iores || irq < 0)
815 r = request_mem_region(iores->start, resource_size(iores), pdev->name);
819 mmc = mmc_alloc_host(sizeof(struct mxcmci_host), &pdev->dev);
822 goto out_release_mem;
825 mmc->ops = &mxcmci_ops;
826 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
828 /* MMC core transfer sizes tunable parameters */
830 mmc->max_blk_size = 2048;
831 mmc->max_blk_count = 65535;
832 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
833 mmc->max_seg_size = mmc->max_req_size;
835 host = mmc_priv(mmc);
836 host->base = ioremap(r->start, resource_size(r));
843 host->pdata = pdev->dev.platform_data;
844 spin_lock_init(&host->lock);
846 mxcmci_init_ocr(host);
848 if (host->pdata && host->pdata->dat3_card_detect)
849 host->default_irq_mask =
850 INT_CARD_INSERTION_EN | INT_CARD_REMOVAL_EN;
852 host->default_irq_mask = 0;
857 host->clk = clk_get(&pdev->dev, NULL);
858 if (IS_ERR(host->clk)) {
859 ret = PTR_ERR(host->clk);
862 clk_enable(host->clk);
864 mxcmci_softreset(host);
866 host->rev_no = readw(host->base + MMC_REG_REV_NO);
867 if (host->rev_no != 0x400) {
869 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
874 mmc->f_min = clk_get_rate(host->clk) >> 16;
875 mmc->f_max = clk_get_rate(host->clk) >> 1;
877 /* recommended in data sheet */
878 writew(0x2db4, host->base + MMC_REG_READ_TO);
880 writel(host->default_irq_mask, host->base + MMC_REG_INT_CNTR);
883 host->dma = imx_dma_request_by_prio(DRIVER_NAME, DMA_PRIO_LOW);
885 dev_err(mmc_dev(host->mmc), "imx_dma_request_by_prio failed\n");
890 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
896 ret = imx_dma_config_channel(host->dma,
897 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_FIFO,
898 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
901 dev_err(mmc_dev(host->mmc), "failed to config DMA channel\n");
905 INIT_WORK(&host->datawork, mxcmci_datawork);
907 ret = request_irq(host->irq, mxcmci_irq, 0, DRIVER_NAME, host);
911 platform_set_drvdata(pdev, mmc);
913 if (host->pdata && host->pdata->init) {
914 ret = host->pdata->init(&pdev->dev, mxcmci_detect_irq,
925 free_irq(host->irq, host);
928 imx_dma_free(host->dma);
931 clk_disable(host->clk);
938 release_mem_region(iores->start, resource_size(iores));
942 static int mxcmci_remove(struct platform_device *pdev)
944 struct mmc_host *mmc = platform_get_drvdata(pdev);
945 struct mxcmci_host *host = mmc_priv(mmc);
947 platform_set_drvdata(pdev, NULL);
949 mmc_remove_host(mmc);
952 regulator_put(host->vcc);
954 if (host->pdata && host->pdata->exit)
955 host->pdata->exit(&pdev->dev, mmc);
957 free_irq(host->irq, host);
960 imx_dma_free(host->dma);
962 clk_disable(host->clk);
965 release_mem_region(host->res->start, resource_size(host->res));
966 release_resource(host->res);
974 static int mxcmci_suspend(struct device *dev)
976 struct mmc_host *mmc = dev_get_drvdata(dev);
977 struct mxcmci_host *host = mmc_priv(mmc);
981 ret = mmc_suspend_host(mmc);
982 clk_disable(host->clk);
987 static int mxcmci_resume(struct device *dev)
989 struct mmc_host *mmc = dev_get_drvdata(dev);
990 struct mxcmci_host *host = mmc_priv(mmc);
993 clk_enable(host->clk);
995 ret = mmc_resume_host(mmc);
1000 static const struct dev_pm_ops mxcmci_pm_ops = {
1001 .suspend = mxcmci_suspend,
1002 .resume = mxcmci_resume,
1006 static struct platform_driver mxcmci_driver = {
1007 .probe = mxcmci_probe,
1008 .remove = mxcmci_remove,
1010 .name = DRIVER_NAME,
1011 .owner = THIS_MODULE,
1013 .pm = &mxcmci_pm_ops,
1018 static int __init mxcmci_init(void)
1020 return platform_driver_register(&mxcmci_driver);
1023 static void __exit mxcmci_exit(void)
1025 platform_driver_unregister(&mxcmci_driver);
1028 module_init(mxcmci_init);
1029 module_exit(mxcmci_exit);
1031 MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
1032 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1033 MODULE_LICENSE("GPL");
1034 MODULE_ALIAS("platform:imx-mmc");