2 * Copyright (c) 2014-2015 MediaTek Inc.
3 * Author: Chaotian.Jing <chaotian.jing@mediatek.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/module.h>
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/ioport.h>
20 #include <linux/irq.h>
21 #include <linux/of_address.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_gpio.h>
24 #include <linux/pinctrl/consumer.h>
25 #include <linux/platform_device.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/regulator/consumer.h>
29 #include <linux/spinlock.h>
31 #include <linux/mmc/card.h>
32 #include <linux/mmc/core.h>
33 #include <linux/mmc/host.h>
34 #include <linux/mmc/mmc.h>
35 #include <linux/mmc/sd.h>
36 #include <linux/mmc/sdio.h>
38 #define MAX_BD_NUM 1024
40 /*--------------------------------------------------------------------------*/
41 /* Common Definition */
42 /*--------------------------------------------------------------------------*/
43 #define MSDC_BUS_1BITS 0x0
44 #define MSDC_BUS_4BITS 0x1
45 #define MSDC_BUS_8BITS 0x2
47 #define MSDC_BURST_64B 0x6
49 /*--------------------------------------------------------------------------*/
51 /*--------------------------------------------------------------------------*/
53 #define MSDC_IOCON 0x04
56 #define MSDC_INTEN 0x10
57 #define MSDC_FIFOCS 0x14
62 #define SDC_RESP0 0x40
63 #define SDC_RESP1 0x44
64 #define SDC_RESP2 0x48
65 #define SDC_RESP3 0x4c
66 #define SDC_BLK_NUM 0x50
67 #define SDC_ACMD_RESP 0x80
68 #define MSDC_DMA_SA 0x90
69 #define MSDC_DMA_CTRL 0x98
70 #define MSDC_DMA_CFG 0x9c
71 #define MSDC_PATCH_BIT 0xb0
72 #define MSDC_PATCH_BIT1 0xb4
73 #define MSDC_PAD_TUNE 0xec
75 /*--------------------------------------------------------------------------*/
77 /*--------------------------------------------------------------------------*/
80 #define MSDC_CFG_MODE (0x1 << 0) /* RW */
81 #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */
82 #define MSDC_CFG_RST (0x1 << 2) /* RW */
83 #define MSDC_CFG_PIO (0x1 << 3) /* RW */
84 #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */
85 #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */
86 #define MSDC_CFG_BV18PSS (0x1 << 6) /* R */
87 #define MSDC_CFG_CKSTB (0x1 << 7) /* R */
88 #define MSDC_CFG_CKDIV (0xff << 8) /* RW */
89 #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */
92 #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */
93 #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */
94 #define MSDC_IOCON_DSPL (0x1 << 2) /* RW */
95 #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */
96 #define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */
97 #define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */
98 #define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */
99 #define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */
100 #define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */
101 #define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */
102 #define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */
103 #define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */
104 #define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */
105 #define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */
106 #define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */
107 #define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */
110 #define MSDC_PS_CDEN (0x1 << 0) /* RW */
111 #define MSDC_PS_CDSTS (0x1 << 1) /* R */
112 #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */
113 #define MSDC_PS_DAT (0xff << 16) /* R */
114 #define MSDC_PS_CMD (0x1 << 24) /* R */
115 #define MSDC_PS_WP (0x1 << 31) /* R */
118 #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */
119 #define MSDC_INT_CDSC (0x1 << 1) /* W1C */
120 #define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */
121 #define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */
122 #define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */
123 #define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */
124 #define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */
125 #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */
126 #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */
127 #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */
128 #define MSDC_INT_CSTA (0x1 << 11) /* R */
129 #define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */
130 #define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */
131 #define MSDC_INT_DATTMO (0x1 << 14) /* W1C */
132 #define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */
133 #define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */
134 #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */
135 #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */
136 #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */
138 /* MSDC_INTEN mask */
139 #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */
140 #define MSDC_INTEN_CDSC (0x1 << 1) /* RW */
141 #define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */
142 #define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */
143 #define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */
144 #define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */
145 #define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */
146 #define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */
147 #define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */
148 #define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */
149 #define MSDC_INTEN_CSTA (0x1 << 11) /* RW */
150 #define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */
151 #define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */
152 #define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */
153 #define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */
154 #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */
155 #define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */
156 #define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */
157 #define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */
159 /* MSDC_FIFOCS mask */
160 #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */
161 #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */
162 #define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */
165 #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */
166 #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */
167 #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */
168 #define SDC_CFG_SDIO (0x1 << 19) /* RW */
169 #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */
170 #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */
171 #define SDC_CFG_DTOC (0xff << 24) /* RW */
174 #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */
175 #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */
176 #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */
178 /* MSDC_DMA_CTRL mask */
179 #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */
180 #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */
181 #define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */
182 #define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */
183 #define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */
184 #define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */
186 /* MSDC_DMA_CFG mask */
187 #define MSDC_DMA_CFG_STS (0x1 << 0) /* R */
188 #define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */
189 #define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */
190 #define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */
191 #define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */
193 /* MSDC_PATCH_BIT mask */
194 #define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */
195 #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7)
196 #define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10)
197 #define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */
198 #define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */
199 #define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */
200 #define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */
201 #define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */
202 #define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */
203 #define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */
204 #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */
205 #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */
207 #define REQ_CMD_EIO (0x1 << 0)
208 #define REQ_CMD_TMO (0x1 << 1)
209 #define REQ_DAT_ERR (0x1 << 2)
210 #define REQ_STOP_EIO (0x1 << 3)
211 #define REQ_STOP_TMO (0x1 << 4)
212 #define REQ_CMD_BUSY (0x1 << 5)
214 #define MSDC_PREPARE_FLAG (0x1 << 0)
215 #define MSDC_ASYNC_FLAG (0x1 << 1)
216 #define MSDC_MMAP_FLAG (0x1 << 2)
218 #define MTK_MMC_AUTOSUSPEND_DELAY 50
219 #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */
220 #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */
222 /*--------------------------------------------------------------------------*/
223 /* Descriptor Structure */
224 /*--------------------------------------------------------------------------*/
225 struct mt_gpdma_desc {
227 #define GPDMA_DESC_HWO (0x1 << 0)
228 #define GPDMA_DESC_BDP (0x1 << 1)
229 #define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */
230 #define GPDMA_DESC_INT (0x1 << 16)
234 #define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */
235 #define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */
241 struct mt_bdma_desc {
243 #define BDMA_DESC_EOL (0x1 << 0)
244 #define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */
245 #define BDMA_DESC_BLKPAD (0x1 << 17)
246 #define BDMA_DESC_DWPAD (0x1 << 18)
250 #define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */
254 struct scatterlist *sg; /* I/O scatter list */
255 struct mt_gpdma_desc *gpd; /* pointer to gpd array */
256 struct mt_bdma_desc *bd; /* pointer to bd array */
257 dma_addr_t gpd_addr; /* the physical address of gpd array */
258 dma_addr_t bd_addr; /* the physical address of bd array */
261 struct msdc_save_para {
272 struct mmc_host *mmc; /* mmc structure */
276 struct mmc_request *mrq;
277 struct mmc_command *cmd;
278 struct mmc_data *data;
281 void __iomem *base; /* host base address */
283 struct msdc_dma dma; /* dma channel */
286 u32 timeout_ns; /* data timeout ns */
287 u32 timeout_clks; /* data timeout clks */
289 struct pinctrl *pinctrl;
290 struct pinctrl_state *pins_default;
291 struct pinctrl_state *pins_uhs;
292 struct delayed_work req_timeout;
293 int irq; /* host interrupt */
295 struct clk *src_clk; /* msdc source clock */
296 struct clk *h_clk; /* msdc h_clk */
297 u32 mclk; /* mmc subsystem clock frequency */
298 u32 src_clk_freq; /* source clock frequency */
299 u32 sclk; /* SD/MS bus clock frequency */
302 struct msdc_save_para save_para; /* used when gate HCLK */
305 static void sdr_set_bits(void __iomem *reg, u32 bs)
307 u32 val = readl(reg);
313 static void sdr_clr_bits(void __iomem *reg, u32 bs)
315 u32 val = readl(reg);
321 static void sdr_set_field(void __iomem *reg, u32 field, u32 val)
323 unsigned int tv = readl(reg);
326 tv |= ((val) << (ffs((unsigned int)field) - 1));
330 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val)
332 unsigned int tv = readl(reg);
334 *val = ((tv & field) >> (ffs((unsigned int)field) - 1));
337 static void msdc_reset_hw(struct msdc_host *host)
341 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST);
342 while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST)
345 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR);
346 while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR)
349 val = readl(host->base + MSDC_INT);
350 writel(val, host->base + MSDC_INT);
353 static void msdc_cmd_next(struct msdc_host *host,
354 struct mmc_request *mrq, struct mmc_command *cmd);
356 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR |
357 MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY |
358 MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO;
359 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO |
360 MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR |
361 MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT;
363 static u8 msdc_dma_calcs(u8 *buf, u32 len)
367 for (i = 0; i < len; i++)
369 return 0xff - (u8) sum;
372 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
373 struct mmc_data *data)
375 unsigned int j, dma_len;
376 dma_addr_t dma_address;
378 struct scatterlist *sg;
379 struct mt_gpdma_desc *gpd;
380 struct mt_bdma_desc *bd;
388 gpd->gpd_info |= GPDMA_DESC_HWO;
389 gpd->gpd_info |= GPDMA_DESC_BDP;
390 /* need to clear first. use these bits to calc checksum */
391 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM;
392 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8;
395 for_each_sg(data->sg, sg, data->sg_count, j) {
396 dma_address = sg_dma_address(sg);
397 dma_len = sg_dma_len(sg);
400 bd[j].bd_info &= ~BDMA_DESC_BLKPAD;
401 bd[j].bd_info &= ~BDMA_DESC_DWPAD;
402 bd[j].ptr = (u32)dma_address;
403 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN;
404 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN);
406 if (j == data->sg_count - 1) /* the last bd */
407 bd[j].bd_info |= BDMA_DESC_EOL;
409 bd[j].bd_info &= ~BDMA_DESC_EOL;
411 /* checksume need to clear first */
412 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM;
413 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8;
416 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1);
417 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL);
418 dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE);
419 dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8);
420 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL);
421 writel((u32)dma->gpd_addr, host->base + MSDC_DMA_SA);
424 static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq)
426 struct mmc_data *data = mrq->data;
428 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) {
429 bool read = (data->flags & MMC_DATA_READ) != 0;
431 data->host_cookie |= MSDC_PREPARE_FLAG;
432 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len,
433 read ? DMA_FROM_DEVICE : DMA_TO_DEVICE);
437 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq)
439 struct mmc_data *data = mrq->data;
441 if (data->host_cookie & MSDC_ASYNC_FLAG)
444 if (data->host_cookie & MSDC_PREPARE_FLAG) {
445 bool read = (data->flags & MMC_DATA_READ) != 0;
447 dma_unmap_sg(host->dev, data->sg, data->sg_len,
448 read ? DMA_FROM_DEVICE : DMA_TO_DEVICE);
449 data->host_cookie &= ~MSDC_PREPARE_FLAG;
453 /* clock control primitives */
454 static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
459 host->timeout_ns = ns;
460 host->timeout_clks = clks;
461 if (host->sclk == 0) {
464 clk_ns = 1000000000UL / host->sclk;
465 timeout = (ns + clk_ns - 1) / clk_ns + clks;
466 /* in 1048576 sclk cycle unit */
467 timeout = (timeout + (0x1 << 20) - 1) >> 20;
468 sdr_get_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD, &mode);
469 /*DDR mode will double the clk cycles for data timeout */
470 timeout = mode >= 2 ? timeout * 2 : timeout;
471 timeout = timeout > 1 ? timeout - 1 : 0;
472 timeout = timeout > 255 ? 255 : timeout;
474 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout);
477 static void msdc_gate_clock(struct msdc_host *host)
479 clk_disable_unprepare(host->src_clk);
480 clk_disable_unprepare(host->h_clk);
483 static void msdc_ungate_clock(struct msdc_host *host)
485 clk_prepare_enable(host->h_clk);
486 clk_prepare_enable(host->src_clk);
487 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
491 static void msdc_set_mclk(struct msdc_host *host, int ddr, u32 hz)
499 dev_dbg(host->dev, "set mclk to 0\n");
501 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
505 flags = readl(host->base + MSDC_INTEN);
506 sdr_clr_bits(host->base + MSDC_INTEN, flags);
507 if (ddr) { /* may need to modify later */
508 mode = 0x2; /* ddr mode and use divisor */
509 if (hz >= (host->src_clk_freq >> 2)) {
510 div = 0; /* mean div = 1/4 */
511 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
513 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
514 sclk = (host->src_clk_freq >> 2) / div;
517 } else if (hz >= host->src_clk_freq) {
518 mode = 0x1; /* no divisor */
520 sclk = host->src_clk_freq;
522 mode = 0x0; /* use divisor */
523 if (hz >= (host->src_clk_freq >> 1)) {
524 div = 0; /* mean div = 1/2 */
525 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
527 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
528 sclk = (host->src_clk_freq >> 2) / div;
531 sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
532 (mode << 8) | (div % 0xff));
533 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
534 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
539 /* need because clk changed. */
540 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
541 sdr_set_bits(host->base + MSDC_INTEN, flags);
543 dev_dbg(host->dev, "sclk: %d, ddr: %d\n", host->sclk, ddr);
546 static inline u32 msdc_cmd_find_resp(struct msdc_host *host,
547 struct mmc_request *mrq, struct mmc_command *cmd)
551 switch (mmc_resp_type(cmd)) {
552 /* Actually, R1, R5, R6, R7 are the same */
574 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
575 struct mmc_request *mrq, struct mmc_command *cmd)
578 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 |
579 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode
581 u32 opcode = cmd->opcode;
582 u32 resp = msdc_cmd_find_resp(host, mrq, cmd);
583 u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7);
585 host->cmd_rsp = resp;
587 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) ||
588 opcode == MMC_STOP_TRANSMISSION)
589 rawcmd |= (0x1 << 14);
590 else if (opcode == SD_SWITCH_VOLTAGE)
591 rawcmd |= (0x1 << 30);
592 else if (opcode == SD_APP_SEND_SCR ||
593 opcode == SD_APP_SEND_NUM_WR_BLKS ||
594 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
595 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
596 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC))
597 rawcmd |= (0x1 << 11);
600 struct mmc_data *data = cmd->data;
602 if (mmc_op_multi(opcode)) {
603 if (mmc_card_mmc(host->mmc->card) && mrq->sbc &&
604 !(mrq->sbc->arg & 0xFFFF0000))
605 rawcmd |= 0x2 << 28; /* AutoCMD23 */
608 rawcmd |= ((data->blksz & 0xFFF) << 16);
609 if (data->flags & MMC_DATA_WRITE)
610 rawcmd |= (0x1 << 13);
611 if (data->blocks > 1)
612 rawcmd |= (0x2 << 11);
614 rawcmd |= (0x1 << 11);
615 /* Always use dma mode */
616 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO);
618 if (host->timeout_ns != data->timeout_ns ||
619 host->timeout_clks != data->timeout_clks)
620 msdc_set_timeout(host, data->timeout_ns,
623 writel(data->blocks, host->base + SDC_BLK_NUM);
628 static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq,
629 struct mmc_command *cmd, struct mmc_data *data)
635 read = data->flags & MMC_DATA_READ;
637 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
638 msdc_dma_setup(host, &host->dma, data);
639 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask);
640 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
641 dev_dbg(host->dev, "DMA start\n");
642 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n",
643 __func__, cmd->opcode, data->blocks, read);
646 static int msdc_auto_cmd_done(struct msdc_host *host, int events,
647 struct mmc_command *cmd)
649 u32 *rsp = cmd->resp;
651 rsp[0] = readl(host->base + SDC_ACMD_RESP);
653 if (events & MSDC_INT_ACMDRDY) {
657 if (events & MSDC_INT_ACMDCRCERR) {
658 cmd->error = -EILSEQ;
659 host->error |= REQ_STOP_EIO;
660 } else if (events & MSDC_INT_ACMDTMO) {
661 cmd->error = -ETIMEDOUT;
662 host->error |= REQ_STOP_TMO;
665 "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n",
666 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error);
671 static void msdc_track_cmd_data(struct msdc_host *host,
672 struct mmc_command *cmd, struct mmc_data *data)
675 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n",
676 __func__, cmd->opcode, cmd->arg, host->error);
679 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq)
684 ret = cancel_delayed_work(&host->req_timeout);
686 /* delay work already running */
689 spin_lock_irqsave(&host->lock, flags);
691 spin_unlock_irqrestore(&host->lock, flags);
693 msdc_track_cmd_data(host, mrq->cmd, mrq->data);
695 msdc_unprepare_data(host, mrq);
696 mmc_request_done(host->mmc, mrq);
698 pm_runtime_mark_last_busy(host->dev);
699 pm_runtime_put_autosuspend(host->dev);
702 /* returns true if command is fully handled; returns false otherwise */
703 static bool msdc_cmd_done(struct msdc_host *host, int events,
704 struct mmc_request *mrq, struct mmc_command *cmd)
709 u32 *rsp = cmd->resp;
711 if (mrq->sbc && cmd == mrq->cmd &&
712 (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR
713 | MSDC_INT_ACMDTMO)))
714 msdc_auto_cmd_done(host, events, mrq->sbc);
716 sbc_error = mrq->sbc && mrq->sbc->error;
718 if (!sbc_error && !(events & (MSDC_INT_CMDRDY
723 spin_lock_irqsave(&host->lock, flags);
726 spin_unlock_irqrestore(&host->lock, flags);
731 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask);
733 if (cmd->flags & MMC_RSP_PRESENT) {
734 if (cmd->flags & MMC_RSP_136) {
735 rsp[0] = readl(host->base + SDC_RESP3);
736 rsp[1] = readl(host->base + SDC_RESP2);
737 rsp[2] = readl(host->base + SDC_RESP1);
738 rsp[3] = readl(host->base + SDC_RESP0);
740 rsp[0] = readl(host->base + SDC_RESP0);
744 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) {
746 if (events & MSDC_INT_RSPCRCERR) {
747 cmd->error = -EILSEQ;
748 host->error |= REQ_CMD_EIO;
749 } else if (events & MSDC_INT_CMDTMO) {
750 cmd->error = -ETIMEDOUT;
751 host->error |= REQ_CMD_TMO;
756 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n",
757 __func__, cmd->opcode, cmd->arg, rsp[0],
760 msdc_cmd_next(host, mrq, cmd);
764 /* It is the core layer's responsibility to ensure card status
765 * is correct before issue a request. but host design do below
766 * checks recommended.
768 static inline bool msdc_cmd_is_ready(struct msdc_host *host,
769 struct mmc_request *mrq, struct mmc_command *cmd)
771 /* The max busy time we can endure is 20ms */
772 unsigned long tmo = jiffies + msecs_to_jiffies(20);
774 while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) &&
775 time_before(jiffies, tmo))
777 if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) {
778 dev_err(host->dev, "CMD bus busy detected\n");
779 host->error |= REQ_CMD_BUSY;
780 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
784 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) {
785 tmo = jiffies + msecs_to_jiffies(20);
786 /* R1B or with data, should check SDCBUSY */
787 while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) &&
788 time_before(jiffies, tmo))
790 if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) {
791 dev_err(host->dev, "Controller busy detected\n");
792 host->error |= REQ_CMD_BUSY;
793 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
800 static void msdc_start_command(struct msdc_host *host,
801 struct mmc_request *mrq, struct mmc_command *cmd)
808 if (!msdc_cmd_is_ready(host, mrq, cmd))
811 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 ||
812 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) {
813 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n");
818 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd);
819 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
821 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask);
822 writel(cmd->arg, host->base + SDC_ARG);
823 writel(rawcmd, host->base + SDC_CMD);
826 static void msdc_cmd_next(struct msdc_host *host,
827 struct mmc_request *mrq, struct mmc_command *cmd)
829 if (cmd->error || (mrq->sbc && mrq->sbc->error))
830 msdc_request_done(host, mrq);
831 else if (cmd == mrq->sbc)
832 msdc_start_command(host, mrq, mrq->cmd);
834 msdc_request_done(host, mrq);
836 msdc_start_data(host, mrq, cmd, cmd->data);
839 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq)
841 struct msdc_host *host = mmc_priv(mmc);
847 pm_runtime_get_sync(host->dev);
850 msdc_prepare_data(host, mrq);
852 /* if SBC is required, we have HW option and SW option.
853 * if HW option is enabled, and SBC does not have "special" flags,
854 * use HW option, otherwise use SW option
856 if (mrq->sbc && (!mmc_card_mmc(mmc->card) ||
857 (mrq->sbc->arg & 0xFFFF0000)))
858 msdc_start_command(host, mrq, mrq->sbc);
860 msdc_start_command(host, mrq, mrq->cmd);
863 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
866 struct msdc_host *host = mmc_priv(mmc);
867 struct mmc_data *data = mrq->data;
872 msdc_prepare_data(host, mrq);
873 data->host_cookie |= MSDC_ASYNC_FLAG;
876 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
879 struct msdc_host *host = mmc_priv(mmc);
880 struct mmc_data *data;
885 if (data->host_cookie) {
886 data->host_cookie &= ~MSDC_ASYNC_FLAG;
887 msdc_unprepare_data(host, mrq);
891 static void msdc_data_xfer_next(struct msdc_host *host,
892 struct mmc_request *mrq, struct mmc_data *data)
894 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error &&
895 (!data->bytes_xfered || !mrq->sbc))
896 msdc_start_command(host, mrq, mrq->stop);
898 msdc_request_done(host, mrq);
901 static bool msdc_data_xfer_done(struct msdc_host *host, u32 events,
902 struct mmc_request *mrq, struct mmc_data *data)
904 struct mmc_command *stop = data->stop;
907 unsigned int check_data = events &
908 (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO
909 | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR
910 | MSDC_INT_DMA_PROTECT);
912 spin_lock_irqsave(&host->lock, flags);
916 spin_unlock_irqrestore(&host->lock, flags);
921 if (check_data || (stop && stop->error)) {
922 dev_dbg(host->dev, "DMA status: 0x%8X\n",
923 readl(host->base + MSDC_DMA_CFG));
924 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP,
926 while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS)
928 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask);
929 dev_dbg(host->dev, "DMA stop\n");
931 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) {
932 data->bytes_xfered = data->blocks * data->blksz;
934 dev_err(host->dev, "interrupt events: %x\n", events);
936 host->error |= REQ_DAT_ERR;
937 data->bytes_xfered = 0;
939 if (events & MSDC_INT_DATTMO)
940 data->error = -ETIMEDOUT;
942 dev_err(host->dev, "%s: cmd=%d; blocks=%d",
943 __func__, mrq->cmd->opcode, data->blocks);
944 dev_err(host->dev, "data_error=%d xfer_size=%d\n",
945 (int)data->error, data->bytes_xfered);
948 msdc_data_xfer_next(host, mrq, data);
954 static void msdc_set_buswidth(struct msdc_host *host, u32 width)
956 u32 val = readl(host->base + SDC_CFG);
958 val &= ~SDC_CFG_BUSWIDTH;
962 case MMC_BUS_WIDTH_1:
963 val |= (MSDC_BUS_1BITS << 16);
965 case MMC_BUS_WIDTH_4:
966 val |= (MSDC_BUS_4BITS << 16);
968 case MMC_BUS_WIDTH_8:
969 val |= (MSDC_BUS_8BITS << 16);
973 writel(val, host->base + SDC_CFG);
974 dev_dbg(host->dev, "Bus Width = %d", width);
977 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios)
979 struct msdc_host *host = mmc_priv(mmc);
983 if (!IS_ERR(mmc->supply.vqmmc)) {
984 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
987 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
991 dev_err(host->dev, "Unsupported signal voltage!\n");
995 ret = regulator_set_voltage(mmc->supply.vqmmc, min_uv, max_uv);
998 "Regulator set error %d: %d - %d\n",
999 ret, min_uv, max_uv);
1001 /* Apply different pinctrl settings for different signal voltage */
1002 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
1003 pinctrl_select_state(host->pinctrl, host->pins_uhs);
1005 pinctrl_select_state(host->pinctrl, host->pins_default);
1011 static int msdc_card_busy(struct mmc_host *mmc)
1013 struct msdc_host *host = mmc_priv(mmc);
1014 u32 status = readl(host->base + MSDC_PS);
1016 /* check if any pin between dat[0:3] is low */
1017 if (((status >> 16) & 0xf) != 0xf)
1023 static void msdc_request_timeout(struct work_struct *work)
1025 struct msdc_host *host = container_of(work, struct msdc_host,
1028 /* simulate HW timeout status */
1029 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__);
1031 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__,
1032 host->mrq, host->mrq->cmd->opcode);
1034 dev_err(host->dev, "%s: aborting cmd=%d\n",
1035 __func__, host->cmd->opcode);
1036 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq,
1038 } else if (host->data) {
1039 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n",
1040 __func__, host->mrq->cmd->opcode,
1041 host->data->blocks);
1042 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq,
1048 static irqreturn_t msdc_irq(int irq, void *dev_id)
1050 struct msdc_host *host = (struct msdc_host *) dev_id;
1053 unsigned long flags;
1054 struct mmc_request *mrq;
1055 struct mmc_command *cmd;
1056 struct mmc_data *data;
1057 u32 events, event_mask;
1059 spin_lock_irqsave(&host->lock, flags);
1060 events = readl(host->base + MSDC_INT);
1061 event_mask = readl(host->base + MSDC_INTEN);
1062 /* clear interrupts */
1063 writel(events & event_mask, host->base + MSDC_INT);
1068 spin_unlock_irqrestore(&host->lock, flags);
1070 if (!(events & event_mask))
1075 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n",
1076 __func__, events, event_mask);
1081 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events);
1084 msdc_cmd_done(host, events, mrq, cmd);
1086 msdc_data_xfer_done(host, events, mrq, data);
1092 static void msdc_init_hw(struct msdc_host *host)
1096 /* Configure to MMC/SD mode, clock free running */
1097 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN);
1100 msdc_reset_hw(host);
1102 /* Disable card detection */
1103 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1105 /* Disable and clear all interrupts */
1106 writel(0, host->base + MSDC_INTEN);
1107 val = readl(host->base + MSDC_INT);
1108 writel(val, host->base + MSDC_INT);
1110 writel(0, host->base + MSDC_PAD_TUNE);
1111 writel(0, host->base + MSDC_IOCON);
1112 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 1);
1113 writel(0x403c004f, host->base + MSDC_PATCH_BIT);
1114 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
1115 writel(0xffff0089, host->base + MSDC_PATCH_BIT1);
1116 /* Configure to enable SDIO mode.
1117 * it's must otherwise sdio cmd5 failed
1119 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1121 /* disable detect SDIO device interrupt function */
1122 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1124 /* Configure to default data timeout */
1125 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
1127 dev_dbg(host->dev, "init hardware done!");
1130 static void msdc_deinit_hw(struct msdc_host *host)
1133 /* Disable and clear all interrupts */
1134 writel(0, host->base + MSDC_INTEN);
1136 val = readl(host->base + MSDC_INT);
1137 writel(val, host->base + MSDC_INT);
1140 /* init gpd and bd list in msdc_drv_probe */
1141 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
1143 struct mt_gpdma_desc *gpd = dma->gpd;
1144 struct mt_bdma_desc *bd = dma->bd;
1147 memset(gpd, 0, sizeof(struct mt_gpdma_desc));
1149 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */
1150 gpd->ptr = (u32)dma->bd_addr; /* physical address */
1152 memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM);
1153 for (i = 0; i < (MAX_BD_NUM - 1); i++)
1154 bd[i].next = (u32)dma->bd_addr + sizeof(*bd) * (i + 1);
1157 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1159 struct msdc_host *host = mmc_priv(mmc);
1163 pm_runtime_get_sync(host->dev);
1165 if (ios->timing == MMC_TIMING_UHS_DDR50 ||
1166 ios->timing == MMC_TIMING_MMC_DDR52)
1169 msdc_set_buswidth(host, ios->bus_width);
1171 /* Suspend/Resume will do power off/on */
1172 switch (ios->power_mode) {
1174 if (!IS_ERR(mmc->supply.vmmc)) {
1175 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1178 dev_err(host->dev, "Failed to set vmmc power!\n");
1184 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1185 ret = regulator_enable(mmc->supply.vqmmc);
1187 dev_err(host->dev, "Failed to set vqmmc power!\n");
1189 host->vqmmc_enabled = true;
1193 if (!IS_ERR(mmc->supply.vmmc))
1194 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1196 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1197 regulator_disable(mmc->supply.vqmmc);
1198 host->vqmmc_enabled = false;
1205 if (host->mclk != ios->clock || host->ddr != ddr)
1206 msdc_set_mclk(host, ddr, ios->clock);
1209 pm_runtime_mark_last_busy(host->dev);
1210 pm_runtime_put_autosuspend(host->dev);
1213 static struct mmc_host_ops mt_msdc_ops = {
1214 .post_req = msdc_post_req,
1215 .pre_req = msdc_pre_req,
1216 .request = msdc_ops_request,
1217 .set_ios = msdc_ops_set_ios,
1218 .start_signal_voltage_switch = msdc_ops_switch_volt,
1219 .card_busy = msdc_card_busy,
1222 static int msdc_drv_probe(struct platform_device *pdev)
1224 struct mmc_host *mmc;
1225 struct msdc_host *host;
1226 struct resource *res;
1229 if (!pdev->dev.of_node) {
1230 dev_err(&pdev->dev, "No DT found\n");
1233 /* Allocate MMC host for this device */
1234 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
1238 host = mmc_priv(mmc);
1239 ret = mmc_of_parse(mmc);
1243 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1244 host->base = devm_ioremap_resource(&pdev->dev, res);
1245 if (IS_ERR(host->base)) {
1246 ret = PTR_ERR(host->base);
1250 ret = mmc_regulator_get_supply(mmc);
1251 if (ret == -EPROBE_DEFER)
1254 host->src_clk = devm_clk_get(&pdev->dev, "source");
1255 if (IS_ERR(host->src_clk)) {
1256 ret = PTR_ERR(host->src_clk);
1260 host->h_clk = devm_clk_get(&pdev->dev, "hclk");
1261 if (IS_ERR(host->h_clk)) {
1262 ret = PTR_ERR(host->h_clk);
1266 host->irq = platform_get_irq(pdev, 0);
1267 if (host->irq < 0) {
1272 host->pinctrl = devm_pinctrl_get(&pdev->dev);
1273 if (IS_ERR(host->pinctrl)) {
1274 ret = PTR_ERR(host->pinctrl);
1275 dev_err(&pdev->dev, "Cannot find pinctrl!\n");
1279 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default");
1280 if (IS_ERR(host->pins_default)) {
1281 ret = PTR_ERR(host->pins_default);
1282 dev_err(&pdev->dev, "Cannot find pinctrl default!\n");
1286 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs");
1287 if (IS_ERR(host->pins_uhs)) {
1288 ret = PTR_ERR(host->pins_uhs);
1289 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n");
1293 host->dev = &pdev->dev;
1295 host->src_clk_freq = clk_get_rate(host->src_clk);
1296 /* Set host parameters to mmc */
1297 mmc->ops = &mt_msdc_ops;
1298 mmc->f_min = host->src_clk_freq / (4 * 255);
1300 mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23;
1301 mmc->caps |= MMC_CAP_RUNTIME_RESUME;
1302 /* MMC core transfer sizes tunable parameters */
1303 mmc->max_segs = MAX_BD_NUM;
1304 mmc->max_seg_size = BDMA_DESC_BUFLEN;
1305 mmc->max_blk_size = 2048;
1306 mmc->max_req_size = 512 * 1024;
1307 mmc->max_blk_count = mmc->max_req_size / 512;
1308 host->dma_mask = DMA_BIT_MASK(32);
1309 mmc_dev(mmc)->dma_mask = &host->dma_mask;
1311 host->timeout_clks = 3 * 1048576;
1312 host->dma.gpd = dma_alloc_coherent(&pdev->dev,
1313 sizeof(struct mt_gpdma_desc),
1314 &host->dma.gpd_addr, GFP_KERNEL);
1315 host->dma.bd = dma_alloc_coherent(&pdev->dev,
1316 MAX_BD_NUM * sizeof(struct mt_bdma_desc),
1317 &host->dma.bd_addr, GFP_KERNEL);
1318 if (!host->dma.gpd || !host->dma.bd) {
1322 msdc_init_gpd_bd(host, &host->dma);
1323 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout);
1324 spin_lock_init(&host->lock);
1326 platform_set_drvdata(pdev, mmc);
1327 msdc_ungate_clock(host);
1330 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq,
1331 IRQF_TRIGGER_LOW | IRQF_ONESHOT, pdev->name, host);
1335 pm_runtime_set_active(host->dev);
1336 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY);
1337 pm_runtime_use_autosuspend(host->dev);
1338 pm_runtime_enable(host->dev);
1339 ret = mmc_add_host(mmc);
1346 pm_runtime_disable(host->dev);
1348 platform_set_drvdata(pdev, NULL);
1349 msdc_deinit_hw(host);
1350 msdc_gate_clock(host);
1353 dma_free_coherent(&pdev->dev,
1354 sizeof(struct mt_gpdma_desc),
1355 host->dma.gpd, host->dma.gpd_addr);
1357 dma_free_coherent(&pdev->dev,
1358 MAX_BD_NUM * sizeof(struct mt_bdma_desc),
1359 host->dma.bd, host->dma.bd_addr);
1366 static int msdc_drv_remove(struct platform_device *pdev)
1368 struct mmc_host *mmc;
1369 struct msdc_host *host;
1371 mmc = platform_get_drvdata(pdev);
1372 host = mmc_priv(mmc);
1374 pm_runtime_get_sync(host->dev);
1376 platform_set_drvdata(pdev, NULL);
1377 mmc_remove_host(host->mmc);
1378 msdc_deinit_hw(host);
1379 msdc_gate_clock(host);
1381 pm_runtime_disable(host->dev);
1382 pm_runtime_put_noidle(host->dev);
1383 dma_free_coherent(&pdev->dev,
1384 sizeof(struct mt_gpdma_desc),
1385 host->dma.gpd, host->dma.gpd_addr);
1386 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc),
1387 host->dma.bd, host->dma.bd_addr);
1389 mmc_free_host(host->mmc);
1395 static void msdc_save_reg(struct msdc_host *host)
1397 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG);
1398 host->save_para.iocon = readl(host->base + MSDC_IOCON);
1399 host->save_para.sdc_cfg = readl(host->base + SDC_CFG);
1400 host->save_para.pad_tune = readl(host->base + MSDC_PAD_TUNE);
1401 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
1402 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
1405 static void msdc_restore_reg(struct msdc_host *host)
1407 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
1408 writel(host->save_para.iocon, host->base + MSDC_IOCON);
1409 writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
1410 writel(host->save_para.pad_tune, host->base + MSDC_PAD_TUNE);
1411 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
1412 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
1415 static int msdc_runtime_suspend(struct device *dev)
1417 struct mmc_host *mmc = dev_get_drvdata(dev);
1418 struct msdc_host *host = mmc_priv(mmc);
1420 msdc_save_reg(host);
1421 msdc_gate_clock(host);
1425 static int msdc_runtime_resume(struct device *dev)
1427 struct mmc_host *mmc = dev_get_drvdata(dev);
1428 struct msdc_host *host = mmc_priv(mmc);
1430 msdc_ungate_clock(host);
1431 msdc_restore_reg(host);
1436 static const struct dev_pm_ops msdc_dev_pm_ops = {
1437 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1438 pm_runtime_force_resume)
1439 SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL)
1442 static const struct of_device_id msdc_of_ids[] = {
1443 { .compatible = "mediatek,mt8135-mmc", },
1447 static struct platform_driver mt_msdc_driver = {
1448 .probe = msdc_drv_probe,
1449 .remove = msdc_drv_remove,
1452 .of_match_table = msdc_of_ids,
1453 .pm = &msdc_dev_pm_ops,
1457 module_platform_driver(mt_msdc_driver);
1458 MODULE_LICENSE("GPL v2");
1459 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver");