2 * Amlogic SD/eMMC driver for the GX/S905 family SoCs
4 * Copyright (c) 2016 BayLibre, SAS.
5 * Author: Kevin Hilman <khilman@baylibre.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution
19 * in the file called COPYING.
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/init.h>
24 #include <linux/device.h>
25 #include <linux/of_device.h>
26 #include <linux/platform_device.h>
27 #include <linux/ioport.h>
28 #include <linux/spinlock.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/mmc/host.h>
31 #include <linux/mmc/mmc.h>
32 #include <linux/mmc/sdio.h>
33 #include <linux/mmc/slot-gpio.h>
35 #include <linux/clk.h>
36 #include <linux/clk-provider.h>
37 #include <linux/regulator/consumer.h>
38 #include <linux/interrupt.h>
39 #include <linux/bitfield.h>
41 #define DRIVER_NAME "meson-gx-mmc"
43 #define SD_EMMC_CLOCK 0x0
44 #define CLK_DIV_MASK GENMASK(5, 0)
45 #define CLK_SRC_MASK GENMASK(7, 6)
46 #define CLK_CORE_PHASE_MASK GENMASK(9, 8)
47 #define CLK_TX_PHASE_MASK GENMASK(11, 10)
48 #define CLK_RX_PHASE_MASK GENMASK(13, 12)
49 #define CLK_TX_DELAY_MASK GENMASK(19, 16)
50 #define CLK_RX_DELAY_MASK GENMASK(23, 20)
51 #define CLK_DELAY_STEP_PS 200
52 #define CLK_PHASE_STEP 30
53 #define CLK_PHASE_POINT_NUM (360 / CLK_PHASE_STEP)
54 #define CLK_ALWAYS_ON BIT(24)
56 #define SD_EMMC_DELAY 0x4
57 #define SD_EMMC_ADJUST 0x8
58 #define SD_EMMC_CALOUT 0x10
59 #define SD_EMMC_START 0x40
60 #define START_DESC_INIT BIT(0)
61 #define START_DESC_BUSY BIT(1)
62 #define START_DESC_ADDR_MASK GENMASK(31, 2)
64 #define SD_EMMC_CFG 0x44
65 #define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
66 #define CFG_BUS_WIDTH_1 0x0
67 #define CFG_BUS_WIDTH_4 0x1
68 #define CFG_BUS_WIDTH_8 0x2
69 #define CFG_DDR BIT(2)
70 #define CFG_BLK_LEN_MASK GENMASK(7, 4)
71 #define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8)
72 #define CFG_RC_CC_MASK GENMASK(15, 12)
73 #define CFG_STOP_CLOCK BIT(22)
74 #define CFG_CLK_ALWAYS_ON BIT(18)
75 #define CFG_CHK_DS BIT(20)
76 #define CFG_AUTO_CLK BIT(23)
78 #define SD_EMMC_STATUS 0x48
79 #define STATUS_BUSY BIT(31)
80 #define STATUS_DATI GENMASK(23, 16)
82 #define SD_EMMC_IRQ_EN 0x4c
83 #define IRQ_RXD_ERR_MASK GENMASK(7, 0)
84 #define IRQ_TXD_ERR BIT(8)
85 #define IRQ_DESC_ERR BIT(9)
86 #define IRQ_RESP_ERR BIT(10)
88 (IRQ_RXD_ERR_MASK | IRQ_TXD_ERR | IRQ_DESC_ERR | IRQ_RESP_ERR)
89 #define IRQ_RESP_TIMEOUT BIT(11)
90 #define IRQ_DESC_TIMEOUT BIT(12)
91 #define IRQ_TIMEOUTS \
92 (IRQ_RESP_TIMEOUT | IRQ_DESC_TIMEOUT)
93 #define IRQ_END_OF_CHAIN BIT(13)
94 #define IRQ_RESP_STATUS BIT(14)
95 #define IRQ_SDIO BIT(15)
97 (IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN | IRQ_RESP_STATUS |\
100 #define SD_EMMC_CMD_CFG 0x50
101 #define SD_EMMC_CMD_ARG 0x54
102 #define SD_EMMC_CMD_DAT 0x58
103 #define SD_EMMC_CMD_RSP 0x5c
104 #define SD_EMMC_CMD_RSP1 0x60
105 #define SD_EMMC_CMD_RSP2 0x64
106 #define SD_EMMC_CMD_RSP3 0x68
108 #define SD_EMMC_RXD 0x94
109 #define SD_EMMC_TXD 0x94
110 #define SD_EMMC_LAST_REG SD_EMMC_TXD
112 #define SD_EMMC_CFG_BLK_SIZE 512 /* internal buffer max: 512 bytes */
113 #define SD_EMMC_CFG_RESP_TIMEOUT 256 /* in clock cycles */
114 #define SD_EMMC_CMD_TIMEOUT 1024 /* in ms */
115 #define SD_EMMC_CMD_TIMEOUT_DATA 4096 /* in ms */
116 #define SD_EMMC_CFG_CMD_GAP 16 /* in clock cycles */
117 #define SD_EMMC_DESC_BUF_LEN PAGE_SIZE
119 #define SD_EMMC_PRE_REQ_DONE BIT(0)
120 #define SD_EMMC_DESC_CHAIN_MODE BIT(1)
122 #define MUX_CLK_NUM_PARENTS 2
124 struct sd_emmc_desc {
133 struct mmc_host *mmc;
134 struct mmc_command *cmd;
138 struct clk *core_clk;
142 unsigned long req_rate;
144 struct pinctrl *pinctrl;
145 struct pinctrl_state *pins_default;
146 struct pinctrl_state *pins_clk_gate;
148 unsigned int bounce_buf_size;
150 dma_addr_t bounce_dma_addr;
151 struct sd_emmc_desc *descs;
152 dma_addr_t descs_dma_addr;
157 #define CMD_CFG_LENGTH_MASK GENMASK(8, 0)
158 #define CMD_CFG_BLOCK_MODE BIT(9)
159 #define CMD_CFG_R1B BIT(10)
160 #define CMD_CFG_END_OF_CHAIN BIT(11)
161 #define CMD_CFG_TIMEOUT_MASK GENMASK(15, 12)
162 #define CMD_CFG_NO_RESP BIT(16)
163 #define CMD_CFG_NO_CMD BIT(17)
164 #define CMD_CFG_DATA_IO BIT(18)
165 #define CMD_CFG_DATA_WR BIT(19)
166 #define CMD_CFG_RESP_NOCRC BIT(20)
167 #define CMD_CFG_RESP_128 BIT(21)
168 #define CMD_CFG_RESP_NUM BIT(22)
169 #define CMD_CFG_DATA_NUM BIT(23)
170 #define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24)
171 #define CMD_CFG_ERROR BIT(30)
172 #define CMD_CFG_OWNER BIT(31)
174 #define CMD_DATA_MASK GENMASK(31, 2)
175 #define CMD_DATA_BIG_ENDIAN BIT(1)
176 #define CMD_DATA_SRAM BIT(0)
177 #define CMD_RESP_MASK GENMASK(31, 1)
178 #define CMD_RESP_SRAM BIT(0)
180 struct meson_mmc_phase {
183 unsigned long phase_mask;
184 unsigned long delay_mask;
185 unsigned int delay_step_ps;
188 #define to_meson_mmc_phase(_hw) container_of(_hw, struct meson_mmc_phase, hw)
190 static int meson_mmc_clk_get_phase(struct clk_hw *hw)
192 struct meson_mmc_phase *mmc = to_meson_mmc_phase(hw);
193 unsigned int phase_num = 1 << hweight_long(mmc->phase_mask);
194 unsigned long period_ps, p, d;
198 val = readl(mmc->reg);
199 p = (val & mmc->phase_mask) >> __ffs(mmc->phase_mask);
200 degrees = p * 360 / phase_num;
202 if (mmc->delay_mask) {
203 period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000,
204 clk_get_rate(hw->clk));
205 d = (val & mmc->delay_mask) >> __ffs(mmc->delay_mask);
206 degrees += d * mmc->delay_step_ps * 360 / period_ps;
213 static void meson_mmc_apply_phase_delay(struct meson_mmc_phase *mmc,
219 val = readl(mmc->reg);
220 val &= ~mmc->phase_mask;
221 val |= phase << __ffs(mmc->phase_mask);
223 if (mmc->delay_mask) {
224 val &= ~mmc->delay_mask;
225 val |= delay << __ffs(mmc->delay_mask);
228 writel(val, mmc->reg);
231 static int meson_mmc_clk_set_phase(struct clk_hw *hw, int degrees)
233 struct meson_mmc_phase *mmc = to_meson_mmc_phase(hw);
234 unsigned int phase_num = 1 << hweight_long(mmc->phase_mask);
235 unsigned long period_ps, d = 0, r;
240 if (!mmc->delay_mask) {
241 p = DIV_ROUND_CLOSEST_ULL(p, 360 / phase_num);
243 period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000,
244 clk_get_rate(hw->clk));
246 /* First compute the phase index (p), the remainder (r) is the
247 * part we'll try to acheive using the delays (d).
249 r = do_div(p, 360 / phase_num);
250 d = DIV_ROUND_CLOSEST(r * period_ps,
251 360 * mmc->delay_step_ps);
252 d = min(d, mmc->delay_mask >> __ffs(mmc->delay_mask));
255 meson_mmc_apply_phase_delay(mmc, p, d);
259 static const struct clk_ops meson_mmc_clk_phase_ops = {
260 .get_phase = meson_mmc_clk_get_phase,
261 .set_phase = meson_mmc_clk_set_phase,
264 static unsigned int meson_mmc_get_timeout_msecs(struct mmc_data *data)
266 unsigned int timeout = data->timeout_ns / NSEC_PER_MSEC;
269 return SD_EMMC_CMD_TIMEOUT_DATA;
271 timeout = roundup_pow_of_two(timeout);
273 return min(timeout, 32768U); /* max. 2^15 ms */
276 static struct mmc_command *meson_mmc_get_next_command(struct mmc_command *cmd)
278 if (cmd->opcode == MMC_SET_BLOCK_COUNT && !cmd->error)
279 return cmd->mrq->cmd;
280 else if (mmc_op_multi(cmd->opcode) &&
281 (!cmd->mrq->sbc || cmd->error || cmd->data->error))
282 return cmd->mrq->stop;
287 static void meson_mmc_get_transfer_mode(struct mmc_host *mmc,
288 struct mmc_request *mrq)
290 struct mmc_data *data = mrq->data;
291 struct scatterlist *sg;
293 bool use_desc_chain_mode = true;
296 * Broken SDIO with AP6255-based WiFi on Khadas VIM Pro has been
297 * reported. For some strange reason this occurs in descriptor
298 * chain mode only. So let's fall back to bounce buffer mode
299 * for command SD_IO_RW_EXTENDED.
301 if (mrq->cmd->opcode == SD_IO_RW_EXTENDED)
304 for_each_sg(data->sg, sg, data->sg_len, i)
305 /* check for 8 byte alignment */
306 if (sg->offset & 7) {
307 WARN_ONCE(1, "unaligned scatterlist buffer\n");
308 use_desc_chain_mode = false;
312 if (use_desc_chain_mode)
313 data->host_cookie |= SD_EMMC_DESC_CHAIN_MODE;
316 static inline bool meson_mmc_desc_chain_mode(const struct mmc_data *data)
318 return data->host_cookie & SD_EMMC_DESC_CHAIN_MODE;
321 static inline bool meson_mmc_bounce_buf_read(const struct mmc_data *data)
323 return data && data->flags & MMC_DATA_READ &&
324 !meson_mmc_desc_chain_mode(data);
327 static void meson_mmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
329 struct mmc_data *data = mrq->data;
334 meson_mmc_get_transfer_mode(mmc, mrq);
335 data->host_cookie |= SD_EMMC_PRE_REQ_DONE;
337 if (!meson_mmc_desc_chain_mode(data))
340 data->sg_count = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len,
341 mmc_get_dma_dir(data));
343 dev_err(mmc_dev(mmc), "dma_map_sg failed");
346 static void meson_mmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
349 struct mmc_data *data = mrq->data;
351 if (data && meson_mmc_desc_chain_mode(data) && data->sg_count)
352 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
353 mmc_get_dma_dir(data));
356 static bool meson_mmc_timing_is_ddr(struct mmc_ios *ios)
358 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
359 ios->timing == MMC_TIMING_UHS_DDR50 ||
360 ios->timing == MMC_TIMING_MMC_HS400)
367 * Gating the clock on this controller is tricky. It seems the mmc clock
368 * is also used by the controller. It may crash during some operation if the
369 * clock is stopped. The safest thing to do, whenever possible, is to keep
370 * clock running at stop it at the pad using the pinmux.
372 static void meson_mmc_clk_gate(struct meson_host *host)
376 if (host->pins_clk_gate) {
377 pinctrl_select_state(host->pinctrl, host->pins_clk_gate);
380 * If the pinmux is not provided - default to the classic and
383 cfg = readl(host->regs + SD_EMMC_CFG);
384 cfg |= CFG_STOP_CLOCK;
385 writel(cfg, host->regs + SD_EMMC_CFG);
389 static void meson_mmc_clk_ungate(struct meson_host *host)
393 if (host->pins_clk_gate)
394 pinctrl_select_state(host->pinctrl, host->pins_default);
396 /* Make sure the clock is not stopped in the controller */
397 cfg = readl(host->regs + SD_EMMC_CFG);
398 cfg &= ~CFG_STOP_CLOCK;
399 writel(cfg, host->regs + SD_EMMC_CFG);
402 static int meson_mmc_clk_set(struct meson_host *host, struct mmc_ios *ios)
404 struct mmc_host *mmc = host->mmc;
405 unsigned long rate = ios->clock;
409 /* DDR modes require higher module clock */
410 if (meson_mmc_timing_is_ddr(ios))
413 /* Same request - bail-out */
414 if (host->req_rate == rate)
418 meson_mmc_clk_gate(host);
422 mmc->actual_clock = 0;
423 /* return with clock being stopped */
427 /* Stop the clock during rate change to avoid glitches */
428 cfg = readl(host->regs + SD_EMMC_CFG);
429 cfg |= CFG_STOP_CLOCK;
430 writel(cfg, host->regs + SD_EMMC_CFG);
432 ret = clk_set_rate(host->mmc_clk, rate);
434 dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n",
439 host->req_rate = rate;
440 mmc->actual_clock = clk_get_rate(host->mmc_clk);
442 /* We should report the real output frequency of the controller */
443 if (meson_mmc_timing_is_ddr(ios))
444 mmc->actual_clock >>= 1;
446 dev_dbg(host->dev, "clk rate: %u Hz\n", mmc->actual_clock);
447 if (ios->clock != mmc->actual_clock)
448 dev_dbg(host->dev, "requested rate was %u\n", ios->clock);
450 /* (re)start clock */
451 meson_mmc_clk_ungate(host);
457 * The SD/eMMC IP block has an internal mux and divider used for
458 * generating the MMC clock. Use the clock framework to create and
459 * manage these clocks.
461 static int meson_mmc_clk_init(struct meson_host *host)
463 struct clk_init_data init;
465 struct clk_divider *div;
466 struct meson_mmc_phase *core, *tx, *rx;
470 const char *mux_parent_names[MUX_CLK_NUM_PARENTS];
471 const char *clk_parent[1];
474 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
476 clk_reg |= CLK_ALWAYS_ON;
477 clk_reg |= CLK_DIV_MASK;
478 writel(clk_reg, host->regs + SD_EMMC_CLOCK);
480 /* get the mux parents */
481 for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) {
485 snprintf(name, sizeof(name), "clkin%d", i);
486 clk = devm_clk_get(host->dev, name);
488 if (clk != ERR_PTR(-EPROBE_DEFER))
489 dev_err(host->dev, "Missing clock %s\n", name);
493 mux_parent_names[i] = __clk_get_name(clk);
497 mux = devm_kzalloc(host->dev, sizeof(*mux), GFP_KERNEL);
501 snprintf(clk_name, sizeof(clk_name), "%s#mux", dev_name(host->dev));
502 init.name = clk_name;
503 init.ops = &clk_mux_ops;
505 init.parent_names = mux_parent_names;
506 init.num_parents = MUX_CLK_NUM_PARENTS;
508 mux->reg = host->regs + SD_EMMC_CLOCK;
509 mux->shift = __ffs(CLK_SRC_MASK);
510 mux->mask = CLK_SRC_MASK >> mux->shift;
511 mux->hw.init = &init;
513 clk = devm_clk_register(host->dev, &mux->hw);
514 if (WARN_ON(IS_ERR(clk)))
517 /* create the divider */
518 div = devm_kzalloc(host->dev, sizeof(*div), GFP_KERNEL);
522 snprintf(clk_name, sizeof(clk_name), "%s#div", dev_name(host->dev));
523 init.name = clk_name;
524 init.ops = &clk_divider_ops;
525 init.flags = CLK_SET_RATE_PARENT;
526 clk_parent[0] = __clk_get_name(clk);
527 init.parent_names = clk_parent;
528 init.num_parents = 1;
530 div->reg = host->regs + SD_EMMC_CLOCK;
531 div->shift = __ffs(CLK_DIV_MASK);
532 div->width = __builtin_popcountl(CLK_DIV_MASK);
533 div->hw.init = &init;
534 div->flags = CLK_DIVIDER_ONE_BASED;
536 clk = devm_clk_register(host->dev, &div->hw);
537 if (WARN_ON(IS_ERR(clk)))
540 /* create the mmc core clock */
541 core = devm_kzalloc(host->dev, sizeof(*core), GFP_KERNEL);
545 snprintf(clk_name, sizeof(clk_name), "%s#core", dev_name(host->dev));
546 init.name = clk_name;
547 init.ops = &meson_mmc_clk_phase_ops;
548 init.flags = CLK_SET_RATE_PARENT;
549 clk_parent[0] = __clk_get_name(clk);
550 init.parent_names = clk_parent;
551 init.num_parents = 1;
553 core->reg = host->regs + SD_EMMC_CLOCK;
554 core->phase_mask = CLK_CORE_PHASE_MASK;
555 core->hw.init = &init;
557 host->mmc_clk = devm_clk_register(host->dev, &core->hw);
558 if (WARN_ON(PTR_ERR_OR_ZERO(host->mmc_clk)))
559 return PTR_ERR(host->mmc_clk);
561 /* create the mmc tx clock */
562 tx = devm_kzalloc(host->dev, sizeof(*tx), GFP_KERNEL);
566 snprintf(clk_name, sizeof(clk_name), "%s#tx", dev_name(host->dev));
567 init.name = clk_name;
568 init.ops = &meson_mmc_clk_phase_ops;
570 clk_parent[0] = __clk_get_name(host->mmc_clk);
571 init.parent_names = clk_parent;
572 init.num_parents = 1;
574 tx->reg = host->regs + SD_EMMC_CLOCK;
575 tx->phase_mask = CLK_TX_PHASE_MASK;
576 tx->delay_mask = CLK_TX_DELAY_MASK;
577 tx->delay_step_ps = CLK_DELAY_STEP_PS;
580 host->tx_clk = devm_clk_register(host->dev, &tx->hw);
581 if (WARN_ON(PTR_ERR_OR_ZERO(host->tx_clk)))
582 return PTR_ERR(host->tx_clk);
584 /* create the mmc rx clock */
585 rx = devm_kzalloc(host->dev, sizeof(*rx), GFP_KERNEL);
589 snprintf(clk_name, sizeof(clk_name), "%s#rx", dev_name(host->dev));
590 init.name = clk_name;
591 init.ops = &meson_mmc_clk_phase_ops;
593 clk_parent[0] = __clk_get_name(host->mmc_clk);
594 init.parent_names = clk_parent;
595 init.num_parents = 1;
597 rx->reg = host->regs + SD_EMMC_CLOCK;
598 rx->phase_mask = CLK_RX_PHASE_MASK;
599 rx->delay_mask = CLK_RX_DELAY_MASK;
600 rx->delay_step_ps = CLK_DELAY_STEP_PS;
603 host->rx_clk = devm_clk_register(host->dev, &rx->hw);
604 if (WARN_ON(PTR_ERR_OR_ZERO(host->rx_clk)))
605 return PTR_ERR(host->rx_clk);
607 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
608 host->mmc->f_min = clk_round_rate(host->mmc_clk, 400000);
609 ret = clk_set_rate(host->mmc_clk, host->mmc->f_min);
614 * Set phases : These values are mostly the datasheet recommended ones
615 * except for the Tx phase. Datasheet recommends 180 but some cards
616 * fail at initialisation with it. 270 works just fine, it fixes these
617 * initialisation issues and enable eMMC DDR52 mode.
619 clk_set_phase(host->mmc_clk, 180);
620 clk_set_phase(host->tx_clk, 270);
621 clk_set_phase(host->rx_clk, 0);
623 return clk_prepare_enable(host->mmc_clk);
626 static void meson_mmc_shift_map(unsigned long *map, unsigned long shift)
628 DECLARE_BITMAP(left, CLK_PHASE_POINT_NUM);
629 DECLARE_BITMAP(right, CLK_PHASE_POINT_NUM);
632 * shift the bitmap right and reintroduce the dropped bits on the left
635 bitmap_shift_right(right, map, shift, CLK_PHASE_POINT_NUM);
636 bitmap_shift_left(left, map, CLK_PHASE_POINT_NUM - shift,
637 CLK_PHASE_POINT_NUM);
638 bitmap_or(map, left, right, CLK_PHASE_POINT_NUM);
641 static void meson_mmc_find_next_region(unsigned long *map,
642 unsigned long *start,
645 *start = find_next_bit(map, CLK_PHASE_POINT_NUM, *start);
646 *stop = find_next_zero_bit(map, CLK_PHASE_POINT_NUM, *start);
649 static int meson_mmc_find_tuning_point(unsigned long *test)
651 unsigned long shift, stop, offset = 0, start = 0, size = 0;
653 /* Get the all good/all bad situation out the way */
654 if (bitmap_full(test, CLK_PHASE_POINT_NUM))
655 return 0; /* All points are good so point 0 will do */
656 else if (bitmap_empty(test, CLK_PHASE_POINT_NUM))
657 return -EIO; /* No successful tuning point */
660 * Now we know there is a least one region find. Make sure it does
661 * not wrap by the shifting the bitmap if necessary
663 shift = find_first_zero_bit(test, CLK_PHASE_POINT_NUM);
665 meson_mmc_shift_map(test, shift);
667 while (start < CLK_PHASE_POINT_NUM) {
668 meson_mmc_find_next_region(test, &start, &stop);
670 if ((stop - start) > size) {
678 /* Get the center point of the region */
679 offset += (size / 2);
681 /* Shift the result back */
682 offset = (offset + shift) % CLK_PHASE_POINT_NUM;
687 static int meson_mmc_clk_phase_tuning(struct mmc_host *mmc, u32 opcode,
691 DECLARE_BITMAP(test, CLK_PHASE_POINT_NUM);
693 dev_dbg(mmc_dev(mmc), "%s phase/delay tunning...\n",
694 __clk_get_name(clk));
695 bitmap_zero(test, CLK_PHASE_POINT_NUM);
697 /* Explore tuning points */
698 for (point = 0; point < CLK_PHASE_POINT_NUM; point++) {
699 clk_set_phase(clk, point * CLK_PHASE_STEP);
700 ret = mmc_send_tuning(mmc, opcode, NULL);
702 set_bit(point, test);
705 /* Find the optimal tuning point and apply it */
706 point = meson_mmc_find_tuning_point(test);
708 return point; /* tuning failed */
710 clk_set_phase(clk, point * CLK_PHASE_STEP);
711 dev_dbg(mmc_dev(mmc), "success with phase: %d\n",
716 static int meson_mmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
718 struct meson_host *host = mmc_priv(mmc);
722 * If this is the initial tuning, try to get a sane Rx starting
723 * phase before doing the actual tuning.
725 if (!mmc->doing_retune) {
726 ret = meson_mmc_clk_phase_tuning(mmc, opcode, host->rx_clk);
732 ret = meson_mmc_clk_phase_tuning(mmc, opcode, host->tx_clk);
736 return meson_mmc_clk_phase_tuning(mmc, opcode, host->rx_clk);
739 static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
741 struct meson_host *host = mmc_priv(mmc);
746 * GPIO regulator, only controls switching between 1v8 and
747 * 3v3, doesn't support MMC_POWER_OFF, MMC_POWER_ON.
749 switch (ios->power_mode) {
751 if (!IS_ERR(mmc->supply.vmmc))
752 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
754 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
755 regulator_disable(mmc->supply.vqmmc);
756 host->vqmmc_enabled = false;
762 if (!IS_ERR(mmc->supply.vmmc))
763 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
766 clk_set_phase(host->rx_clk, 0);
767 clk_set_phase(host->tx_clk, 270);
772 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
773 int ret = regulator_enable(mmc->supply.vqmmc);
777 "failed to enable vqmmc regulator\n");
779 host->vqmmc_enabled = true;
786 switch (ios->bus_width) {
787 case MMC_BUS_WIDTH_1:
788 bus_width = CFG_BUS_WIDTH_1;
790 case MMC_BUS_WIDTH_4:
791 bus_width = CFG_BUS_WIDTH_4;
793 case MMC_BUS_WIDTH_8:
794 bus_width = CFG_BUS_WIDTH_8;
797 dev_err(host->dev, "Invalid ios->bus_width: %u. Setting to 4.\n",
799 bus_width = CFG_BUS_WIDTH_4;
802 val = readl(host->regs + SD_EMMC_CFG);
803 val &= ~CFG_BUS_WIDTH_MASK;
804 val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width);
807 if (meson_mmc_timing_is_ddr(ios))
811 if (ios->timing == MMC_TIMING_MMC_HS400)
814 err = meson_mmc_clk_set(host, ios);
816 dev_err(host->dev, "Failed to set clock: %d\n,", err);
818 writel(val, host->regs + SD_EMMC_CFG);
819 dev_dbg(host->dev, "SD_EMMC_CFG: 0x%08x\n", val);
822 static void meson_mmc_request_done(struct mmc_host *mmc,
823 struct mmc_request *mrq)
825 struct meson_host *host = mmc_priv(mmc);
828 mmc_request_done(host->mmc, mrq);
831 static void meson_mmc_set_blksz(struct mmc_host *mmc, unsigned int blksz)
833 struct meson_host *host = mmc_priv(mmc);
836 cfg = readl(host->regs + SD_EMMC_CFG);
837 blksz_old = FIELD_GET(CFG_BLK_LEN_MASK, cfg);
839 if (!is_power_of_2(blksz))
840 dev_err(host->dev, "blksz %u is not a power of 2\n", blksz);
842 blksz = ilog2(blksz);
844 /* check if block-size matches, if not update */
845 if (blksz == blksz_old)
848 dev_dbg(host->dev, "%s: update blk_len %d -> %d\n", __func__,
851 cfg &= ~CFG_BLK_LEN_MASK;
852 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, blksz);
853 writel(cfg, host->regs + SD_EMMC_CFG);
856 static void meson_mmc_set_response_bits(struct mmc_command *cmd, u32 *cmd_cfg)
858 if (cmd->flags & MMC_RSP_PRESENT) {
859 if (cmd->flags & MMC_RSP_136)
860 *cmd_cfg |= CMD_CFG_RESP_128;
861 *cmd_cfg |= CMD_CFG_RESP_NUM;
863 if (!(cmd->flags & MMC_RSP_CRC))
864 *cmd_cfg |= CMD_CFG_RESP_NOCRC;
866 if (cmd->flags & MMC_RSP_BUSY)
867 *cmd_cfg |= CMD_CFG_R1B;
869 *cmd_cfg |= CMD_CFG_NO_RESP;
873 static void meson_mmc_desc_chain_transfer(struct mmc_host *mmc, u32 cmd_cfg)
875 struct meson_host *host = mmc_priv(mmc);
876 struct sd_emmc_desc *desc = host->descs;
877 struct mmc_data *data = host->cmd->data;
878 struct scatterlist *sg;
882 if (data->flags & MMC_DATA_WRITE)
883 cmd_cfg |= CMD_CFG_DATA_WR;
885 if (data->blocks > 1) {
886 cmd_cfg |= CMD_CFG_BLOCK_MODE;
887 meson_mmc_set_blksz(mmc, data->blksz);
890 for_each_sg(data->sg, sg, data->sg_count, i) {
891 unsigned int len = sg_dma_len(sg);
893 if (data->blocks > 1)
896 desc[i].cmd_cfg = cmd_cfg;
897 desc[i].cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, len);
899 desc[i].cmd_cfg |= CMD_CFG_NO_CMD;
900 desc[i].cmd_arg = host->cmd->arg;
901 desc[i].cmd_resp = 0;
902 desc[i].cmd_data = sg_dma_address(sg);
904 desc[data->sg_count - 1].cmd_cfg |= CMD_CFG_END_OF_CHAIN;
906 dma_wmb(); /* ensure descriptor is written before kicked */
907 start = host->descs_dma_addr | START_DESC_BUSY;
908 writel(start, host->regs + SD_EMMC_START);
911 static void meson_mmc_start_cmd(struct mmc_host *mmc, struct mmc_command *cmd)
913 struct meson_host *host = mmc_priv(mmc);
914 struct mmc_data *data = cmd->data;
915 u32 cmd_cfg = 0, cmd_data = 0;
916 unsigned int xfer_bytes = 0;
918 /* Setup descriptors */
923 cmd_cfg |= FIELD_PREP(CMD_CFG_CMD_INDEX_MASK, cmd->opcode);
924 cmd_cfg |= CMD_CFG_OWNER; /* owned by CPU */
926 meson_mmc_set_response_bits(cmd, &cmd_cfg);
930 data->bytes_xfered = 0;
931 cmd_cfg |= CMD_CFG_DATA_IO;
932 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK,
933 ilog2(meson_mmc_get_timeout_msecs(data)));
935 if (meson_mmc_desc_chain_mode(data)) {
936 meson_mmc_desc_chain_transfer(mmc, cmd_cfg);
940 if (data->blocks > 1) {
941 cmd_cfg |= CMD_CFG_BLOCK_MODE;
942 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK,
944 meson_mmc_set_blksz(mmc, data->blksz);
946 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, data->blksz);
949 xfer_bytes = data->blksz * data->blocks;
950 if (data->flags & MMC_DATA_WRITE) {
951 cmd_cfg |= CMD_CFG_DATA_WR;
952 WARN_ON(xfer_bytes > host->bounce_buf_size);
953 sg_copy_to_buffer(data->sg, data->sg_len,
954 host->bounce_buf, xfer_bytes);
958 cmd_data = host->bounce_dma_addr & CMD_DATA_MASK;
960 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK,
961 ilog2(SD_EMMC_CMD_TIMEOUT));
964 /* Last descriptor */
965 cmd_cfg |= CMD_CFG_END_OF_CHAIN;
966 writel(cmd_cfg, host->regs + SD_EMMC_CMD_CFG);
967 writel(cmd_data, host->regs + SD_EMMC_CMD_DAT);
968 writel(0, host->regs + SD_EMMC_CMD_RSP);
969 wmb(); /* ensure descriptor is written before kicked */
970 writel(cmd->arg, host->regs + SD_EMMC_CMD_ARG);
973 static void meson_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
975 struct meson_host *host = mmc_priv(mmc);
976 bool needs_pre_post_req = mrq->data &&
977 !(mrq->data->host_cookie & SD_EMMC_PRE_REQ_DONE);
979 if (needs_pre_post_req) {
980 meson_mmc_get_transfer_mode(mmc, mrq);
981 if (!meson_mmc_desc_chain_mode(mrq->data))
982 needs_pre_post_req = false;
985 if (needs_pre_post_req)
986 meson_mmc_pre_req(mmc, mrq);
989 writel(0, host->regs + SD_EMMC_START);
991 meson_mmc_start_cmd(mmc, mrq->sbc ?: mrq->cmd);
993 if (needs_pre_post_req)
994 meson_mmc_post_req(mmc, mrq, 0);
997 static void meson_mmc_read_resp(struct mmc_host *mmc, struct mmc_command *cmd)
999 struct meson_host *host = mmc_priv(mmc);
1001 if (cmd->flags & MMC_RSP_136) {
1002 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP3);
1003 cmd->resp[1] = readl(host->regs + SD_EMMC_CMD_RSP2);
1004 cmd->resp[2] = readl(host->regs + SD_EMMC_CMD_RSP1);
1005 cmd->resp[3] = readl(host->regs + SD_EMMC_CMD_RSP);
1006 } else if (cmd->flags & MMC_RSP_PRESENT) {
1007 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP);
1011 static irqreturn_t meson_mmc_irq(int irq, void *dev_id)
1013 struct meson_host *host = dev_id;
1014 struct mmc_command *cmd;
1015 struct mmc_data *data;
1016 u32 irq_en, status, raw_status;
1017 irqreturn_t ret = IRQ_NONE;
1019 if (WARN_ON(!host) || WARN_ON(!host->cmd))
1022 spin_lock(&host->lock);
1026 irq_en = readl(host->regs + SD_EMMC_IRQ_EN);
1027 raw_status = readl(host->regs + SD_EMMC_STATUS);
1028 status = raw_status & irq_en;
1031 if (status & IRQ_CRC_ERR) {
1032 dev_dbg(host->dev, "CRC Error - status 0x%08x\n", status);
1033 cmd->error = -EILSEQ;
1038 if (status & IRQ_TIMEOUTS) {
1039 dev_dbg(host->dev, "Timeout - status 0x%08x\n", status);
1040 cmd->error = -ETIMEDOUT;
1045 meson_mmc_read_resp(host->mmc, cmd);
1047 if (status & IRQ_SDIO) {
1048 dev_dbg(host->dev, "IRQ: SDIO TODO.\n");
1052 if (status & (IRQ_END_OF_CHAIN | IRQ_RESP_STATUS)) {
1053 if (data && !cmd->error)
1054 data->bytes_xfered = data->blksz * data->blocks;
1055 if (meson_mmc_bounce_buf_read(data) ||
1056 meson_mmc_get_next_command(cmd))
1057 ret = IRQ_WAKE_THREAD;
1063 /* ack all enabled interrupts */
1064 writel(irq_en, host->regs + SD_EMMC_STATUS);
1066 if (ret == IRQ_HANDLED)
1067 meson_mmc_request_done(host->mmc, cmd->mrq);
1068 else if (ret == IRQ_NONE)
1070 "Unexpected IRQ! status=0x%08x, irq_en=0x%08x\n",
1071 raw_status, irq_en);
1073 spin_unlock(&host->lock);
1077 static irqreturn_t meson_mmc_irq_thread(int irq, void *dev_id)
1079 struct meson_host *host = dev_id;
1080 struct mmc_command *next_cmd, *cmd = host->cmd;
1081 struct mmc_data *data;
1082 unsigned int xfer_bytes;
1088 if (meson_mmc_bounce_buf_read(data)) {
1089 xfer_bytes = data->blksz * data->blocks;
1090 WARN_ON(xfer_bytes > host->bounce_buf_size);
1091 sg_copy_from_buffer(data->sg, data->sg_len,
1092 host->bounce_buf, xfer_bytes);
1095 next_cmd = meson_mmc_get_next_command(cmd);
1097 meson_mmc_start_cmd(host->mmc, next_cmd);
1099 meson_mmc_request_done(host->mmc, cmd->mrq);
1105 * NOTE: we only need this until the GPIO/pinctrl driver can handle
1106 * interrupts. For now, the MMC core will use this for polling.
1108 static int meson_mmc_get_cd(struct mmc_host *mmc)
1110 int status = mmc_gpio_get_cd(mmc);
1112 if (status == -ENOSYS)
1113 return 1; /* assume present */
1118 static void meson_mmc_cfg_init(struct meson_host *host)
1122 cfg |= FIELD_PREP(CFG_RESP_TIMEOUT_MASK,
1123 ilog2(SD_EMMC_CFG_RESP_TIMEOUT));
1124 cfg |= FIELD_PREP(CFG_RC_CC_MASK, ilog2(SD_EMMC_CFG_CMD_GAP));
1125 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, ilog2(SD_EMMC_CFG_BLK_SIZE));
1127 writel(cfg, host->regs + SD_EMMC_CFG);
1130 static int meson_mmc_card_busy(struct mmc_host *mmc)
1132 struct meson_host *host = mmc_priv(mmc);
1135 regval = readl(host->regs + SD_EMMC_STATUS);
1137 /* We are only interrested in lines 0 to 3, so mask the other ones */
1138 return !(FIELD_GET(STATUS_DATI, regval) & 0xf);
1141 static int meson_mmc_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios)
1143 /* vqmmc regulator is available */
1144 if (!IS_ERR(mmc->supply.vqmmc)) {
1146 * The usual amlogic setup uses a GPIO to switch from one
1147 * regulator to the other. While the voltage ramp up is
1148 * pretty fast, care must be taken when switching from 3.3v
1149 * to 1.8v. Please make sure the regulator framework is aware
1150 * of your own regulator constraints
1152 return mmc_regulator_set_vqmmc(mmc, ios);
1155 /* no vqmmc regulator, assume fixed regulator at 3/3.3V */
1156 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1162 static const struct mmc_host_ops meson_mmc_ops = {
1163 .request = meson_mmc_request,
1164 .set_ios = meson_mmc_set_ios,
1165 .get_cd = meson_mmc_get_cd,
1166 .pre_req = meson_mmc_pre_req,
1167 .post_req = meson_mmc_post_req,
1168 .execute_tuning = meson_mmc_execute_tuning,
1169 .card_busy = meson_mmc_card_busy,
1170 .start_signal_voltage_switch = meson_mmc_voltage_switch,
1173 static int meson_mmc_probe(struct platform_device *pdev)
1175 struct resource *res;
1176 struct meson_host *host;
1177 struct mmc_host *mmc;
1180 mmc = mmc_alloc_host(sizeof(struct meson_host), &pdev->dev);
1183 host = mmc_priv(mmc);
1185 host->dev = &pdev->dev;
1186 dev_set_drvdata(&pdev->dev, host);
1188 spin_lock_init(&host->lock);
1190 /* Get regulators and the supported OCR mask */
1191 host->vqmmc_enabled = false;
1192 ret = mmc_regulator_get_supply(mmc);
1193 if (ret == -EPROBE_DEFER)
1196 ret = mmc_of_parse(mmc);
1198 if (ret != -EPROBE_DEFER)
1199 dev_warn(&pdev->dev, "error parsing DT: %d\n", ret);
1203 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1204 host->regs = devm_ioremap_resource(&pdev->dev, res);
1205 if (IS_ERR(host->regs)) {
1206 ret = PTR_ERR(host->regs);
1210 irq = platform_get_irq(pdev, 0);
1212 dev_err(&pdev->dev, "failed to get interrupt resource.\n");
1217 host->pinctrl = devm_pinctrl_get(&pdev->dev);
1218 if (IS_ERR(host->pinctrl)) {
1219 ret = PTR_ERR(host->pinctrl);
1223 host->pins_default = pinctrl_lookup_state(host->pinctrl,
1224 PINCTRL_STATE_DEFAULT);
1225 if (IS_ERR(host->pins_default)) {
1226 ret = PTR_ERR(host->pins_default);
1230 host->pins_clk_gate = pinctrl_lookup_state(host->pinctrl,
1232 if (IS_ERR(host->pins_clk_gate)) {
1233 dev_warn(&pdev->dev,
1234 "can't get clk-gate pinctrl, using clk_stop bit\n");
1235 host->pins_clk_gate = NULL;
1238 host->core_clk = devm_clk_get(&pdev->dev, "core");
1239 if (IS_ERR(host->core_clk)) {
1240 ret = PTR_ERR(host->core_clk);
1244 ret = clk_prepare_enable(host->core_clk);
1248 ret = meson_mmc_clk_init(host);
1252 /* set config to sane default */
1253 meson_mmc_cfg_init(host);
1255 /* Stop execution */
1256 writel(0, host->regs + SD_EMMC_START);
1258 /* clear, ack and enable interrupts */
1259 writel(0, host->regs + SD_EMMC_IRQ_EN);
1260 writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN,
1261 host->regs + SD_EMMC_STATUS);
1262 writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN,
1263 host->regs + SD_EMMC_IRQ_EN);
1265 ret = devm_request_threaded_irq(&pdev->dev, irq, meson_mmc_irq,
1266 meson_mmc_irq_thread, IRQF_SHARED,
1271 mmc->caps |= MMC_CAP_CMD23;
1272 mmc->max_blk_count = CMD_CFG_LENGTH_MASK;
1273 mmc->max_req_size = mmc->max_blk_count * mmc->max_blk_size;
1274 mmc->max_segs = SD_EMMC_DESC_BUF_LEN / sizeof(struct sd_emmc_desc);
1275 mmc->max_seg_size = mmc->max_req_size;
1277 /* data bounce buffer */
1278 host->bounce_buf_size = mmc->max_req_size;
1280 dma_alloc_coherent(host->dev, host->bounce_buf_size,
1281 &host->bounce_dma_addr, GFP_KERNEL);
1282 if (host->bounce_buf == NULL) {
1283 dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n");
1288 host->descs = dma_alloc_coherent(host->dev, SD_EMMC_DESC_BUF_LEN,
1289 &host->descs_dma_addr, GFP_KERNEL);
1291 dev_err(host->dev, "Allocating descriptor DMA buffer failed\n");
1293 goto err_bounce_buf;
1296 mmc->ops = &meson_mmc_ops;
1302 dma_free_coherent(host->dev, host->bounce_buf_size,
1303 host->bounce_buf, host->bounce_dma_addr);
1305 clk_disable_unprepare(host->mmc_clk);
1307 clk_disable_unprepare(host->core_clk);
1313 static int meson_mmc_remove(struct platform_device *pdev)
1315 struct meson_host *host = dev_get_drvdata(&pdev->dev);
1317 mmc_remove_host(host->mmc);
1319 /* disable interrupts */
1320 writel(0, host->regs + SD_EMMC_IRQ_EN);
1322 dma_free_coherent(host->dev, SD_EMMC_DESC_BUF_LEN,
1323 host->descs, host->descs_dma_addr);
1324 dma_free_coherent(host->dev, host->bounce_buf_size,
1325 host->bounce_buf, host->bounce_dma_addr);
1327 clk_disable_unprepare(host->mmc_clk);
1328 clk_disable_unprepare(host->core_clk);
1330 mmc_free_host(host->mmc);
1334 static const struct of_device_id meson_mmc_of_match[] = {
1335 { .compatible = "amlogic,meson-gx-mmc", },
1336 { .compatible = "amlogic,meson-gxbb-mmc", },
1337 { .compatible = "amlogic,meson-gxl-mmc", },
1338 { .compatible = "amlogic,meson-gxm-mmc", },
1341 MODULE_DEVICE_TABLE(of, meson_mmc_of_match);
1343 static struct platform_driver meson_mmc_driver = {
1344 .probe = meson_mmc_probe,
1345 .remove = meson_mmc_remove,
1347 .name = DRIVER_NAME,
1348 .of_match_table = of_match_ptr(meson_mmc_of_match),
1352 module_platform_driver(meson_mmc_driver);
1354 MODULE_DESCRIPTION("Amlogic S905*/GX* SD/eMMC driver");
1355 MODULE_AUTHOR("Kevin Hilman <khilman@baylibre.com>");
1356 MODULE_LICENSE("GPL v2");