drivers/mmc/host/dw_mmc.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Synopsys DesignWare Multimedia Card Interface driver
   4  *  (Based on NXP driver for lpc 31xx)
   5  *
   6  * Copyright (C) 2009 NXP Semiconductors
   7  * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
   8  */
   9
  10 #include <linux/blkdev.h>
  11 #include <linux/clk.h>
  12 #include <linux/debugfs.h>
  13 #include <linux/device.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/err.h>
  16 #include <linux/init.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/iopoll.h>
  19 #include <linux/ioport.h>
  20 #include <linux/module.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/pm_runtime.h>
  23 #include <linux/seq_file.h>
  24 #include <linux/slab.h>
  25 #include <linux/stat.h>
  26 #include <linux/delay.h>
  27 #include <linux/irq.h>
  28 #include <linux/mmc/card.h>
  29 #include <linux/mmc/host.h>
  30 #include <linux/mmc/mmc.h>
  31 #include <linux/mmc/sd.h>
  32 #include <linux/mmc/sdio.h>
  33 #include <linux/bitops.h>
  34 #include <linux/regulator/consumer.h>
  35 #include <linux/of.h>
  36 #include <linux/of_gpio.h>
  37 #include <linux/mmc/slot-gpio.h>
  38
  39 #include "dw_mmc.h"
  40
  41 /* Common flag combinations */
  42 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
  43                                  SDMMC_INT_HTO | SDMMC_INT_SBE  | \
  44                                  SDMMC_INT_EBE | SDMMC_INT_HLE)
  45 #define DW_MCI_CMD_ERROR_FLAGS  (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
  46                                  SDMMC_INT_RESP_ERR | SDMMC_INT_HLE)
  47 #define DW_MCI_ERROR_FLAGS      (DW_MCI_DATA_ERROR_FLAGS | \
  48                                  DW_MCI_CMD_ERROR_FLAGS)
  49 #define DW_MCI_SEND_STATUS      1
  50 #define DW_MCI_RECV_STATUS      2
  51 #define DW_MCI_DMA_THRESHOLD    16
  52
  53 #define DW_MCI_FREQ_MAX 200000000       /* unit: HZ */
  54 #define DW_MCI_FREQ_MIN 100000          /* unit: HZ */
  55
  56 #define IDMAC_INT_CLR           (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
  57                                  SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
  58                                  SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
  59                                  SDMMC_IDMAC_INT_TI)
  60
  61 #define DESC_RING_BUF_SZ        PAGE_SIZE
  62
  63 struct idmac_desc_64addr {
  64         u32             des0;   /* Control Descriptor */
  65 #define IDMAC_OWN_CLR64(x) \
  66         !((x) & cpu_to_le32(IDMAC_DES0_OWN))
  67
  68         u32             des1;   /* Reserved */
  69
  70         u32             des2;   /*Buffer sizes */
  71 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
  72         ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
  73          ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
  74
  75         u32             des3;   /* Reserved */
  76
  77         u32             des4;   /* Lower 32-bits of Buffer Address Pointer 1*/
  78         u32             des5;   /* Upper 32-bits of Buffer Address Pointer 1*/
  79
  80         u32             des6;   /* Lower 32-bits of Next Descriptor Address */
  81         u32             des7;   /* Upper 32-bits of Next Descriptor Address */
  82 };
  83
  84 struct idmac_desc {
  85         __le32          des0;   /* Control Descriptor */
  86 #define IDMAC_DES0_DIC  BIT(1)
  87 #define IDMAC_DES0_LD   BIT(2)
  88 #define IDMAC_DES0_FD   BIT(3)
  89 #define IDMAC_DES0_CH   BIT(4)
  90 #define IDMAC_DES0_ER   BIT(5)
  91 #define IDMAC_DES0_CES  BIT(30)
  92 #define IDMAC_DES0_OWN  BIT(31)
  93
  94         __le32          des1;   /* Buffer sizes */
  95 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
  96         ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff)))
  97
  98         __le32          des2;   /* buffer 1 physical address */
  99
 100         __le32          des3;   /* buffer 2 physical address */
 101 };
 102
 103 /* Each descriptor can transfer up to 4KB of data in chained mode */
 104 #define DW_MCI_DESC_DATA_LENGTH 0x1000
 105
 106 #if defined(CONFIG_DEBUG_FS)
 107 static int dw_mci_req_show(struct seq_file *s, void *v)
 108 {
 109         struct dw_mci_slot *slot = s->private;
 110         struct mmc_request *mrq;
 111         struct mmc_command *cmd;
 112         struct mmc_command *stop;
 113         struct mmc_data *data;
 114
 115         /* Make sure we get a consistent snapshot */
 116         spin_lock_bh(&slot->host->lock);
 117         mrq = slot->mrq;
 118
 119         if (mrq) {
 120                 cmd = mrq->cmd;
 121                 data = mrq->data;
 122                 stop = mrq->stop;
 123
 124                 if (cmd)
 125                         seq_printf(s,
 126                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 127                                    cmd->opcode, cmd->arg, cmd->flags,
 128                                    cmd->resp[0], cmd->resp[1], cmd->resp[2],
 129                                    cmd->resp[2], cmd->error);
 130                 if (data)
 131                         seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
 132                                    data->bytes_xfered, data->blocks,
 133                                    data->blksz, data->flags, data->error);
 134                 if (stop)
 135                         seq_printf(s,
 136                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 137                                    stop->opcode, stop->arg, stop->flags,
 138                                    stop->resp[0], stop->resp[1], stop->resp[2],
 139                                    stop->resp[2], stop->error);
 140         }
 141
 142         spin_unlock_bh(&slot->host->lock);
 143
 144         return 0;
 145 }
 146 DEFINE_SHOW_ATTRIBUTE(dw_mci_req);
 147
 148 static int dw_mci_regs_show(struct seq_file *s, void *v)
 149 {
 150         struct dw_mci *host = s->private;
 151
 152         pm_runtime_get_sync(host->dev);
 153
 154         seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS));
 155         seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS));
 156         seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD));
 157         seq_printf(s, "CTRL:\t0x%08x\n", mci_readl(host, CTRL));
 158         seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK));
 159         seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA));
 160
 161         pm_runtime_put_autosuspend(host->dev);
 162
 163         return 0;
 164 }
 165 DEFINE_SHOW_ATTRIBUTE(dw_mci_regs);
 166
 167 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
 168 {
 169         struct mmc_host *mmc = slot->mmc;
 170         struct dw_mci *host = slot->host;
 171         struct dentry *root;
 172         struct dentry *node;
 173
 174         root = mmc->debugfs_root;
 175         if (!root)
 176                 return;
 177
 178         node = debugfs_create_file("regs", S_IRUSR, root, host,
 179                                    &dw_mci_regs_fops);
 180         if (!node)
 181                 goto err;
 182
 183         node = debugfs_create_file("req", S_IRUSR, root, slot,
 184                                    &dw_mci_req_fops);
 185         if (!node)
 186                 goto err;
 187
 188         node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
 189         if (!node)
 190                 goto err;
 191
 192         node = debugfs_create_x32("pending_events", S_IRUSR, root,
 193                                   (u32 *)&host->pending_events);
 194         if (!node)
 195                 goto err;
 196
 197         node = debugfs_create_x32("completed_events", S_IRUSR, root,
 198                                   (u32 *)&host->completed_events);
 199         if (!node)
 200                 goto err;
 201
 202         return;
 203
 204 err:
 205         dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
 206 }
 207 #endif /* defined(CONFIG_DEBUG_FS) */
 208
 209 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
 210 {
 211         u32 ctrl;
 212
 213         ctrl = mci_readl(host, CTRL);
 214         ctrl |= reset;
 215         mci_writel(host, CTRL, ctrl);
 216
 217         /* wait till resets clear */
 218         if (readl_poll_timeout_atomic(host->regs + SDMMC_CTRL, ctrl,
 219                                       !(ctrl & reset),
 220                                       1, 500 * USEC_PER_MSEC)) {
 221                 dev_err(host->dev,
 222                         "Timeout resetting block (ctrl reset %#x)\n",
 223                         ctrl & reset);
 224                 return false;
 225         }
 226
 227         return true;
 228 }
 229
 230 static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
 231 {
 232         u32 status;
 233
 234         /*
 235          * Databook says that before issuing a new data transfer command
 236          * we need to check to see if the card is busy.  Data transfer commands
 237          * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
 238          *
 239          * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
 240          * expected.
 241          */
 242         if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
 243             !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
 244                 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
 245                                               status,
 246                                               !(status & SDMMC_STATUS_BUSY),
 247                                               10, 500 * USEC_PER_MSEC))
 248                         dev_err(host->dev, "Busy; trying anyway\n");
 249         }
 250 }
 251
 252 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
 253 {
 254         struct dw_mci *host = slot->host;
 255         unsigned int cmd_status = 0;
 256
 257         mci_writel(host, CMDARG, arg);
 258         wmb(); /* drain writebuffer */
 259         dw_mci_wait_while_busy(host, cmd);
 260         mci_writel(host, CMD, SDMMC_CMD_START | cmd);
 261
 262         if (readl_poll_timeout_atomic(host->regs + SDMMC_CMD, cmd_status,
 263                                       !(cmd_status & SDMMC_CMD_START),
 264                                       1, 500 * USEC_PER_MSEC))
 265                 dev_err(&slot->mmc->class_dev,
 266                         "Timeout sending command (cmd %#x arg %#x status %#x)\n",
 267                         cmd, arg, cmd_status);
 268 }
 269
 270 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
 271 {
 272         struct dw_mci_slot *slot = mmc_priv(mmc);
 273         struct dw_mci *host = slot->host;
 274         u32 cmdr;
 275
 276         cmd->error = -EINPROGRESS;
 277         cmdr = cmd->opcode;
 278
 279         if (cmd->opcode == MMC_STOP_TRANSMISSION ||
 280             cmd->opcode == MMC_GO_IDLE_STATE ||
 281             cmd->opcode == MMC_GO_INACTIVE_STATE ||
 282             (cmd->opcode == SD_IO_RW_DIRECT &&
 283              ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
 284                 cmdr |= SDMMC_CMD_STOP;
 285         else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
 286                 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
 287
 288         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
 289                 u32 clk_en_a;
 290
 291                 /* Special bit makes CMD11 not die */
 292                 cmdr |= SDMMC_CMD_VOLT_SWITCH;
 293
 294                 /* Change state to continue to handle CMD11 weirdness */
 295                 WARN_ON(slot->host->state != STATE_SENDING_CMD);
 296                 slot->host->state = STATE_SENDING_CMD11;
 297
 298                 /*
 299                  * We need to disable low power mode (automatic clock stop)
 300                  * while doing voltage switch so we don't confuse the card,
 301                  * since stopping the clock is a specific part of the UHS
 302                  * voltage change dance.
 303                  *
 304                  * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
 305                  * unconditionally turned back on in dw_mci_setup_bus() if it's
 306                  * ever called with a non-zero clock.  That shouldn't happen
 307                  * until the voltage change is all done.
 308                  */
 309                 clk_en_a = mci_readl(host, CLKENA);
 310                 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
 311                 mci_writel(host, CLKENA, clk_en_a);
 312                 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
 313                              SDMMC_CMD_PRV_DAT_WAIT, 0);
 314         }
 315
 316         if (cmd->flags & MMC_RSP_PRESENT) {
 317                 /* We expect a response, so set this bit */
 318                 cmdr |= SDMMC_CMD_RESP_EXP;
 319                 if (cmd->flags & MMC_RSP_136)
 320                         cmdr |= SDMMC_CMD_RESP_LONG;
 321         }
 322
 323         if (cmd->flags & MMC_RSP_CRC)
 324                 cmdr |= SDMMC_CMD_RESP_CRC;
 325
 326         if (cmd->data) {
 327                 cmdr |= SDMMC_CMD_DAT_EXP;
 328                 if (cmd->data->flags & MMC_DATA_WRITE)
 329                         cmdr |= SDMMC_CMD_DAT_WR;
 330         }
 331
 332         if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags))
 333                 cmdr |= SDMMC_CMD_USE_HOLD_REG;
 334
 335         return cmdr;
 336 }
 337
 338 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
 339 {
 340         struct mmc_command *stop;
 341         u32 cmdr;
 342
 343         if (!cmd->data)
 344                 return 0;
 345
 346         stop = &host->stop_abort;
 347         cmdr = cmd->opcode;
 348         memset(stop, 0, sizeof(struct mmc_command));
 349
 350         if (cmdr == MMC_READ_SINGLE_BLOCK ||
 351             cmdr == MMC_READ_MULTIPLE_BLOCK ||
 352             cmdr == MMC_WRITE_BLOCK ||
 353             cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
 354             cmdr == MMC_SEND_TUNING_BLOCK ||
 355             cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
 356                 stop->opcode = MMC_STOP_TRANSMISSION;
 357                 stop->arg = 0;
 358                 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
 359         } else if (cmdr == SD_IO_RW_EXTENDED) {
 360                 stop->opcode = SD_IO_RW_DIRECT;
 361                 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
 362                              ((cmd->arg >> 28) & 0x7);
 363                 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
 364         } else {
 365                 return 0;
 366         }
 367
 368         cmdr = stop->opcode | SDMMC_CMD_STOP |
 369                 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
 370
 371         if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &host->slot->flags))
 372                 cmdr |= SDMMC_CMD_USE_HOLD_REG;
 373
 374         return cmdr;
 375 }
 376
 377 static inline void dw_mci_set_cto(struct dw_mci *host)
 378 {
 379         unsigned int cto_clks;
 380         unsigned int cto_div;
 381         unsigned int cto_ms;
 382         unsigned long irqflags;
 383
 384         cto_clks = mci_readl(host, TMOUT) & 0xff;
 385         cto_div = (mci_readl(host, CLKDIV) & 0xff) * 2;
 386         if (cto_div == 0)
 387                 cto_div = 1;
 388
 389         cto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * cto_clks * cto_div,
 390                                   host->bus_hz);
 391
 392         /* add a bit spare time */
 393         cto_ms += 10;
 394
 395         /*
 396          * The durations we're working with are fairly short so we have to be
 397          * extra careful about synchronization here.  Specifically in hardware a
 398          * command timeout is _at most_ 5.1 ms, so that means we expect an
 399          * interrupt (either command done or timeout) to come rather quickly
 400          * after the mci_writel.  ...but just in case we have a long interrupt
 401          * latency let's add a bit of paranoia.
 402          *
 403          * In general we'll assume that at least an interrupt will be asserted
 404          * in hardware by the time the cto_timer runs.  ...and if it hasn't
 405          * been asserted in hardware by that time then we'll assume it'll never
 406          * come.
 407          */
 408         spin_lock_irqsave(&host->irq_lock, irqflags);
 409         if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
 410                 mod_timer(&host->cto_timer,
 411                         jiffies + msecs_to_jiffies(cto_ms) + 1);
 412         spin_unlock_irqrestore(&host->irq_lock, irqflags);
 413 }
 414
 415 static void dw_mci_start_command(struct dw_mci *host,
 416                                  struct mmc_command *cmd, u32 cmd_flags)
 417 {
 418         host->cmd = cmd;
 419         dev_vdbg(host->dev,
 420                  "start command: ARGR=0x%08x CMDR=0x%08x\n",
 421                  cmd->arg, cmd_flags);
 422
 423         mci_writel(host, CMDARG, cmd->arg);
 424         wmb(); /* drain writebuffer */
 425         dw_mci_wait_while_busy(host, cmd_flags);
 426
 427         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
 428
 429         /* response expected command only */
 430         if (cmd_flags & SDMMC_CMD_RESP_EXP)
 431                 dw_mci_set_cto(host);
 432 }
 433
 434 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
 435 {
 436         struct mmc_command *stop = &host->stop_abort;
 437
 438         dw_mci_start_command(host, stop, host->stop_cmdr);
 439 }
 440
 441 /* DMA interface functions */
 442 static void dw_mci_stop_dma(struct dw_mci *host)
 443 {
 444         if (host->using_dma) {
 445                 host->dma_ops->stop(host);
 446                 host->dma_ops->cleanup(host);
 447         }
 448
 449         /* Data transfer was stopped by the interrupt handler */
 450         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 451 }
 452
 453 static void dw_mci_dma_cleanup(struct dw_mci *host)
 454 {
 455         struct mmc_data *data = host->data;
 456
 457         if (data && data->host_cookie == COOKIE_MAPPED) {
 458                 dma_unmap_sg(host->dev,
 459                              data->sg,
 460                              data->sg_len,
 461                              mmc_get_dma_dir(data));
 462                 data->host_cookie = COOKIE_UNMAPPED;
 463         }
 464 }
 465
 466 static void dw_mci_idmac_reset(struct dw_mci *host)
 467 {
 468         u32 bmod = mci_readl(host, BMOD);
 469         /* Software reset of DMA */
 470         bmod |= SDMMC_IDMAC_SWRESET;
 471         mci_writel(host, BMOD, bmod);
 472 }
 473
 474 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
 475 {
 476         u32 temp;
 477
 478         /* Disable and reset the IDMAC interface */
 479         temp = mci_readl(host, CTRL);
 480         temp &= ~SDMMC_CTRL_USE_IDMAC;
 481         temp |= SDMMC_CTRL_DMA_RESET;
 482         mci_writel(host, CTRL, temp);
 483
 484         /* Stop the IDMAC running */
 485         temp = mci_readl(host, BMOD);
 486         temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
 487         temp |= SDMMC_IDMAC_SWRESET;
 488         mci_writel(host, BMOD, temp);
 489 }
 490
 491 static void dw_mci_dmac_complete_dma(void *arg)
 492 {
 493         struct dw_mci *host = arg;
 494         struct mmc_data *data = host->data;
 495
 496         dev_vdbg(host->dev, "DMA complete\n");
 497
 498         if ((host->use_dma == TRANS_MODE_EDMAC) &&
 499             data && (data->flags & MMC_DATA_READ))
 500                 /* Invalidate cache after read */
 501                 dma_sync_sg_for_cpu(mmc_dev(host->slot->mmc),
 502                                     data->sg,
 503                                     data->sg_len,
 504                                     DMA_FROM_DEVICE);
 505
 506         host->dma_ops->cleanup(host);
 507
 508         /*
 509          * If the card was removed, data will be NULL. No point in trying to
 510          * send the stop command or waiting for NBUSY in this case.
 511          */
 512         if (data) {
 513                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 514                 tasklet_schedule(&host->tasklet);
 515         }
 516 }
 517
 518 static int dw_mci_idmac_init(struct dw_mci *host)
 519 {
 520         int i;
 521
 522         if (host->dma_64bit_address == 1) {
 523                 struct idmac_desc_64addr *p;
 524                 /* Number of descriptors in the ring buffer */
 525                 host->ring_size =
 526                         DESC_RING_BUF_SZ / sizeof(struct idmac_desc_64addr);
 527
 528                 /* Forward link the descriptor list */
 529                 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
 530                                                                 i++, p++) {
 531                         p->des6 = (host->sg_dma +
 532                                         (sizeof(struct idmac_desc_64addr) *
 533                                                         (i + 1))) & 0xffffffff;
 534
 535                         p->des7 = (u64)(host->sg_dma +
 536                                         (sizeof(struct idmac_desc_64addr) *
 537                                                         (i + 1))) >> 32;
 538                         /* Initialize reserved and buffer size fields to "0" */
 539                         p->des0 = 0;
 540                         p->des1 = 0;
 541                         p->des2 = 0;
 542                         p->des3 = 0;
 543                 }
 544
 545                 /* Set the last descriptor as the end-of-ring descriptor */
 546                 p->des6 = host->sg_dma & 0xffffffff;
 547                 p->des7 = (u64)host->sg_dma >> 32;
 548                 p->des0 = IDMAC_DES0_ER;
 549
 550         } else {
 551                 struct idmac_desc *p;
 552                 /* Number of descriptors in the ring buffer */
 553                 host->ring_size =
 554                         DESC_RING_BUF_SZ / sizeof(struct idmac_desc);
 555
 556                 /* Forward link the descriptor list */
 557                 for (i = 0, p = host->sg_cpu;
 558                      i < host->ring_size - 1;
 559                      i++, p++) {
 560                         p->des3 = cpu_to_le32(host->sg_dma +
 561                                         (sizeof(struct idmac_desc) * (i + 1)));
 562                         p->des0 = 0;
 563                         p->des1 = 0;
 564                 }
 565
 566                 /* Set the last descriptor as the end-of-ring descriptor */
 567                 p->des3 = cpu_to_le32(host->sg_dma);
 568                 p->des0 = cpu_to_le32(IDMAC_DES0_ER);
 569         }
 570
 571         dw_mci_idmac_reset(host);
 572
 573         if (host->dma_64bit_address == 1) {
 574                 /* Mask out interrupts - get Tx & Rx complete only */
 575                 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
 576                 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
 577                                 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
 578
 579                 /* Set the descriptor base address */
 580                 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
 581                 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
 582
 583         } else {
 584                 /* Mask out interrupts - get Tx & Rx complete only */
 585                 mci_writel(host, IDSTS, IDMAC_INT_CLR);
 586                 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
 587                                 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
 588
 589                 /* Set the descriptor base address */
 590                 mci_writel(host, DBADDR, host->sg_dma);
 591         }
 592
 593         return 0;
 594 }
 595
 596 static inline int dw_mci_prepare_desc64(struct dw_mci *host,
 597                                          struct mmc_data *data,
 598                                          unsigned int sg_len)
 599 {
 600         unsigned int desc_len;
 601         struct idmac_desc_64addr *desc_first, *desc_last, *desc;
 602         u32 val;
 603         int i;
 604
 605         desc_first = desc_last = desc = host->sg_cpu;
 606
 607         for (i = 0; i < sg_len; i++) {
 608                 unsigned int length = sg_dma_len(&data->sg[i]);
 609
 610                 u64 mem_addr = sg_dma_address(&data->sg[i]);
 611
 612                 for ( ; length ; desc++) {
 613                         desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
 614                                    length : DW_MCI_DESC_DATA_LENGTH;
 615
 616                         length -= desc_len;
 617
 618                         /*
 619                          * Wait for the former clear OWN bit operation
 620                          * of IDMAC to make sure that this descriptor
 621                          * isn't still owned by IDMAC as IDMAC's write
 622                          * ops and CPU's read ops are asynchronous.
 623                          */
 624                         if (readl_poll_timeout_atomic(&desc->des0, val,
 625                                                 !(val & IDMAC_DES0_OWN),
 626                                                 10, 100 * USEC_PER_MSEC))
 627                                 goto err_own_bit;
 628
 629                         /*
 630                          * Set the OWN bit and disable interrupts
 631                          * for this descriptor
 632                          */
 633                         desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
 634                                                 IDMAC_DES0_CH;
 635
 636                         /* Buffer length */
 637                         IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len);
 638
 639                         /* Physical address to DMA to/from */
 640                         desc->des4 = mem_addr & 0xffffffff;
 641                         desc->des5 = mem_addr >> 32;
 642
 643                         /* Update physical address for the next desc */
 644                         mem_addr += desc_len;
 645
 646                         /* Save pointer to the last descriptor */
 647                         desc_last = desc;
 648                 }
 649         }
 650
 651         /* Set first descriptor */
 652         desc_first->des0 |= IDMAC_DES0_FD;
 653
 654         /* Set last descriptor */
 655         desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
 656         desc_last->des0 |= IDMAC_DES0_LD;
 657
 658         return 0;
 659 err_own_bit:
 660         /* restore the descriptor chain as it's polluted */
 661         dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
 662         memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
 663         dw_mci_idmac_init(host);
 664         return -EINVAL;
 665 }
 666
 667
 668 static inline int dw_mci_prepare_desc32(struct dw_mci *host,
 669                                          struct mmc_data *data,
 670                                          unsigned int sg_len)
 671 {
 672         unsigned int desc_len;
 673         struct idmac_desc *desc_first, *desc_last, *desc;
 674         u32 val;
 675         int i;
 676
 677         desc_first = desc_last = desc = host->sg_cpu;
 678
 679         for (i = 0; i < sg_len; i++) {
 680                 unsigned int length = sg_dma_len(&data->sg[i]);
 681
 682                 u32 mem_addr = sg_dma_address(&data->sg[i]);
 683
 684                 for ( ; length ; desc++) {
 685                         desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
 686                                    length : DW_MCI_DESC_DATA_LENGTH;
 687
 688                         length -= desc_len;
 689
 690                         /*
 691                          * Wait for the former clear OWN bit operation
 692                          * of IDMAC to make sure that this descriptor
 693                          * isn't still owned by IDMAC as IDMAC's write
 694                          * ops and CPU's read ops are asynchronous.
 695                          */
 696                         if (readl_poll_timeout_atomic(&desc->des0, val,
 697                                                       IDMAC_OWN_CLR64(val),
 698                                                       10,
 699                                                       100 * USEC_PER_MSEC))
 700                                 goto err_own_bit;
 701
 702                         /*
 703                          * Set the OWN bit and disable interrupts
 704                          * for this descriptor
 705                          */
 706                         desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
 707                                                  IDMAC_DES0_DIC |
 708                                                  IDMAC_DES0_CH);
 709
 710                         /* Buffer length */
 711                         IDMAC_SET_BUFFER1_SIZE(desc, desc_len);
 712
 713                         /* Physical address to DMA to/from */
 714                         desc->des2 = cpu_to_le32(mem_addr);
 715
 716                         /* Update physical address for the next desc */
 717                         mem_addr += desc_len;
 718
 719                         /* Save pointer to the last descriptor */
 720                         desc_last = desc;
 721                 }
 722         }
 723
 724         /* Set first descriptor */
 725         desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
 726
 727         /* Set last descriptor */
 728         desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH |
 729                                        IDMAC_DES0_DIC));
 730         desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD);
 731
 732         return 0;
 733 err_own_bit:
 734         /* restore the descriptor chain as it's polluted */
 735         dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
 736         memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
 737         dw_mci_idmac_init(host);
 738         return -EINVAL;
 739 }
 740
 741 static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
 742 {
 743         u32 temp;
 744         int ret;
 745
 746         if (host->dma_64bit_address == 1)
 747                 ret = dw_mci_prepare_desc64(host, host->data, sg_len);
 748         else
 749                 ret = dw_mci_prepare_desc32(host, host->data, sg_len);
 750
 751         if (ret)
 752                 goto out;
 753
 754         /* drain writebuffer */
 755         wmb();
 756
 757         /* Make sure to reset DMA in case we did PIO before this */
 758         dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
 759         dw_mci_idmac_reset(host);
 760
 761         /* Select IDMAC interface */
 762         temp = mci_readl(host, CTRL);
 763         temp |= SDMMC_CTRL_USE_IDMAC;
 764         mci_writel(host, CTRL, temp);
 765
 766         /* drain writebuffer */
 767         wmb();
 768
 769         /* Enable the IDMAC */
 770         temp = mci_readl(host, BMOD);
 771         temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
 772         mci_writel(host, BMOD, temp);
 773
 774         /* Start it running */
 775         mci_writel(host, PLDMND, 1);
 776
 777 out:
 778         return ret;
 779 }
 780
 781 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
 782         .init = dw_mci_idmac_init,
 783         .start = dw_mci_idmac_start_dma,
 784         .stop = dw_mci_idmac_stop_dma,
 785         .complete = dw_mci_dmac_complete_dma,
 786         .cleanup = dw_mci_dma_cleanup,
 787 };
 788
 789 static void dw_mci_edmac_stop_dma(struct dw_mci *host)
 790 {
 791         dmaengine_terminate_async(host->dms->ch);
 792 }
 793
 794 static int dw_mci_edmac_start_dma(struct dw_mci *host,
 795                                             unsigned int sg_len)
 796 {
 797         struct dma_slave_config cfg;
 798         struct dma_async_tx_descriptor *desc = NULL;
 799         struct scatterlist *sgl = host->data->sg;
 800         static const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
 801         u32 sg_elems = host->data->sg_len;
 802         u32 fifoth_val;
 803         u32 fifo_offset = host->fifo_reg - host->regs;
 804         int ret = 0;
 805
 806         /* Set external dma config: burst size, burst width */
 807         cfg.dst_addr = host->phy_regs + fifo_offset;
 808         cfg.src_addr = cfg.dst_addr;
 809         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 810         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 811
 812         /* Match burst msize with external dma config */
 813         fifoth_val = mci_readl(host, FIFOTH);
 814         cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7];
 815         cfg.src_maxburst = cfg.dst_maxburst;
 816
 817         if (host->data->flags & MMC_DATA_WRITE)
 818                 cfg.direction = DMA_MEM_TO_DEV;
 819         else
 820                 cfg.direction = DMA_DEV_TO_MEM;
 821
 822         ret = dmaengine_slave_config(host->dms->ch, &cfg);
 823         if (ret) {
 824                 dev_err(host->dev, "Failed to config edmac.\n");
 825                 return -EBUSY;
 826         }
 827
 828         desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
 829                                        sg_len, cfg.direction,
 830                                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 831         if (!desc) {
 832                 dev_err(host->dev, "Can't prepare slave sg.\n");
 833                 return -EBUSY;
 834         }
 835
 836         /* Set dw_mci_dmac_complete_dma as callback */
 837         desc->callback = dw_mci_dmac_complete_dma;
 838         desc->callback_param = (void *)host;
 839         dmaengine_submit(desc);
 840
 841         /* Flush cache before write */
 842         if (host->data->flags & MMC_DATA_WRITE)
 843                 dma_sync_sg_for_device(mmc_dev(host->slot->mmc), sgl,
 844                                        sg_elems, DMA_TO_DEVICE);
 845
 846         dma_async_issue_pending(host->dms->ch);
 847
 848         return 0;
 849 }
 850
 851 static int dw_mci_edmac_init(struct dw_mci *host)
 852 {
 853         /* Request external dma channel */
 854         host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
 855         if (!host->dms)
 856                 return -ENOMEM;
 857
 858         host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx");
 859         if (!host->dms->ch) {
 860                 dev_err(host->dev, "Failed to get external DMA channel.\n");
 861                 kfree(host->dms);
 862                 host->dms = NULL;
 863                 return -ENXIO;
 864         }
 865
 866         return 0;
 867 }
 868
 869 static void dw_mci_edmac_exit(struct dw_mci *host)
 870 {
 871         if (host->dms) {
 872                 if (host->dms->ch) {
 873                         dma_release_channel(host->dms->ch);
 874                         host->dms->ch = NULL;
 875                 }
 876                 kfree(host->dms);
 877                 host->dms = NULL;
 878         }
 879 }
 880
 881 static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
 882         .init = dw_mci_edmac_init,
 883         .exit = dw_mci_edmac_exit,
 884         .start = dw_mci_edmac_start_dma,
 885         .stop = dw_mci_edmac_stop_dma,
 886         .complete = dw_mci_dmac_complete_dma,
 887         .cleanup = dw_mci_dma_cleanup,
 888 };
 889
 890 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
 891                                    struct mmc_data *data,
 892                                    int cookie)
 893 {
 894         struct scatterlist *sg;
 895         unsigned int i, sg_len;
 896
 897         if (data->host_cookie == COOKIE_PRE_MAPPED)
 898                 return data->sg_len;
 899
 900         /*
 901          * We don't do DMA on "complex" transfers, i.e. with
 902          * non-word-aligned buffers or lengths. Also, we don't bother
 903          * with all the DMA setup overhead for short transfers.
 904          */
 905         if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
 906                 return -EINVAL;
 907
 908         if (data->blksz & 3)
 909                 return -EINVAL;
 910
 911         for_each_sg(data->sg, sg, data->sg_len, i) {
 912                 if (sg->offset & 3 || sg->length & 3)
 913                         return -EINVAL;
 914         }
 915
 916         sg_len = dma_map_sg(host->dev,
 917                             data->sg,
 918                             data->sg_len,
 919                             mmc_get_dma_dir(data));
 920         if (sg_len == 0)
 921                 return -EINVAL;
 922
 923         data->host_cookie = cookie;
 924
 925         return sg_len;
 926 }
 927
 928 static void dw_mci_pre_req(struct mmc_host *mmc,
 929                            struct mmc_request *mrq)
 930 {
 931         struct dw_mci_slot *slot = mmc_priv(mmc);
 932         struct mmc_data *data = mrq->data;
 933
 934         if (!slot->host->use_dma || !data)
 935                 return;
 936
 937         /* This data might be unmapped at this time */
 938         data->host_cookie = COOKIE_UNMAPPED;
 939
 940         if (dw_mci_pre_dma_transfer(slot->host, mrq->data,
 941                                 COOKIE_PRE_MAPPED) < 0)
 942                 data->host_cookie = COOKIE_UNMAPPED;
 943 }
 944
 945 static void dw_mci_post_req(struct mmc_host *mmc,
 946                             struct mmc_request *mrq,
 947                             int err)
 948 {
 949         struct dw_mci_slot *slot = mmc_priv(mmc);
 950         struct mmc_data *data = mrq->data;
 951
 952         if (!slot->host->use_dma || !data)
 953                 return;
 954
 955         if (data->host_cookie != COOKIE_UNMAPPED)
 956                 dma_unmap_sg(slot->host->dev,
 957                              data->sg,
 958                              data->sg_len,
 959                              mmc_get_dma_dir(data));
 960         data->host_cookie = COOKIE_UNMAPPED;
 961 }
 962
 963 static int dw_mci_get_cd(struct mmc_host *mmc)
 964 {
 965         int present;
 966         struct dw_mci_slot *slot = mmc_priv(mmc);
 967         struct dw_mci *host = slot->host;
 968         int gpio_cd = mmc_gpio_get_cd(mmc);
 969
 970         /* Use platform get_cd function, else try onboard card detect */
 971         if (((mmc->caps & MMC_CAP_NEEDS_POLL)
 972                                 || !mmc_card_is_removable(mmc))) {
 973                 present = 1;
 974
 975                 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
 976                         if (mmc->caps & MMC_CAP_NEEDS_POLL) {
 977                                 dev_info(&mmc->class_dev,
 978                                         "card is polling.\n");
 979                         } else {
 980                                 dev_info(&mmc->class_dev,
 981                                         "card is non-removable.\n");
 982                         }
 983                         set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
 984                 }
 985
 986                 return present;
 987         } else if (gpio_cd >= 0)
 988                 present = gpio_cd;
 989         else
 990                 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
 991                         == 0 ? 1 : 0;
 992
 993         spin_lock_bh(&host->lock);
 994         if (present && !test_and_set_bit(DW_MMC_CARD_PRESENT, &slot->flags))
 995                 dev_dbg(&mmc->class_dev, "card is present\n");
 996         else if (!present &&
 997                         !test_and_clear_bit(DW_MMC_CARD_PRESENT, &slot->flags))
 998                 dev_dbg(&mmc->class_dev, "card is not present\n");
 999         spin_unlock_bh(&host->lock);
1000
1001         return present;
1002 }
1003
1004 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
1005 {
1006         unsigned int blksz = data->blksz;
1007         static const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
1008         u32 fifo_width = 1 << host->data_shift;
1009         u32 blksz_depth = blksz / fifo_width, fifoth_val;
1010         u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
1011         int idx = ARRAY_SIZE(mszs) - 1;
1012
1013         /* pio should ship this scenario */
1014         if (!host->use_dma)
1015                 return;
1016
1017         tx_wmark = (host->fifo_depth) / 2;
1018         tx_wmark_invers = host->fifo_depth - tx_wmark;
1019
1020         /*
1021          * MSIZE is '1',
1022          * if blksz is not a multiple of the FIFO width
1023          */
1024         if (blksz % fifo_width)
1025                 goto done;
1026
1027         do {
1028                 if (!((blksz_depth % mszs[idx]) ||
1029                      (tx_wmark_invers % mszs[idx]))) {
1030                         msize = idx;
1031                         rx_wmark = mszs[idx] - 1;
1032                         break;
1033                 }
1034         } while (--idx > 0);
1035         /*
1036          * If idx is '0', it won't be tried
1037          * Thus, initial values are uesed
1038          */
1039 done:
1040         fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
1041         mci_writel(host, FIFOTH, fifoth_val);
1042 }
1043
1044 static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data)
1045 {
1046         unsigned int blksz = data->blksz;
1047         u32 blksz_depth, fifo_depth;
1048         u16 thld_size;
1049         u8 enable;
1050
1051         /*
1052          * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
1053          * in the FIFO region, so we really shouldn't access it).
1054          */
1055         if (host->verid < DW_MMC_240A ||
1056                 (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE))
1057                 return;
1058
1059         /*
1060          * Card write Threshold is introduced since 2.80a
1061          * It's used when HS400 mode is enabled.
1062          */
1063         if (data->flags & MMC_DATA_WRITE &&
1064                 host->timing != MMC_TIMING_MMC_HS400)
1065                 goto disable;
1066
1067         if (data->flags & MMC_DATA_WRITE)
1068                 enable = SDMMC_CARD_WR_THR_EN;
1069         else
1070                 enable = SDMMC_CARD_RD_THR_EN;
1071
1072         if (host->timing != MMC_TIMING_MMC_HS200 &&
1073             host->timing != MMC_TIMING_UHS_SDR104 &&
1074             host->timing != MMC_TIMING_MMC_HS400)
1075                 goto disable;
1076
1077         blksz_depth = blksz / (1 << host->data_shift);
1078         fifo_depth = host->fifo_depth;
1079
1080         if (blksz_depth > fifo_depth)
1081                 goto disable;
1082
1083         /*
1084          * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
1085          * If (blksz_depth) <  (fifo_depth >> 1), should be thld_size = blksz
1086          * Currently just choose blksz.
1087          */
1088         thld_size = blksz;
1089         mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable));
1090         return;
1091
1092 disable:
1093         mci_writel(host, CDTHRCTL, 0);
1094 }
1095
1096 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
1097 {
1098         unsigned long irqflags;
1099         int sg_len;
1100         u32 temp;
1101
1102         host->using_dma = 0;
1103
1104         /* If we don't have a channel, we can't do DMA */
1105         if (!host->use_dma)
1106                 return -ENODEV;
1107
1108         sg_len = dw_mci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1109         if (sg_len < 0) {
1110                 host->dma_ops->stop(host);
1111                 return sg_len;
1112         }
1113
1114         host->using_dma = 1;
1115
1116         if (host->use_dma == TRANS_MODE_IDMAC)
1117                 dev_vdbg(host->dev,
1118                          "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
1119                          (unsigned long)host->sg_cpu,
1120                          (unsigned long)host->sg_dma,
1121                          sg_len);
1122
1123         /*
1124          * Decide the MSIZE and RX/TX Watermark.
1125          * If current block size is same with previous size,
1126          * no need to update fifoth.
1127          */
1128         if (host->prev_blksz != data->blksz)
1129                 dw_mci_adjust_fifoth(host, data);
1130
1131         /* Enable the DMA interface */
1132         temp = mci_readl(host, CTRL);
1133         temp |= SDMMC_CTRL_DMA_ENABLE;
1134         mci_writel(host, CTRL, temp);
1135
1136         /* Disable RX/TX IRQs, let DMA handle it */
1137         spin_lock_irqsave(&host->irq_lock, irqflags);
1138         temp = mci_readl(host, INTMASK);
1139         temp  &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
1140         mci_writel(host, INTMASK, temp);
1141         spin_unlock_irqrestore(&host->irq_lock, irqflags);
1142
1143         if (host->dma_ops->start(host, sg_len)) {
1144                 host->dma_ops->stop(host);
1145                 /* We can't do DMA, try PIO for this one */
1146                 dev_dbg(host->dev,
1147                         "%s: fall back to PIO mode for current transfer\n",
1148                         __func__);
1149                 return -ENODEV;
1150         }
1151
1152         return 0;
1153 }
1154
1155 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
1156 {
1157         unsigned long irqflags;
1158         int flags = SG_MITER_ATOMIC;
1159         u32 temp;
1160
1161         data->error = -EINPROGRESS;
1162
1163         WARN_ON(host->data);
1164         host->sg = NULL;
1165         host->data = data;
1166
1167         if (data->flags & MMC_DATA_READ)
1168                 host->dir_status = DW_MCI_RECV_STATUS;
1169         else
1170                 host->dir_status = DW_MCI_SEND_STATUS;
1171
1172         dw_mci_ctrl_thld(host, data);
1173
1174         if (dw_mci_submit_data_dma(host, data)) {
1175                 if (host->data->flags & MMC_DATA_READ)
1176                         flags |= SG_MITER_TO_SG;
1177                 else
1178                         flags |= SG_MITER_FROM_SG;
1179
1180                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1181                 host->sg = data->sg;
1182                 host->part_buf_start = 0;
1183                 host->part_buf_count = 0;
1184
1185                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
1186
1187                 spin_lock_irqsave(&host->irq_lock, irqflags);
1188                 temp = mci_readl(host, INTMASK);
1189                 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
1190                 mci_writel(host, INTMASK, temp);
1191                 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1192
1193                 temp = mci_readl(host, CTRL);
1194                 temp &= ~SDMMC_CTRL_DMA_ENABLE;
1195                 mci_writel(host, CTRL, temp);
1196
1197                 /*
1198                  * Use the initial fifoth_val for PIO mode. If wm_algined
1199                  * is set, we set watermark same as data size.
1200                  * If next issued data may be transfered by DMA mode,
1201                  * prev_blksz should be invalidated.
1202                  */
1203                 if (host->wm_aligned)
1204                         dw_mci_adjust_fifoth(host, data);
1205                 else
1206                         mci_writel(host, FIFOTH, host->fifoth_val);
1207                 host->prev_blksz = 0;
1208         } else {
1209                 /*
1210                  * Keep the current block size.
1211                  * It will be used to decide whether to update
1212                  * fifoth register next time.
1213                  */
1214                 host->prev_blksz = data->blksz;
1215         }
1216 }
1217
1218 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
1219 {
1220         struct dw_mci *host = slot->host;
1221         unsigned int clock = slot->clock;
1222         u32 div;
1223         u32 clk_en_a;
1224         u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
1225
1226         /* We must continue to set bit 28 in CMD until the change is complete */
1227         if (host->state == STATE_WAITING_CMD11_DONE)
1228                 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
1229
1230         slot->mmc->actual_clock = 0;
1231
1232         if (!clock) {
1233                 mci_writel(host, CLKENA, 0);
1234                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1235         } else if (clock != host->current_speed || force_clkinit) {
1236                 div = host->bus_hz / clock;
1237                 if (host->bus_hz % clock && host->bus_hz > clock)
1238                         /*
1239                          * move the + 1 after the divide to prevent
1240                          * over-clocking the card.
1241                          */
1242                         div += 1;
1243
1244                 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
1245
1246                 if ((clock != slot->__clk_old &&
1247                         !test_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags)) ||
1248                         force_clkinit) {
1249                         /* Silent the verbose log if calling from PM context */
1250                         if (!force_clkinit)
1251                                 dev_info(&slot->mmc->class_dev,
1252                                          "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1253                                          slot->id, host->bus_hz, clock,
1254                                          div ? ((host->bus_hz / div) >> 1) :
1255                                          host->bus_hz, div);
1256
1257                         /*
1258                          * If card is polling, display the message only
1259                          * one time at boot time.
1260                          */
1261                         if (slot->mmc->caps & MMC_CAP_NEEDS_POLL &&
1262                                         slot->mmc->f_min == clock)
1263                                 set_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags);
1264                 }
1265
1266                 /* disable clock */
1267                 mci_writel(host, CLKENA, 0);
1268                 mci_writel(host, CLKSRC, 0);
1269
1270                 /* inform CIU */
1271                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1272
1273                 /* set clock to desired speed */
1274                 mci_writel(host, CLKDIV, div);
1275
1276                 /* inform CIU */
1277                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1278
1279                 /* enable clock; only low power if no SDIO */
1280                 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
1281                 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
1282                         clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1283                 mci_writel(host, CLKENA, clk_en_a);
1284
1285                 /* inform CIU */
1286                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1287
1288                 /* keep the last clock value that was requested from core */
1289                 slot->__clk_old = clock;
1290                 slot->mmc->actual_clock = div ? ((host->bus_hz / div) >> 1) :
1291                                           host->bus_hz;
1292         }
1293
1294         host->current_speed = clock;
1295
1296         /* Set the current slot bus width */
1297         mci_writel(host, CTYPE, (slot->ctype << slot->id));
1298 }
1299
1300 static void __dw_mci_start_request(struct dw_mci *host,
1301                                    struct dw_mci_slot *slot,
1302                                    struct mmc_command *cmd)
1303 {
1304         struct mmc_request *mrq;
1305         struct mmc_data *data;
1306         u32 cmdflags;
1307
1308         mrq = slot->mrq;
1309
1310         host->mrq = mrq;
1311
1312         host->pending_events = 0;
1313         host->completed_events = 0;
1314         host->cmd_status = 0;
1315         host->data_status = 0;
1316         host->dir_status = 0;
1317
1318         data = cmd->data;
1319         if (data) {
1320                 mci_writel(host, TMOUT, 0xFFFFFFFF);
1321                 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1322                 mci_writel(host, BLKSIZ, data->blksz);
1323         }
1324
1325         cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1326
1327         /* this is the first command, send the initialization clock */
1328         if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1329                 cmdflags |= SDMMC_CMD_INIT;
1330
1331         if (data) {
1332                 dw_mci_submit_data(host, data);
1333                 wmb(); /* drain writebuffer */
1334         }
1335
1336         dw_mci_start_command(host, cmd, cmdflags);
1337
1338         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
1339                 unsigned long irqflags;
1340
1341                 /*
1342                  * Databook says to fail after 2ms w/ no response, but evidence
1343                  * shows that sometimes the cmd11 interrupt takes over 130ms.
1344                  * We'll set to 500ms, plus an extra jiffy just in case jiffies
1345                  * is just about to roll over.
1346                  *
1347                  * We do this whole thing under spinlock and only if the
1348                  * command hasn't already completed (indicating the the irq
1349                  * already ran so we don't want the timeout).
1350                  */
1351                 spin_lock_irqsave(&host->irq_lock, irqflags);
1352                 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1353                         mod_timer(&host->cmd11_timer,
1354                                 jiffies + msecs_to_jiffies(500) + 1);
1355                 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1356         }
1357
1358         host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
1359 }
1360
1361 static void dw_mci_start_request(struct dw_mci *host,
1362                                  struct dw_mci_slot *slot)
1363 {
1364         struct mmc_request *mrq = slot->mrq;
1365         struct mmc_command *cmd;
1366
1367         cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1368         __dw_mci_start_request(host, slot, cmd);
1369 }
1370
1371 /* must be called with host->lock held */
1372 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1373                                  struct mmc_request *mrq)
1374 {
1375         dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1376                  host->state);
1377
1378         slot->mrq = mrq;
1379
1380         if (host->state == STATE_WAITING_CMD11_DONE) {
1381                 dev_warn(&slot->mmc->class_dev,
1382                          "Voltage change didn't complete\n");
1383                 /*
1384                  * this case isn't expected to happen, so we can
1385                  * either crash here or just try to continue on
1386                  * in the closest possible state
1387                  */
1388                 host->state = STATE_IDLE;
1389         }
1390
1391         if (host->state == STATE_IDLE) {
1392                 host->state = STATE_SENDING_CMD;
1393                 dw_mci_start_request(host, slot);
1394         } else {
1395                 list_add_tail(&slot->queue_node, &host->queue);
1396         }
1397 }
1398
1399 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1400 {
1401         struct dw_mci_slot *slot = mmc_priv(mmc);
1402         struct dw_mci *host = slot->host;
1403
1404         WARN_ON(slot->mrq);
1405
1406         /*
1407          * The check for card presence and queueing of the request must be
1408          * atomic, otherwise the card could be removed in between and the
1409          * request wouldn't fail until another card was inserted.
1410          */
1411
1412         if (!dw_mci_get_cd(mmc)) {
1413                 mrq->cmd->error = -ENOMEDIUM;
1414                 mmc_request_done(mmc, mrq);
1415                 return;
1416         }
1417
1418         spin_lock_bh(&host->lock);
1419
1420         dw_mci_queue_request(host, slot, mrq);
1421
1422         spin_unlock_bh(&host->lock);
1423 }
1424
1425 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1426 {
1427         struct dw_mci_slot *slot = mmc_priv(mmc);
1428         const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1429         u32 regs;
1430         int ret;
1431
1432         switch (ios->bus_width) {
1433         case MMC_BUS_WIDTH_4:
1434                 slot->ctype = SDMMC_CTYPE_4BIT;
1435                 break;
1436         case MMC_BUS_WIDTH_8:
1437                 slot->ctype = SDMMC_CTYPE_8BIT;
1438                 break;
1439         default:
1440                 /* set default 1 bit mode */
1441                 slot->ctype = SDMMC_CTYPE_1BIT;
1442         }
1443
1444         regs = mci_readl(slot->host, UHS_REG);
1445
1446         /* DDR mode set */
1447         if (ios->timing == MMC_TIMING_MMC_DDR52 ||
1448             ios->timing == MMC_TIMING_UHS_DDR50 ||
1449             ios->timing == MMC_TIMING_MMC_HS400)
1450                 regs |= ((0x1 << slot->id) << 16);
1451         else
1452                 regs &= ~((0x1 << slot->id) << 16);
1453
1454         mci_writel(slot->host, UHS_REG, regs);
1455         slot->host->timing = ios->timing;
1456
1457         /*
1458          * Use mirror of ios->clock to prevent race with mmc
1459          * core ios update when finding the minimum.
1460          */
1461         slot->clock = ios->clock;
1462
1463         if (drv_data && drv_data->set_ios)
1464                 drv_data->set_ios(slot->host, ios);
1465
1466         switch (ios->power_mode) {
1467         case MMC_POWER_UP:
1468                 if (!IS_ERR(mmc->supply.vmmc)) {
1469                         ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1470                                         ios->vdd);
1471                         if (ret) {
1472                                 dev_err(slot->host->dev,
1473                                         "failed to enable vmmc regulator\n");
1474                                 /*return, if failed turn on vmmc*/
1475                                 return;
1476                         }
1477                 }
1478                 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1479                 regs = mci_readl(slot->host, PWREN);
1480                 regs |= (1 << slot->id);
1481                 mci_writel(slot->host, PWREN, regs);
1482                 break;
1483         case MMC_POWER_ON:
1484                 if (!slot->host->vqmmc_enabled) {
1485                         if (!IS_ERR(mmc->supply.vqmmc)) {
1486                                 ret = regulator_enable(mmc->supply.vqmmc);
1487                                 if (ret < 0)
1488                                         dev_err(slot->host->dev,
1489                                                 "failed to enable vqmmc\n");
1490                                 else
1491                                         slot->host->vqmmc_enabled = true;
1492
1493                         } else {
1494                                 /* Keep track so we don't reset again */
1495                                 slot->host->vqmmc_enabled = true;
1496                         }
1497
1498                         /* Reset our state machine after powering on */
1499                         dw_mci_ctrl_reset(slot->host,
1500                                           SDMMC_CTRL_ALL_RESET_FLAGS);
1501                 }
1502
1503                 /* Adjust clock / bus width after power is up */
1504                 dw_mci_setup_bus(slot, false);
1505
1506                 break;
1507         case MMC_POWER_OFF:
1508                 /* Turn clock off before power goes down */
1509                 dw_mci_setup_bus(slot, false);
1510
1511                 if (!IS_ERR(mmc->supply.vmmc))
1512                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1513
1514                 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
1515                         regulator_disable(mmc->supply.vqmmc);
1516                 slot->host->vqmmc_enabled = false;
1517
1518                 regs = mci_readl(slot->host, PWREN);
1519                 regs &= ~(1 << slot->id);
1520                 mci_writel(slot->host, PWREN, regs);
1521                 break;
1522         default:
1523                 break;
1524         }
1525
1526         if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1527                 slot->host->state = STATE_IDLE;
1528 }
1529
1530 static int dw_mci_card_busy(struct mmc_host *mmc)
1531 {
1532         struct dw_mci_slot *slot = mmc_priv(mmc);
1533         u32 status;
1534
1535         /*
1536          * Check the busy bit which is low when DAT[3:0]
1537          * (the data lines) are 0000
1538          */
1539         status = mci_readl(slot->host, STATUS);
1540
1541         return !!(status & SDMMC_STATUS_BUSY);
1542 }
1543
1544 static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1545 {
1546         struct dw_mci_slot *slot = mmc_priv(mmc);
1547         struct dw_mci *host = slot->host;
1548         const struct dw_mci_drv_data *drv_data = host->drv_data;
1549         u32 uhs;
1550         u32 v18 = SDMMC_UHS_18V << slot->id;
1551         int ret;
1552
1553         if (drv_data && drv_data->switch_voltage)
1554                 return drv_data->switch_voltage(mmc, ios);
1555
1556         /*
1557          * Program the voltage.  Note that some instances of dw_mmc may use
1558          * the UHS_REG for this.  For other instances (like exynos) the UHS_REG
1559          * does no harm but you need to set the regulator directly.  Try both.
1560          */
1561         uhs = mci_readl(host, UHS_REG);
1562         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1563                 uhs &= ~v18;
1564         else
1565                 uhs |= v18;
1566
1567         if (!IS_ERR(mmc->supply.vqmmc)) {
1568                 ret = mmc_regulator_set_vqmmc(mmc, ios);
1569
1570                 if (ret) {
1571                         dev_dbg(&mmc->class_dev,
1572                                          "Regulator set error %d - %s V\n",
1573                                          ret, uhs & v18 ? "1.8" : "3.3");
1574                         return ret;
1575                 }
1576         }
1577         mci_writel(host, UHS_REG, uhs);
1578
1579         return 0;
1580 }
1581
1582 static int dw_mci_get_ro(struct mmc_host *mmc)
1583 {
1584         int read_only;
1585         struct dw_mci_slot *slot = mmc_priv(mmc);
1586         int gpio_ro = mmc_gpio_get_ro(mmc);
1587
1588         /* Use platform get_ro function, else try on board write protect */
1589         if (gpio_ro >= 0)
1590                 read_only = gpio_ro;
1591         else
1592                 read_only =
1593                         mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1594
1595         dev_dbg(&mmc->class_dev, "card is %s\n",
1596                 read_only ? "read-only" : "read-write");
1597
1598         return read_only;
1599 }
1600
1601 static void dw_mci_hw_reset(struct mmc_host *mmc)
1602 {
1603         struct dw_mci_slot *slot = mmc_priv(mmc);
1604         struct dw_mci *host = slot->host;
1605         int reset;
1606
1607         if (host->use_dma == TRANS_MODE_IDMAC)
1608                 dw_mci_idmac_reset(host);
1609
1610         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET |
1611                                      SDMMC_CTRL_FIFO_RESET))
1612                 return;
1613
1614         /*
1615          * According to eMMC spec, card reset procedure:
1616          * tRstW >= 1us:   RST_n pulse width
1617          * tRSCA >= 200us: RST_n to Command time
1618          * tRSTH >= 1us:   RST_n high period
1619          */
1620         reset = mci_readl(host, RST_N);
1621         reset &= ~(SDMMC_RST_HWACTIVE << slot->id);
1622         mci_writel(host, RST_N, reset);
1623         usleep_range(1, 2);
1624         reset |= SDMMC_RST_HWACTIVE << slot->id;
1625         mci_writel(host, RST_N, reset);
1626         usleep_range(200, 300);
1627 }
1628
1629 static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
1630 {
1631         struct dw_mci_slot *slot = mmc_priv(mmc);
1632         struct dw_mci *host = slot->host;
1633
1634         /*
1635          * Low power mode will stop the card clock when idle.  According to the
1636          * description of the CLKENA register we should disable low power mode
1637          * for SDIO cards if we need SDIO interrupts to work.
1638          */
1639         if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1640                 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1641                 u32 clk_en_a_old;
1642                 u32 clk_en_a;
1643
1644                 clk_en_a_old = mci_readl(host, CLKENA);
1645
1646                 if (card->type == MMC_TYPE_SDIO ||
1647                     card->type == MMC_TYPE_SD_COMBO) {
1648                         set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1649                         clk_en_a = clk_en_a_old & ~clken_low_pwr;
1650                 } else {
1651                         clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1652                         clk_en_a = clk_en_a_old | clken_low_pwr;
1653                 }
1654
1655                 if (clk_en_a != clk_en_a_old) {
1656                         mci_writel(host, CLKENA, clk_en_a);
1657                         mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1658                                      SDMMC_CMD_PRV_DAT_WAIT, 0);
1659                 }
1660         }
1661 }
1662
1663 static void __dw_mci_enable_sdio_irq(struct dw_mci_slot *slot, int enb)
1664 {
1665         struct dw_mci *host = slot->host;
1666         unsigned long irqflags;
1667         u32 int_mask;
1668
1669         spin_lock_irqsave(&host->irq_lock, irqflags);
1670
1671         /* Enable/disable Slot Specific SDIO interrupt */
1672         int_mask = mci_readl(host, INTMASK);
1673         if (enb)
1674                 int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
1675         else
1676                 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
1677         mci_writel(host, INTMASK, int_mask);
1678
1679         spin_unlock_irqrestore(&host->irq_lock, irqflags);
1680 }
1681
1682 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1683 {
1684         struct dw_mci_slot *slot = mmc_priv(mmc);
1685         struct dw_mci *host = slot->host;
1686
1687         __dw_mci_enable_sdio_irq(slot, enb);
1688
1689         /* Avoid runtime suspending the device when SDIO IRQ is enabled */
1690         if (enb)
1691                 pm_runtime_get_noresume(host->dev);
1692         else
1693                 pm_runtime_put_noidle(host->dev);
1694 }
1695
1696 static void dw_mci_ack_sdio_irq(struct mmc_host *mmc)
1697 {
1698         struct dw_mci_slot *slot = mmc_priv(mmc);
1699
1700         __dw_mci_enable_sdio_irq(slot, 1);
1701 }
1702
1703 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1704 {
1705         struct dw_mci_slot *slot = mmc_priv(mmc);
1706         struct dw_mci *host = slot->host;
1707         const struct dw_mci_drv_data *drv_data = host->drv_data;
1708         int err = -EINVAL;
1709
1710         if (drv_data && drv_data->execute_tuning)
1711                 err = drv_data->execute_tuning(slot, opcode);
1712         return err;
1713 }
1714
1715 static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc,
1716                                        struct mmc_ios *ios)
1717 {
1718         struct dw_mci_slot *slot = mmc_priv(mmc);
1719         struct dw_mci *host = slot->host;
1720         const struct dw_mci_drv_data *drv_data = host->drv_data;
1721
1722         if (drv_data && drv_data->prepare_hs400_tuning)
1723                 return drv_data->prepare_hs400_tuning(host, ios);
1724
1725         return 0;
1726 }
1727
1728 static bool dw_mci_reset(struct dw_mci *host)
1729 {
1730         u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
1731         bool ret = false;
1732         u32 status = 0;
1733
1734         /*
1735          * Resetting generates a block interrupt, hence setting
1736          * the scatter-gather pointer to NULL.
1737          */
1738         if (host->sg) {
1739                 sg_miter_stop(&host->sg_miter);
1740                 host->sg = NULL;
1741         }
1742
1743         if (host->use_dma)
1744                 flags |= SDMMC_CTRL_DMA_RESET;
1745
1746         if (dw_mci_ctrl_reset(host, flags)) {
1747                 /*
1748                  * In all cases we clear the RAWINTS
1749                  * register to clear any interrupts.
1750                  */
1751                 mci_writel(host, RINTSTS, 0xFFFFFFFF);
1752
1753                 if (!host->use_dma) {
1754                         ret = true;
1755                         goto ciu_out;
1756                 }
1757
1758                 /* Wait for dma_req to be cleared */
1759                 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
1760                                               status,
1761                                               !(status & SDMMC_STATUS_DMA_REQ),
1762                                               1, 500 * USEC_PER_MSEC)) {
1763                         dev_err(host->dev,
1764                                 "%s: Timeout waiting for dma_req to be cleared\n",
1765                                 __func__);
1766                         goto ciu_out;
1767                 }
1768
1769                 /* when using DMA next we reset the fifo again */
1770                 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
1771                         goto ciu_out;
1772         } else {
1773                 /* if the controller reset bit did clear, then set clock regs */
1774                 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
1775                         dev_err(host->dev,
1776                                 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
1777                                 __func__);
1778                         goto ciu_out;
1779                 }
1780         }
1781
1782         if (host->use_dma == TRANS_MODE_IDMAC)
1783                 /* It is also required that we reinit idmac */
1784                 dw_mci_idmac_init(host);
1785
1786         ret = true;
1787
1788 ciu_out:
1789         /* After a CTRL reset we need to have CIU set clock registers  */
1790         mci_send_cmd(host->slot, SDMMC_CMD_UPD_CLK, 0);
1791
1792         return ret;
1793 }
1794
1795 static const struct mmc_host_ops dw_mci_ops = {
1796         .request                = dw_mci_request,
1797         .pre_req                = dw_mci_pre_req,
1798         .post_req               = dw_mci_post_req,
1799         .set_ios                = dw_mci_set_ios,
1800         .get_ro                 = dw_mci_get_ro,
1801         .get_cd                 = dw_mci_get_cd,
1802         .hw_reset               = dw_mci_hw_reset,
1803         .enable_sdio_irq        = dw_mci_enable_sdio_irq,
1804         .ack_sdio_irq           = dw_mci_ack_sdio_irq,
1805         .execute_tuning         = dw_mci_execute_tuning,
1806         .card_busy              = dw_mci_card_busy,
1807         .start_signal_voltage_switch = dw_mci_switch_voltage,
1808         .init_card              = dw_mci_init_card,
1809         .prepare_hs400_tuning   = dw_mci_prepare_hs400_tuning,
1810 };
1811
1812 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1813         __releases(&host->lock)
1814         __acquires(&host->lock)
1815 {
1816         struct dw_mci_slot *slot;
1817         struct mmc_host *prev_mmc = host->slot->mmc;
1818
1819         WARN_ON(host->cmd || host->data);
1820
1821         host->slot->mrq = NULL;
1822         host->mrq = NULL;
1823         if (!list_empty(&host->queue)) {
1824                 slot = list_entry(host->queue.next,
1825                                   struct dw_mci_slot, queue_node);
1826                 list_del(&slot->queue_node);
1827                 dev_vdbg(host->dev, "list not empty: %s is next\n",
1828                          mmc_hostname(slot->mmc));
1829                 host->state = STATE_SENDING_CMD;
1830                 dw_mci_start_request(host, slot);
1831         } else {
1832                 dev_vdbg(host->dev, "list empty\n");
1833
1834                 if (host->state == STATE_SENDING_CMD11)
1835                         host->state = STATE_WAITING_CMD11_DONE;
1836                 else
1837                         host->state = STATE_IDLE;
1838         }
1839
1840         spin_unlock(&host->lock);
1841         mmc_request_done(prev_mmc, mrq);
1842         spin_lock(&host->lock);
1843 }
1844
1845 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
1846 {
1847         u32 status = host->cmd_status;
1848
1849         host->cmd_status = 0;
1850
1851         /* Read the response from the card (up to 16 bytes) */
1852         if (cmd->flags & MMC_RSP_PRESENT) {
1853                 if (cmd->flags & MMC_RSP_136) {
1854                         cmd->resp[3] = mci_readl(host, RESP0);
1855                         cmd->resp[2] = mci_readl(host, RESP1);
1856                         cmd->resp[1] = mci_readl(host, RESP2);
1857                         cmd->resp[0] = mci_readl(host, RESP3);
1858                 } else {
1859                         cmd->resp[0] = mci_readl(host, RESP0);
1860                         cmd->resp[1] = 0;
1861                         cmd->resp[2] = 0;
1862                         cmd->resp[3] = 0;
1863                 }
1864         }
1865
1866         if (status & SDMMC_INT_RTO)
1867                 cmd->error = -ETIMEDOUT;
1868         else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1869                 cmd->error = -EILSEQ;
1870         else if (status & SDMMC_INT_RESP_ERR)
1871                 cmd->error = -EIO;
1872         else
1873                 cmd->error = 0;
1874
1875         return cmd->error;
1876 }
1877
1878 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1879 {
1880         u32 status = host->data_status;
1881
1882         if (status & DW_MCI_DATA_ERROR_FLAGS) {
1883                 if (status & SDMMC_INT_DRTO) {
1884                         data->error = -ETIMEDOUT;
1885                 } else if (status & SDMMC_INT_DCRC) {
1886                         data->error = -EILSEQ;
1887                 } else if (status & SDMMC_INT_EBE) {
1888                         if (host->dir_status ==
1889                                 DW_MCI_SEND_STATUS) {
1890                                 /*
1891                                  * No data CRC status was returned.
1892                                  * The number of bytes transferred
1893                                  * will be exaggerated in PIO mode.
1894                                  */
1895                                 data->bytes_xfered = 0;
1896                                 data->error = -ETIMEDOUT;
1897                         } else if (host->dir_status ==
1898                                         DW_MCI_RECV_STATUS) {
1899                                 data->error = -EILSEQ;
1900                         }
1901                 } else {
1902                         /* SDMMC_INT_SBE is included */
1903                         data->error = -EILSEQ;
1904                 }
1905
1906                 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
1907
1908                 /*
1909                  * After an error, there may be data lingering
1910                  * in the FIFO
1911                  */
1912                 dw_mci_reset(host);
1913         } else {
1914                 data->bytes_xfered = data->blocks * data->blksz;
1915                 data->error = 0;
1916         }
1917
1918         return data->error;
1919 }
1920
1921 static void dw_mci_set_drto(struct dw_mci *host)
1922 {
1923         unsigned int drto_clks;
1924         unsigned int drto_div;
1925         unsigned int drto_ms;
1926         unsigned long irqflags;
1927
1928         drto_clks = mci_readl(host, TMOUT) >> 8;
1929         drto_div = (mci_readl(host, CLKDIV) & 0xff) * 2;
1930         if (drto_div == 0)
1931                 drto_div = 1;
1932
1933         drto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * drto_clks * drto_div,
1934                                    host->bus_hz);
1935
1936         /* add a bit spare time */
1937         drto_ms += 10;
1938
1939         spin_lock_irqsave(&host->irq_lock, irqflags);
1940         if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events))
1941                 mod_timer(&host->dto_timer,
1942                           jiffies + msecs_to_jiffies(drto_ms));
1943         spin_unlock_irqrestore(&host->irq_lock, irqflags);
1944 }
1945
1946 static bool dw_mci_clear_pending_cmd_complete(struct dw_mci *host)
1947 {
1948         if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1949                 return false;
1950
1951         /*
1952          * Really be certain that the timer has stopped.  This is a bit of
1953          * paranoia and could only really happen if we had really bad
1954          * interrupt latency and the interrupt routine and timeout were
1955          * running concurrently so that the del_timer() in the interrupt
1956          * handler couldn't run.
1957          */
1958         WARN_ON(del_timer_sync(&host->cto_timer));
1959         clear_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1960
1961         return true;
1962 }
1963
1964 static bool dw_mci_clear_pending_data_complete(struct dw_mci *host)
1965 {
1966         if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events))
1967                 return false;
1968
1969         /* Extra paranoia just like dw_mci_clear_pending_cmd_complete() */
1970         WARN_ON(del_timer_sync(&host->dto_timer));
1971         clear_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1972
1973         return true;
1974 }
1975
1976 static void dw_mci_tasklet_func(unsigned long priv)
1977 {
1978         struct dw_mci *host = (struct dw_mci *)priv;
1979         struct mmc_data *data;
1980         struct mmc_command *cmd;
1981         struct mmc_request *mrq;
1982         enum dw_mci_state state;
1983         enum dw_mci_state prev_state;
1984         unsigned int err;
1985
1986         spin_lock(&host->lock);
1987
1988         state = host->state;
1989         data = host->data;
1990         mrq = host->mrq;
1991
1992         do {
1993                 prev_state = state;
1994
1995                 switch (state) {
1996                 case STATE_IDLE:
1997                 case STATE_WAITING_CMD11_DONE:
1998                         break;
1999
2000                 case STATE_SENDING_CMD11:
2001                 case STATE_SENDING_CMD:
2002                         if (!dw_mci_clear_pending_cmd_complete(host))
2003                                 break;
2004
2005                         cmd = host->cmd;
2006                         host->cmd = NULL;
2007                         set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
2008                         err = dw_mci_command_complete(host, cmd);
2009                         if (cmd == mrq->sbc && !err) {
2010                                 __dw_mci_start_request(host, host->slot,
2011                                                        mrq->cmd);
2012                                 goto unlock;
2013                         }
2014
2015                         if (cmd->data && err) {
2016                                 /*
2017                                  * During UHS tuning sequence, sending the stop
2018                                  * command after the response CRC error would
2019                                  * throw the system into a confused state
2020                                  * causing all future tuning phases to report
2021                                  * failure.
2022                                  *
2023                                  * In such case controller will move into a data
2024                                  * transfer state after a response error or
2025                                  * response CRC error. Let's let that finish
2026                                  * before trying to send a stop, so we'll go to
2027                                  * STATE_SENDING_DATA.
2028                                  *
2029                                  * Although letting the data transfer take place
2030                                  * will waste a bit of time (we already know
2031                                  * the command was bad), it can't cause any
2032                                  * errors since it's possible it would have
2033                                  * taken place anyway if this tasklet got
2034                                  * delayed. Allowing the transfer to take place
2035                                  * avoids races and keeps things simple.
2036                                  */
2037                                 if ((err != -ETIMEDOUT) &&
2038                                     (cmd->opcode == MMC_SEND_TUNING_BLOCK)) {
2039                                         state = STATE_SENDING_DATA;
2040                                         continue;
2041                                 }
2042
2043                                 dw_mci_stop_dma(host);
2044                                 send_stop_abort(host, data);
2045                                 state = STATE_SENDING_STOP;
2046                                 break;
2047                         }
2048
2049                         if (!cmd->data || err) {
2050                                 dw_mci_request_end(host, mrq);
2051                                 goto unlock;
2052                         }
2053
2054                         prev_state = state = STATE_SENDING_DATA;
2055                         /* fall through */
2056
2057                 case STATE_SENDING_DATA:
2058                         /*
2059                          * We could get a data error and never a transfer
2060                          * complete so we'd better check for it here.
2061                          *
2062                          * Note that we don't really care if we also got a
2063                          * transfer complete; stopping the DMA and sending an
2064                          * abort won't hurt.
2065                          */
2066                         if (test_and_clear_bit(EVENT_DATA_ERROR,
2067                                                &host->pending_events)) {
2068                                 dw_mci_stop_dma(host);
2069                                 if (!(host->data_status & (SDMMC_INT_DRTO |
2070                                                            SDMMC_INT_EBE)))
2071                                         send_stop_abort(host, data);
2072                                 state = STATE_DATA_ERROR;
2073                                 break;
2074                         }
2075
2076                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2077                                                 &host->pending_events)) {
2078                                 /*
2079                                  * If all data-related interrupts don't come
2080                                  * within the given time in reading data state.
2081                                  */
2082                                 if (host->dir_status == DW_MCI_RECV_STATUS)
2083                                         dw_mci_set_drto(host);
2084                                 break;
2085                         }
2086
2087                         set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
2088
2089                         /*
2090                          * Handle an EVENT_DATA_ERROR that might have shown up
2091                          * before the transfer completed.  This might not have
2092                          * been caught by the check above because the interrupt
2093                          * could have gone off between the previous check and
2094                          * the check for transfer complete.
2095                          *
2096                          * Technically this ought not be needed assuming we
2097                          * get a DATA_COMPLETE eventually (we'll notice the
2098                          * error and end the request), but it shouldn't hurt.
2099                          *
2100                          * This has the advantage of sending the stop command.
2101                          */
2102                         if (test_and_clear_bit(EVENT_DATA_ERROR,
2103                                                &host->pending_events)) {
2104                                 dw_mci_stop_dma(host);
2105                                 if (!(host->data_status & (SDMMC_INT_DRTO |
2106                                                            SDMMC_INT_EBE)))
2107                                         send_stop_abort(host, data);
2108                                 state = STATE_DATA_ERROR;
2109                                 break;
2110                         }
2111                         prev_state = state = STATE_DATA_BUSY;
2112
2113                         /* fall through */
2114
2115                 case STATE_DATA_BUSY:
2116                         if (!dw_mci_clear_pending_data_complete(host)) {
2117                                 /*
2118                                  * If data error interrupt comes but data over
2119                                  * interrupt doesn't come within the given time.
2120                                  * in reading data state.
2121                                  */
2122                                 if (host->dir_status == DW_MCI_RECV_STATUS)
2123                                         dw_mci_set_drto(host);
2124                                 break;
2125                         }
2126
2127                         host->data = NULL;
2128                         set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
2129                         err = dw_mci_data_complete(host, data);
2130
2131                         if (!err) {
2132                                 if (!data->stop || mrq->sbc) {
2133                                         if (mrq->sbc && data->stop)
2134                                                 data->stop->error = 0;
2135                                         dw_mci_request_end(host, mrq);
2136                                         goto unlock;
2137                                 }
2138
2139                                 /* stop command for open-ended transfer*/
2140                                 if (data->stop)
2141                                         send_stop_abort(host, data);
2142                         } else {
2143                                 /*
2144                                  * If we don't have a command complete now we'll
2145                                  * never get one since we just reset everything;
2146                                  * better end the request.
2147                                  *
2148                                  * If we do have a command complete we'll fall
2149                                  * through to the SENDING_STOP command and
2150                                  * everything will be peachy keen.
2151                                  */
2152                                 if (!test_bit(EVENT_CMD_COMPLETE,
2153                                               &host->pending_events)) {
2154                                         host->cmd = NULL;
2155                                         dw_mci_request_end(host, mrq);
2156                                         goto unlock;
2157                                 }
2158                         }
2159
2160                         /*
2161                          * If err has non-zero,
2162                          * stop-abort command has been already issued.
2163                          */
2164                         prev_state = state = STATE_SENDING_STOP;
2165
2166                         /* fall through */
2167
2168                 case STATE_SENDING_STOP:
2169                         if (!dw_mci_clear_pending_cmd_complete(host))
2170                                 break;
2171
2172                         /* CMD error in data command */
2173                         if (mrq->cmd->error && mrq->data)
2174                                 dw_mci_reset(host);
2175
2176                         host->cmd = NULL;
2177                         host->data = NULL;
2178
2179                         if (!mrq->sbc && mrq->stop)
2180                                 dw_mci_command_complete(host, mrq->stop);
2181                         else
2182                                 host->cmd_status = 0;
2183
2184                         dw_mci_request_end(host, mrq);
2185                         goto unlock;
2186
2187                 case STATE_DATA_ERROR:
2188                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2189                                                 &host->pending_events))
2190                                 break;
2191
2192                         state = STATE_DATA_BUSY;
2193                         break;
2194                 }
2195         } while (state != prev_state);
2196
2197         host->state = state;
2198 unlock:
2199         spin_unlock(&host->lock);
2200
2201 }
2202
2203 /* push final bytes to part_buf, only use during push */
2204 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
2205 {
2206         memcpy((void *)&host->part_buf, buf, cnt);
2207         host->part_buf_count = cnt;
2208 }
2209
2210 /* append bytes to part_buf, only use during push */
2211 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
2212 {
2213         cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
2214         memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
2215         host->part_buf_count += cnt;
2216         return cnt;
2217 }
2218
2219 /* pull first bytes from part_buf, only use during pull */
2220 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
2221 {
2222         cnt = min_t(int, cnt, host->part_buf_count);
2223         if (cnt) {
2224                 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
2225                        cnt);
2226                 host->part_buf_count -= cnt;
2227                 host->part_buf_start += cnt;
2228         }
2229         return cnt;
2230 }
2231
2232 /* pull final bytes from the part_buf, assuming it's just been filled */
2233 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
2234 {
2235         memcpy(buf, &host->part_buf, cnt);
2236         host->part_buf_start = cnt;
2237         host->part_buf_count = (1 << host->data_shift) - cnt;
2238 }
2239
2240 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
2241 {
2242         struct mmc_data *data = host->data;
2243         int init_cnt = cnt;
2244
2245         /* try and push anything in the part_buf */
2246         if (unlikely(host->part_buf_count)) {
2247                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2248
2249                 buf += len;
2250                 cnt -= len;
2251                 if (host->part_buf_count == 2) {
2252                         mci_fifo_writew(host->fifo_reg, host->part_buf16);
2253                         host->part_buf_count = 0;
2254                 }
2255         }
2256 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2257         if (unlikely((unsigned long)buf & 0x1)) {
2258                 while (cnt >= 2) {
2259                         u16 aligned_buf[64];
2260                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
2261                         int items = len >> 1;
2262                         int i;
2263                         /* memcpy from input buffer into aligned buffer */
2264                         memcpy(aligned_buf, buf, len);
2265                         buf += len;
2266                         cnt -= len;
2267                         /* push data from aligned buffer into fifo */
2268                         for (i = 0; i < items; ++i)
2269                                 mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
2270                 }
2271         } else
2272 #endif
2273         {
2274                 u16 *pdata = buf;
2275
2276                 for (; cnt >= 2; cnt -= 2)
2277                         mci_fifo_writew(host->fifo_reg, *pdata++);
2278                 buf = pdata;
2279         }
2280         /* put anything remaining in the part_buf */
2281         if (cnt) {
2282                 dw_mci_set_part_bytes(host, buf, cnt);
2283                  /* Push data if we have reached the expected data length */
2284                 if ((data->bytes_xfered + init_cnt) ==
2285                     (data->blksz * data->blocks))
2286                         mci_fifo_writew(host->fifo_reg, host->part_buf16);
2287         }
2288 }
2289
2290 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2291 {
2292 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2293         if (unlikely((unsigned long)buf & 0x1)) {
2294                 while (cnt >= 2) {
2295                         /* pull data from fifo into aligned buffer */
2296                         u16 aligned_buf[64];
2297                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
2298                         int items = len >> 1;
2299                         int i;
2300
2301                         for (i = 0; i < items; ++i)
2302                                 aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
2303                         /* memcpy from aligned buffer into output buffer */
2304                         memcpy(buf, aligned_buf, len);
2305                         buf += len;
2306                         cnt -= len;
2307                 }
2308         } else
2309 #endif
2310         {
2311                 u16 *pdata = buf;
2312
2313                 for (; cnt >= 2; cnt -= 2)
2314                         *pdata++ = mci_fifo_readw(host->fifo_reg);
2315                 buf = pdata;
2316         }
2317         if (cnt) {
2318                 host->part_buf16 = mci_fifo_readw(host->fifo_reg);
2319                 dw_mci_pull_final_bytes(host, buf, cnt);
2320         }
2321 }
2322
2323 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2324 {
2325         struct mmc_data *data = host->data;
2326         int init_cnt = cnt;
2327
2328         /* try and push anything in the part_buf */
2329         if (unlikely(host->part_buf_count)) {
2330                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2331
2332                 buf += len;
2333                 cnt -= len;
2334                 if (host->part_buf_count == 4) {
2335                         mci_fifo_writel(host->fifo_reg, host->part_buf32);
2336                         host->part_buf_count = 0;
2337                 }
2338         }
2339 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2340         if (unlikely((unsigned long)buf & 0x3)) {
2341                 while (cnt >= 4) {
2342                         u32 aligned_buf[32];
2343                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
2344                         int items = len >> 2;
2345                         int i;
2346                         /* memcpy from input buffer into aligned buffer */
2347                         memcpy(aligned_buf, buf, len);
2348                         buf += len;
2349                         cnt -= len;
2350                         /* push data from aligned buffer into fifo */
2351                         for (i = 0; i < items; ++i)
2352                                 mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
2353                 }
2354         } else
2355 #endif
2356         {
2357                 u32 *pdata = buf;
2358
2359                 for (; cnt >= 4; cnt -= 4)
2360                         mci_fifo_writel(host->fifo_reg, *pdata++);
2361                 buf = pdata;
2362         }
2363         /* put anything remaining in the part_buf */
2364         if (cnt) {
2365                 dw_mci_set_part_bytes(host, buf, cnt);
2366                  /* Push data if we have reached the expected data length */
2367                 if ((data->bytes_xfered + init_cnt) ==
2368                     (data->blksz * data->blocks))
2369                         mci_fifo_writel(host->fifo_reg, host->part_buf32);
2370         }
2371 }
2372
2373 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2374 {
2375 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2376         if (unlikely((unsigned long)buf & 0x3)) {
2377                 while (cnt >= 4) {
2378                         /* pull data from fifo into aligned buffer */
2379                         u32 aligned_buf[32];
2380                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
2381                         int items = len >> 2;
2382                         int i;
2383
2384                         for (i = 0; i < items; ++i)
2385                                 aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
2386                         /* memcpy from aligned buffer into output buffer */
2387                         memcpy(buf, aligned_buf, len);
2388                         buf += len;
2389                         cnt -= len;
2390                 }
2391         } else
2392 #endif
2393         {
2394                 u32 *pdata = buf;
2395
2396                 for (; cnt >= 4; cnt -= 4)
2397                         *pdata++ = mci_fifo_readl(host->fifo_reg);
2398                 buf = pdata;
2399         }
2400         if (cnt) {
2401                 host->part_buf32 = mci_fifo_readl(host->fifo_reg);
2402                 dw_mci_pull_final_bytes(host, buf, cnt);
2403         }
2404 }
2405
2406 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2407 {
2408         struct mmc_data *data = host->data;
2409         int init_cnt = cnt;
2410
2411         /* try and push anything in the part_buf */
2412         if (unlikely(host->part_buf_count)) {
2413                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2414
2415                 buf += len;
2416                 cnt -= len;
2417
2418                 if (host->part_buf_count == 8) {
2419                         mci_fifo_writeq(host->fifo_reg, host->part_buf);
2420                         host->part_buf_count = 0;
2421                 }
2422         }
2423 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2424         if (unlikely((unsigned long)buf & 0x7)) {
2425                 while (cnt >= 8) {
2426                         u64 aligned_buf[16];
2427                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
2428                         int items = len >> 3;
2429                         int i;
2430                         /* memcpy from input buffer into aligned buffer */
2431                         memcpy(aligned_buf, buf, len);
2432                         buf += len;
2433                         cnt -= len;
2434                         /* push data from aligned buffer into fifo */
2435                         for (i = 0; i < items; ++i)
2436                                 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
2437                 }
2438         } else
2439 #endif
2440         {
2441                 u64 *pdata = buf;
2442
2443                 for (; cnt >= 8; cnt -= 8)
2444                         mci_fifo_writeq(host->fifo_reg, *pdata++);
2445                 buf = pdata;
2446         }
2447         /* put anything remaining in the part_buf */
2448         if (cnt) {
2449                 dw_mci_set_part_bytes(host, buf, cnt);
2450                 /* Push data if we have reached the expected data length */
2451                 if ((data->bytes_xfered + init_cnt) ==
2452                     (data->blksz * data->blocks))
2453                         mci_fifo_writeq(host->fifo_reg, host->part_buf);
2454         }
2455 }
2456
2457 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2458 {
2459 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2460         if (unlikely((unsigned long)buf & 0x7)) {
2461                 while (cnt >= 8) {
2462                         /* pull data from fifo into aligned buffer */
2463                         u64 aligned_buf[16];
2464                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
2465                         int items = len >> 3;
2466                         int i;
2467
2468                         for (i = 0; i < items; ++i)
2469                                 aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
2470
2471                         /* memcpy from aligned buffer into output buffer */
2472                         memcpy(buf, aligned_buf, len);
2473                         buf += len;
2474                         cnt -= len;
2475                 }
2476         } else
2477 #endif
2478         {
2479                 u64 *pdata = buf;
2480
2481                 for (; cnt >= 8; cnt -= 8)
2482                         *pdata++ = mci_fifo_readq(host->fifo_reg);
2483                 buf = pdata;
2484         }
2485         if (cnt) {
2486                 host->part_buf = mci_fifo_readq(host->fifo_reg);
2487                 dw_mci_pull_final_bytes(host, buf, cnt);
2488         }
2489 }
2490
2491 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2492 {
2493         int len;
2494
2495         /* get remaining partial bytes */
2496         len = dw_mci_pull_part_bytes(host, buf, cnt);
2497         if (unlikely(len == cnt))
2498                 return;
2499         buf += len;
2500         cnt -= len;
2501
2502         /* get the rest of the data */
2503         host->pull_data(host, buf, cnt);
2504 }
2505
2506 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2507 {
2508         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2509         void *buf;
2510         unsigned int offset;
2511         struct mmc_data *data = host->data;
2512         int shift = host->data_shift;
2513         u32 status;
2514         unsigned int len;
2515         unsigned int remain, fcnt;
2516
2517         do {
2518                 if (!sg_miter_next(sg_miter))
2519                         goto done;
2520
2521                 host->sg = sg_miter->piter.sg;
2522                 buf = sg_miter->addr;
2523                 remain = sg_miter->length;
2524                 offset = 0;
2525
2526                 do {
2527                         fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2528                                         << shift) + host->part_buf_count;
2529                         len = min(remain, fcnt);
2530                         if (!len)
2531                                 break;
2532                         dw_mci_pull_data(host, (void *)(buf + offset), len);
2533                         data->bytes_xfered += len;
2534                         offset += len;
2535                         remain -= len;
2536                 } while (remain);
2537
2538                 sg_miter->consumed = offset;
2539                 status = mci_readl(host, MINTSTS);
2540                 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2541         /* if the RXDR is ready read again */
2542         } while ((status & SDMMC_INT_RXDR) ||
2543                  (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2544
2545         if (!remain) {
2546                 if (!sg_miter_next(sg_miter))
2547                         goto done;
2548                 sg_miter->consumed = 0;
2549         }
2550         sg_miter_stop(sg_miter);
2551         return;
2552
2553 done:
2554         sg_miter_stop(sg_miter);
2555         host->sg = NULL;
2556         smp_wmb(); /* drain writebuffer */
2557         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2558 }
2559
2560 static void dw_mci_write_data_pio(struct dw_mci *host)
2561 {
2562         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2563         void *buf;
2564         unsigned int offset;
2565         struct mmc_data *data = host->data;
2566         int shift = host->data_shift;
2567         u32 status;
2568         unsigned int len;
2569         unsigned int fifo_depth = host->fifo_depth;
2570         unsigned int remain, fcnt;
2571
2572         do {
2573                 if (!sg_miter_next(sg_miter))
2574                         goto done;
2575
2576                 host->sg = sg_miter->piter.sg;
2577                 buf = sg_miter->addr;
2578                 remain = sg_miter->length;
2579                 offset = 0;
2580
2581                 do {
2582                         fcnt = ((fifo_depth -
2583                                  SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2584                                         << shift) - host->part_buf_count;
2585                         len = min(remain, fcnt);
2586                         if (!len)
2587                                 break;
2588                         host->push_data(host, (void *)(buf + offset), len);
2589                         data->bytes_xfered += len;
2590                         offset += len;
2591                         remain -= len;
2592                 } while (remain);
2593
2594                 sg_miter->consumed = offset;
2595                 status = mci_readl(host, MINTSTS);
2596                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2597         } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
2598
2599         if (!remain) {
2600                 if (!sg_miter_next(sg_miter))
2601                         goto done;
2602                 sg_miter->consumed = 0;
2603         }
2604         sg_miter_stop(sg_miter);
2605         return;
2606
2607 done:
2608         sg_miter_stop(sg_miter);
2609         host->sg = NULL;
2610         smp_wmb(); /* drain writebuffer */
2611         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2612 }
2613
2614 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2615 {
2616         del_timer(&host->cto_timer);
2617
2618         if (!host->cmd_status)
2619                 host->cmd_status = status;
2620
2621         smp_wmb(); /* drain writebuffer */
2622
2623         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2624         tasklet_schedule(&host->tasklet);
2625 }
2626
2627 static void dw_mci_handle_cd(struct dw_mci *host)
2628 {
2629         struct dw_mci_slot *slot = host->slot;
2630
2631         if (slot->mmc->ops->card_event)
2632                 slot->mmc->ops->card_event(slot->mmc);
2633         mmc_detect_change(slot->mmc,
2634                 msecs_to_jiffies(host->pdata->detect_delay_ms));
2635 }
2636
2637 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2638 {
2639         struct dw_mci *host = dev_id;
2640         u32 pending;
2641         struct dw_mci_slot *slot = host->slot;
2642         unsigned long irqflags;
2643
2644         pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2645
2646         if (pending) {
2647                 /* Check volt switch first, since it can look like an error */
2648                 if ((host->state == STATE_SENDING_CMD11) &&
2649                     (pending & SDMMC_INT_VOLT_SWITCH)) {
2650                         mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2651                         pending &= ~SDMMC_INT_VOLT_SWITCH;
2652
2653                         /*
2654                          * Hold the lock; we know cmd11_timer can't be kicked
2655                          * off after the lock is released, so safe to delete.
2656                          */
2657                         spin_lock_irqsave(&host->irq_lock, irqflags);
2658                         dw_mci_cmd_interrupt(host, pending);
2659                         spin_unlock_irqrestore(&host->irq_lock, irqflags);
2660
2661                         del_timer(&host->cmd11_timer);
2662                 }
2663
2664                 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2665                         spin_lock_irqsave(&host->irq_lock, irqflags);
2666
2667                         del_timer(&host->cto_timer);
2668                         mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2669                         host->cmd_status = pending;
2670                         smp_wmb(); /* drain writebuffer */
2671                         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2672
2673                         spin_unlock_irqrestore(&host->irq_lock, irqflags);
2674                 }
2675
2676                 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2677                         /* if there is an error report DATA_ERROR */
2678                         mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2679                         host->data_status = pending;
2680                         smp_wmb(); /* drain writebuffer */
2681                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
2682                         tasklet_schedule(&host->tasklet);
2683                 }
2684
2685                 if (pending & SDMMC_INT_DATA_OVER) {
2686                         spin_lock_irqsave(&host->irq_lock, irqflags);
2687
2688                         del_timer(&host->dto_timer);
2689
2690                         mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2691                         if (!host->data_status)
2692                                 host->data_status = pending;
2693                         smp_wmb(); /* drain writebuffer */
2694                         if (host->dir_status == DW_MCI_RECV_STATUS) {
2695                                 if (host->sg != NULL)
2696                                         dw_mci_read_data_pio(host, true);
2697                         }
2698                         set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2699                         tasklet_schedule(&host->tasklet);
2700
2701                         spin_unlock_irqrestore(&host->irq_lock, irqflags);
2702                 }
2703
2704                 if (pending & SDMMC_INT_RXDR) {
2705                         mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2706                         if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2707                                 dw_mci_read_data_pio(host, false);
2708                 }
2709
2710                 if (pending & SDMMC_INT_TXDR) {
2711                         mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2712                         if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2713                                 dw_mci_write_data_pio(host);
2714                 }
2715
2716                 if (pending & SDMMC_INT_CMD_DONE) {
2717                         spin_lock_irqsave(&host->irq_lock, irqflags);
2718
2719                         mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2720                         dw_mci_cmd_interrupt(host, pending);
2721
2722                         spin_unlock_irqrestore(&host->irq_lock, irqflags);
2723                 }
2724
2725                 if (pending & SDMMC_INT_CD) {
2726                         mci_writel(host, RINTSTS, SDMMC_INT_CD);
2727                         dw_mci_handle_cd(host);
2728                 }
2729
2730                 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
2731                         mci_writel(host, RINTSTS,
2732                                    SDMMC_INT_SDIO(slot->sdio_id));
2733                         __dw_mci_enable_sdio_irq(slot, 0);
2734                         sdio_signal_irq(slot->mmc);
2735                 }
2736
2737         }
2738
2739         if (host->use_dma != TRANS_MODE_IDMAC)
2740                 return IRQ_HANDLED;
2741
2742         /* Handle IDMA interrupts */
2743         if (host->dma_64bit_address == 1) {
2744                 pending = mci_readl(host, IDSTS64);
2745                 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2746                         mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2747                                                         SDMMC_IDMAC_INT_RI);
2748                         mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
2749                         if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2750                                 host->dma_ops->complete((void *)host);
2751                 }
2752         } else {
2753                 pending = mci_readl(host, IDSTS);
2754                 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2755                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2756                                                         SDMMC_IDMAC_INT_RI);
2757                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2758                         if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2759                                 host->dma_ops->complete((void *)host);
2760                 }
2761         }
2762
2763         return IRQ_HANDLED;
2764 }
2765
2766 static int dw_mci_init_slot_caps(struct dw_mci_slot *slot)
2767 {
2768         struct dw_mci *host = slot->host;
2769         const struct dw_mci_drv_data *drv_data = host->drv_data;
2770         struct mmc_host *mmc = slot->mmc;
2771         int ctrl_id;
2772
2773         if (host->pdata->caps)
2774                 mmc->caps = host->pdata->caps;
2775
2776         /*
2777          * Support MMC_CAP_ERASE by default.
2778          * It needs to use trim/discard/erase commands.
2779          */
2780         mmc->caps |= MMC_CAP_ERASE;
2781
2782         if (host->pdata->pm_caps)
2783                 mmc->pm_caps = host->pdata->pm_caps;
2784
2785         if (host->dev->of_node) {
2786                 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2787                 if (ctrl_id < 0)
2788                         ctrl_id = 0;
2789         } else {
2790                 ctrl_id = to_platform_device(host->dev)->id;
2791         }
2792
2793         if (drv_data && drv_data->caps) {
2794                 if (ctrl_id >= drv_data->num_caps) {
2795                         dev_err(host->dev, "invalid controller id %d\n",
2796                                 ctrl_id);
2797                         return -EINVAL;
2798                 }
2799                 mmc->caps |= drv_data->caps[ctrl_id];
2800         }
2801
2802         if (host->pdata->caps2)
2803                 mmc->caps2 = host->pdata->caps2;
2804
2805         mmc->f_min = DW_MCI_FREQ_MIN;
2806         if (!mmc->f_max)
2807                 mmc->f_max = DW_MCI_FREQ_MAX;
2808
2809         /* Process SDIO IRQs through the sdio_irq_work. */
2810         if (mmc->caps & MMC_CAP_SDIO_IRQ)
2811                 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
2812
2813         return 0;
2814 }
2815
2816 static int dw_mci_init_slot(struct dw_mci *host)
2817 {
2818         struct mmc_host *mmc;
2819         struct dw_mci_slot *slot;
2820         int ret;
2821
2822         mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
2823         if (!mmc)
2824                 return -ENOMEM;
2825
2826         slot = mmc_priv(mmc);
2827         slot->id = 0;
2828         slot->sdio_id = host->sdio_id0 + slot->id;
2829         slot->mmc = mmc;
2830         slot->host = host;
2831         host->slot = slot;
2832
2833         mmc->ops = &dw_mci_ops;
2834
2835         /*if there are external regulators, get them*/
2836         ret = mmc_regulator_get_supply(mmc);
2837         if (ret)
2838                 goto err_host_allocated;
2839
2840         if (!mmc->ocr_avail)
2841                 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2842
2843         ret = mmc_of_parse(mmc);
2844         if (ret)
2845                 goto err_host_allocated;
2846
2847         ret = dw_mci_init_slot_caps(slot);
2848         if (ret)
2849                 goto err_host_allocated;
2850
2851         /* Useful defaults if platform data is unset. */
2852         if (host->use_dma == TRANS_MODE_IDMAC) {
2853                 mmc->max_segs = host->ring_size;
2854                 mmc->max_blk_size = 65535;
2855                 mmc->max_seg_size = 0x1000;
2856                 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2857                 mmc->max_blk_count = mmc->max_req_size / 512;
2858         } else if (host->use_dma == TRANS_MODE_EDMAC) {
2859                 mmc->max_segs = 64;
2860                 mmc->max_blk_size = 65535;
2861                 mmc->max_blk_count = 65535;
2862                 mmc->max_req_size =
2863                                 mmc->max_blk_size * mmc->max_blk_count;
2864                 mmc->max_seg_size = mmc->max_req_size;
2865         } else {
2866                 /* TRANS_MODE_PIO */
2867                 mmc->max_segs = 64;
2868                 mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */
2869                 mmc->max_blk_count = 512;
2870                 mmc->max_req_size = mmc->max_blk_size *
2871                                     mmc->max_blk_count;
2872                 mmc->max_seg_size = mmc->max_req_size;
2873         }
2874
2875         dw_mci_get_cd(mmc);
2876
2877         ret = mmc_add_host(mmc);
2878         if (ret)
2879                 goto err_host_allocated;
2880
2881 #if defined(CONFIG_DEBUG_FS)
2882         dw_mci_init_debugfs(slot);
2883 #endif
2884
2885         return 0;
2886
2887 err_host_allocated:
2888         mmc_free_host(mmc);
2889         return ret;
2890 }
2891
2892 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot)
2893 {
2894         /* Debugfs stuff is cleaned up by mmc core */
2895         mmc_remove_host(slot->mmc);
2896         slot->host->slot = NULL;
2897         mmc_free_host(slot->mmc);
2898 }
2899
2900 static void dw_mci_init_dma(struct dw_mci *host)
2901 {
2902         int addr_config;
2903         struct device *dev = host->dev;
2904
2905         /*
2906         * Check tansfer mode from HCON[17:16]
2907         * Clear the ambiguous description of dw_mmc databook:
2908         * 2b'00: No DMA Interface -> Actually means using Internal DMA block
2909         * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block
2910         * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block
2911         * 2b'11: Non DW DMA Interface -> pio only
2912         * Compared to DesignWare DMA Interface, Generic DMA Interface has a
2913         * simpler request/acknowledge handshake mechanism and both of them
2914         * are regarded as external dma master for dw_mmc.
2915         */
2916         host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
2917         if (host->use_dma == DMA_INTERFACE_IDMA) {
2918                 host->use_dma = TRANS_MODE_IDMAC;
2919         } else if (host->use_dma == DMA_INTERFACE_DWDMA ||
2920                    host->use_dma == DMA_INTERFACE_GDMA) {
2921                 host->use_dma = TRANS_MODE_EDMAC;
2922         } else {
2923                 goto no_dma;
2924         }
2925
2926         /* Determine which DMA interface to use */
2927         if (host->use_dma == TRANS_MODE_IDMAC) {
2928                 /*
2929                 * Check ADDR_CONFIG bit in HCON to find
2930                 * IDMAC address bus width
2931                 */
2932                 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
2933
2934                 if (addr_config == 1) {
2935                         /* host supports IDMAC in 64-bit address mode */
2936                         host->dma_64bit_address = 1;
2937                         dev_info(host->dev,
2938                                  "IDMAC supports 64-bit address mode.\n");
2939                         if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
2940                                 dma_set_coherent_mask(host->dev,
2941                                                       DMA_BIT_MASK(64));
2942                 } else {
2943                         /* host supports IDMAC in 32-bit address mode */
2944                         host->dma_64bit_address = 0;
2945                         dev_info(host->dev,
2946                                  "IDMAC supports 32-bit address mode.\n");
2947                 }
2948
2949                 /* Alloc memory for sg translation */
2950                 host->sg_cpu = dmam_alloc_coherent(host->dev,
2951                                                    DESC_RING_BUF_SZ,
2952                                                    &host->sg_dma, GFP_KERNEL);
2953                 if (!host->sg_cpu) {
2954                         dev_err(host->dev,
2955                                 "%s: could not alloc DMA memory\n",
2956                                 __func__);
2957                         goto no_dma;
2958                 }
2959
2960                 host->dma_ops = &dw_mci_idmac_ops;
2961                 dev_info(host->dev, "Using internal DMA controller.\n");
2962         } else {
2963                 /* TRANS_MODE_EDMAC: check dma bindings again */
2964                 if ((device_property_read_string_array(dev, "dma-names",
2965                                                        NULL, 0) < 0) ||
2966                     !device_property_present(dev, "dmas")) {
2967                         goto no_dma;
2968                 }
2969                 host->dma_ops = &dw_mci_edmac_ops;
2970                 dev_info(host->dev, "Using external DMA controller.\n");
2971         }
2972
2973         if (host->dma_ops->init && host->dma_ops->start &&
2974             host->dma_ops->stop && host->dma_ops->cleanup) {
2975                 if (host->dma_ops->init(host)) {
2976                         dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n",
2977                                 __func__);
2978                         goto no_dma;
2979                 }
2980         } else {
2981                 dev_err(host->dev, "DMA initialization not found.\n");
2982                 goto no_dma;
2983         }
2984
2985         return;
2986
2987 no_dma:
2988         dev_info(host->dev, "Using PIO mode.\n");
2989         host->use_dma = TRANS_MODE_PIO;
2990 }
2991
2992 static void dw_mci_cmd11_timer(struct timer_list *t)
2993 {
2994         struct dw_mci *host = from_timer(host, t, cmd11_timer);
2995
2996         if (host->state != STATE_SENDING_CMD11) {
2997                 dev_warn(host->dev, "Unexpected CMD11 timeout\n");
2998                 return;
2999         }
3000
3001         host->cmd_status = SDMMC_INT_RTO;
3002         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
3003         tasklet_schedule(&host->tasklet);
3004 }
3005
3006 static void dw_mci_cto_timer(struct timer_list *t)
3007 {
3008         struct dw_mci *host = from_timer(host, t, cto_timer);
3009         unsigned long irqflags;
3010         u32 pending;
3011
3012         spin_lock_irqsave(&host->irq_lock, irqflags);
3013
3014         /*
3015          * If somehow we have very bad interrupt latency it's remotely possible
3016          * that the timer could fire while the interrupt is still pending or
3017          * while the interrupt is midway through running.  Let's be paranoid
3018          * and detect those two cases.  Note that this is paranoia is somewhat
3019          * justified because in this function we don't actually cancel the
3020          * pending command in the controller--we just assume it will never come.
3021          */
3022         pending = mci_readl(host, MINTSTS); /* read-only mask reg */
3023         if (pending & (DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_CMD_DONE)) {
3024                 /* The interrupt should fire; no need to act but we can warn */
3025                 dev_warn(host->dev, "Unexpected interrupt latency\n");
3026                 goto exit;
3027         }
3028         if (test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) {
3029                 /* Presumably interrupt handler couldn't delete the timer */
3030                 dev_warn(host->dev, "CTO timeout when already completed\n");
3031                 goto exit;
3032         }
3033
3034         /*
3035          * Continued paranoia to make sure we're in the state we expect.
3036          * This paranoia isn't really justified but it seems good to be safe.
3037          */
3038         switch (host->state) {
3039         case STATE_SENDING_CMD11:
3040         case STATE_SENDING_CMD:
3041         case STATE_SENDING_STOP:
3042                 /*
3043                  * If CMD_DONE interrupt does NOT come in sending command
3044                  * state, we should notify the driver to terminate current
3045                  * transfer and report a command timeout to the core.
3046                  */
3047                 host->cmd_status = SDMMC_INT_RTO;
3048                 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
3049                 tasklet_schedule(&host->tasklet);
3050                 break;
3051         default:
3052                 dev_warn(host->dev, "Unexpected command timeout, state %d\n",
3053                          host->state);
3054                 break;
3055         }
3056
3057 exit:
3058         spin_unlock_irqrestore(&host->irq_lock, irqflags);
3059 }
3060
3061 static void dw_mci_dto_timer(struct timer_list *t)
3062 {
3063         struct dw_mci *host = from_timer(host, t, dto_timer);
3064         unsigned long irqflags;
3065         u32 pending;
3066
3067         spin_lock_irqsave(&host->irq_lock, irqflags);
3068
3069         /*
3070          * The DTO timer is much longer than the CTO timer, so it's even less
3071          * likely that we'll these cases, but it pays to be paranoid.
3072          */
3073         pending = mci_readl(host, MINTSTS); /* read-only mask reg */
3074         if (pending & SDMMC_INT_DATA_OVER) {
3075                 /* The interrupt should fire; no need to act but we can warn */
3076                 dev_warn(host->dev, "Unexpected data interrupt latency\n");
3077                 goto exit;
3078         }
3079         if (test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) {
3080                 /* Presumably interrupt handler couldn't delete the timer */
3081                 dev_warn(host->dev, "DTO timeout when already completed\n");
3082                 goto exit;
3083         }
3084
3085         /*
3086          * Continued paranoia to make sure we're in the state we expect.
3087          * This paranoia isn't really justified but it seems good to be safe.
3088          */
3089         switch (host->state) {
3090         case STATE_SENDING_DATA:
3091         case STATE_DATA_BUSY:
3092                 /*
3093                  * If DTO interrupt does NOT come in sending data state,
3094                  * we should notify the driver to terminate current transfer
3095                  * and report a data timeout to the core.
3096                  */
3097                 host->data_status = SDMMC_INT_DRTO;
3098                 set_bit(EVENT_DATA_ERROR, &host->pending_events);
3099                 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
3100                 tasklet_schedule(&host->tasklet);
3101                 break;
3102         default:
3103                 dev_warn(host->dev, "Unexpected data timeout, state %d\n",
3104                          host->state);
3105                 break;
3106         }
3107
3108 exit:
3109         spin_unlock_irqrestore(&host->irq_lock, irqflags);
3110 }
3111
3112 #ifdef CONFIG_OF
3113 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3114 {
3115         struct dw_mci_board *pdata;
3116         struct device *dev = host->dev;
3117         const struct dw_mci_drv_data *drv_data = host->drv_data;
3118         int ret;
3119         u32 clock_frequency;
3120
3121         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3122         if (!pdata)
3123                 return ERR_PTR(-ENOMEM);
3124
3125         /* find reset controller when exist */
3126         pdata->rstc = devm_reset_control_get_optional_exclusive(dev, "reset");
3127         if (IS_ERR(pdata->rstc)) {
3128                 if (PTR_ERR(pdata->rstc) == -EPROBE_DEFER)
3129                         return ERR_PTR(-EPROBE_DEFER);
3130         }
3131
3132         if (device_property_read_u32(dev, "fifo-depth", &pdata->fifo_depth))
3133                 dev_info(dev,
3134                          "fifo-depth property not found, using value of FIFOTH register as default\n");
3135
3136         device_property_read_u32(dev, "card-detect-delay",
3137                                  &pdata->detect_delay_ms);
3138
3139         device_property_read_u32(dev, "data-addr", &host->data_addr_override);
3140
3141         if (device_property_present(dev, "fifo-watermark-aligned"))
3142                 host->wm_aligned = true;
3143
3144         if (!device_property_read_u32(dev, "clock-frequency", &clock_frequency))
3145                 pdata->bus_hz = clock_frequency;
3146
3147         if (drv_data && drv_data->parse_dt) {
3148                 ret = drv_data->parse_dt(host);
3149                 if (ret)
3150                         return ERR_PTR(ret);
3151         }
3152
3153         return pdata;
3154 }
3155
3156 #else /* CONFIG_OF */
3157 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3158 {
3159         return ERR_PTR(-EINVAL);
3160 }
3161 #endif /* CONFIG_OF */
3162
3163 static void dw_mci_enable_cd(struct dw_mci *host)
3164 {
3165         unsigned long irqflags;
3166         u32 temp;
3167
3168         /*
3169          * No need for CD if all slots have a non-error GPIO
3170          * as well as broken card detection is found.
3171          */
3172         if (host->slot->mmc->caps & MMC_CAP_NEEDS_POLL)
3173                 return;
3174
3175         if (mmc_gpio_get_cd(host->slot->mmc) < 0) {
3176                 spin_lock_irqsave(&host->irq_lock, irqflags);
3177                 temp = mci_readl(host, INTMASK);
3178                 temp  |= SDMMC_INT_CD;
3179                 mci_writel(host, INTMASK, temp);
3180                 spin_unlock_irqrestore(&host->irq_lock, irqflags);
3181         }
3182 }
3183
3184 int dw_mci_probe(struct dw_mci *host)
3185 {
3186         const struct dw_mci_drv_data *drv_data = host->drv_data;
3187         int width, i, ret = 0;
3188         u32 fifo_size;
3189
3190         if (!host->pdata) {
3191                 host->pdata = dw_mci_parse_dt(host);
3192                 if (PTR_ERR(host->pdata) == -EPROBE_DEFER) {
3193                         return -EPROBE_DEFER;
3194                 } else if (IS_ERR(host->pdata)) {
3195                         dev_err(host->dev, "platform data not available\n");
3196                         return -EINVAL;
3197                 }
3198         }
3199
3200         host->biu_clk = devm_clk_get(host->dev, "biu");
3201         if (IS_ERR(host->biu_clk)) {
3202                 dev_dbg(host->dev, "biu clock not available\n");
3203         } else {
3204                 ret = clk_prepare_enable(host->biu_clk);
3205                 if (ret) {
3206                         dev_err(host->dev, "failed to enable biu clock\n");
3207                         return ret;
3208                 }
3209         }
3210
3211         host->ciu_clk = devm_clk_get(host->dev, "ciu");
3212         if (IS_ERR(host->ciu_clk)) {
3213                 dev_dbg(host->dev, "ciu clock not available\n");
3214                 host->bus_hz = host->pdata->bus_hz;
3215         } else {
3216                 ret = clk_prepare_enable(host->ciu_clk);
3217                 if (ret) {
3218                         dev_err(host->dev, "failed to enable ciu clock\n");
3219                         goto err_clk_biu;
3220                 }
3221
3222                 if (host->pdata->bus_hz) {
3223                         ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
3224                         if (ret)
3225                                 dev_warn(host->dev,
3226                                          "Unable to set bus rate to %uHz\n",
3227                                          host->pdata->bus_hz);
3228                 }
3229                 host->bus_hz = clk_get_rate(host->ciu_clk);
3230         }
3231
3232         if (!host->bus_hz) {
3233                 dev_err(host->dev,
3234                         "Platform data must supply bus speed\n");
3235                 ret = -ENODEV;
3236                 goto err_clk_ciu;
3237         }
3238
3239         if (!IS_ERR(host->pdata->rstc)) {
3240                 reset_control_assert(host->pdata->rstc);
3241                 usleep_range(10, 50);
3242                 reset_control_deassert(host->pdata->rstc);
3243         }
3244
3245         if (drv_data && drv_data->init) {
3246                 ret = drv_data->init(host);
3247                 if (ret) {
3248                         dev_err(host->dev,
3249                                 "implementation specific init failed\n");
3250                         goto err_clk_ciu;
3251                 }
3252         }
3253
3254         timer_setup(&host->cmd11_timer, dw_mci_cmd11_timer, 0);
3255         timer_setup(&host->cto_timer, dw_mci_cto_timer, 0);
3256         timer_setup(&host->dto_timer, dw_mci_dto_timer, 0);
3257
3258         spin_lock_init(&host->lock);
3259         spin_lock_init(&host->irq_lock);
3260         INIT_LIST_HEAD(&host->queue);
3261
3262         /*
3263          * Get the host data width - this assumes that HCON has been set with
3264          * the correct values.
3265          */
3266         i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
3267         if (!i) {
3268                 host->push_data = dw_mci_push_data16;
3269                 host->pull_data = dw_mci_pull_data16;
3270                 width = 16;
3271                 host->data_shift = 1;
3272         } else if (i == 2) {
3273                 host->push_data = dw_mci_push_data64;
3274                 host->pull_data = dw_mci_pull_data64;
3275                 width = 64;
3276                 host->data_shift = 3;
3277         } else {
3278                 /* Check for a reserved value, and warn if it is */
3279                 WARN((i != 1),
3280                      "HCON reports a reserved host data width!\n"
3281                      "Defaulting to 32-bit access.\n");
3282                 host->push_data = dw_mci_push_data32;
3283                 host->pull_data = dw_mci_pull_data32;
3284                 width = 32;
3285                 host->data_shift = 2;
3286         }
3287
3288         /* Reset all blocks */
3289         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3290                 ret = -ENODEV;
3291                 goto err_clk_ciu;
3292         }
3293
3294         host->dma_ops = host->pdata->dma_ops;
3295         dw_mci_init_dma(host);
3296
3297         /* Clear the interrupts for the host controller */
3298         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3299         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3300
3301         /* Put in max timeout */
3302         mci_writel(host, TMOUT, 0xFFFFFFFF);
3303
3304         /*
3305          * FIFO threshold settings  RxMark  = fifo_size / 2 - 1,
3306          *                          Tx Mark = fifo_size / 2 DMA Size = 8
3307          */
3308         if (!host->pdata->fifo_depth) {
3309                 /*
3310                  * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
3311                  * have been overwritten by the bootloader, just like we're
3312                  * about to do, so if you know the value for your hardware, you
3313                  * should put it in the platform data.
3314                  */
3315                 fifo_size = mci_readl(host, FIFOTH);
3316                 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
3317         } else {
3318                 fifo_size = host->pdata->fifo_depth;
3319         }
3320         host->fifo_depth = fifo_size;
3321         host->fifoth_val =
3322                 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
3323         mci_writel(host, FIFOTH, host->fifoth_val);
3324
3325         /* disable clock to CIU */
3326         mci_writel(host, CLKENA, 0);
3327         mci_writel(host, CLKSRC, 0);
3328
3329         /*
3330          * In 2.40a spec, Data offset is changed.
3331          * Need to check the version-id and set data-offset for DATA register.
3332          */
3333         host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3334         dev_info(host->dev, "Version ID is %04x\n", host->verid);
3335
3336         if (host->data_addr_override)
3337                 host->fifo_reg = host->regs + host->data_addr_override;
3338         else if (host->verid < DW_MMC_240A)
3339                 host->fifo_reg = host->regs + DATA_OFFSET;
3340         else
3341                 host->fifo_reg = host->regs + DATA_240A_OFFSET;
3342
3343         tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
3344         ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
3345                                host->irq_flags, "dw-mci", host);
3346         if (ret)
3347                 goto err_dmaunmap;
3348
3349         /*
3350          * Enable interrupts for command done, data over, data empty,
3351          * receive ready and error such as transmit, receive timeout, crc error
3352          */
3353         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3354                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3355                    DW_MCI_ERROR_FLAGS);
3356         /* Enable mci interrupt */
3357         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3358
3359         dev_info(host->dev,
3360                  "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
3361                  host->irq, width, fifo_size);
3362
3363         /* We need at least one slot to succeed */
3364         ret = dw_mci_init_slot(host);
3365         if (ret) {
3366                 dev_dbg(host->dev, "slot %d init failed\n", i);
3367                 goto err_dmaunmap;
3368         }
3369
3370         /* Now that slots are all setup, we can enable card detect */
3371         dw_mci_enable_cd(host);
3372
3373         return 0;
3374
3375 err_dmaunmap:
3376         if (host->use_dma && host->dma_ops->exit)
3377                 host->dma_ops->exit(host);
3378
3379         if (!IS_ERR(host->pdata->rstc))
3380                 reset_control_assert(host->pdata->rstc);
3381
3382 err_clk_ciu:
3383         clk_disable_unprepare(host->ciu_clk);
3384
3385 err_clk_biu:
3386         clk_disable_unprepare(host->biu_clk);
3387
3388         return ret;
3389 }
3390 EXPORT_SYMBOL(dw_mci_probe);
3391
3392 void dw_mci_remove(struct dw_mci *host)
3393 {
3394         dev_dbg(host->dev, "remove slot\n");
3395         if (host->slot)
3396                 dw_mci_cleanup_slot(host->slot);
3397
3398         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3399         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3400
3401         /* disable clock to CIU */
3402         mci_writel(host, CLKENA, 0);
3403         mci_writel(host, CLKSRC, 0);
3404
3405         if (host->use_dma && host->dma_ops->exit)
3406                 host->dma_ops->exit(host);
3407
3408         if (!IS_ERR(host->pdata->rstc))
3409                 reset_control_assert(host->pdata->rstc);
3410
3411         clk_disable_unprepare(host->ciu_clk);
3412         clk_disable_unprepare(host->biu_clk);
3413 }
3414 EXPORT_SYMBOL(dw_mci_remove);
3415
3416
3417
3418 #ifdef CONFIG_PM
3419 int dw_mci_runtime_suspend(struct device *dev)
3420 {
3421         struct dw_mci *host = dev_get_drvdata(dev);
3422
3423         if (host->use_dma && host->dma_ops->exit)
3424                 host->dma_ops->exit(host);
3425
3426         clk_disable_unprepare(host->ciu_clk);
3427
3428         if (host->slot &&
3429             (mmc_can_gpio_cd(host->slot->mmc) ||
3430              !mmc_card_is_removable(host->slot->mmc)))
3431                 clk_disable_unprepare(host->biu_clk);
3432
3433         return 0;
3434 }
3435 EXPORT_SYMBOL(dw_mci_runtime_suspend);
3436
3437 int dw_mci_runtime_resume(struct device *dev)
3438 {
3439         int ret = 0;
3440         struct dw_mci *host = dev_get_drvdata(dev);
3441
3442         if (host->slot &&
3443             (mmc_can_gpio_cd(host->slot->mmc) ||
3444              !mmc_card_is_removable(host->slot->mmc))) {
3445                 ret = clk_prepare_enable(host->biu_clk);
3446                 if (ret)
3447                         return ret;
3448         }
3449
3450         ret = clk_prepare_enable(host->ciu_clk);
3451         if (ret)
3452                 goto err;
3453
3454         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3455                 clk_disable_unprepare(host->ciu_clk);
3456                 ret = -ENODEV;
3457                 goto err;
3458         }
3459
3460         if (host->use_dma && host->dma_ops->init)
3461                 host->dma_ops->init(host);
3462
3463         /*
3464          * Restore the initial value at FIFOTH register
3465          * And Invalidate the prev_blksz with zero
3466          */
3467          mci_writel(host, FIFOTH, host->fifoth_val);
3468          host->prev_blksz = 0;
3469
3470         /* Put in max timeout */
3471         mci_writel(host, TMOUT, 0xFFFFFFFF);
3472
3473         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3474         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3475                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3476                    DW_MCI_ERROR_FLAGS);
3477         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3478
3479
3480         if (host->slot->mmc->pm_flags & MMC_PM_KEEP_POWER)
3481                 dw_mci_set_ios(host->slot->mmc, &host->slot->mmc->ios);
3482
3483         /* Force setup bus to guarantee available clock output */
3484         dw_mci_setup_bus(host->slot, true);
3485
3486         /* Now that slots are all setup, we can enable card detect */
3487         dw_mci_enable_cd(host);
3488
3489         return 0;
3490
3491 err:
3492         if (host->slot &&
3493             (mmc_can_gpio_cd(host->slot->mmc) ||
3494              !mmc_card_is_removable(host->slot->mmc)))
3495                 clk_disable_unprepare(host->biu_clk);
3496
3497         return ret;
3498 }
3499 EXPORT_SYMBOL(dw_mci_runtime_resume);
3500 #endif /* CONFIG_PM */
3501
3502 static int __init dw_mci_init(void)
3503 {
3504         pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
3505         return 0;
3506 }
3507
3508 static void __exit dw_mci_exit(void)
3509 {
3510 }
3511
3512 module_init(dw_mci_init);
3513 module_exit(dw_mci_exit);
3514
3515 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3516 MODULE_AUTHOR("NXP Semiconductor VietNam");
3517 MODULE_AUTHOR("Imagination Technologies Ltd");
3518 MODULE_LICENSE("GPL v2");