drivers/mmc/host/dw_mmc.c

   1 /*
   2  * Synopsys DesignWare Multimedia Card Interface driver
   3  *  (Based on NXP driver for lpc 31xx)
   4  *
   5  * Copyright (C) 2009 NXP Semiconductors
   6  * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/blkdev.h>
  15 #include <linux/clk.h>
  16 #include <linux/debugfs.h>
  17 #include <linux/device.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/err.h>
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/ioport.h>
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/seq_file.h>
  26 #include <linux/slab.h>
  27 #include <linux/stat.h>
  28 #include <linux/delay.h>
  29 #include <linux/irq.h>
  30 #include <linux/mmc/card.h>
  31 #include <linux/mmc/host.h>
  32 #include <linux/mmc/mmc.h>
  33 #include <linux/mmc/sd.h>
  34 #include <linux/mmc/sdio.h>
  35 #include <linux/mmc/dw_mmc.h>
  36 #include <linux/bitops.h>
  37 #include <linux/regulator/consumer.h>
  38 #include <linux/of.h>
  39 #include <linux/of_gpio.h>
  40 #include <linux/mmc/slot-gpio.h>
  41
  42 #include "dw_mmc.h"
  43
  44 /* Common flag combinations */
  45 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
  46                                  SDMMC_INT_HTO | SDMMC_INT_SBE  | \
  47                                  SDMMC_INT_EBE)
  48 #define DW_MCI_CMD_ERROR_FLAGS  (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
  49                                  SDMMC_INT_RESP_ERR)
  50 #define DW_MCI_ERROR_FLAGS      (DW_MCI_DATA_ERROR_FLAGS | \
  51                                  DW_MCI_CMD_ERROR_FLAGS  | SDMMC_INT_HLE)
  52 #define DW_MCI_SEND_STATUS      1
  53 #define DW_MCI_RECV_STATUS      2
  54 #define DW_MCI_DMA_THRESHOLD    16
  55
  56 #define DW_MCI_FREQ_MAX 200000000       /* unit: HZ */
  57 #define DW_MCI_FREQ_MIN 400000          /* unit: HZ */
  58
  59 #ifdef CONFIG_MMC_DW_IDMAC
  60 #define IDMAC_INT_CLR           (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
  61                                  SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
  62                                  SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
  63                                  SDMMC_IDMAC_INT_TI)
  64
  65 struct idmac_desc_64addr {
  66         u32             des0;   /* Control Descriptor */
  67
  68         u32             des1;   /* Reserved */
  69
  70         u32             des2;   /*Buffer sizes */
  71 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
  72         ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
  73          ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
  74
  75         u32             des3;   /* Reserved */
  76
  77         u32             des4;   /* Lower 32-bits of Buffer Address Pointer 1*/
  78         u32             des5;   /* Upper 32-bits of Buffer Address Pointer 1*/
  79
  80         u32             des6;   /* Lower 32-bits of Next Descriptor Address */
  81         u32             des7;   /* Upper 32-bits of Next Descriptor Address */
  82 };
  83
  84 struct idmac_desc {
  85         __le32          des0;   /* Control Descriptor */
  86 #define IDMAC_DES0_DIC  BIT(1)
  87 #define IDMAC_DES0_LD   BIT(2)
  88 #define IDMAC_DES0_FD   BIT(3)
  89 #define IDMAC_DES0_CH   BIT(4)
  90 #define IDMAC_DES0_ER   BIT(5)
  91 #define IDMAC_DES0_CES  BIT(30)
  92 #define IDMAC_DES0_OWN  BIT(31)
  93
  94         __le32          des1;   /* Buffer sizes */
  95 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
  96         ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
  97
  98         __le32          des2;   /* buffer 1 physical address */
  99
 100         __le32          des3;   /* buffer 2 physical address */
 101 };
 102 #endif /* CONFIG_MMC_DW_IDMAC */
 103
 104 static bool dw_mci_reset(struct dw_mci *host);
 105 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
 106 static int dw_mci_card_busy(struct mmc_host *mmc);
 107
 108 #if defined(CONFIG_DEBUG_FS)
 109 static int dw_mci_req_show(struct seq_file *s, void *v)
 110 {
 111         struct dw_mci_slot *slot = s->private;
 112         struct mmc_request *mrq;
 113         struct mmc_command *cmd;
 114         struct mmc_command *stop;
 115         struct mmc_data *data;
 116
 117         /* Make sure we get a consistent snapshot */
 118         spin_lock_bh(&slot->host->lock);
 119         mrq = slot->mrq;
 120
 121         if (mrq) {
 122                 cmd = mrq->cmd;
 123                 data = mrq->data;
 124                 stop = mrq->stop;
 125
 126                 if (cmd)
 127                         seq_printf(s,
 128                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 129                                    cmd->opcode, cmd->arg, cmd->flags,
 130                                    cmd->resp[0], cmd->resp[1], cmd->resp[2],
 131                                    cmd->resp[2], cmd->error);
 132                 if (data)
 133                         seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
 134                                    data->bytes_xfered, data->blocks,
 135                                    data->blksz, data->flags, data->error);
 136                 if (stop)
 137                         seq_printf(s,
 138                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 139                                    stop->opcode, stop->arg, stop->flags,
 140                                    stop->resp[0], stop->resp[1], stop->resp[2],
 141                                    stop->resp[2], stop->error);
 142         }
 143
 144         spin_unlock_bh(&slot->host->lock);
 145
 146         return 0;
 147 }
 148
 149 static int dw_mci_req_open(struct inode *inode, struct file *file)
 150 {
 151         return single_open(file, dw_mci_req_show, inode->i_private);
 152 }
 153
 154 static const struct file_operations dw_mci_req_fops = {
 155         .owner          = THIS_MODULE,
 156         .open           = dw_mci_req_open,
 157         .read           = seq_read,
 158         .llseek         = seq_lseek,
 159         .release        = single_release,
 160 };
 161
 162 static int dw_mci_regs_show(struct seq_file *s, void *v)
 163 {
 164         seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
 165         seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
 166         seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
 167         seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
 168         seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
 169         seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
 170
 171         return 0;
 172 }
 173
 174 static int dw_mci_regs_open(struct inode *inode, struct file *file)
 175 {
 176         return single_open(file, dw_mci_regs_show, inode->i_private);
 177 }
 178
 179 static const struct file_operations dw_mci_regs_fops = {
 180         .owner          = THIS_MODULE,
 181         .open           = dw_mci_regs_open,
 182         .read           = seq_read,
 183         .llseek         = seq_lseek,
 184         .release        = single_release,
 185 };
 186
 187 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
 188 {
 189         struct mmc_host *mmc = slot->mmc;
 190         struct dw_mci *host = slot->host;
 191         struct dentry *root;
 192         struct dentry *node;
 193
 194         root = mmc->debugfs_root;
 195         if (!root)
 196                 return;
 197
 198         node = debugfs_create_file("regs", S_IRUSR, root, host,
 199                                    &dw_mci_regs_fops);
 200         if (!node)
 201                 goto err;
 202
 203         node = debugfs_create_file("req", S_IRUSR, root, slot,
 204                                    &dw_mci_req_fops);
 205         if (!node)
 206                 goto err;
 207
 208         node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
 209         if (!node)
 210                 goto err;
 211
 212         node = debugfs_create_x32("pending_events", S_IRUSR, root,
 213                                   (u32 *)&host->pending_events);
 214         if (!node)
 215                 goto err;
 216
 217         node = debugfs_create_x32("completed_events", S_IRUSR, root,
 218                                   (u32 *)&host->completed_events);
 219         if (!node)
 220                 goto err;
 221
 222         return;
 223
 224 err:
 225         dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
 226 }
 227 #endif /* defined(CONFIG_DEBUG_FS) */
 228
 229 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg);
 230
 231 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
 232 {
 233         struct mmc_data *data;
 234         struct dw_mci_slot *slot = mmc_priv(mmc);
 235         struct dw_mci *host = slot->host;
 236         const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
 237         u32 cmdr;
 238         cmd->error = -EINPROGRESS;
 239
 240         cmdr = cmd->opcode;
 241
 242         if (cmd->opcode == MMC_STOP_TRANSMISSION ||
 243             cmd->opcode == MMC_GO_IDLE_STATE ||
 244             cmd->opcode == MMC_GO_INACTIVE_STATE ||
 245             (cmd->opcode == SD_IO_RW_DIRECT &&
 246              ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
 247                 cmdr |= SDMMC_CMD_STOP;
 248         else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
 249                 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
 250
 251         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
 252                 u32 clk_en_a;
 253
 254                 /* Special bit makes CMD11 not die */
 255                 cmdr |= SDMMC_CMD_VOLT_SWITCH;
 256
 257                 /* Change state to continue to handle CMD11 weirdness */
 258                 WARN_ON(slot->host->state != STATE_SENDING_CMD);
 259                 slot->host->state = STATE_SENDING_CMD11;
 260
 261                 /*
 262                  * We need to disable low power mode (automatic clock stop)
 263                  * while doing voltage switch so we don't confuse the card,
 264                  * since stopping the clock is a specific part of the UHS
 265                  * voltage change dance.
 266                  *
 267                  * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
 268                  * unconditionally turned back on in dw_mci_setup_bus() if it's
 269                  * ever called with a non-zero clock.  That shouldn't happen
 270                  * until the voltage change is all done.
 271                  */
 272                 clk_en_a = mci_readl(host, CLKENA);
 273                 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
 274                 mci_writel(host, CLKENA, clk_en_a);
 275                 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
 276                              SDMMC_CMD_PRV_DAT_WAIT, 0);
 277         }
 278
 279         if (cmd->flags & MMC_RSP_PRESENT) {
 280                 /* We expect a response, so set this bit */
 281                 cmdr |= SDMMC_CMD_RESP_EXP;
 282                 if (cmd->flags & MMC_RSP_136)
 283                         cmdr |= SDMMC_CMD_RESP_LONG;
 284         }
 285
 286         if (cmd->flags & MMC_RSP_CRC)
 287                 cmdr |= SDMMC_CMD_RESP_CRC;
 288
 289         data = cmd->data;
 290         if (data) {
 291                 cmdr |= SDMMC_CMD_DAT_EXP;
 292                 if (data->flags & MMC_DATA_STREAM)
 293                         cmdr |= SDMMC_CMD_STRM_MODE;
 294                 if (data->flags & MMC_DATA_WRITE)
 295                         cmdr |= SDMMC_CMD_DAT_WR;
 296         }
 297
 298         if (drv_data && drv_data->prepare_command)
 299                 drv_data->prepare_command(slot->host, &cmdr);
 300
 301         return cmdr;
 302 }
 303
 304 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
 305 {
 306         struct mmc_command *stop;
 307         u32 cmdr;
 308
 309         if (!cmd->data)
 310                 return 0;
 311
 312         stop = &host->stop_abort;
 313         cmdr = cmd->opcode;
 314         memset(stop, 0, sizeof(struct mmc_command));
 315
 316         if (cmdr == MMC_READ_SINGLE_BLOCK ||
 317             cmdr == MMC_READ_MULTIPLE_BLOCK ||
 318             cmdr == MMC_WRITE_BLOCK ||
 319             cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
 320             cmdr == MMC_SEND_TUNING_BLOCK ||
 321             cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
 322                 stop->opcode = MMC_STOP_TRANSMISSION;
 323                 stop->arg = 0;
 324                 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
 325         } else if (cmdr == SD_IO_RW_EXTENDED) {
 326                 stop->opcode = SD_IO_RW_DIRECT;
 327                 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
 328                              ((cmd->arg >> 28) & 0x7);
 329                 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
 330         } else {
 331                 return 0;
 332         }
 333
 334         cmdr = stop->opcode | SDMMC_CMD_STOP |
 335                 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
 336
 337         return cmdr;
 338 }
 339
 340 static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
 341 {
 342         unsigned long timeout = jiffies + msecs_to_jiffies(500);
 343
 344         /*
 345          * Databook says that before issuing a new data transfer command
 346          * we need to check to see if the card is busy.  Data transfer commands
 347          * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
 348          *
 349          * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
 350          * expected.
 351          */
 352         if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
 353             !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
 354                 while (mci_readl(host, STATUS) & SDMMC_STATUS_BUSY) {
 355                         if (time_after(jiffies, timeout)) {
 356                                 /* Command will fail; we'll pass error then */
 357                                 dev_err(host->dev, "Busy; trying anyway\n");
 358                                 break;
 359                         }
 360                         udelay(10);
 361                 }
 362         }
 363 }
 364
 365 static void dw_mci_start_command(struct dw_mci *host,
 366                                  struct mmc_command *cmd, u32 cmd_flags)
 367 {
 368         host->cmd = cmd;
 369         dev_vdbg(host->dev,
 370                  "start command: ARGR=0x%08x CMDR=0x%08x\n",
 371                  cmd->arg, cmd_flags);
 372
 373         mci_writel(host, CMDARG, cmd->arg);
 374         wmb();
 375         dw_mci_wait_while_busy(host, cmd_flags);
 376
 377         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
 378 }
 379
 380 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
 381 {
 382         struct mmc_command *stop = data->stop ? data->stop : &host->stop_abort;
 383         dw_mci_start_command(host, stop, host->stop_cmdr);
 384 }
 385
 386 /* DMA interface functions */
 387 static void dw_mci_stop_dma(struct dw_mci *host)
 388 {
 389         if (host->using_dma) {
 390                 host->dma_ops->stop(host);
 391                 host->dma_ops->cleanup(host);
 392         }
 393
 394         /* Data transfer was stopped by the interrupt handler */
 395         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 396 }
 397
 398 static int dw_mci_get_dma_dir(struct mmc_data *data)
 399 {
 400         if (data->flags & MMC_DATA_WRITE)
 401                 return DMA_TO_DEVICE;
 402         else
 403                 return DMA_FROM_DEVICE;
 404 }
 405
 406 #ifdef CONFIG_MMC_DW_IDMAC
 407 static void dw_mci_dma_cleanup(struct dw_mci *host)
 408 {
 409         struct mmc_data *data = host->data;
 410
 411         if (data)
 412                 if (!data->host_cookie)
 413                         dma_unmap_sg(host->dev,
 414                                      data->sg,
 415                                      data->sg_len,
 416                                      dw_mci_get_dma_dir(data));
 417 }
 418
 419 static void dw_mci_idmac_reset(struct dw_mci *host)
 420 {
 421         u32 bmod = mci_readl(host, BMOD);
 422         /* Software reset of DMA */
 423         bmod |= SDMMC_IDMAC_SWRESET;
 424         mci_writel(host, BMOD, bmod);
 425 }
 426
 427 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
 428 {
 429         u32 temp;
 430
 431         /* Disable and reset the IDMAC interface */
 432         temp = mci_readl(host, CTRL);
 433         temp &= ~SDMMC_CTRL_USE_IDMAC;
 434         temp |= SDMMC_CTRL_DMA_RESET;
 435         mci_writel(host, CTRL, temp);
 436
 437         /* Stop the IDMAC running */
 438         temp = mci_readl(host, BMOD);
 439         temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
 440         temp |= SDMMC_IDMAC_SWRESET;
 441         mci_writel(host, BMOD, temp);
 442 }
 443
 444 static void dw_mci_idmac_complete_dma(struct dw_mci *host)
 445 {
 446         struct mmc_data *data = host->data;
 447
 448         dev_vdbg(host->dev, "DMA complete\n");
 449
 450         host->dma_ops->cleanup(host);
 451
 452         /*
 453          * If the card was removed, data will be NULL. No point in trying to
 454          * send the stop command or waiting for NBUSY in this case.
 455          */
 456         if (data) {
 457                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 458                 tasklet_schedule(&host->tasklet);
 459         }
 460 }
 461
 462 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
 463                                     unsigned int sg_len)
 464 {
 465         int i;
 466         if (host->dma_64bit_address == 1) {
 467                 struct idmac_desc_64addr *desc = host->sg_cpu;
 468
 469                 for (i = 0; i < sg_len; i++, desc++) {
 470                         unsigned int length = sg_dma_len(&data->sg[i]);
 471                         u64 mem_addr = sg_dma_address(&data->sg[i]);
 472
 473                         /*
 474                          * Set the OWN bit and disable interrupts for this
 475                          * descriptor
 476                          */
 477                         desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
 478                                                 IDMAC_DES0_CH;
 479                         /* Buffer length */
 480                         IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, length);
 481
 482                         /* Physical address to DMA to/from */
 483                         desc->des4 = mem_addr & 0xffffffff;
 484                         desc->des5 = mem_addr >> 32;
 485                 }
 486
 487                 /* Set first descriptor */
 488                 desc = host->sg_cpu;
 489                 desc->des0 |= IDMAC_DES0_FD;
 490
 491                 /* Set last descriptor */
 492                 desc = host->sg_cpu + (i - 1) *
 493                                 sizeof(struct idmac_desc_64addr);
 494                 desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
 495                 desc->des0 |= IDMAC_DES0_LD;
 496
 497         } else {
 498                 struct idmac_desc *desc = host->sg_cpu;
 499
 500                 for (i = 0; i < sg_len; i++, desc++) {
 501                         unsigned int length = sg_dma_len(&data->sg[i]);
 502                         u32 mem_addr = sg_dma_address(&data->sg[i]);
 503
 504                         /*
 505                          * Set the OWN bit and disable interrupts for this
 506                          * descriptor
 507                          */
 508                         desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
 509                                         IDMAC_DES0_DIC | IDMAC_DES0_CH);
 510                         /* Buffer length */
 511                         IDMAC_SET_BUFFER1_SIZE(desc, length);
 512
 513                         /* Physical address to DMA to/from */
 514                         desc->des2 = cpu_to_le32(mem_addr);
 515                 }
 516
 517                 /* Set first descriptor */
 518                 desc = host->sg_cpu;
 519                 desc->des0 |= cpu_to_le32(IDMAC_DES0_FD);
 520
 521                 /* Set last descriptor */
 522                 desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
 523                 desc->des0 &= cpu_to_le32(~(IDMAC_DES0_CH | IDMAC_DES0_DIC));
 524                 desc->des0 |= cpu_to_le32(IDMAC_DES0_LD);
 525         }
 526
 527         wmb();
 528 }
 529
 530 static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
 531 {
 532         u32 temp;
 533
 534         dw_mci_translate_sglist(host, host->data, sg_len);
 535
 536         /* Make sure to reset DMA in case we did PIO before this */
 537         dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
 538         dw_mci_idmac_reset(host);
 539
 540         /* Select IDMAC interface */
 541         temp = mci_readl(host, CTRL);
 542         temp |= SDMMC_CTRL_USE_IDMAC;
 543         mci_writel(host, CTRL, temp);
 544
 545         wmb();
 546
 547         /* Enable the IDMAC */
 548         temp = mci_readl(host, BMOD);
 549         temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
 550         mci_writel(host, BMOD, temp);
 551
 552         /* Start it running */
 553         mci_writel(host, PLDMND, 1);
 554 }
 555
 556 static int dw_mci_idmac_init(struct dw_mci *host)
 557 {
 558         int i;
 559
 560         if (host->dma_64bit_address == 1) {
 561                 struct idmac_desc_64addr *p;
 562                 /* Number of descriptors in the ring buffer */
 563                 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc_64addr);
 564
 565                 /* Forward link the descriptor list */
 566                 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
 567                                                                 i++, p++) {
 568                         p->des6 = (host->sg_dma +
 569                                         (sizeof(struct idmac_desc_64addr) *
 570                                                         (i + 1))) & 0xffffffff;
 571
 572                         p->des7 = (u64)(host->sg_dma +
 573                                         (sizeof(struct idmac_desc_64addr) *
 574                                                         (i + 1))) >> 32;
 575                         /* Initialize reserved and buffer size fields to "0" */
 576                         p->des1 = 0;
 577                         p->des2 = 0;
 578                         p->des3 = 0;
 579                 }
 580
 581                 /* Set the last descriptor as the end-of-ring descriptor */
 582                 p->des6 = host->sg_dma & 0xffffffff;
 583                 p->des7 = (u64)host->sg_dma >> 32;
 584                 p->des0 = IDMAC_DES0_ER;
 585
 586         } else {
 587                 struct idmac_desc *p;
 588                 /* Number of descriptors in the ring buffer */
 589                 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
 590
 591                 /* Forward link the descriptor list */
 592                 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++)
 593                         p->des3 = cpu_to_le32(host->sg_dma +
 594                                         (sizeof(struct idmac_desc) * (i + 1)));
 595
 596                 /* Set the last descriptor as the end-of-ring descriptor */
 597                 p->des3 = cpu_to_le32(host->sg_dma);
 598                 p->des0 = cpu_to_le32(IDMAC_DES0_ER);
 599         }
 600
 601         dw_mci_idmac_reset(host);
 602
 603         if (host->dma_64bit_address == 1) {
 604                 /* Mask out interrupts - get Tx & Rx complete only */
 605                 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
 606                 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
 607                                 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
 608
 609                 /* Set the descriptor base address */
 610                 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
 611                 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
 612
 613         } else {
 614                 /* Mask out interrupts - get Tx & Rx complete only */
 615                 mci_writel(host, IDSTS, IDMAC_INT_CLR);
 616                 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
 617                                 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
 618
 619                 /* Set the descriptor base address */
 620                 mci_writel(host, DBADDR, host->sg_dma);
 621         }
 622
 623         return 0;
 624 }
 625
 626 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
 627         .init = dw_mci_idmac_init,
 628         .start = dw_mci_idmac_start_dma,
 629         .stop = dw_mci_idmac_stop_dma,
 630         .complete = dw_mci_idmac_complete_dma,
 631         .cleanup = dw_mci_dma_cleanup,
 632 };
 633 #endif /* CONFIG_MMC_DW_IDMAC */
 634
 635 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
 636                                    struct mmc_data *data,
 637                                    bool next)
 638 {
 639         struct scatterlist *sg;
 640         unsigned int i, sg_len;
 641
 642         if (!next && data->host_cookie)
 643                 return data->host_cookie;
 644
 645         /*
 646          * We don't do DMA on "complex" transfers, i.e. with
 647          * non-word-aligned buffers or lengths. Also, we don't bother
 648          * with all the DMA setup overhead for short transfers.
 649          */
 650         if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
 651                 return -EINVAL;
 652
 653         if (data->blksz & 3)
 654                 return -EINVAL;
 655
 656         for_each_sg(data->sg, sg, data->sg_len, i) {
 657                 if (sg->offset & 3 || sg->length & 3)
 658                         return -EINVAL;
 659         }
 660
 661         sg_len = dma_map_sg(host->dev,
 662                             data->sg,
 663                             data->sg_len,
 664                             dw_mci_get_dma_dir(data));
 665         if (sg_len == 0)
 666                 return -EINVAL;
 667
 668         if (next)
 669                 data->host_cookie = sg_len;
 670
 671         return sg_len;
 672 }
 673
 674 static void dw_mci_pre_req(struct mmc_host *mmc,
 675                            struct mmc_request *mrq,
 676                            bool is_first_req)
 677 {
 678         struct dw_mci_slot *slot = mmc_priv(mmc);
 679         struct mmc_data *data = mrq->data;
 680
 681         if (!slot->host->use_dma || !data)
 682                 return;
 683
 684         if (data->host_cookie) {
 685                 data->host_cookie = 0;
 686                 return;
 687         }
 688
 689         if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
 690                 data->host_cookie = 0;
 691 }
 692
 693 static void dw_mci_post_req(struct mmc_host *mmc,
 694                             struct mmc_request *mrq,
 695                             int err)
 696 {
 697         struct dw_mci_slot *slot = mmc_priv(mmc);
 698         struct mmc_data *data = mrq->data;
 699
 700         if (!slot->host->use_dma || !data)
 701                 return;
 702
 703         if (data->host_cookie)
 704                 dma_unmap_sg(slot->host->dev,
 705                              data->sg,
 706                              data->sg_len,
 707                              dw_mci_get_dma_dir(data));
 708         data->host_cookie = 0;
 709 }
 710
 711 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
 712 {
 713 #ifdef CONFIG_MMC_DW_IDMAC
 714         unsigned int blksz = data->blksz;
 715         const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
 716         u32 fifo_width = 1 << host->data_shift;
 717         u32 blksz_depth = blksz / fifo_width, fifoth_val;
 718         u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
 719         int idx = (sizeof(mszs) / sizeof(mszs[0])) - 1;
 720
 721         tx_wmark = (host->fifo_depth) / 2;
 722         tx_wmark_invers = host->fifo_depth - tx_wmark;
 723
 724         /*
 725          * MSIZE is '1',
 726          * if blksz is not a multiple of the FIFO width
 727          */
 728         if (blksz % fifo_width) {
 729                 msize = 0;
 730                 rx_wmark = 1;
 731                 goto done;
 732         }
 733
 734         do {
 735                 if (!((blksz_depth % mszs[idx]) ||
 736                      (tx_wmark_invers % mszs[idx]))) {
 737                         msize = idx;
 738                         rx_wmark = mszs[idx] - 1;
 739                         break;
 740                 }
 741         } while (--idx > 0);
 742         /*
 743          * If idx is '0', it won't be tried
 744          * Thus, initial values are uesed
 745          */
 746 done:
 747         fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
 748         mci_writel(host, FIFOTH, fifoth_val);
 749 #endif
 750 }
 751
 752 static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data)
 753 {
 754         unsigned int blksz = data->blksz;
 755         u32 blksz_depth, fifo_depth;
 756         u16 thld_size;
 757
 758         WARN_ON(!(data->flags & MMC_DATA_READ));
 759
 760         /*
 761          * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
 762          * in the FIFO region, so we really shouldn't access it).
 763          */
 764         if (host->verid < DW_MMC_240A)
 765                 return;
 766
 767         if (host->timing != MMC_TIMING_MMC_HS200 &&
 768             host->timing != MMC_TIMING_MMC_HS400 &&
 769             host->timing != MMC_TIMING_UHS_SDR104)
 770                 goto disable;
 771
 772         blksz_depth = blksz / (1 << host->data_shift);
 773         fifo_depth = host->fifo_depth;
 774
 775         if (blksz_depth > fifo_depth)
 776                 goto disable;
 777
 778         /*
 779          * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
 780          * If (blksz_depth) <  (fifo_depth >> 1), should be thld_size = blksz
 781          * Currently just choose blksz.
 782          */
 783         thld_size = blksz;
 784         mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1));
 785         return;
 786
 787 disable:
 788         mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0));
 789 }
 790
 791 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
 792 {
 793         unsigned long irqflags;
 794         int sg_len;
 795         u32 temp;
 796
 797         host->using_dma = 0;
 798
 799         /* If we don't have a channel, we can't do DMA */
 800         if (!host->use_dma)
 801                 return -ENODEV;
 802
 803         sg_len = dw_mci_pre_dma_transfer(host, data, 0);
 804         if (sg_len < 0) {
 805                 host->dma_ops->stop(host);
 806                 return sg_len;
 807         }
 808
 809         host->using_dma = 1;
 810
 811         dev_vdbg(host->dev,
 812                  "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
 813                  (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
 814                  sg_len);
 815
 816         /*
 817          * Decide the MSIZE and RX/TX Watermark.
 818          * If current block size is same with previous size,
 819          * no need to update fifoth.
 820          */
 821         if (host->prev_blksz != data->blksz)
 822                 dw_mci_adjust_fifoth(host, data);
 823
 824         /* Enable the DMA interface */
 825         temp = mci_readl(host, CTRL);
 826         temp |= SDMMC_CTRL_DMA_ENABLE;
 827         mci_writel(host, CTRL, temp);
 828
 829         /* Disable RX/TX IRQs, let DMA handle it */
 830         spin_lock_irqsave(&host->irq_lock, irqflags);
 831         temp = mci_readl(host, INTMASK);
 832         temp  &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
 833         mci_writel(host, INTMASK, temp);
 834         spin_unlock_irqrestore(&host->irq_lock, irqflags);
 835
 836         host->dma_ops->start(host, sg_len);
 837
 838         return 0;
 839 }
 840
 841 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
 842 {
 843         unsigned long irqflags;
 844         u32 temp;
 845
 846         data->error = -EINPROGRESS;
 847
 848         WARN_ON(host->data);
 849         host->sg = NULL;
 850         host->data = data;
 851
 852         if (data->flags & MMC_DATA_READ) {
 853                 host->dir_status = DW_MCI_RECV_STATUS;
 854                 dw_mci_ctrl_rd_thld(host, data);
 855         } else {
 856                 host->dir_status = DW_MCI_SEND_STATUS;
 857         }
 858
 859         if (dw_mci_submit_data_dma(host, data)) {
 860                 int flags = SG_MITER_ATOMIC;
 861                 if (host->data->flags & MMC_DATA_READ)
 862                         flags |= SG_MITER_TO_SG;
 863                 else
 864                         flags |= SG_MITER_FROM_SG;
 865
 866                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 867                 host->sg = data->sg;
 868                 host->part_buf_start = 0;
 869                 host->part_buf_count = 0;
 870
 871                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
 872
 873                 spin_lock_irqsave(&host->irq_lock, irqflags);
 874                 temp = mci_readl(host, INTMASK);
 875                 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
 876                 mci_writel(host, INTMASK, temp);
 877                 spin_unlock_irqrestore(&host->irq_lock, irqflags);
 878
 879                 temp = mci_readl(host, CTRL);
 880                 temp &= ~SDMMC_CTRL_DMA_ENABLE;
 881                 mci_writel(host, CTRL, temp);
 882
 883                 /*
 884                  * Use the initial fifoth_val for PIO mode.
 885                  * If next issued data may be transfered by DMA mode,
 886                  * prev_blksz should be invalidated.
 887                  */
 888                 mci_writel(host, FIFOTH, host->fifoth_val);
 889                 host->prev_blksz = 0;
 890         } else {
 891                 /*
 892                  * Keep the current block size.
 893                  * It will be used to decide whether to update
 894                  * fifoth register next time.
 895                  */
 896                 host->prev_blksz = data->blksz;
 897         }
 898 }
 899
 900 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
 901 {
 902         struct dw_mci *host = slot->host;
 903         unsigned long timeout = jiffies + msecs_to_jiffies(500);
 904         unsigned int cmd_status = 0;
 905
 906         mci_writel(host, CMDARG, arg);
 907         wmb();
 908         dw_mci_wait_while_busy(host, cmd);
 909         mci_writel(host, CMD, SDMMC_CMD_START | cmd);
 910
 911         while (time_before(jiffies, timeout)) {
 912                 cmd_status = mci_readl(host, CMD);
 913                 if (!(cmd_status & SDMMC_CMD_START))
 914                         return;
 915         }
 916         dev_err(&slot->mmc->class_dev,
 917                 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
 918                 cmd, arg, cmd_status);
 919 }
 920
 921 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
 922 {
 923         struct dw_mci *host = slot->host;
 924         unsigned int clock = slot->clock;
 925         u32 div;
 926         u32 clk_en_a;
 927         u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
 928
 929         /* We must continue to set bit 28 in CMD until the change is complete */
 930         if (host->state == STATE_WAITING_CMD11_DONE)
 931                 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
 932
 933         if (!clock) {
 934                 mci_writel(host, CLKENA, 0);
 935                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
 936         } else if (clock != host->current_speed || force_clkinit) {
 937                 div = host->bus_hz / clock;
 938                 if (host->bus_hz % clock && host->bus_hz > clock)
 939                         /*
 940                          * move the + 1 after the divide to prevent
 941                          * over-clocking the card.
 942                          */
 943                         div += 1;
 944
 945                 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
 946
 947                 if ((clock << div) != slot->__clk_old || force_clkinit)
 948                         dev_info(&slot->mmc->class_dev,
 949                                  "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
 950                                  slot->id, host->bus_hz, clock,
 951                                  div ? ((host->bus_hz / div) >> 1) :
 952                                  host->bus_hz, div);
 953
 954                 /* disable clock */
 955                 mci_writel(host, CLKENA, 0);
 956                 mci_writel(host, CLKSRC, 0);
 957
 958                 /* inform CIU */
 959                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
 960
 961                 /* set clock to desired speed */
 962                 mci_writel(host, CLKDIV, div);
 963
 964                 /* inform CIU */
 965                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
 966
 967                 /* enable clock; only low power if no SDIO */
 968                 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
 969                 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
 970                         clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
 971                 mci_writel(host, CLKENA, clk_en_a);
 972
 973                 /* inform CIU */
 974                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
 975
 976                 /* keep the clock with reflecting clock dividor */
 977                 slot->__clk_old = clock << div;
 978         }
 979
 980         host->current_speed = clock;
 981
 982         /* Set the current slot bus width */
 983         mci_writel(host, CTYPE, (slot->ctype << slot->id));
 984 }
 985
 986 static void __dw_mci_start_request(struct dw_mci *host,
 987                                    struct dw_mci_slot *slot,
 988                                    struct mmc_command *cmd)
 989 {
 990         struct mmc_request *mrq;
 991         struct mmc_data *data;
 992         u32 cmdflags;
 993
 994         mrq = slot->mrq;
 995
 996         host->cur_slot = slot;
 997         host->mrq = mrq;
 998
 999         host->pending_events = 0;
1000         host->completed_events = 0;
1001         host->cmd_status = 0;
1002         host->data_status = 0;
1003         host->dir_status = 0;
1004
1005         data = cmd->data;
1006         if (data) {
1007                 mci_writel(host, TMOUT, 0xFFFFFFFF);
1008                 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1009                 mci_writel(host, BLKSIZ, data->blksz);
1010         }
1011
1012         cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1013
1014         /* this is the first command, send the initialization clock */
1015         if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1016                 cmdflags |= SDMMC_CMD_INIT;
1017
1018         if (data) {
1019                 dw_mci_submit_data(host, data);
1020                 wmb();
1021         }
1022
1023         dw_mci_start_command(host, cmd, cmdflags);
1024
1025         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
1026                 unsigned long irqflags;
1027
1028                 /*
1029                  * Databook says to fail after 2ms w/ no response, but evidence
1030                  * shows that sometimes the cmd11 interrupt takes over 130ms.
1031                  * We'll set to 500ms, plus an extra jiffy just in case jiffies
1032                  * is just about to roll over.
1033                  *
1034                  * We do this whole thing under spinlock and only if the
1035                  * command hasn't already completed (indicating the the irq
1036                  * already ran so we don't want the timeout).
1037                  */
1038                 spin_lock_irqsave(&host->irq_lock, irqflags);
1039                 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1040                         mod_timer(&host->cmd11_timer,
1041                                 jiffies + msecs_to_jiffies(500) + 1);
1042                 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1043         }
1044
1045         if (mrq->stop)
1046                 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
1047         else
1048                 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
1049 }
1050
1051 static void dw_mci_start_request(struct dw_mci *host,
1052                                  struct dw_mci_slot *slot)
1053 {
1054         struct mmc_request *mrq = slot->mrq;
1055         struct mmc_command *cmd;
1056
1057         cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1058         __dw_mci_start_request(host, slot, cmd);
1059 }
1060
1061 /* must be called with host->lock held */
1062 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1063                                  struct mmc_request *mrq)
1064 {
1065         dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1066                  host->state);
1067
1068         slot->mrq = mrq;
1069
1070         if (host->state == STATE_WAITING_CMD11_DONE) {
1071                 dev_warn(&slot->mmc->class_dev,
1072                          "Voltage change didn't complete\n");
1073                 /*
1074                  * this case isn't expected to happen, so we can
1075                  * either crash here or just try to continue on
1076                  * in the closest possible state
1077                  */
1078                 host->state = STATE_IDLE;
1079         }
1080
1081         if (host->state == STATE_IDLE) {
1082                 host->state = STATE_SENDING_CMD;
1083                 dw_mci_start_request(host, slot);
1084         } else {
1085                 list_add_tail(&slot->queue_node, &host->queue);
1086         }
1087 }
1088
1089 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1090 {
1091         struct dw_mci_slot *slot = mmc_priv(mmc);
1092         struct dw_mci *host = slot->host;
1093
1094         WARN_ON(slot->mrq);
1095
1096         /*
1097          * The check for card presence and queueing of the request must be
1098          * atomic, otherwise the card could be removed in between and the
1099          * request wouldn't fail until another card was inserted.
1100          */
1101         spin_lock_bh(&host->lock);
1102
1103         if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
1104                 spin_unlock_bh(&host->lock);
1105                 mrq->cmd->error = -ENOMEDIUM;
1106                 mmc_request_done(mmc, mrq);
1107                 return;
1108         }
1109
1110         dw_mci_queue_request(host, slot, mrq);
1111
1112         spin_unlock_bh(&host->lock);
1113 }
1114
1115 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1116 {
1117         struct dw_mci_slot *slot = mmc_priv(mmc);
1118         const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1119         u32 regs;
1120         int ret;
1121
1122         switch (ios->bus_width) {
1123         case MMC_BUS_WIDTH_4:
1124                 slot->ctype = SDMMC_CTYPE_4BIT;
1125                 break;
1126         case MMC_BUS_WIDTH_8:
1127                 slot->ctype = SDMMC_CTYPE_8BIT;
1128                 break;
1129         default:
1130                 /* set default 1 bit mode */
1131                 slot->ctype = SDMMC_CTYPE_1BIT;
1132         }
1133
1134         regs = mci_readl(slot->host, UHS_REG);
1135
1136         /* DDR mode set */
1137         if (ios->timing == MMC_TIMING_MMC_DDR52 ||
1138             ios->timing == MMC_TIMING_MMC_HS400)
1139                 regs |= ((0x1 << slot->id) << 16);
1140         else
1141                 regs &= ~((0x1 << slot->id) << 16);
1142
1143         mci_writel(slot->host, UHS_REG, regs);
1144         slot->host->timing = ios->timing;
1145
1146         /*
1147          * Use mirror of ios->clock to prevent race with mmc
1148          * core ios update when finding the minimum.
1149          */
1150         slot->clock = ios->clock;
1151
1152         if (drv_data && drv_data->set_ios)
1153                 drv_data->set_ios(slot->host, ios);
1154
1155         switch (ios->power_mode) {
1156         case MMC_POWER_UP:
1157                 if (!IS_ERR(mmc->supply.vmmc)) {
1158                         ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1159                                         ios->vdd);
1160                         if (ret) {
1161                                 dev_err(slot->host->dev,
1162                                         "failed to enable vmmc regulator\n");
1163                                 /*return, if failed turn on vmmc*/
1164                                 return;
1165                         }
1166                 }
1167                 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1168                 regs = mci_readl(slot->host, PWREN);
1169                 regs |= (1 << slot->id);
1170                 mci_writel(slot->host, PWREN, regs);
1171                 break;
1172         case MMC_POWER_ON:
1173                 if (!slot->host->vqmmc_enabled) {
1174                         if (!IS_ERR(mmc->supply.vqmmc)) {
1175                                 ret = regulator_enable(mmc->supply.vqmmc);
1176                                 if (ret < 0)
1177                                         dev_err(slot->host->dev,
1178                                                 "failed to enable vqmmc\n");
1179                                 else
1180                                         slot->host->vqmmc_enabled = true;
1181
1182                         } else {
1183                                 /* Keep track so we don't reset again */
1184                                 slot->host->vqmmc_enabled = true;
1185                         }
1186
1187                         /* Reset our state machine after powering on */
1188                         dw_mci_ctrl_reset(slot->host,
1189                                           SDMMC_CTRL_ALL_RESET_FLAGS);
1190                 }
1191
1192                 /* Adjust clock / bus width after power is up */
1193                 dw_mci_setup_bus(slot, false);
1194
1195                 break;
1196         case MMC_POWER_OFF:
1197                 /* Turn clock off before power goes down */
1198                 dw_mci_setup_bus(slot, false);
1199
1200                 if (!IS_ERR(mmc->supply.vmmc))
1201                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1202
1203                 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
1204                         regulator_disable(mmc->supply.vqmmc);
1205                 slot->host->vqmmc_enabled = false;
1206
1207                 regs = mci_readl(slot->host, PWREN);
1208                 regs &= ~(1 << slot->id);
1209                 mci_writel(slot->host, PWREN, regs);
1210                 break;
1211         default:
1212                 break;
1213         }
1214
1215         if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1216                 slot->host->state = STATE_IDLE;
1217 }
1218
1219 static int dw_mci_card_busy(struct mmc_host *mmc)
1220 {
1221         struct dw_mci_slot *slot = mmc_priv(mmc);
1222         u32 status;
1223
1224         /*
1225          * Check the busy bit which is low when DAT[3:0]
1226          * (the data lines) are 0000
1227          */
1228         status = mci_readl(slot->host, STATUS);
1229
1230         return !!(status & SDMMC_STATUS_BUSY);
1231 }
1232
1233 static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1234 {
1235         struct dw_mci_slot *slot = mmc_priv(mmc);
1236         struct dw_mci *host = slot->host;
1237         u32 uhs;
1238         u32 v18 = SDMMC_UHS_18V << slot->id;
1239         int min_uv, max_uv;
1240         int ret;
1241
1242         /*
1243          * Program the voltage.  Note that some instances of dw_mmc may use
1244          * the UHS_REG for this.  For other instances (like exynos) the UHS_REG
1245          * does no harm but you need to set the regulator directly.  Try both.
1246          */
1247         uhs = mci_readl(host, UHS_REG);
1248         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1249                 min_uv = 2700000;
1250                 max_uv = 3600000;
1251                 uhs &= ~v18;
1252         } else {
1253                 min_uv = 1700000;
1254                 max_uv = 1950000;
1255                 uhs |= v18;
1256         }
1257         if (!IS_ERR(mmc->supply.vqmmc)) {
1258                 ret = regulator_set_voltage(mmc->supply.vqmmc, min_uv, max_uv);
1259
1260                 if (ret) {
1261                         dev_dbg(&mmc->class_dev,
1262                                          "Regulator set error %d: %d - %d\n",
1263                                          ret, min_uv, max_uv);
1264                         return ret;
1265                 }
1266         }
1267         mci_writel(host, UHS_REG, uhs);
1268
1269         return 0;
1270 }
1271
1272 static int dw_mci_get_ro(struct mmc_host *mmc)
1273 {
1274         int read_only;
1275         struct dw_mci_slot *slot = mmc_priv(mmc);
1276         int gpio_ro = mmc_gpio_get_ro(mmc);
1277
1278         /* Use platform get_ro function, else try on board write protect */
1279         if ((slot->quirks & DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT) ||
1280                         (slot->host->quirks & DW_MCI_QUIRK_NO_WRITE_PROTECT))
1281                 read_only = 0;
1282         else if (!IS_ERR_VALUE(gpio_ro))
1283                 read_only = gpio_ro;
1284         else
1285                 read_only =
1286                         mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1287
1288         dev_dbg(&mmc->class_dev, "card is %s\n",
1289                 read_only ? "read-only" : "read-write");
1290
1291         return read_only;
1292 }
1293
1294 static int dw_mci_get_cd(struct mmc_host *mmc)
1295 {
1296         int present;
1297         struct dw_mci_slot *slot = mmc_priv(mmc);
1298         struct dw_mci_board *brd = slot->host->pdata;
1299         struct dw_mci *host = slot->host;
1300         int gpio_cd = mmc_gpio_get_cd(mmc);
1301
1302         /* Use platform get_cd function, else try onboard card detect */
1303         if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
1304                 present = 1;
1305         else if (!IS_ERR_VALUE(gpio_cd))
1306                 present = gpio_cd;
1307         else
1308                 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
1309                         == 0 ? 1 : 0;
1310
1311         spin_lock_bh(&host->lock);
1312         if (present) {
1313                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1314                 dev_dbg(&mmc->class_dev, "card is present\n");
1315         } else {
1316                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1317                 dev_dbg(&mmc->class_dev, "card is not present\n");
1318         }
1319         spin_unlock_bh(&host->lock);
1320
1321         return present;
1322 }
1323
1324 static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
1325 {
1326         struct dw_mci_slot *slot = mmc_priv(mmc);
1327         struct dw_mci *host = slot->host;
1328
1329         /*
1330          * Low power mode will stop the card clock when idle.  According to the
1331          * description of the CLKENA register we should disable low power mode
1332          * for SDIO cards if we need SDIO interrupts to work.
1333          */
1334         if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1335                 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1336                 u32 clk_en_a_old;
1337                 u32 clk_en_a;
1338
1339                 clk_en_a_old = mci_readl(host, CLKENA);
1340
1341                 if (card->type == MMC_TYPE_SDIO ||
1342                     card->type == MMC_TYPE_SD_COMBO) {
1343                         set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1344                         clk_en_a = clk_en_a_old & ~clken_low_pwr;
1345                 } else {
1346                         clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1347                         clk_en_a = clk_en_a_old | clken_low_pwr;
1348                 }
1349
1350                 if (clk_en_a != clk_en_a_old) {
1351                         mci_writel(host, CLKENA, clk_en_a);
1352                         mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1353                                      SDMMC_CMD_PRV_DAT_WAIT, 0);
1354                 }
1355         }
1356 }
1357
1358 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1359 {
1360         struct dw_mci_slot *slot = mmc_priv(mmc);
1361         struct dw_mci *host = slot->host;
1362         unsigned long irqflags;
1363         u32 int_mask;
1364
1365         spin_lock_irqsave(&host->irq_lock, irqflags);
1366
1367         /* Enable/disable Slot Specific SDIO interrupt */
1368         int_mask = mci_readl(host, INTMASK);
1369         if (enb)
1370                 int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
1371         else
1372                 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
1373         mci_writel(host, INTMASK, int_mask);
1374
1375         spin_unlock_irqrestore(&host->irq_lock, irqflags);
1376 }
1377
1378 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1379 {
1380         struct dw_mci_slot *slot = mmc_priv(mmc);
1381         struct dw_mci *host = slot->host;
1382         const struct dw_mci_drv_data *drv_data = host->drv_data;
1383         int err = -ENOSYS;
1384
1385         if (drv_data && drv_data->execute_tuning)
1386                 err = drv_data->execute_tuning(slot);
1387         return err;
1388 }
1389
1390 static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1391 {
1392         struct dw_mci_slot *slot = mmc_priv(mmc);
1393         struct dw_mci *host = slot->host;
1394         const struct dw_mci_drv_data *drv_data = host->drv_data;
1395
1396         if (drv_data && drv_data->prepare_hs400_tuning)
1397                 return drv_data->prepare_hs400_tuning(host, ios);
1398
1399         return 0;
1400 }
1401
1402 static const struct mmc_host_ops dw_mci_ops = {
1403         .request                = dw_mci_request,
1404         .pre_req                = dw_mci_pre_req,
1405         .post_req               = dw_mci_post_req,
1406         .set_ios                = dw_mci_set_ios,
1407         .get_ro                 = dw_mci_get_ro,
1408         .get_cd                 = dw_mci_get_cd,
1409         .enable_sdio_irq        = dw_mci_enable_sdio_irq,
1410         .execute_tuning         = dw_mci_execute_tuning,
1411         .card_busy              = dw_mci_card_busy,
1412         .start_signal_voltage_switch = dw_mci_switch_voltage,
1413         .init_card              = dw_mci_init_card,
1414         .prepare_hs400_tuning   = dw_mci_prepare_hs400_tuning,
1415 };
1416
1417 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1418         __releases(&host->lock)
1419         __acquires(&host->lock)
1420 {
1421         struct dw_mci_slot *slot;
1422         struct mmc_host *prev_mmc = host->cur_slot->mmc;
1423
1424         WARN_ON(host->cmd || host->data);
1425
1426         host->cur_slot->mrq = NULL;
1427         host->mrq = NULL;
1428         if (!list_empty(&host->queue)) {
1429                 slot = list_entry(host->queue.next,
1430                                   struct dw_mci_slot, queue_node);
1431                 list_del(&slot->queue_node);
1432                 dev_vdbg(host->dev, "list not empty: %s is next\n",
1433                          mmc_hostname(slot->mmc));
1434                 host->state = STATE_SENDING_CMD;
1435                 dw_mci_start_request(host, slot);
1436         } else {
1437                 dev_vdbg(host->dev, "list empty\n");
1438
1439                 if (host->state == STATE_SENDING_CMD11)
1440                         host->state = STATE_WAITING_CMD11_DONE;
1441                 else
1442                         host->state = STATE_IDLE;
1443         }
1444
1445         spin_unlock(&host->lock);
1446         mmc_request_done(prev_mmc, mrq);
1447         spin_lock(&host->lock);
1448 }
1449
1450 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
1451 {
1452         u32 status = host->cmd_status;
1453
1454         host->cmd_status = 0;
1455
1456         /* Read the response from the card (up to 16 bytes) */
1457         if (cmd->flags & MMC_RSP_PRESENT) {
1458                 if (cmd->flags & MMC_RSP_136) {
1459                         cmd->resp[3] = mci_readl(host, RESP0);
1460                         cmd->resp[2] = mci_readl(host, RESP1);
1461                         cmd->resp[1] = mci_readl(host, RESP2);
1462                         cmd->resp[0] = mci_readl(host, RESP3);
1463                 } else {
1464                         cmd->resp[0] = mci_readl(host, RESP0);
1465                         cmd->resp[1] = 0;
1466                         cmd->resp[2] = 0;
1467                         cmd->resp[3] = 0;
1468                 }
1469         }
1470
1471         if (status & SDMMC_INT_RTO)
1472                 cmd->error = -ETIMEDOUT;
1473         else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1474                 cmd->error = -EILSEQ;
1475         else if (status & SDMMC_INT_RESP_ERR)
1476                 cmd->error = -EIO;
1477         else
1478                 cmd->error = 0;
1479
1480         if (cmd->error) {
1481                 /* newer ip versions need a delay between retries */
1482                 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
1483                         mdelay(20);
1484         }
1485
1486         return cmd->error;
1487 }
1488
1489 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1490 {
1491         u32 status = host->data_status;
1492
1493         if (status & DW_MCI_DATA_ERROR_FLAGS) {
1494                 if (status & SDMMC_INT_DRTO) {
1495                         data->error = -ETIMEDOUT;
1496                 } else if (status & SDMMC_INT_DCRC) {
1497                         data->error = -EILSEQ;
1498                 } else if (status & SDMMC_INT_EBE) {
1499                         if (host->dir_status ==
1500                                 DW_MCI_SEND_STATUS) {
1501                                 /*
1502                                  * No data CRC status was returned.
1503                                  * The number of bytes transferred
1504                                  * will be exaggerated in PIO mode.
1505                                  */
1506                                 data->bytes_xfered = 0;
1507                                 data->error = -ETIMEDOUT;
1508                         } else if (host->dir_status ==
1509                                         DW_MCI_RECV_STATUS) {
1510                                 data->error = -EIO;
1511                         }
1512                 } else {
1513                         /* SDMMC_INT_SBE is included */
1514                         data->error = -EIO;
1515                 }
1516
1517                 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
1518
1519                 /*
1520                  * After an error, there may be data lingering
1521                  * in the FIFO
1522                  */
1523                 dw_mci_reset(host);
1524         } else {
1525                 data->bytes_xfered = data->blocks * data->blksz;
1526                 data->error = 0;
1527         }
1528
1529         return data->error;
1530 }
1531
1532 static void dw_mci_tasklet_func(unsigned long priv)
1533 {
1534         struct dw_mci *host = (struct dw_mci *)priv;
1535         struct mmc_data *data;
1536         struct mmc_command *cmd;
1537         struct mmc_request *mrq;
1538         enum dw_mci_state state;
1539         enum dw_mci_state prev_state;
1540         unsigned int err;
1541
1542         spin_lock(&host->lock);
1543
1544         state = host->state;
1545         data = host->data;
1546         mrq = host->mrq;
1547
1548         do {
1549                 prev_state = state;
1550
1551                 switch (state) {
1552                 case STATE_IDLE:
1553                 case STATE_WAITING_CMD11_DONE:
1554                         break;
1555
1556                 case STATE_SENDING_CMD11:
1557                 case STATE_SENDING_CMD:
1558                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1559                                                 &host->pending_events))
1560                                 break;
1561
1562                         cmd = host->cmd;
1563                         host->cmd = NULL;
1564                         set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
1565                         err = dw_mci_command_complete(host, cmd);
1566                         if (cmd == mrq->sbc && !err) {
1567                                 prev_state = state = STATE_SENDING_CMD;
1568                                 __dw_mci_start_request(host, host->cur_slot,
1569                                                        mrq->cmd);
1570                                 goto unlock;
1571                         }
1572
1573                         if (cmd->data && err) {
1574                                 dw_mci_stop_dma(host);
1575                                 send_stop_abort(host, data);
1576                                 state = STATE_SENDING_STOP;
1577                                 break;
1578                         }
1579
1580                         if (!cmd->data || err) {
1581                                 dw_mci_request_end(host, mrq);
1582                                 goto unlock;
1583                         }
1584
1585                         prev_state = state = STATE_SENDING_DATA;
1586                         /* fall through */
1587
1588                 case STATE_SENDING_DATA:
1589                         /*
1590                          * We could get a data error and never a transfer
1591                          * complete so we'd better check for it here.
1592                          *
1593                          * Note that we don't really care if we also got a
1594                          * transfer complete; stopping the DMA and sending an
1595                          * abort won't hurt.
1596                          */
1597                         if (test_and_clear_bit(EVENT_DATA_ERROR,
1598                                                &host->pending_events)) {
1599                                 dw_mci_stop_dma(host);
1600                                 if (data->stop ||
1601                                     !(host->data_status & (SDMMC_INT_DRTO |
1602                                                            SDMMC_INT_EBE)))
1603                                         send_stop_abort(host, data);
1604                                 state = STATE_DATA_ERROR;
1605                                 break;
1606                         }
1607
1608                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1609                                                 &host->pending_events))
1610                                 break;
1611
1612                         set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
1613
1614                         /*
1615                          * Handle an EVENT_DATA_ERROR that might have shown up
1616                          * before the transfer completed.  This might not have
1617                          * been caught by the check above because the interrupt
1618                          * could have gone off between the previous check and
1619                          * the check for transfer complete.
1620                          *
1621                          * Technically this ought not be needed assuming we
1622                          * get a DATA_COMPLETE eventually (we'll notice the
1623                          * error and end the request), but it shouldn't hurt.
1624                          *
1625                          * This has the advantage of sending the stop command.
1626                          */
1627                         if (test_and_clear_bit(EVENT_DATA_ERROR,
1628                                                &host->pending_events)) {
1629                                 dw_mci_stop_dma(host);
1630                                 if (data->stop ||
1631                                     !(host->data_status & (SDMMC_INT_DRTO |
1632                                                            SDMMC_INT_EBE)))
1633                                         send_stop_abort(host, data);
1634                                 state = STATE_DATA_ERROR;
1635                                 break;
1636                         }
1637                         prev_state = state = STATE_DATA_BUSY;
1638
1639                         /* fall through */
1640
1641                 case STATE_DATA_BUSY:
1642                         if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
1643                                                 &host->pending_events))
1644                                 break;
1645
1646                         host->data = NULL;
1647                         set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
1648                         err = dw_mci_data_complete(host, data);
1649
1650                         if (!err) {
1651                                 if (!data->stop || mrq->sbc) {
1652                                         if (mrq->sbc && data->stop)
1653                                                 data->stop->error = 0;
1654                                         dw_mci_request_end(host, mrq);
1655                                         goto unlock;
1656                                 }
1657
1658                                 /* stop command for open-ended transfer*/
1659                                 if (data->stop)
1660                                         send_stop_abort(host, data);
1661                         } else {
1662                                 /*
1663                                  * If we don't have a command complete now we'll
1664                                  * never get one since we just reset everything;
1665                                  * better end the request.
1666                                  *
1667                                  * If we do have a command complete we'll fall
1668                                  * through to the SENDING_STOP command and
1669                                  * everything will be peachy keen.
1670                                  */
1671                                 if (!test_bit(EVENT_CMD_COMPLETE,
1672                                               &host->pending_events)) {
1673                                         host->cmd = NULL;
1674                                         dw_mci_request_end(host, mrq);
1675                                         goto unlock;
1676                                 }
1677                         }
1678
1679                         /*
1680                          * If err has non-zero,
1681                          * stop-abort command has been already issued.
1682                          */
1683                         prev_state = state = STATE_SENDING_STOP;
1684
1685                         /* fall through */
1686
1687                 case STATE_SENDING_STOP:
1688                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1689                                                 &host->pending_events))
1690                                 break;
1691
1692                         /* CMD error in data command */
1693                         if (mrq->cmd->error && mrq->data)
1694                                 dw_mci_reset(host);
1695
1696                         host->cmd = NULL;
1697                         host->data = NULL;
1698
1699                         if (mrq->stop)
1700                                 dw_mci_command_complete(host, mrq->stop);
1701                         else
1702                                 host->cmd_status = 0;
1703
1704                         dw_mci_request_end(host, mrq);
1705                         goto unlock;
1706
1707                 case STATE_DATA_ERROR:
1708                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1709                                                 &host->pending_events))
1710                                 break;
1711
1712                         state = STATE_DATA_BUSY;
1713                         break;
1714                 }
1715         } while (state != prev_state);
1716
1717         host->state = state;
1718 unlock:
1719         spin_unlock(&host->lock);
1720
1721 }
1722
1723 /* push final bytes to part_buf, only use during push */
1724 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
1725 {
1726         memcpy((void *)&host->part_buf, buf, cnt);
1727         host->part_buf_count = cnt;
1728 }
1729
1730 /* append bytes to part_buf, only use during push */
1731 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
1732 {
1733         cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
1734         memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
1735         host->part_buf_count += cnt;
1736         return cnt;
1737 }
1738
1739 /* pull first bytes from part_buf, only use during pull */
1740 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
1741 {
1742         cnt = min(cnt, (int)host->part_buf_count);
1743         if (cnt) {
1744                 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
1745                        cnt);
1746                 host->part_buf_count -= cnt;
1747                 host->part_buf_start += cnt;
1748         }
1749         return cnt;
1750 }
1751
1752 /* pull final bytes from the part_buf, assuming it's just been filled */
1753 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
1754 {
1755         memcpy(buf, &host->part_buf, cnt);
1756         host->part_buf_start = cnt;
1757         host->part_buf_count = (1 << host->data_shift) - cnt;
1758 }
1759
1760 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
1761 {
1762         struct mmc_data *data = host->data;
1763         int init_cnt = cnt;
1764
1765         /* try and push anything in the part_buf */
1766         if (unlikely(host->part_buf_count)) {
1767                 int len = dw_mci_push_part_bytes(host, buf, cnt);
1768                 buf += len;
1769                 cnt -= len;
1770                 if (host->part_buf_count == 2) {
1771                         mci_fifo_writew(host->fifo_reg, host->part_buf16);
1772                         host->part_buf_count = 0;
1773                 }
1774         }
1775 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1776         if (unlikely((unsigned long)buf & 0x1)) {
1777                 while (cnt >= 2) {
1778                         u16 aligned_buf[64];
1779                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
1780                         int items = len >> 1;
1781                         int i;
1782                         /* memcpy from input buffer into aligned buffer */
1783                         memcpy(aligned_buf, buf, len);
1784                         buf += len;
1785                         cnt -= len;
1786                         /* push data from aligned buffer into fifo */
1787                         for (i = 0; i < items; ++i)
1788                                 mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
1789                 }
1790         } else
1791 #endif
1792         {
1793                 u16 *pdata = buf;
1794                 for (; cnt >= 2; cnt -= 2)
1795                         mci_fifo_writew(host->fifo_reg, *pdata++);
1796                 buf = pdata;
1797         }
1798         /* put anything remaining in the part_buf */
1799         if (cnt) {
1800                 dw_mci_set_part_bytes(host, buf, cnt);
1801                  /* Push data if we have reached the expected data length */
1802                 if ((data->bytes_xfered + init_cnt) ==
1803                     (data->blksz * data->blocks))
1804                         mci_fifo_writew(host->fifo_reg, host->part_buf16);
1805         }
1806 }
1807
1808 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
1809 {
1810 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1811         if (unlikely((unsigned long)buf & 0x1)) {
1812                 while (cnt >= 2) {
1813                         /* pull data from fifo into aligned buffer */
1814                         u16 aligned_buf[64];
1815                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
1816                         int items = len >> 1;
1817                         int i;
1818                         for (i = 0; i < items; ++i)
1819                                 aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
1820                         /* memcpy from aligned buffer into output buffer */
1821                         memcpy(buf, aligned_buf, len);
1822                         buf += len;
1823                         cnt -= len;
1824                 }
1825         } else
1826 #endif
1827         {
1828                 u16 *pdata = buf;
1829                 for (; cnt >= 2; cnt -= 2)
1830                         *pdata++ = mci_fifo_readw(host->fifo_reg);
1831                 buf = pdata;
1832         }
1833         if (cnt) {
1834                 host->part_buf16 = mci_fifo_readw(host->fifo_reg);
1835                 dw_mci_pull_final_bytes(host, buf, cnt);
1836         }
1837 }
1838
1839 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
1840 {
1841         struct mmc_data *data = host->data;
1842         int init_cnt = cnt;
1843
1844         /* try and push anything in the part_buf */
1845         if (unlikely(host->part_buf_count)) {
1846                 int len = dw_mci_push_part_bytes(host, buf, cnt);
1847                 buf += len;
1848                 cnt -= len;
1849                 if (host->part_buf_count == 4) {
1850                         mci_fifo_writel(host->fifo_reg, host->part_buf32);
1851                         host->part_buf_count = 0;
1852                 }
1853         }
1854 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1855         if (unlikely((unsigned long)buf & 0x3)) {
1856                 while (cnt >= 4) {
1857                         u32 aligned_buf[32];
1858                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
1859                         int items = len >> 2;
1860                         int i;
1861                         /* memcpy from input buffer into aligned buffer */
1862                         memcpy(aligned_buf, buf, len);
1863                         buf += len;
1864                         cnt -= len;
1865                         /* push data from aligned buffer into fifo */
1866                         for (i = 0; i < items; ++i)
1867                                 mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
1868                 }
1869         } else
1870 #endif
1871         {
1872                 u32 *pdata = buf;
1873                 for (; cnt >= 4; cnt -= 4)
1874                         mci_fifo_writel(host->fifo_reg, *pdata++);
1875                 buf = pdata;
1876         }
1877         /* put anything remaining in the part_buf */
1878         if (cnt) {
1879                 dw_mci_set_part_bytes(host, buf, cnt);
1880                  /* Push data if we have reached the expected data length */
1881                 if ((data->bytes_xfered + init_cnt) ==
1882                     (data->blksz * data->blocks))
1883                         mci_fifo_writel(host->fifo_reg, host->part_buf32);
1884         }
1885 }
1886
1887 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
1888 {
1889 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1890         if (unlikely((unsigned long)buf & 0x3)) {
1891                 while (cnt >= 4) {
1892                         /* pull data from fifo into aligned buffer */
1893                         u32 aligned_buf[32];
1894                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
1895                         int items = len >> 2;
1896                         int i;
1897                         for (i = 0; i < items; ++i)
1898                                 aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
1899                         /* memcpy from aligned buffer into output buffer */
1900                         memcpy(buf, aligned_buf, len);
1901                         buf += len;
1902                         cnt -= len;
1903                 }
1904         } else
1905 #endif
1906         {
1907                 u32 *pdata = buf;
1908                 for (; cnt >= 4; cnt -= 4)
1909                         *pdata++ = mci_fifo_readl(host->fifo_reg);
1910                 buf = pdata;
1911         }
1912         if (cnt) {
1913                 host->part_buf32 = mci_fifo_readl(host->fifo_reg);
1914                 dw_mci_pull_final_bytes(host, buf, cnt);
1915         }
1916 }
1917
1918 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
1919 {
1920         struct mmc_data *data = host->data;
1921         int init_cnt = cnt;
1922
1923         /* try and push anything in the part_buf */
1924         if (unlikely(host->part_buf_count)) {
1925                 int len = dw_mci_push_part_bytes(host, buf, cnt);
1926                 buf += len;
1927                 cnt -= len;
1928
1929                 if (host->part_buf_count == 8) {
1930                         mci_fifo_writeq(host->fifo_reg, host->part_buf);
1931                         host->part_buf_count = 0;
1932                 }
1933         }
1934 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1935         if (unlikely((unsigned long)buf & 0x7)) {
1936                 while (cnt >= 8) {
1937                         u64 aligned_buf[16];
1938                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
1939                         int items = len >> 3;
1940                         int i;
1941                         /* memcpy from input buffer into aligned buffer */
1942                         memcpy(aligned_buf, buf, len);
1943                         buf += len;
1944                         cnt -= len;
1945                         /* push data from aligned buffer into fifo */
1946                         for (i = 0; i < items; ++i)
1947                                 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
1948                 }
1949         } else
1950 #endif
1951         {
1952                 u64 *pdata = buf;
1953                 for (; cnt >= 8; cnt -= 8)
1954                         mci_fifo_writeq(host->fifo_reg, *pdata++);
1955                 buf = pdata;
1956         }
1957         /* put anything remaining in the part_buf */
1958         if (cnt) {
1959                 dw_mci_set_part_bytes(host, buf, cnt);
1960                 /* Push data if we have reached the expected data length */
1961                 if ((data->bytes_xfered + init_cnt) ==
1962                     (data->blksz * data->blocks))
1963                         mci_fifo_writeq(host->fifo_reg, host->part_buf);
1964         }
1965 }
1966
1967 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
1968 {
1969 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1970         if (unlikely((unsigned long)buf & 0x7)) {
1971                 while (cnt >= 8) {
1972                         /* pull data from fifo into aligned buffer */
1973                         u64 aligned_buf[16];
1974                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
1975                         int items = len >> 3;
1976                         int i;
1977                         for (i = 0; i < items; ++i)
1978                                 aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
1979
1980                         /* memcpy from aligned buffer into output buffer */
1981                         memcpy(buf, aligned_buf, len);
1982                         buf += len;
1983                         cnt -= len;
1984                 }
1985         } else
1986 #endif
1987         {
1988                 u64 *pdata = buf;
1989                 for (; cnt >= 8; cnt -= 8)
1990                         *pdata++ = mci_fifo_readq(host->fifo_reg);
1991                 buf = pdata;
1992         }
1993         if (cnt) {
1994                 host->part_buf = mci_fifo_readq(host->fifo_reg);
1995                 dw_mci_pull_final_bytes(host, buf, cnt);
1996         }
1997 }
1998
1999 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2000 {
2001         int len;
2002
2003         /* get remaining partial bytes */
2004         len = dw_mci_pull_part_bytes(host, buf, cnt);
2005         if (unlikely(len == cnt))
2006                 return;
2007         buf += len;
2008         cnt -= len;
2009
2010         /* get the rest of the data */
2011         host->pull_data(host, buf, cnt);
2012 }
2013
2014 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2015 {
2016         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2017         void *buf;
2018         unsigned int offset;
2019         struct mmc_data *data = host->data;
2020         int shift = host->data_shift;
2021         u32 status;
2022         unsigned int len;
2023         unsigned int remain, fcnt;
2024
2025         do {
2026                 if (!sg_miter_next(sg_miter))
2027                         goto done;
2028
2029                 host->sg = sg_miter->piter.sg;
2030                 buf = sg_miter->addr;
2031                 remain = sg_miter->length;
2032                 offset = 0;
2033
2034                 do {
2035                         fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2036                                         << shift) + host->part_buf_count;
2037                         len = min(remain, fcnt);
2038                         if (!len)
2039                                 break;
2040                         dw_mci_pull_data(host, (void *)(buf + offset), len);
2041                         data->bytes_xfered += len;
2042                         offset += len;
2043                         remain -= len;
2044                 } while (remain);
2045
2046                 sg_miter->consumed = offset;
2047                 status = mci_readl(host, MINTSTS);
2048                 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2049         /* if the RXDR is ready read again */
2050         } while ((status & SDMMC_INT_RXDR) ||
2051                  (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2052
2053         if (!remain) {
2054                 if (!sg_miter_next(sg_miter))
2055                         goto done;
2056                 sg_miter->consumed = 0;
2057         }
2058         sg_miter_stop(sg_miter);
2059         return;
2060
2061 done:
2062         sg_miter_stop(sg_miter);
2063         host->sg = NULL;
2064         smp_wmb();
2065         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2066 }
2067
2068 static void dw_mci_write_data_pio(struct dw_mci *host)
2069 {
2070         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2071         void *buf;
2072         unsigned int offset;
2073         struct mmc_data *data = host->data;
2074         int shift = host->data_shift;
2075         u32 status;
2076         unsigned int len;
2077         unsigned int fifo_depth = host->fifo_depth;
2078         unsigned int remain, fcnt;
2079
2080         do {
2081                 if (!sg_miter_next(sg_miter))
2082                         goto done;
2083
2084                 host->sg = sg_miter->piter.sg;
2085                 buf = sg_miter->addr;
2086                 remain = sg_miter->length;
2087                 offset = 0;
2088
2089                 do {
2090                         fcnt = ((fifo_depth -
2091                                  SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2092                                         << shift) - host->part_buf_count;
2093                         len = min(remain, fcnt);
2094                         if (!len)
2095                                 break;
2096                         host->push_data(host, (void *)(buf + offset), len);
2097                         data->bytes_xfered += len;
2098                         offset += len;
2099                         remain -= len;
2100                 } while (remain);
2101
2102                 sg_miter->consumed = offset;
2103                 status = mci_readl(host, MINTSTS);
2104                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2105         } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
2106
2107         if (!remain) {
2108                 if (!sg_miter_next(sg_miter))
2109                         goto done;
2110                 sg_miter->consumed = 0;
2111         }
2112         sg_miter_stop(sg_miter);
2113         return;
2114
2115 done:
2116         sg_miter_stop(sg_miter);
2117         host->sg = NULL;
2118         smp_wmb();
2119         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2120 }
2121
2122 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2123 {
2124         if (!host->cmd_status)
2125                 host->cmd_status = status;
2126
2127         smp_wmb();
2128
2129         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2130         tasklet_schedule(&host->tasklet);
2131 }
2132
2133 static void dw_mci_handle_cd(struct dw_mci *host)
2134 {
2135         int i;
2136
2137         for (i = 0; i < host->num_slots; i++) {
2138                 struct dw_mci_slot *slot = host->slot[i];
2139
2140                 if (!slot)
2141                         continue;
2142
2143                 if (slot->mmc->ops->card_event)
2144                         slot->mmc->ops->card_event(slot->mmc);
2145                 mmc_detect_change(slot->mmc,
2146                         msecs_to_jiffies(host->pdata->detect_delay_ms));
2147         }
2148 }
2149
2150 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2151 {
2152         struct dw_mci *host = dev_id;
2153         u32 pending;
2154         int i;
2155
2156         pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2157
2158         /*
2159          * DTO fix - version 2.10a and below, and only if internal DMA
2160          * is configured.
2161          */
2162         if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
2163                 if (!pending &&
2164                     ((mci_readl(host, STATUS) >> 17) & 0x1fff))
2165                         pending |= SDMMC_INT_DATA_OVER;
2166         }
2167
2168         if (pending) {
2169                 /* Check volt switch first, since it can look like an error */
2170                 if ((host->state == STATE_SENDING_CMD11) &&
2171                     (pending & SDMMC_INT_VOLT_SWITCH)) {
2172                         unsigned long irqflags;
2173
2174                         mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2175                         pending &= ~SDMMC_INT_VOLT_SWITCH;
2176
2177                         /*
2178                          * Hold the lock; we know cmd11_timer can't be kicked
2179                          * off after the lock is released, so safe to delete.
2180                          */
2181                         spin_lock_irqsave(&host->irq_lock, irqflags);
2182                         dw_mci_cmd_interrupt(host, pending);
2183                         spin_unlock_irqrestore(&host->irq_lock, irqflags);
2184
2185                         del_timer(&host->cmd11_timer);
2186                 }
2187
2188                 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2189                         mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2190                         host->cmd_status = pending;
2191                         smp_wmb();
2192                         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2193                 }
2194
2195                 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2196                         /* if there is an error report DATA_ERROR */
2197                         mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2198                         host->data_status = pending;
2199                         smp_wmb();
2200                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
2201                         tasklet_schedule(&host->tasklet);
2202                 }
2203
2204                 if (pending & SDMMC_INT_DATA_OVER) {
2205                         mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2206                         if (!host->data_status)
2207                                 host->data_status = pending;
2208                         smp_wmb();
2209                         if (host->dir_status == DW_MCI_RECV_STATUS) {
2210                                 if (host->sg != NULL)
2211                                         dw_mci_read_data_pio(host, true);
2212                         }
2213                         set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2214                         tasklet_schedule(&host->tasklet);
2215                 }
2216
2217                 if (pending & SDMMC_INT_RXDR) {
2218                         mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2219                         if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2220                                 dw_mci_read_data_pio(host, false);
2221                 }
2222
2223                 if (pending & SDMMC_INT_TXDR) {
2224                         mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2225                         if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2226                                 dw_mci_write_data_pio(host);
2227                 }
2228
2229                 if (pending & SDMMC_INT_CMD_DONE) {
2230                         mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2231                         dw_mci_cmd_interrupt(host, pending);
2232                 }
2233
2234                 if (pending & SDMMC_INT_CD) {
2235                         mci_writel(host, RINTSTS, SDMMC_INT_CD);
2236                         dw_mci_handle_cd(host);
2237                 }
2238
2239                 /* Handle SDIO Interrupts */
2240                 for (i = 0; i < host->num_slots; i++) {
2241                         struct dw_mci_slot *slot = host->slot[i];
2242
2243                         if (!slot)
2244                                 continue;
2245
2246                         if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
2247                                 mci_writel(host, RINTSTS,
2248                                            SDMMC_INT_SDIO(slot->sdio_id));
2249                                 mmc_signal_sdio_irq(slot->mmc);
2250                         }
2251                 }
2252
2253         }
2254
2255 #ifdef CONFIG_MMC_DW_IDMAC
2256         /* Handle DMA interrupts */
2257         if (host->dma_64bit_address == 1) {
2258                 pending = mci_readl(host, IDSTS64);
2259                 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2260                         mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2261                                                         SDMMC_IDMAC_INT_RI);
2262                         mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
2263                         host->dma_ops->complete(host);
2264                 }
2265         } else {
2266                 pending = mci_readl(host, IDSTS);
2267                 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2268                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2269                                                         SDMMC_IDMAC_INT_RI);
2270                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2271                         host->dma_ops->complete(host);
2272                 }
2273         }
2274 #endif
2275
2276         return IRQ_HANDLED;
2277 }
2278
2279 #ifdef CONFIG_OF
2280 /* given a slot id, find out the device node representing that slot */
2281 static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
2282 {
2283         struct device_node *np;
2284         const __be32 *addr;
2285         int len;
2286
2287         if (!dev || !dev->of_node)
2288                 return NULL;
2289
2290         for_each_child_of_node(dev->of_node, np) {
2291                 addr = of_get_property(np, "reg", &len);
2292                 if (!addr || (len < sizeof(int)))
2293                         continue;
2294                 if (be32_to_cpup(addr) == slot)
2295                         return np;
2296         }
2297         return NULL;
2298 }
2299
2300 static struct dw_mci_of_slot_quirks {
2301         char *quirk;
2302         int id;
2303 } of_slot_quirks[] = {
2304         {
2305                 .quirk  = "disable-wp",
2306                 .id     = DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT,
2307         },
2308 };
2309
2310 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
2311 {
2312         struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
2313         int quirks = 0;
2314         int idx;
2315
2316         /* get quirks */
2317         for (idx = 0; idx < ARRAY_SIZE(of_slot_quirks); idx++)
2318                 if (of_get_property(np, of_slot_quirks[idx].quirk, NULL)) {
2319                         dev_warn(dev, "Slot quirk %s is deprecated\n",
2320                                         of_slot_quirks[idx].quirk);
2321                         quirks |= of_slot_quirks[idx].id;
2322                 }
2323
2324         return quirks;
2325 }
2326 #else /* CONFIG_OF */
2327 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
2328 {
2329         return 0;
2330 }
2331 #endif /* CONFIG_OF */
2332
2333 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
2334 {
2335         struct mmc_host *mmc;
2336         struct dw_mci_slot *slot;
2337         const struct dw_mci_drv_data *drv_data = host->drv_data;
2338         int ctrl_id, ret;
2339         u32 freq[2];
2340
2341         mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
2342         if (!mmc)
2343                 return -ENOMEM;
2344
2345         slot = mmc_priv(mmc);
2346         slot->id = id;
2347         slot->sdio_id = host->sdio_id0 + id;
2348         slot->mmc = mmc;
2349         slot->host = host;
2350         host->slot[id] = slot;
2351
2352         slot->quirks = dw_mci_of_get_slot_quirks(host->dev, slot->id);
2353
2354         mmc->ops = &dw_mci_ops;
2355         if (of_property_read_u32_array(host->dev->of_node,
2356                                        "clock-freq-min-max", freq, 2)) {
2357                 mmc->f_min = DW_MCI_FREQ_MIN;
2358                 mmc->f_max = DW_MCI_FREQ_MAX;
2359         } else {
2360                 mmc->f_min = freq[0];
2361                 mmc->f_max = freq[1];
2362         }
2363
2364         /*if there are external regulators, get them*/
2365         ret = mmc_regulator_get_supply(mmc);
2366         if (ret == -EPROBE_DEFER)
2367                 goto err_host_allocated;
2368
2369         if (!mmc->ocr_avail)
2370                 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2371
2372         if (host->pdata->caps)
2373                 mmc->caps = host->pdata->caps;
2374
2375         if (host->pdata->pm_caps)
2376                 mmc->pm_caps = host->pdata->pm_caps;
2377
2378         if (host->dev->of_node) {
2379                 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2380                 if (ctrl_id < 0)
2381                         ctrl_id = 0;
2382         } else {
2383                 ctrl_id = to_platform_device(host->dev)->id;
2384         }
2385         if (drv_data && drv_data->caps)
2386                 mmc->caps |= drv_data->caps[ctrl_id];
2387
2388         if (host->pdata->caps2)
2389                 mmc->caps2 = host->pdata->caps2;
2390
2391         ret = mmc_of_parse(mmc);
2392         if (ret)
2393                 goto err_host_allocated;
2394
2395         if (host->pdata->blk_settings) {
2396                 mmc->max_segs = host->pdata->blk_settings->max_segs;
2397                 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
2398                 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
2399                 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
2400                 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
2401         } else {
2402                 /* Useful defaults if platform data is unset. */
2403 #ifdef CONFIG_MMC_DW_IDMAC
2404                 mmc->max_segs = host->ring_size;
2405                 mmc->max_blk_size = 65536;
2406                 mmc->max_seg_size = 0x1000;
2407                 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2408                 mmc->max_blk_count = mmc->max_req_size / 512;
2409 #else
2410                 mmc->max_segs = 64;
2411                 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
2412                 mmc->max_blk_count = 512;
2413                 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2414                 mmc->max_seg_size = mmc->max_req_size;
2415 #endif /* CONFIG_MMC_DW_IDMAC */
2416         }
2417
2418         if (dw_mci_get_cd(mmc))
2419                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
2420         else
2421                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
2422
2423         ret = mmc_add_host(mmc);
2424         if (ret)
2425                 goto err_host_allocated;
2426
2427 #if defined(CONFIG_DEBUG_FS)
2428         dw_mci_init_debugfs(slot);
2429 #endif
2430
2431         return 0;
2432
2433 err_host_allocated:
2434         mmc_free_host(mmc);
2435         return ret;
2436 }
2437
2438 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
2439 {
2440         /* Debugfs stuff is cleaned up by mmc core */
2441         mmc_remove_host(slot->mmc);
2442         slot->host->slot[id] = NULL;
2443         mmc_free_host(slot->mmc);
2444 }
2445
2446 static void dw_mci_init_dma(struct dw_mci *host)
2447 {
2448         int addr_config;
2449         /* Check ADDR_CONFIG bit in HCON to find IDMAC address bus width */
2450         addr_config = (mci_readl(host, HCON) >> 27) & 0x01;
2451
2452         if (addr_config == 1) {
2453                 /* host supports IDMAC in 64-bit address mode */
2454                 host->dma_64bit_address = 1;
2455                 dev_info(host->dev, "IDMAC supports 64-bit address mode.\n");
2456                 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
2457                         dma_set_coherent_mask(host->dev, DMA_BIT_MASK(64));
2458         } else {
2459                 /* host supports IDMAC in 32-bit address mode */
2460                 host->dma_64bit_address = 0;
2461                 dev_info(host->dev, "IDMAC supports 32-bit address mode.\n");
2462         }
2463
2464         /* Alloc memory for sg translation */
2465         host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE,
2466                                           &host->sg_dma, GFP_KERNEL);
2467         if (!host->sg_cpu) {
2468                 dev_err(host->dev, "%s: could not alloc DMA memory\n",
2469                         __func__);
2470                 goto no_dma;
2471         }
2472
2473         /* Determine which DMA interface to use */
2474 #ifdef CONFIG_MMC_DW_IDMAC
2475         host->dma_ops = &dw_mci_idmac_ops;
2476         dev_info(host->dev, "Using internal DMA controller.\n");
2477 #endif
2478
2479         if (!host->dma_ops)
2480                 goto no_dma;
2481
2482         if (host->dma_ops->init && host->dma_ops->start &&
2483             host->dma_ops->stop && host->dma_ops->cleanup) {
2484                 if (host->dma_ops->init(host)) {
2485                         dev_err(host->dev, "%s: Unable to initialize "
2486                                 "DMA Controller.\n", __func__);
2487                         goto no_dma;
2488                 }
2489         } else {
2490                 dev_err(host->dev, "DMA initialization not found.\n");
2491                 goto no_dma;
2492         }
2493
2494         host->use_dma = 1;
2495         return;
2496
2497 no_dma:
2498         dev_info(host->dev, "Using PIO mode.\n");
2499         host->use_dma = 0;
2500         return;
2501 }
2502
2503 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
2504 {
2505         unsigned long timeout = jiffies + msecs_to_jiffies(500);
2506         u32 ctrl;
2507
2508         ctrl = mci_readl(host, CTRL);
2509         ctrl |= reset;
2510         mci_writel(host, CTRL, ctrl);
2511
2512         /* wait till resets clear */
2513         do {
2514                 ctrl = mci_readl(host, CTRL);
2515                 if (!(ctrl & reset))
2516                         return true;
2517         } while (time_before(jiffies, timeout));
2518
2519         dev_err(host->dev,
2520                 "Timeout resetting block (ctrl reset %#x)\n",
2521                 ctrl & reset);
2522
2523         return false;
2524 }
2525
2526 static bool dw_mci_reset(struct dw_mci *host)
2527 {
2528         u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
2529         bool ret = false;
2530
2531         /*
2532          * Reseting generates a block interrupt, hence setting
2533          * the scatter-gather pointer to NULL.
2534          */
2535         if (host->sg) {
2536                 sg_miter_stop(&host->sg_miter);
2537                 host->sg = NULL;
2538         }
2539
2540         if (host->use_dma)
2541                 flags |= SDMMC_CTRL_DMA_RESET;
2542
2543         if (dw_mci_ctrl_reset(host, flags)) {
2544                 /*
2545                  * In all cases we clear the RAWINTS register to clear any
2546                  * interrupts.
2547                  */
2548                 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2549
2550                 /* if using dma we wait for dma_req to clear */
2551                 if (host->use_dma) {
2552                         unsigned long timeout = jiffies + msecs_to_jiffies(500);
2553                         u32 status;
2554                         do {
2555                                 status = mci_readl(host, STATUS);
2556                                 if (!(status & SDMMC_STATUS_DMA_REQ))
2557                                         break;
2558                                 cpu_relax();
2559                         } while (time_before(jiffies, timeout));
2560
2561                         if (status & SDMMC_STATUS_DMA_REQ) {
2562                                 dev_err(host->dev,
2563                                         "%s: Timeout waiting for dma_req to "
2564                                         "clear during reset\n", __func__);
2565                                 goto ciu_out;
2566                         }
2567
2568                         /* when using DMA next we reset the fifo again */
2569                         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
2570                                 goto ciu_out;
2571                 }
2572         } else {
2573                 /* if the controller reset bit did clear, then set clock regs */
2574                 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
2575                         dev_err(host->dev, "%s: fifo/dma reset bits didn't "
2576                                 "clear but ciu was reset, doing clock update\n",
2577                                 __func__);
2578                         goto ciu_out;
2579                 }
2580         }
2581
2582 #if IS_ENABLED(CONFIG_MMC_DW_IDMAC)
2583         /* It is also recommended that we reset and reprogram idmac */
2584         dw_mci_idmac_reset(host);
2585 #endif
2586
2587         ret = true;
2588
2589 ciu_out:
2590         /* After a CTRL reset we need to have CIU set clock registers  */
2591         mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0);
2592
2593         return ret;
2594 }
2595
2596 static void dw_mci_cmd11_timer(unsigned long arg)
2597 {
2598         struct dw_mci *host = (struct dw_mci *)arg;
2599
2600         if (host->state != STATE_SENDING_CMD11) {
2601                 dev_warn(host->dev, "Unexpected CMD11 timeout\n");
2602                 return;
2603         }
2604
2605         host->cmd_status = SDMMC_INT_RTO;
2606         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2607         tasklet_schedule(&host->tasklet);
2608 }
2609
2610 #ifdef CONFIG_OF
2611 static struct dw_mci_of_quirks {
2612         char *quirk;
2613         int id;
2614 } of_quirks[] = {
2615         {
2616                 .quirk  = "broken-cd",
2617                 .id     = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
2618         }, {
2619                 .quirk  = "disable-wp",
2620                 .id     = DW_MCI_QUIRK_NO_WRITE_PROTECT,
2621         },
2622 };
2623
2624 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2625 {
2626         struct dw_mci_board *pdata;
2627         struct device *dev = host->dev;
2628         struct device_node *np = dev->of_node;
2629         const struct dw_mci_drv_data *drv_data = host->drv_data;
2630         int idx, ret;
2631         u32 clock_frequency;
2632
2633         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2634         if (!pdata)
2635                 return ERR_PTR(-ENOMEM);
2636
2637         /* find out number of slots supported */
2638         if (of_property_read_u32(dev->of_node, "num-slots",
2639                                 &pdata->num_slots)) {
2640                 dev_info(dev, "num-slots property not found, "
2641                                 "assuming 1 slot is available\n");
2642                 pdata->num_slots = 1;
2643         }
2644
2645         /* get quirks */
2646         for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++)
2647                 if (of_get_property(np, of_quirks[idx].quirk, NULL))
2648                         pdata->quirks |= of_quirks[idx].id;
2649
2650         if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
2651                 dev_info(dev, "fifo-depth property not found, using "
2652                                 "value of FIFOTH register as default\n");
2653
2654         of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
2655
2656         if (!of_property_read_u32(np, "clock-frequency", &clock_frequency))
2657                 pdata->bus_hz = clock_frequency;
2658
2659         if (drv_data && drv_data->parse_dt) {
2660                 ret = drv_data->parse_dt(host);
2661                 if (ret)
2662                         return ERR_PTR(ret);
2663         }
2664
2665         if (of_find_property(np, "supports-highspeed", NULL))
2666                 pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2667
2668         return pdata;
2669 }
2670
2671 #else /* CONFIG_OF */
2672 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2673 {
2674         return ERR_PTR(-EINVAL);
2675 }
2676 #endif /* CONFIG_OF */
2677
2678 static void dw_mci_enable_cd(struct dw_mci *host)
2679 {
2680         struct dw_mci_board *brd = host->pdata;
2681         unsigned long irqflags;
2682         u32 temp;
2683         int i;
2684
2685         /* No need for CD if broken card detection */
2686         if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
2687                 return;
2688
2689         /* No need for CD if all slots have a non-error GPIO */
2690         for (i = 0; i < host->num_slots; i++) {
2691                 struct dw_mci_slot *slot = host->slot[i];
2692
2693                 if (IS_ERR_VALUE(mmc_gpio_get_cd(slot->mmc)))
2694                         break;
2695         }
2696         if (i == host->num_slots)
2697                 return;
2698
2699         spin_lock_irqsave(&host->irq_lock, irqflags);
2700         temp = mci_readl(host, INTMASK);
2701         temp  |= SDMMC_INT_CD;
2702         mci_writel(host, INTMASK, temp);
2703         spin_unlock_irqrestore(&host->irq_lock, irqflags);
2704 }
2705
2706 int dw_mci_probe(struct dw_mci *host)
2707 {
2708         const struct dw_mci_drv_data *drv_data = host->drv_data;
2709         int width, i, ret = 0;
2710         u32 fifo_size;
2711         int init_slots = 0;
2712
2713         if (!host->pdata) {
2714                 host->pdata = dw_mci_parse_dt(host);
2715                 if (IS_ERR(host->pdata)) {
2716                         dev_err(host->dev, "platform data not available\n");
2717                         return -EINVAL;
2718                 }
2719         }
2720
2721         if (host->pdata->num_slots > 1) {
2722                 dev_err(host->dev,
2723                         "Platform data must supply num_slots.\n");
2724                 return -ENODEV;
2725         }
2726
2727         host->biu_clk = devm_clk_get(host->dev, "biu");
2728         if (IS_ERR(host->biu_clk)) {
2729                 dev_dbg(host->dev, "biu clock not available\n");
2730         } else {
2731                 ret = clk_prepare_enable(host->biu_clk);
2732                 if (ret) {
2733                         dev_err(host->dev, "failed to enable biu clock\n");
2734                         return ret;
2735                 }
2736         }
2737
2738         host->ciu_clk = devm_clk_get(host->dev, "ciu");
2739         if (IS_ERR(host->ciu_clk)) {
2740                 dev_dbg(host->dev, "ciu clock not available\n");
2741                 host->bus_hz = host->pdata->bus_hz;
2742         } else {
2743                 ret = clk_prepare_enable(host->ciu_clk);
2744                 if (ret) {
2745                         dev_err(host->dev, "failed to enable ciu clock\n");
2746                         goto err_clk_biu;
2747                 }
2748
2749                 if (host->pdata->bus_hz) {
2750                         ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
2751                         if (ret)
2752                                 dev_warn(host->dev,
2753                                          "Unable to set bus rate to %uHz\n",
2754                                          host->pdata->bus_hz);
2755                 }
2756                 host->bus_hz = clk_get_rate(host->ciu_clk);
2757         }
2758
2759         if (!host->bus_hz) {
2760                 dev_err(host->dev,
2761                         "Platform data must supply bus speed\n");
2762                 ret = -ENODEV;
2763                 goto err_clk_ciu;
2764         }
2765
2766         if (drv_data && drv_data->init) {
2767                 ret = drv_data->init(host);
2768                 if (ret) {
2769                         dev_err(host->dev,
2770                                 "implementation specific init failed\n");
2771                         goto err_clk_ciu;
2772                 }
2773         }
2774
2775         if (drv_data && drv_data->setup_clock) {
2776                 ret = drv_data->setup_clock(host);
2777                 if (ret) {
2778                         dev_err(host->dev,
2779                                 "implementation specific clock setup failed\n");
2780                         goto err_clk_ciu;
2781                 }
2782         }
2783
2784         setup_timer(&host->cmd11_timer,
2785                     dw_mci_cmd11_timer, (unsigned long)host);
2786
2787         host->quirks = host->pdata->quirks;
2788
2789         spin_lock_init(&host->lock);
2790         spin_lock_init(&host->irq_lock);
2791         INIT_LIST_HEAD(&host->queue);
2792
2793         /*
2794          * Get the host data width - this assumes that HCON has been set with
2795          * the correct values.
2796          */
2797         i = (mci_readl(host, HCON) >> 7) & 0x7;
2798         if (!i) {
2799                 host->push_data = dw_mci_push_data16;
2800                 host->pull_data = dw_mci_pull_data16;
2801                 width = 16;
2802                 host->data_shift = 1;
2803         } else if (i == 2) {
2804                 host->push_data = dw_mci_push_data64;
2805                 host->pull_data = dw_mci_pull_data64;
2806                 width = 64;
2807                 host->data_shift = 3;
2808         } else {
2809                 /* Check for a reserved value, and warn if it is */
2810                 WARN((i != 1),
2811                      "HCON reports a reserved host data width!\n"
2812                      "Defaulting to 32-bit access.\n");
2813                 host->push_data = dw_mci_push_data32;
2814                 host->pull_data = dw_mci_pull_data32;
2815                 width = 32;
2816                 host->data_shift = 2;
2817         }
2818
2819         /* Reset all blocks */
2820         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS))
2821                 return -ENODEV;
2822
2823         host->dma_ops = host->pdata->dma_ops;
2824         dw_mci_init_dma(host);
2825
2826         /* Clear the interrupts for the host controller */
2827         mci_writel(host, RINTSTS, 0xFFFFFFFF);
2828         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2829
2830         /* Put in max timeout */
2831         mci_writel(host, TMOUT, 0xFFFFFFFF);
2832
2833         /*
2834          * FIFO threshold settings  RxMark  = fifo_size / 2 - 1,
2835          *                          Tx Mark = fifo_size / 2 DMA Size = 8
2836          */
2837         if (!host->pdata->fifo_depth) {
2838                 /*
2839                  * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
2840                  * have been overwritten by the bootloader, just like we're
2841                  * about to do, so if you know the value for your hardware, you
2842                  * should put it in the platform data.
2843                  */
2844                 fifo_size = mci_readl(host, FIFOTH);
2845                 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
2846         } else {
2847                 fifo_size = host->pdata->fifo_depth;
2848         }
2849         host->fifo_depth = fifo_size;
2850         host->fifoth_val =
2851                 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
2852         mci_writel(host, FIFOTH, host->fifoth_val);
2853
2854         /* disable clock to CIU */
2855         mci_writel(host, CLKENA, 0);
2856         mci_writel(host, CLKSRC, 0);
2857
2858         /*
2859          * In 2.40a spec, Data offset is changed.
2860          * Need to check the version-id and set data-offset for DATA register.
2861          */
2862         host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
2863         dev_info(host->dev, "Version ID is %04x\n", host->verid);
2864
2865         if (host->verid < DW_MMC_240A)
2866                 host->fifo_reg = host->regs + DATA_OFFSET;
2867         else
2868                 host->fifo_reg = host->regs + DATA_240A_OFFSET;
2869
2870         tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
2871         ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
2872                                host->irq_flags, "dw-mci", host);
2873         if (ret)
2874                 goto err_dmaunmap;
2875
2876         if (host->pdata->num_slots)
2877                 host->num_slots = host->pdata->num_slots;
2878         else
2879                 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
2880
2881         /*
2882          * Enable interrupts for command done, data over, data empty,
2883          * receive ready and error such as transmit, receive timeout, crc error
2884          */
2885         mci_writel(host, RINTSTS, 0xFFFFFFFF);
2886         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2887                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2888                    DW_MCI_ERROR_FLAGS);
2889         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
2890
2891         dev_info(host->dev, "DW MMC controller at irq %d, "
2892                  "%d bit host data width, "
2893                  "%u deep fifo\n",
2894                  host->irq, width, fifo_size);
2895
2896         /* We need at least one slot to succeed */
2897         for (i = 0; i < host->num_slots; i++) {
2898                 ret = dw_mci_init_slot(host, i);
2899                 if (ret)
2900                         dev_dbg(host->dev, "slot %d init failed\n", i);
2901                 else
2902                         init_slots++;
2903         }
2904
2905         if (init_slots) {
2906                 dev_info(host->dev, "%d slots initialized\n", init_slots);
2907         } else {
2908                 dev_dbg(host->dev, "attempted to initialize %d slots, "
2909                                         "but failed on all\n", host->num_slots);
2910                 goto err_dmaunmap;
2911         }
2912
2913         /* Now that slots are all setup, we can enable card detect */
2914         dw_mci_enable_cd(host);
2915
2916         if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
2917                 dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n");
2918
2919         return 0;
2920
2921 err_dmaunmap:
2922         if (host->use_dma && host->dma_ops->exit)
2923                 host->dma_ops->exit(host);
2924
2925 err_clk_ciu:
2926         if (!IS_ERR(host->ciu_clk))
2927                 clk_disable_unprepare(host->ciu_clk);
2928
2929 err_clk_biu:
2930         if (!IS_ERR(host->biu_clk))
2931                 clk_disable_unprepare(host->biu_clk);
2932
2933         return ret;
2934 }
2935 EXPORT_SYMBOL(dw_mci_probe);
2936
2937 void dw_mci_remove(struct dw_mci *host)
2938 {
2939         int i;
2940
2941         mci_writel(host, RINTSTS, 0xFFFFFFFF);
2942         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2943
2944         for (i = 0; i < host->num_slots; i++) {
2945                 dev_dbg(host->dev, "remove slot %d\n", i);
2946                 if (host->slot[i])
2947                         dw_mci_cleanup_slot(host->slot[i], i);
2948         }
2949
2950         /* disable clock to CIU */
2951         mci_writel(host, CLKENA, 0);
2952         mci_writel(host, CLKSRC, 0);
2953
2954         if (host->use_dma && host->dma_ops->exit)
2955                 host->dma_ops->exit(host);
2956
2957         if (!IS_ERR(host->ciu_clk))
2958                 clk_disable_unprepare(host->ciu_clk);
2959
2960         if (!IS_ERR(host->biu_clk))
2961                 clk_disable_unprepare(host->biu_clk);
2962 }
2963 EXPORT_SYMBOL(dw_mci_remove);
2964
2965
2966
2967 #ifdef CONFIG_PM_SLEEP
2968 /*
2969  * TODO: we should probably disable the clock to the card in the suspend path.
2970  */
2971 int dw_mci_suspend(struct dw_mci *host)
2972 {
2973         return 0;
2974 }
2975 EXPORT_SYMBOL(dw_mci_suspend);
2976
2977 int dw_mci_resume(struct dw_mci *host)
2978 {
2979         int i, ret;
2980
2981         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
2982                 ret = -ENODEV;
2983                 return ret;
2984         }
2985
2986         if (host->use_dma && host->dma_ops->init)
2987                 host->dma_ops->init(host);
2988
2989         /*
2990          * Restore the initial value at FIFOTH register
2991          * And Invalidate the prev_blksz with zero
2992          */
2993         mci_writel(host, FIFOTH, host->fifoth_val);
2994         host->prev_blksz = 0;
2995
2996         /* Put in max timeout */
2997         mci_writel(host, TMOUT, 0xFFFFFFFF);
2998
2999         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3000         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3001                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3002                    DW_MCI_ERROR_FLAGS);
3003         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3004
3005         for (i = 0; i < host->num_slots; i++) {
3006                 struct dw_mci_slot *slot = host->slot[i];
3007                 if (!slot)
3008                         continue;
3009                 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
3010                         dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
3011                         dw_mci_setup_bus(slot, true);
3012                 }
3013         }
3014
3015         /* Now that slots are all setup, we can enable card detect */
3016         dw_mci_enable_cd(host);
3017
3018         return 0;
3019 }
3020 EXPORT_SYMBOL(dw_mci_resume);
3021 #endif /* CONFIG_PM_SLEEP */
3022
3023 static int __init dw_mci_init(void)
3024 {
3025         pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
3026         return 0;
3027 }
3028
3029 static void __exit dw_mci_exit(void)
3030 {
3031 }
3032
3033 module_init(dw_mci_init);
3034 module_exit(dw_mci_exit);
3035
3036 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3037 MODULE_AUTHOR("NXP Semiconductor VietNam");
3038 MODULE_AUTHOR("Imagination Technologies Ltd");
3039 MODULE_LICENSE("GPL v2");