drivers/mmc/host/au1xmmc.c

   1 /*
   2  * linux/drivers/mmc/host/au1xmmc.c - AU1XX0 MMC driver
   3  *
   4  *  Copyright (c) 2005, Advanced Micro Devices, Inc.
   5  *
   6  *  Developed with help from the 2.4.30 MMC AU1XXX controller including
   7  *  the following copyright notices:
   8  *     Copyright (c) 2003-2004 Embedded Edge, LLC.
   9  *     Portions Copyright (C) 2002 Embedix, Inc
  10  *     Copyright 2002 Hewlett-Packard Company
  11
  12  *  2.6 version of this driver inspired by:
  13  *     (drivers/mmc/wbsd.c) Copyright (C) 2004-2005 Pierre Ossman,
  14  *     All Rights Reserved.
  15  *     (drivers/mmc/pxa.c) Copyright (C) 2003 Russell King,
  16  *     All Rights Reserved.
  17  *
  18
  19  * This program is free software; you can redistribute it and/or modify
  20  * it under the terms of the GNU General Public License version 2 as
  21  * published by the Free Software Foundation.
  22  */
  23
  24 /* Why don't we use the SD controllers' carddetect feature?
  25  *
  26  * From the AU1100 MMC application guide:
  27  * If the Au1100-based design is intended to support both MultiMediaCards
  28  * and 1- or 4-data bit SecureDigital cards, then the solution is to
  29  * connect a weak (560KOhm) pull-up resistor to connector pin 1.
  30  * In doing so, a MMC card never enters SPI-mode communications,
  31  * but now the SecureDigital card-detect feature of CD/DAT3 is ineffective
  32  * (the low to high transition will not occur).
  33  */
  34
  35 #include <linux/module.h>
  36 #include <linux/init.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/mm.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/dma-mapping.h>
  41 #include <linux/scatterlist.h>
  42 #include <linux/leds.h>
  43 #include <linux/mmc/host.h>
  44 #include <linux/slab.h>
  45
  46 #include <asm/io.h>
  47 #include <asm/mach-au1x00/au1000.h>
  48 #include <asm/mach-au1x00/au1xxx_dbdma.h>
  49 #include <asm/mach-au1x00/au1100_mmc.h>
  50
  51 #define DRIVER_NAME "au1xxx-mmc"
  52
  53 /* Set this to enable special debugging macros */
  54 /* #define DEBUG */
  55
  56 #ifdef DEBUG
  57 #define DBG(fmt, idx, args...)  \
  58         pr_debug("au1xmmc(%d): DEBUG: " fmt, idx, ##args)
  59 #else
  60 #define DBG(fmt, idx, args...) do {} while (0)
  61 #endif
  62
  63 /* Hardware definitions */
  64 #define AU1XMMC_DESCRIPTOR_COUNT 1
  65
  66 /* max DMA seg size: 64KB on Au1100, 4MB on Au1200 */
  67 #define AU1100_MMC_DESCRIPTOR_SIZE 0x0000ffff
  68 #define AU1200_MMC_DESCRIPTOR_SIZE 0x003fffff
  69
  70 #define AU1XMMC_OCR (MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | \
  71                      MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 | \
  72                      MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36)
  73
  74 /* This gives us a hard value for the stop command that we can write directly
  75  * to the command register.
  76  */
  77 #define STOP_CMD        \
  78         (SD_CMD_RT_1B | SD_CMD_CT_7 | (0xC << SD_CMD_CI_SHIFT) | SD_CMD_GO)
  79
  80 /* This is the set of interrupts that we configure by default. */
  81 #define AU1XMMC_INTERRUPTS                              \
  82         (SD_CONFIG_SC | SD_CONFIG_DT | SD_CONFIG_RAT |  \
  83          SD_CONFIG_CR | SD_CONFIG_I)
  84
  85 /* The poll event (looking for insert/remove events runs twice a second. */
  86 #define AU1XMMC_DETECT_TIMEOUT (HZ/2)
  87
  88 struct au1xmmc_host {
  89         struct mmc_host *mmc;
  90         struct mmc_request *mrq;
  91
  92         u32 flags;
  93         void __iomem *iobase;
  94         u32 clock;
  95         u32 bus_width;
  96         u32 power_mode;
  97
  98         int status;
  99
 100         struct {
 101                 int len;
 102                 int dir;
 103         } dma;
 104
 105         struct {
 106                 int index;
 107                 int offset;
 108                 int len;
 109         } pio;
 110
 111         u32 tx_chan;
 112         u32 rx_chan;
 113
 114         int irq;
 115
 116         struct tasklet_struct finish_task;
 117         struct tasklet_struct data_task;
 118         struct au1xmmc_platform_data *platdata;
 119         struct platform_device *pdev;
 120         struct resource *ioarea;
 121 };
 122
 123 /* Status flags used by the host structure */
 124 #define HOST_F_XMIT     0x0001
 125 #define HOST_F_RECV     0x0002
 126 #define HOST_F_DMA      0x0010
 127 #define HOST_F_DBDMA    0x0020
 128 #define HOST_F_ACTIVE   0x0100
 129 #define HOST_F_STOP     0x1000
 130
 131 #define HOST_S_IDLE     0x0001
 132 #define HOST_S_CMD      0x0002
 133 #define HOST_S_DATA     0x0003
 134 #define HOST_S_STOP     0x0004
 135
 136 /* Easy access macros */
 137 #define HOST_STATUS(h)  ((h)->iobase + SD_STATUS)
 138 #define HOST_CONFIG(h)  ((h)->iobase + SD_CONFIG)
 139 #define HOST_ENABLE(h)  ((h)->iobase + SD_ENABLE)
 140 #define HOST_TXPORT(h)  ((h)->iobase + SD_TXPORT)
 141 #define HOST_RXPORT(h)  ((h)->iobase + SD_RXPORT)
 142 #define HOST_CMDARG(h)  ((h)->iobase + SD_CMDARG)
 143 #define HOST_BLKSIZE(h) ((h)->iobase + SD_BLKSIZE)
 144 #define HOST_CMD(h)     ((h)->iobase + SD_CMD)
 145 #define HOST_CONFIG2(h) ((h)->iobase + SD_CONFIG2)
 146 #define HOST_TIMEOUT(h) ((h)->iobase + SD_TIMEOUT)
 147 #define HOST_DEBUG(h)   ((h)->iobase + SD_DEBUG)
 148
 149 #define DMA_CHANNEL(h)  \
 150         (((h)->flags & HOST_F_XMIT) ? (h)->tx_chan : (h)->rx_chan)
 151
 152 static inline int has_dbdma(void)
 153 {
 154         switch (alchemy_get_cputype()) {
 155         case ALCHEMY_CPU_AU1200:
 156         case ALCHEMY_CPU_AU1300:
 157                 return 1;
 158         default:
 159                 return 0;
 160         }
 161 }
 162
 163 static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask)
 164 {
 165         u32 val = __raw_readl(HOST_CONFIG(host));
 166         val |= mask;
 167         __raw_writel(val, HOST_CONFIG(host));
 168         wmb(); /* drain writebuffer */
 169 }
 170
 171 static inline void FLUSH_FIFO(struct au1xmmc_host *host)
 172 {
 173         u32 val = __raw_readl(HOST_CONFIG2(host));
 174
 175         __raw_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host));
 176         wmb(); /* drain writebuffer */
 177         mdelay(1);
 178
 179         /* SEND_STOP will turn off clock control - this re-enables it */
 180         val &= ~SD_CONFIG2_DF;
 181
 182         __raw_writel(val, HOST_CONFIG2(host));
 183         wmb(); /* drain writebuffer */
 184 }
 185
 186 static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask)
 187 {
 188         u32 val = __raw_readl(HOST_CONFIG(host));
 189         val &= ~mask;
 190         __raw_writel(val, HOST_CONFIG(host));
 191         wmb(); /* drain writebuffer */
 192 }
 193
 194 static inline void SEND_STOP(struct au1xmmc_host *host)
 195 {
 196         u32 config2;
 197
 198         WARN_ON(host->status != HOST_S_DATA);
 199         host->status = HOST_S_STOP;
 200
 201         config2 = __raw_readl(HOST_CONFIG2(host));
 202         __raw_writel(config2 | SD_CONFIG2_DF, HOST_CONFIG2(host));
 203         wmb(); /* drain writebuffer */
 204
 205         /* Send the stop command */
 206         __raw_writel(STOP_CMD, HOST_CMD(host));
 207         wmb(); /* drain writebuffer */
 208 }
 209
 210 static void au1xmmc_set_power(struct au1xmmc_host *host, int state)
 211 {
 212         if (host->platdata && host->platdata->set_power)
 213                 host->platdata->set_power(host->mmc, state);
 214 }
 215
 216 static int au1xmmc_card_inserted(struct mmc_host *mmc)
 217 {
 218         struct au1xmmc_host *host = mmc_priv(mmc);
 219
 220         if (host->platdata && host->platdata->card_inserted)
 221                 return !!host->platdata->card_inserted(host->mmc);
 222
 223         return -ENOSYS;
 224 }
 225
 226 static int au1xmmc_card_readonly(struct mmc_host *mmc)
 227 {
 228         struct au1xmmc_host *host = mmc_priv(mmc);
 229
 230         if (host->platdata && host->platdata->card_readonly)
 231                 return !!host->platdata->card_readonly(mmc);
 232
 233         return -ENOSYS;
 234 }
 235
 236 static void au1xmmc_finish_request(struct au1xmmc_host *host)
 237 {
 238         struct mmc_request *mrq = host->mrq;
 239
 240         host->mrq = NULL;
 241         host->flags &= HOST_F_ACTIVE | HOST_F_DMA;
 242
 243         host->dma.len = 0;
 244         host->dma.dir = 0;
 245
 246         host->pio.index  = 0;
 247         host->pio.offset = 0;
 248         host->pio.len = 0;
 249
 250         host->status = HOST_S_IDLE;
 251
 252         mmc_request_done(host->mmc, mrq);
 253 }
 254
 255 static void au1xmmc_tasklet_finish(unsigned long param)
 256 {
 257         struct au1xmmc_host *host = (struct au1xmmc_host *) param;
 258         au1xmmc_finish_request(host);
 259 }
 260
 261 static int au1xmmc_send_command(struct au1xmmc_host *host, int wait,
 262                                 struct mmc_command *cmd, struct mmc_data *data)
 263 {
 264         u32 mmccmd = (cmd->opcode << SD_CMD_CI_SHIFT);
 265
 266         switch (mmc_resp_type(cmd)) {
 267         case MMC_RSP_NONE:
 268                 break;
 269         case MMC_RSP_R1:
 270                 mmccmd |= SD_CMD_RT_1;
 271                 break;
 272         case MMC_RSP_R1B:
 273                 mmccmd |= SD_CMD_RT_1B;
 274                 break;
 275         case MMC_RSP_R2:
 276                 mmccmd |= SD_CMD_RT_2;
 277                 break;
 278         case MMC_RSP_R3:
 279                 mmccmd |= SD_CMD_RT_3;
 280                 break;
 281         default:
 282                 pr_info("au1xmmc: unhandled response type %02x\n",
 283                         mmc_resp_type(cmd));
 284                 return -EINVAL;
 285         }
 286
 287         if (data) {
 288                 if (data->flags & MMC_DATA_READ) {
 289                         if (data->blocks > 1)
 290                                 mmccmd |= SD_CMD_CT_4;
 291                         else
 292                                 mmccmd |= SD_CMD_CT_2;
 293                 } else if (data->flags & MMC_DATA_WRITE) {
 294                         if (data->blocks > 1)
 295                                 mmccmd |= SD_CMD_CT_3;
 296                         else
 297                                 mmccmd |= SD_CMD_CT_1;
 298                 }
 299         }
 300
 301         __raw_writel(cmd->arg, HOST_CMDARG(host));
 302         wmb(); /* drain writebuffer */
 303
 304         if (wait)
 305                 IRQ_OFF(host, SD_CONFIG_CR);
 306
 307         __raw_writel((mmccmd | SD_CMD_GO), HOST_CMD(host));
 308         wmb(); /* drain writebuffer */
 309
 310         /* Wait for the command to go on the line */
 311         while (__raw_readl(HOST_CMD(host)) & SD_CMD_GO)
 312                 /* nop */;
 313
 314         /* Wait for the command to come back */
 315         if (wait) {
 316                 u32 status = __raw_readl(HOST_STATUS(host));
 317
 318                 while (!(status & SD_STATUS_CR))
 319                         status = __raw_readl(HOST_STATUS(host));
 320
 321                 /* Clear the CR status */
 322                 __raw_writel(SD_STATUS_CR, HOST_STATUS(host));
 323
 324                 IRQ_ON(host, SD_CONFIG_CR);
 325         }
 326
 327         return 0;
 328 }
 329
 330 static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status)
 331 {
 332         struct mmc_request *mrq = host->mrq;
 333         struct mmc_data *data;
 334         u32 crc;
 335
 336         WARN_ON((host->status != HOST_S_DATA) && (host->status != HOST_S_STOP));
 337
 338         if (host->mrq == NULL)
 339                 return;
 340
 341         data = mrq->cmd->data;
 342
 343         if (status == 0)
 344                 status = __raw_readl(HOST_STATUS(host));
 345
 346         /* The transaction is really over when the SD_STATUS_DB bit is clear */
 347         while ((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB))
 348                 status = __raw_readl(HOST_STATUS(host));
 349
 350         data->error = 0;
 351         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir);
 352
 353         /* Process any errors */
 354         crc = (status & (SD_STATUS_WC | SD_STATUS_RC));
 355         if (host->flags & HOST_F_XMIT)
 356                 crc |= ((status & 0x07) == 0x02) ? 0 : 1;
 357
 358         if (crc)
 359                 data->error = -EILSEQ;
 360
 361         /* Clear the CRC bits */
 362         __raw_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host));
 363
 364         data->bytes_xfered = 0;
 365
 366         if (!data->error) {
 367                 if (host->flags & (HOST_F_DMA | HOST_F_DBDMA)) {
 368                         u32 chan = DMA_CHANNEL(host);
 369
 370                         chan_tab_t *c = *((chan_tab_t **)chan);
 371                         au1x_dma_chan_t *cp = c->chan_ptr;
 372                         data->bytes_xfered = cp->ddma_bytecnt;
 373                 } else
 374                         data->bytes_xfered =
 375                                 (data->blocks * data->blksz) - host->pio.len;
 376         }
 377
 378         au1xmmc_finish_request(host);
 379 }
 380
 381 static void au1xmmc_tasklet_data(unsigned long param)
 382 {
 383         struct au1xmmc_host *host = (struct au1xmmc_host *)param;
 384
 385         u32 status = __raw_readl(HOST_STATUS(host));
 386         au1xmmc_data_complete(host, status);
 387 }
 388
 389 #define AU1XMMC_MAX_TRANSFER 8
 390
 391 static void au1xmmc_send_pio(struct au1xmmc_host *host)
 392 {
 393         struct mmc_data *data;
 394         int sg_len, max, count;
 395         unsigned char *sg_ptr, val;
 396         u32 status;
 397         struct scatterlist *sg;
 398
 399         data = host->mrq->data;
 400
 401         if (!(host->flags & HOST_F_XMIT))
 402                 return;
 403
 404         /* This is the pointer to the data buffer */
 405         sg = &data->sg[host->pio.index];
 406         sg_ptr = sg_virt(sg) + host->pio.offset;
 407
 408         /* This is the space left inside the buffer */
 409         sg_len = data->sg[host->pio.index].length - host->pio.offset;
 410
 411         /* Check if we need less than the size of the sg_buffer */
 412         max = (sg_len > host->pio.len) ? host->pio.len : sg_len;
 413         if (max > AU1XMMC_MAX_TRANSFER)
 414                 max = AU1XMMC_MAX_TRANSFER;
 415
 416         for (count = 0; count < max; count++) {
 417                 status = __raw_readl(HOST_STATUS(host));
 418
 419                 if (!(status & SD_STATUS_TH))
 420                         break;
 421
 422                 val = *sg_ptr++;
 423
 424                 __raw_writel((unsigned long)val, HOST_TXPORT(host));
 425                 wmb(); /* drain writebuffer */
 426         }
 427
 428         host->pio.len -= count;
 429         host->pio.offset += count;
 430
 431         if (count == sg_len) {
 432                 host->pio.index++;
 433                 host->pio.offset = 0;
 434         }
 435
 436         if (host->pio.len == 0) {
 437                 IRQ_OFF(host, SD_CONFIG_TH);
 438
 439                 if (host->flags & HOST_F_STOP)
 440                         SEND_STOP(host);
 441
 442                 tasklet_schedule(&host->data_task);
 443         }
 444 }
 445
 446 static void au1xmmc_receive_pio(struct au1xmmc_host *host)
 447 {
 448         struct mmc_data *data;
 449         int max, count, sg_len = 0;
 450         unsigned char *sg_ptr = NULL;
 451         u32 status, val;
 452         struct scatterlist *sg;
 453
 454         data = host->mrq->data;
 455
 456         if (!(host->flags & HOST_F_RECV))
 457                 return;
 458
 459         max = host->pio.len;
 460
 461         if (host->pio.index < host->dma.len) {
 462                 sg = &data->sg[host->pio.index];
 463                 sg_ptr = sg_virt(sg) + host->pio.offset;
 464
 465                 /* This is the space left inside the buffer */
 466                 sg_len = sg_dma_len(&data->sg[host->pio.index]) - host->pio.offset;
 467
 468                 /* Check if we need less than the size of the sg_buffer */
 469                 if (sg_len < max)
 470                         max = sg_len;
 471         }
 472
 473         if (max > AU1XMMC_MAX_TRANSFER)
 474                 max = AU1XMMC_MAX_TRANSFER;
 475
 476         for (count = 0; count < max; count++) {
 477                 status = __raw_readl(HOST_STATUS(host));
 478
 479                 if (!(status & SD_STATUS_NE))
 480                         break;
 481
 482                 if (status & SD_STATUS_RC) {
 483                         DBG("RX CRC Error [%d + %d].\n", host->pdev->id,
 484                                         host->pio.len, count);
 485                         break;
 486                 }
 487
 488                 if (status & SD_STATUS_RO) {
 489                         DBG("RX Overrun [%d + %d]\n", host->pdev->id,
 490                                         host->pio.len, count);
 491                         break;
 492                 }
 493                 else if (status & SD_STATUS_RU) {
 494                         DBG("RX Underrun [%d + %d]\n", host->pdev->id,
 495                                         host->pio.len,  count);
 496                         break;
 497                 }
 498
 499                 val = __raw_readl(HOST_RXPORT(host));
 500
 501                 if (sg_ptr)
 502                         *sg_ptr++ = (unsigned char)(val & 0xFF);
 503         }
 504
 505         host->pio.len -= count;
 506         host->pio.offset += count;
 507
 508         if (sg_len && count == sg_len) {
 509                 host->pio.index++;
 510                 host->pio.offset = 0;
 511         }
 512
 513         if (host->pio.len == 0) {
 514                 /* IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF); */
 515                 IRQ_OFF(host, SD_CONFIG_NE);
 516
 517                 if (host->flags & HOST_F_STOP)
 518                         SEND_STOP(host);
 519
 520                 tasklet_schedule(&host->data_task);
 521         }
 522 }
 523
 524 /* This is called when a command has been completed - grab the response
 525  * and check for errors.  Then start the data transfer if it is indicated.
 526  */
 527 static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status)
 528 {
 529         struct mmc_request *mrq = host->mrq;
 530         struct mmc_command *cmd;
 531         u32 r[4];
 532         int i, trans;
 533
 534         if (!host->mrq)
 535                 return;
 536
 537         cmd = mrq->cmd;
 538         cmd->error = 0;
 539
 540         if (cmd->flags & MMC_RSP_PRESENT) {
 541                 if (cmd->flags & MMC_RSP_136) {
 542                         r[0] = __raw_readl(host->iobase + SD_RESP3);
 543                         r[1] = __raw_readl(host->iobase + SD_RESP2);
 544                         r[2] = __raw_readl(host->iobase + SD_RESP1);
 545                         r[3] = __raw_readl(host->iobase + SD_RESP0);
 546
 547                         /* The CRC is omitted from the response, so really
 548                          * we only got 120 bytes, but the engine expects
 549                          * 128 bits, so we have to shift things up.
 550                          */
 551                         for (i = 0; i < 4; i++) {
 552                                 cmd->resp[i] = (r[i] & 0x00FFFFFF) << 8;
 553                                 if (i != 3)
 554                                         cmd->resp[i] |= (r[i + 1] & 0xFF000000) >> 24;
 555                         }
 556                 } else {
 557                         /* Techincally, we should be getting all 48 bits of
 558                          * the response (SD_RESP1 + SD_RESP2), but because
 559                          * our response omits the CRC, our data ends up
 560                          * being shifted 8 bits to the right.  In this case,
 561                          * that means that the OSR data starts at bit 31,
 562                          * so we can just read RESP0 and return that.
 563                          */
 564                         cmd->resp[0] = __raw_readl(host->iobase + SD_RESP0);
 565                 }
 566         }
 567
 568         /* Figure out errors */
 569         if (status & (SD_STATUS_SC | SD_STATUS_WC | SD_STATUS_RC))
 570                 cmd->error = -EILSEQ;
 571
 572         trans = host->flags & (HOST_F_XMIT | HOST_F_RECV);
 573
 574         if (!trans || cmd->error) {
 575                 IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF);
 576                 tasklet_schedule(&host->finish_task);
 577                 return;
 578         }
 579
 580         host->status = HOST_S_DATA;
 581
 582         if ((host->flags & (HOST_F_DMA | HOST_F_DBDMA))) {
 583                 u32 channel = DMA_CHANNEL(host);
 584
 585                 /* Start the DBDMA as soon as the buffer gets something in it */
 586
 587                 if (host->flags & HOST_F_RECV) {
 588                         u32 mask = SD_STATUS_DB | SD_STATUS_NE;
 589
 590                         while((status & mask) != mask)
 591                                 status = __raw_readl(HOST_STATUS(host));
 592                 }
 593
 594                 au1xxx_dbdma_start(channel);
 595         }
 596 }
 597
 598 static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate)
 599 {
 600         unsigned int pbus = get_au1x00_speed();
 601         unsigned int divisor;
 602         u32 config;
 603
 604         /* From databook:
 605          * divisor = ((((cpuclock / sbus_divisor) / 2) / mmcclock) / 2) - 1
 606          */
 607         pbus /= ((alchemy_rdsys(AU1000_SYS_POWERCTRL) & 0x3) + 2);
 608         pbus /= 2;
 609         divisor = ((pbus / rate) / 2) - 1;
 610
 611         config = __raw_readl(HOST_CONFIG(host));
 612
 613         config &= ~(SD_CONFIG_DIV);
 614         config |= (divisor & SD_CONFIG_DIV) | SD_CONFIG_DE;
 615
 616         __raw_writel(config, HOST_CONFIG(host));
 617         wmb(); /* drain writebuffer */
 618 }
 619
 620 static int au1xmmc_prepare_data(struct au1xmmc_host *host,
 621                                 struct mmc_data *data)
 622 {
 623         int datalen = data->blocks * data->blksz;
 624
 625         if (data->flags & MMC_DATA_READ)
 626                 host->flags |= HOST_F_RECV;
 627         else
 628                 host->flags |= HOST_F_XMIT;
 629
 630         if (host->mrq->stop)
 631                 host->flags |= HOST_F_STOP;
 632
 633         host->dma.dir = DMA_BIDIRECTIONAL;
 634
 635         host->dma.len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 636                                    data->sg_len, host->dma.dir);
 637
 638         if (host->dma.len == 0)
 639                 return -ETIMEDOUT;
 640
 641         __raw_writel(data->blksz - 1, HOST_BLKSIZE(host));
 642
 643         if (host->flags & (HOST_F_DMA | HOST_F_DBDMA)) {
 644                 int i;
 645                 u32 channel = DMA_CHANNEL(host);
 646
 647                 au1xxx_dbdma_stop(channel);
 648
 649                 for (i = 0; i < host->dma.len; i++) {
 650                         u32 ret = 0, flags = DDMA_FLAGS_NOIE;
 651                         struct scatterlist *sg = &data->sg[i];
 652                         int sg_len = sg->length;
 653
 654                         int len = (datalen > sg_len) ? sg_len : datalen;
 655
 656                         if (i == host->dma.len - 1)
 657                                 flags = DDMA_FLAGS_IE;
 658
 659                         if (host->flags & HOST_F_XMIT) {
 660                                 ret = au1xxx_dbdma_put_source(channel,
 661                                         sg_phys(sg), len, flags);
 662                         } else {
 663                                 ret = au1xxx_dbdma_put_dest(channel,
 664                                         sg_phys(sg), len, flags);
 665                         }
 666
 667                         if (!ret)
 668                                 goto dataerr;
 669
 670                         datalen -= len;
 671                 }
 672         } else {
 673                 host->pio.index = 0;
 674                 host->pio.offset = 0;
 675                 host->pio.len = datalen;
 676
 677                 if (host->flags & HOST_F_XMIT)
 678                         IRQ_ON(host, SD_CONFIG_TH);
 679                 else
 680                         IRQ_ON(host, SD_CONFIG_NE);
 681                         /* IRQ_ON(host, SD_CONFIG_RA | SD_CONFIG_RF); */
 682         }
 683
 684         return 0;
 685
 686 dataerr:
 687         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
 688                         host->dma.dir);
 689         return -ETIMEDOUT;
 690 }
 691
 692 /* This actually starts a command or data transaction */
 693 static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq)
 694 {
 695         struct au1xmmc_host *host = mmc_priv(mmc);
 696         int ret = 0;
 697
 698         WARN_ON(irqs_disabled());
 699         WARN_ON(host->status != HOST_S_IDLE);
 700
 701         host->mrq = mrq;
 702         host->status = HOST_S_CMD;
 703
 704         /* fail request immediately if no card is present */
 705         if (0 == au1xmmc_card_inserted(mmc)) {
 706                 mrq->cmd->error = -ENOMEDIUM;
 707                 au1xmmc_finish_request(host);
 708                 return;
 709         }
 710
 711         if (mrq->data) {
 712                 FLUSH_FIFO(host);
 713                 ret = au1xmmc_prepare_data(host, mrq->data);
 714         }
 715
 716         if (!ret)
 717                 ret = au1xmmc_send_command(host, 0, mrq->cmd, mrq->data);
 718
 719         if (ret) {
 720                 mrq->cmd->error = ret;
 721                 au1xmmc_finish_request(host);
 722         }
 723 }
 724
 725 static void au1xmmc_reset_controller(struct au1xmmc_host *host)
 726 {
 727         /* Apply the clock */
 728         __raw_writel(SD_ENABLE_CE, HOST_ENABLE(host));
 729         wmb(); /* drain writebuffer */
 730         mdelay(1);
 731
 732         __raw_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host));
 733         wmb(); /* drain writebuffer */
 734         mdelay(5);
 735
 736         __raw_writel(~0, HOST_STATUS(host));
 737         wmb(); /* drain writebuffer */
 738
 739         __raw_writel(0, HOST_BLKSIZE(host));
 740         __raw_writel(0x001fffff, HOST_TIMEOUT(host));
 741         wmb(); /* drain writebuffer */
 742
 743         __raw_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
 744         wmb(); /* drain writebuffer */
 745
 746         __raw_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host));
 747         wmb(); /* drain writebuffer */
 748         mdelay(1);
 749
 750         __raw_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
 751         wmb(); /* drain writebuffer */
 752
 753         /* Configure interrupts */
 754         __raw_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host));
 755         wmb(); /* drain writebuffer */
 756 }
 757
 758
 759 static void au1xmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 760 {
 761         struct au1xmmc_host *host = mmc_priv(mmc);
 762         u32 config2;
 763
 764         if (ios->power_mode == MMC_POWER_OFF)
 765                 au1xmmc_set_power(host, 0);
 766         else if (ios->power_mode == MMC_POWER_ON) {
 767                 au1xmmc_set_power(host, 1);
 768         }
 769
 770         if (ios->clock && ios->clock != host->clock) {
 771                 au1xmmc_set_clock(host, ios->clock);
 772                 host->clock = ios->clock;
 773         }
 774
 775         config2 = __raw_readl(HOST_CONFIG2(host));
 776         switch (ios->bus_width) {
 777         case MMC_BUS_WIDTH_8:
 778                 config2 |= SD_CONFIG2_BB;
 779                 break;
 780         case MMC_BUS_WIDTH_4:
 781                 config2 &= ~SD_CONFIG2_BB;
 782                 config2 |= SD_CONFIG2_WB;
 783                 break;
 784         case MMC_BUS_WIDTH_1:
 785                 config2 &= ~(SD_CONFIG2_WB | SD_CONFIG2_BB);
 786                 break;
 787         }
 788         __raw_writel(config2, HOST_CONFIG2(host));
 789         wmb(); /* drain writebuffer */
 790 }
 791
 792 #define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT)
 793 #define STATUS_DATA_IN  (SD_STATUS_NE)
 794 #define STATUS_DATA_OUT (SD_STATUS_TH)
 795
 796 static irqreturn_t au1xmmc_irq(int irq, void *dev_id)
 797 {
 798         struct au1xmmc_host *host = dev_id;
 799         u32 status;
 800
 801         status = __raw_readl(HOST_STATUS(host));
 802
 803         if (!(status & SD_STATUS_I))
 804                 return IRQ_NONE;        /* not ours */
 805
 806         if (status & SD_STATUS_SI)      /* SDIO */
 807                 mmc_signal_sdio_irq(host->mmc);
 808
 809         if (host->mrq && (status & STATUS_TIMEOUT)) {
 810                 if (status & SD_STATUS_RAT)
 811                         host->mrq->cmd->error = -ETIMEDOUT;
 812                 else if (status & SD_STATUS_DT)
 813                         host->mrq->data->error = -ETIMEDOUT;
 814
 815                 /* In PIO mode, interrupts might still be enabled */
 816                 IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH);
 817
 818                 /* IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF); */
 819                 tasklet_schedule(&host->finish_task);
 820         }
 821 #if 0
 822         else if (status & SD_STATUS_DD) {
 823                 /* Sometimes we get a DD before a NE in PIO mode */
 824                 if (!(host->flags & HOST_F_DMA) && (status & SD_STATUS_NE))
 825                         au1xmmc_receive_pio(host);
 826                 else {
 827                         au1xmmc_data_complete(host, status);
 828                         /* tasklet_schedule(&host->data_task); */
 829                 }
 830         }
 831 #endif
 832         else if (status & SD_STATUS_CR) {
 833                 if (host->status == HOST_S_CMD)
 834                         au1xmmc_cmd_complete(host, status);
 835
 836         } else if (!(host->flags & HOST_F_DMA)) {
 837                 if ((host->flags & HOST_F_XMIT) && (status & STATUS_DATA_OUT))
 838                         au1xmmc_send_pio(host);
 839                 else if ((host->flags & HOST_F_RECV) && (status & STATUS_DATA_IN))
 840                         au1xmmc_receive_pio(host);
 841
 842         } else if (status & 0x203F3C70) {
 843                         DBG("Unhandled status %8.8x\n", host->pdev->id,
 844                                 status);
 845         }
 846
 847         __raw_writel(status, HOST_STATUS(host));
 848         wmb(); /* drain writebuffer */
 849
 850         return IRQ_HANDLED;
 851 }
 852
 853 /* 8bit memory DMA device */
 854 static dbdev_tab_t au1xmmc_mem_dbdev = {
 855         .dev_id         = DSCR_CMD0_ALWAYS,
 856         .dev_flags      = DEV_FLAGS_ANYUSE,
 857         .dev_tsize      = 0,
 858         .dev_devwidth   = 8,
 859         .dev_physaddr   = 0x00000000,
 860         .dev_intlevel   = 0,
 861         .dev_intpolarity = 0,
 862 };
 863 static int memid;
 864
 865 static void au1xmmc_dbdma_callback(int irq, void *dev_id)
 866 {
 867         struct au1xmmc_host *host = (struct au1xmmc_host *)dev_id;
 868
 869         /* Avoid spurious interrupts */
 870         if (!host->mrq)
 871                 return;
 872
 873         if (host->flags & HOST_F_STOP)
 874                 SEND_STOP(host);
 875
 876         tasklet_schedule(&host->data_task);
 877 }
 878
 879 static int au1xmmc_dbdma_init(struct au1xmmc_host *host)
 880 {
 881         struct resource *res;
 882         int txid, rxid;
 883
 884         res = platform_get_resource(host->pdev, IORESOURCE_DMA, 0);
 885         if (!res)
 886                 return -ENODEV;
 887         txid = res->start;
 888
 889         res = platform_get_resource(host->pdev, IORESOURCE_DMA, 1);
 890         if (!res)
 891                 return -ENODEV;
 892         rxid = res->start;
 893
 894         if (!memid)
 895                 return -ENODEV;
 896
 897         host->tx_chan = au1xxx_dbdma_chan_alloc(memid, txid,
 898                                 au1xmmc_dbdma_callback, (void *)host);
 899         if (!host->tx_chan) {
 900                 dev_err(&host->pdev->dev, "cannot allocate TX DMA\n");
 901                 return -ENODEV;
 902         }
 903
 904         host->rx_chan = au1xxx_dbdma_chan_alloc(rxid, memid,
 905                                 au1xmmc_dbdma_callback, (void *)host);
 906         if (!host->rx_chan) {
 907                 dev_err(&host->pdev->dev, "cannot allocate RX DMA\n");
 908                 au1xxx_dbdma_chan_free(host->tx_chan);
 909                 return -ENODEV;
 910         }
 911
 912         au1xxx_dbdma_set_devwidth(host->tx_chan, 8);
 913         au1xxx_dbdma_set_devwidth(host->rx_chan, 8);
 914
 915         au1xxx_dbdma_ring_alloc(host->tx_chan, AU1XMMC_DESCRIPTOR_COUNT);
 916         au1xxx_dbdma_ring_alloc(host->rx_chan, AU1XMMC_DESCRIPTOR_COUNT);
 917
 918         /* DBDMA is good to go */
 919         host->flags |= HOST_F_DMA | HOST_F_DBDMA;
 920
 921         return 0;
 922 }
 923
 924 static void au1xmmc_dbdma_shutdown(struct au1xmmc_host *host)
 925 {
 926         if (host->flags & HOST_F_DMA) {
 927                 host->flags &= ~HOST_F_DMA;
 928                 au1xxx_dbdma_chan_free(host->tx_chan);
 929                 au1xxx_dbdma_chan_free(host->rx_chan);
 930         }
 931 }
 932
 933 static void au1xmmc_enable_sdio_irq(struct mmc_host *mmc, int en)
 934 {
 935         struct au1xmmc_host *host = mmc_priv(mmc);
 936
 937         if (en)
 938                 IRQ_ON(host, SD_CONFIG_SI);
 939         else
 940                 IRQ_OFF(host, SD_CONFIG_SI);
 941 }
 942
 943 static const struct mmc_host_ops au1xmmc_ops = {
 944         .request        = au1xmmc_request,
 945         .set_ios        = au1xmmc_set_ios,
 946         .get_ro         = au1xmmc_card_readonly,
 947         .get_cd         = au1xmmc_card_inserted,
 948         .enable_sdio_irq = au1xmmc_enable_sdio_irq,
 949 };
 950
 951 static int au1xmmc_probe(struct platform_device *pdev)
 952 {
 953         struct mmc_host *mmc;
 954         struct au1xmmc_host *host;
 955         struct resource *r;
 956         int ret, iflag;
 957
 958         mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev);
 959         if (!mmc) {
 960                 dev_err(&pdev->dev, "no memory for mmc_host\n");
 961                 ret = -ENOMEM;
 962                 goto out0;
 963         }
 964
 965         host = mmc_priv(mmc);
 966         host->mmc = mmc;
 967         host->platdata = pdev->dev.platform_data;
 968         host->pdev = pdev;
 969
 970         ret = -ENODEV;
 971         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 972         if (!r) {
 973                 dev_err(&pdev->dev, "no mmio defined\n");
 974                 goto out1;
 975         }
 976
 977         host->ioarea = request_mem_region(r->start, resource_size(r),
 978                                            pdev->name);
 979         if (!host->ioarea) {
 980                 dev_err(&pdev->dev, "mmio already in use\n");
 981                 goto out1;
 982         }
 983
 984         host->iobase = ioremap(r->start, 0x3c);
 985         if (!host->iobase) {
 986                 dev_err(&pdev->dev, "cannot remap mmio\n");
 987                 goto out2;
 988         }
 989
 990         r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 991         if (!r) {
 992                 dev_err(&pdev->dev, "no IRQ defined\n");
 993                 goto out3;
 994         }
 995         host->irq = r->start;
 996
 997         mmc->ops = &au1xmmc_ops;
 998
 999         mmc->f_min =   450000;
1000         mmc->f_max = 24000000;
1001
1002         mmc->max_blk_size = 2048;
1003         mmc->max_blk_count = 512;
1004
1005         mmc->ocr_avail = AU1XMMC_OCR;
1006         mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1007         mmc->max_segs = AU1XMMC_DESCRIPTOR_COUNT;
1008
1009         iflag = IRQF_SHARED;    /* Au1100/Au1200: one int for both ctrls */
1010
1011         switch (alchemy_get_cputype()) {
1012         case ALCHEMY_CPU_AU1100:
1013                 mmc->max_seg_size = AU1100_MMC_DESCRIPTOR_SIZE;
1014                 break;
1015         case ALCHEMY_CPU_AU1200:
1016                 mmc->max_seg_size = AU1200_MMC_DESCRIPTOR_SIZE;
1017                 break;
1018         case ALCHEMY_CPU_AU1300:
1019                 iflag = 0;      /* nothing is shared */
1020                 mmc->max_seg_size = AU1200_MMC_DESCRIPTOR_SIZE;
1021                 mmc->f_max = 52000000;
1022                 if (host->ioarea->start == AU1100_SD0_PHYS_ADDR)
1023                         mmc->caps |= MMC_CAP_8_BIT_DATA;
1024                 break;
1025         }
1026
1027         ret = request_irq(host->irq, au1xmmc_irq, iflag, DRIVER_NAME, host);
1028         if (ret) {
1029                 dev_err(&pdev->dev, "cannot grab IRQ\n");
1030                 goto out3;
1031         }
1032
1033         host->status = HOST_S_IDLE;
1034
1035         /* board-specific carddetect setup, if any */
1036         if (host->platdata && host->platdata->cd_setup) {
1037                 ret = host->platdata->cd_setup(mmc, 1);
1038                 if (ret) {
1039                         dev_warn(&pdev->dev, "board CD setup failed\n");
1040                         mmc->caps |= MMC_CAP_NEEDS_POLL;
1041                 }
1042         } else
1043                 mmc->caps |= MMC_CAP_NEEDS_POLL;
1044
1045         /* platform may not be able to use all advertised caps */
1046         if (host->platdata)
1047                 mmc->caps &= ~(host->platdata->mask_host_caps);
1048
1049         tasklet_init(&host->data_task, au1xmmc_tasklet_data,
1050                         (unsigned long)host);
1051
1052         tasklet_init(&host->finish_task, au1xmmc_tasklet_finish,
1053                         (unsigned long)host);
1054
1055         if (has_dbdma()) {
1056                 ret = au1xmmc_dbdma_init(host);
1057                 if (ret)
1058                         pr_info(DRIVER_NAME ": DBDMA init failed; using PIO\n");
1059         }
1060
1061 #ifdef CONFIG_LEDS_CLASS
1062         if (host->platdata && host->platdata->led) {
1063                 struct led_classdev *led = host->platdata->led;
1064                 led->name = mmc_hostname(mmc);
1065                 led->brightness = LED_OFF;
1066                 led->default_trigger = mmc_hostname(mmc);
1067                 ret = led_classdev_register(mmc_dev(mmc), led);
1068                 if (ret)
1069                         goto out5;
1070         }
1071 #endif
1072
1073         au1xmmc_reset_controller(host);
1074
1075         ret = mmc_add_host(mmc);
1076         if (ret) {
1077                 dev_err(&pdev->dev, "cannot add mmc host\n");
1078                 goto out6;
1079         }
1080
1081         platform_set_drvdata(pdev, host);
1082
1083         pr_info(DRIVER_NAME ": MMC Controller %d set up at %p"
1084                 " (mode=%s)\n", pdev->id, host->iobase,
1085                 host->flags & HOST_F_DMA ? "dma" : "pio");
1086
1087         return 0;       /* all ok */
1088
1089 out6:
1090 #ifdef CONFIG_LEDS_CLASS
1091         if (host->platdata && host->platdata->led)
1092                 led_classdev_unregister(host->platdata->led);
1093 out5:
1094 #endif
1095         __raw_writel(0, HOST_ENABLE(host));
1096         __raw_writel(0, HOST_CONFIG(host));
1097         __raw_writel(0, HOST_CONFIG2(host));
1098         wmb(); /* drain writebuffer */
1099
1100         if (host->flags & HOST_F_DBDMA)
1101                 au1xmmc_dbdma_shutdown(host);
1102
1103         tasklet_kill(&host->data_task);
1104         tasklet_kill(&host->finish_task);
1105
1106         if (host->platdata && host->platdata->cd_setup &&
1107             !(mmc->caps & MMC_CAP_NEEDS_POLL))
1108                 host->platdata->cd_setup(mmc, 0);
1109
1110         free_irq(host->irq, host);
1111 out3:
1112         iounmap((void *)host->iobase);
1113 out2:
1114         release_resource(host->ioarea);
1115         kfree(host->ioarea);
1116 out1:
1117         mmc_free_host(mmc);
1118 out0:
1119         return ret;
1120 }
1121
1122 static int au1xmmc_remove(struct platform_device *pdev)
1123 {
1124         struct au1xmmc_host *host = platform_get_drvdata(pdev);
1125
1126         if (host) {
1127                 mmc_remove_host(host->mmc);
1128
1129 #ifdef CONFIG_LEDS_CLASS
1130                 if (host->platdata && host->platdata->led)
1131                         led_classdev_unregister(host->platdata->led);
1132 #endif
1133
1134                 if (host->platdata && host->platdata->cd_setup &&
1135                     !(host->mmc->caps & MMC_CAP_NEEDS_POLL))
1136                         host->platdata->cd_setup(host->mmc, 0);
1137
1138                 __raw_writel(0, HOST_ENABLE(host));
1139                 __raw_writel(0, HOST_CONFIG(host));
1140                 __raw_writel(0, HOST_CONFIG2(host));
1141                 wmb(); /* drain writebuffer */
1142
1143                 tasklet_kill(&host->data_task);
1144                 tasklet_kill(&host->finish_task);
1145
1146                 if (host->flags & HOST_F_DBDMA)
1147                         au1xmmc_dbdma_shutdown(host);
1148
1149                 au1xmmc_set_power(host, 0);
1150
1151                 free_irq(host->irq, host);
1152                 iounmap((void *)host->iobase);
1153                 release_resource(host->ioarea);
1154                 kfree(host->ioarea);
1155
1156                 mmc_free_host(host->mmc);
1157         }
1158         return 0;
1159 }
1160
1161 #ifdef CONFIG_PM
1162 static int au1xmmc_suspend(struct platform_device *pdev, pm_message_t state)
1163 {
1164         struct au1xmmc_host *host = platform_get_drvdata(pdev);
1165
1166         __raw_writel(0, HOST_CONFIG2(host));
1167         __raw_writel(0, HOST_CONFIG(host));
1168         __raw_writel(0xffffffff, HOST_STATUS(host));
1169         __raw_writel(0, HOST_ENABLE(host));
1170         wmb(); /* drain writebuffer */
1171
1172         return 0;
1173 }
1174
1175 static int au1xmmc_resume(struct platform_device *pdev)
1176 {
1177         struct au1xmmc_host *host = platform_get_drvdata(pdev);
1178
1179         au1xmmc_reset_controller(host);
1180
1181         return 0;
1182 }
1183 #else
1184 #define au1xmmc_suspend NULL
1185 #define au1xmmc_resume NULL
1186 #endif
1187
1188 static struct platform_driver au1xmmc_driver = {
1189         .probe         = au1xmmc_probe,
1190         .remove        = au1xmmc_remove,
1191         .suspend       = au1xmmc_suspend,
1192         .resume        = au1xmmc_resume,
1193         .driver        = {
1194                 .name  = DRIVER_NAME,
1195                 .owner = THIS_MODULE,
1196         },
1197 };
1198
1199 static int __init au1xmmc_init(void)
1200 {
1201         if (has_dbdma()) {
1202                 /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride
1203                 * of 8 bits.  And since devices are shared, we need to create
1204                 * our own to avoid freaking out other devices.
1205                 */
1206                 memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev);
1207                 if (!memid)
1208                         pr_err("au1xmmc: cannot add memory dbdma\n");
1209         }
1210         return platform_driver_register(&au1xmmc_driver);
1211 }
1212
1213 static void __exit au1xmmc_exit(void)
1214 {
1215         if (has_dbdma() && memid)
1216                 au1xxx_ddma_del_device(memid);
1217
1218         platform_driver_unregister(&au1xmmc_driver);
1219 }
1220
1221 module_init(au1xmmc_init);
1222 module_exit(au1xmmc_exit);
1223
1224 MODULE_AUTHOR("Advanced Micro Devices, Inc");
1225 MODULE_DESCRIPTION("MMC/SD driver for the Alchemy Au1XXX");
1226 MODULE_LICENSE("GPL");
1227 MODULE_ALIAS("platform:au1xxx-mmc");