2 * Host side test driver to test endpoint functionality
4 * Copyright (C) 2017 Texas Instruments
5 * Author: Kishon Vijay Abraham I <kishon@ti.com>
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 of
9 * the License as published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #include <linux/crc32.h>
21 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/miscdevice.h>
27 #include <linux/module.h>
28 #include <linux/mutex.h>
29 #include <linux/random.h>
30 #include <linux/slab.h>
31 #include <linux/pci.h>
32 #include <linux/pci_ids.h>
34 #include <linux/pci_regs.h>
36 #include <uapi/linux/pcitest.h>
38 #define DRV_MODULE_NAME "pci-endpoint-test"
40 #define PCI_ENDPOINT_TEST_MAGIC 0x0
42 #define PCI_ENDPOINT_TEST_COMMAND 0x4
43 #define COMMAND_RAISE_LEGACY_IRQ BIT(0)
44 #define COMMAND_RAISE_MSI_IRQ BIT(1)
45 #define MSI_NUMBER_SHIFT 2
46 /* 6 bits for MSI number */
47 #define COMMAND_READ BIT(8)
48 #define COMMAND_WRITE BIT(9)
49 #define COMMAND_COPY BIT(10)
51 #define PCI_ENDPOINT_TEST_STATUS 0x8
52 #define STATUS_READ_SUCCESS BIT(0)
53 #define STATUS_READ_FAIL BIT(1)
54 #define STATUS_WRITE_SUCCESS BIT(2)
55 #define STATUS_WRITE_FAIL BIT(3)
56 #define STATUS_COPY_SUCCESS BIT(4)
57 #define STATUS_COPY_FAIL BIT(5)
58 #define STATUS_IRQ_RAISED BIT(6)
59 #define STATUS_SRC_ADDR_INVALID BIT(7)
60 #define STATUS_DST_ADDR_INVALID BIT(8)
62 #define PCI_ENDPOINT_TEST_LOWER_SRC_ADDR 0xc
63 #define PCI_ENDPOINT_TEST_UPPER_SRC_ADDR 0x10
65 #define PCI_ENDPOINT_TEST_LOWER_DST_ADDR 0x14
66 #define PCI_ENDPOINT_TEST_UPPER_DST_ADDR 0x18
68 #define PCI_ENDPOINT_TEST_SIZE 0x1c
69 #define PCI_ENDPOINT_TEST_CHECKSUM 0x20
71 static DEFINE_IDA(pci_endpoint_test_ida);
73 #define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \
84 struct pci_endpoint_test {
88 struct completion irq_raised;
90 /* mutex to protect the ioctls */
92 struct miscdevice miscdev;
93 enum pci_barno test_reg_bar;
97 struct pci_endpoint_test_data {
98 enum pci_barno test_reg_bar;
102 static int bar_size[] = { 512, 512, 1024, 16384, 131072, 1048576 };
104 static inline u32 pci_endpoint_test_readl(struct pci_endpoint_test *test,
107 return readl(test->base + offset);
110 static inline void pci_endpoint_test_writel(struct pci_endpoint_test *test,
111 u32 offset, u32 value)
113 writel(value, test->base + offset);
116 static inline u32 pci_endpoint_test_bar_readl(struct pci_endpoint_test *test,
119 return readl(test->bar[bar] + offset);
122 static inline void pci_endpoint_test_bar_writel(struct pci_endpoint_test *test,
123 int bar, u32 offset, u32 value)
125 writel(value, test->bar[bar] + offset);
128 static irqreturn_t pci_endpoint_test_irqhandler(int irq, void *dev_id)
130 struct pci_endpoint_test *test = dev_id;
133 reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS);
134 if (reg & STATUS_IRQ_RAISED) {
135 test->last_irq = irq;
136 complete(&test->irq_raised);
137 reg &= ~STATUS_IRQ_RAISED;
139 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_STATUS,
145 static bool pci_endpoint_test_bar(struct pci_endpoint_test *test,
146 enum pci_barno barno)
152 if (!test->bar[barno])
155 size = bar_size[barno];
157 if (barno == test->test_reg_bar)
160 for (j = 0; j < size; j += 4)
161 pci_endpoint_test_bar_writel(test, barno, j, 0xA0A0A0A0);
163 for (j = 0; j < size; j += 4) {
164 val = pci_endpoint_test_bar_readl(test, barno, j);
165 if (val != 0xA0A0A0A0)
172 static bool pci_endpoint_test_legacy_irq(struct pci_endpoint_test *test)
176 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
177 COMMAND_RAISE_LEGACY_IRQ);
178 val = wait_for_completion_timeout(&test->irq_raised,
179 msecs_to_jiffies(1000));
186 static bool pci_endpoint_test_msi_irq(struct pci_endpoint_test *test,
190 struct pci_dev *pdev = test->pdev;
192 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
193 msi_num << MSI_NUMBER_SHIFT |
194 COMMAND_RAISE_MSI_IRQ);
195 val = wait_for_completion_timeout(&test->irq_raised,
196 msecs_to_jiffies(1000));
200 if (test->last_irq - pdev->irq == msi_num - 1)
206 static bool pci_endpoint_test_copy(struct pci_endpoint_test *test, size_t size)
211 dma_addr_t src_phys_addr;
212 dma_addr_t dst_phys_addr;
213 struct pci_dev *pdev = test->pdev;
214 struct device *dev = &pdev->dev;
216 dma_addr_t orig_src_phys_addr;
218 dma_addr_t orig_dst_phys_addr;
220 size_t alignment = test->alignment;
224 orig_src_addr = dma_alloc_coherent(dev, size + alignment,
225 &orig_src_phys_addr, GFP_KERNEL);
226 if (!orig_src_addr) {
227 dev_err(dev, "failed to allocate source buffer\n");
232 if (alignment && !IS_ALIGNED(orig_src_phys_addr, alignment)) {
233 src_phys_addr = PTR_ALIGN(orig_src_phys_addr, alignment);
234 offset = src_phys_addr - orig_src_phys_addr;
235 src_addr = orig_src_addr + offset;
237 src_phys_addr = orig_src_phys_addr;
238 src_addr = orig_src_addr;
241 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR,
242 lower_32_bits(src_phys_addr));
244 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR,
245 upper_32_bits(src_phys_addr));
247 get_random_bytes(src_addr, size);
248 src_crc32 = crc32_le(~0, src_addr, size);
250 orig_dst_addr = dma_alloc_coherent(dev, size + alignment,
251 &orig_dst_phys_addr, GFP_KERNEL);
252 if (!orig_dst_addr) {
253 dev_err(dev, "failed to allocate destination address\n");
255 goto err_orig_src_addr;
258 if (alignment && !IS_ALIGNED(orig_dst_phys_addr, alignment)) {
259 dst_phys_addr = PTR_ALIGN(orig_dst_phys_addr, alignment);
260 offset = dst_phys_addr - orig_dst_phys_addr;
261 dst_addr = orig_dst_addr + offset;
263 dst_phys_addr = orig_dst_phys_addr;
264 dst_addr = orig_dst_addr;
267 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR,
268 lower_32_bits(dst_phys_addr));
269 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR,
270 upper_32_bits(dst_phys_addr));
272 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE,
275 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
276 1 << MSI_NUMBER_SHIFT | COMMAND_COPY);
278 wait_for_completion(&test->irq_raised);
280 dst_crc32 = crc32_le(~0, dst_addr, size);
281 if (dst_crc32 == src_crc32)
284 dma_free_coherent(dev, size + alignment, orig_dst_addr,
288 dma_free_coherent(dev, size + alignment, orig_src_addr,
295 static bool pci_endpoint_test_write(struct pci_endpoint_test *test, size_t size)
300 dma_addr_t phys_addr;
301 struct pci_dev *pdev = test->pdev;
302 struct device *dev = &pdev->dev;
304 dma_addr_t orig_phys_addr;
306 size_t alignment = test->alignment;
309 orig_addr = dma_alloc_coherent(dev, size + alignment, &orig_phys_addr,
312 dev_err(dev, "failed to allocate address\n");
317 if (alignment && !IS_ALIGNED(orig_phys_addr, alignment)) {
318 phys_addr = PTR_ALIGN(orig_phys_addr, alignment);
319 offset = phys_addr - orig_phys_addr;
320 addr = orig_addr + offset;
322 phys_addr = orig_phys_addr;
326 get_random_bytes(addr, size);
328 crc32 = crc32_le(~0, addr, size);
329 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_CHECKSUM,
332 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR,
333 lower_32_bits(phys_addr));
334 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR,
335 upper_32_bits(phys_addr));
337 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
339 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
340 1 << MSI_NUMBER_SHIFT | COMMAND_READ);
342 wait_for_completion(&test->irq_raised);
344 reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS);
345 if (reg & STATUS_READ_SUCCESS)
348 dma_free_coherent(dev, size + alignment, orig_addr, orig_phys_addr);
354 static bool pci_endpoint_test_read(struct pci_endpoint_test *test, size_t size)
358 dma_addr_t phys_addr;
359 struct pci_dev *pdev = test->pdev;
360 struct device *dev = &pdev->dev;
362 dma_addr_t orig_phys_addr;
364 size_t alignment = test->alignment;
367 orig_addr = dma_alloc_coherent(dev, size + alignment, &orig_phys_addr,
370 dev_err(dev, "failed to allocate destination address\n");
375 if (alignment && !IS_ALIGNED(orig_phys_addr, alignment)) {
376 phys_addr = PTR_ALIGN(orig_phys_addr, alignment);
377 offset = phys_addr - orig_phys_addr;
378 addr = orig_addr + offset;
380 phys_addr = orig_phys_addr;
384 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR,
385 lower_32_bits(phys_addr));
386 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR,
387 upper_32_bits(phys_addr));
389 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
391 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
392 1 << MSI_NUMBER_SHIFT | COMMAND_WRITE);
394 wait_for_completion(&test->irq_raised);
396 crc32 = crc32_le(~0, addr, size);
397 if (crc32 == pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_CHECKSUM))
400 dma_free_coherent(dev, size + alignment, orig_addr, orig_phys_addr);
405 static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd,
410 struct pci_endpoint_test *test = to_endpoint_test(file->private_data);
412 mutex_lock(&test->mutex);
416 if (bar < 0 || bar > 5)
418 ret = pci_endpoint_test_bar(test, bar);
420 case PCITEST_LEGACY_IRQ:
421 ret = pci_endpoint_test_legacy_irq(test);
424 ret = pci_endpoint_test_msi_irq(test, arg);
427 ret = pci_endpoint_test_write(test, arg);
430 ret = pci_endpoint_test_read(test, arg);
433 ret = pci_endpoint_test_copy(test, arg);
438 mutex_unlock(&test->mutex);
442 static const struct file_operations pci_endpoint_test_fops = {
443 .owner = THIS_MODULE,
444 .unlocked_ioctl = pci_endpoint_test_ioctl,
447 static int pci_endpoint_test_probe(struct pci_dev *pdev,
448 const struct pci_device_id *ent)
457 struct device *dev = &pdev->dev;
458 struct pci_endpoint_test *test;
459 struct pci_endpoint_test_data *data;
460 enum pci_barno test_reg_bar = BAR_0;
461 struct miscdevice *misc_device;
463 if (pci_is_bridge(pdev))
466 test = devm_kzalloc(dev, sizeof(*test), GFP_KERNEL);
470 test->test_reg_bar = 0;
474 data = (struct pci_endpoint_test_data *)ent->driver_data;
476 test_reg_bar = data->test_reg_bar;
477 test->alignment = data->alignment;
480 init_completion(&test->irq_raised);
481 mutex_init(&test->mutex);
483 err = pci_enable_device(pdev);
485 dev_err(dev, "Cannot enable PCI device\n");
489 err = pci_request_regions(pdev, DRV_MODULE_NAME);
491 dev_err(dev, "Cannot obtain PCI resources\n");
492 goto err_disable_pdev;
495 pci_set_master(pdev);
497 irq = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI);
499 dev_err(dev, "failed to get MSI interrupts\n");
501 err = devm_request_irq(dev, pdev->irq, pci_endpoint_test_irqhandler,
502 IRQF_SHARED, DRV_MODULE_NAME, test);
504 dev_err(dev, "failed to request IRQ %d\n", pdev->irq);
505 goto err_disable_msi;
508 for (i = 1; i < irq; i++) {
509 err = devm_request_irq(dev, pdev->irq + i,
510 pci_endpoint_test_irqhandler,
511 IRQF_SHARED, DRV_MODULE_NAME, test);
513 dev_err(dev, "failed to request IRQ %d for MSI %d\n",
514 pdev->irq + i, i + 1);
517 for (bar = BAR_0; bar <= BAR_5; bar++) {
518 base = pci_ioremap_bar(pdev, bar);
520 dev_err(dev, "failed to read BAR%d\n", bar);
521 WARN_ON(bar == test_reg_bar);
523 test->bar[bar] = base;
526 test->base = test->bar[test_reg_bar];
528 dev_err(dev, "Cannot perform PCI test without BAR%d\n",
533 pci_set_drvdata(pdev, test);
535 id = ida_simple_get(&pci_endpoint_test_ida, 0, 0, GFP_KERNEL);
537 dev_err(dev, "unable to get id\n");
541 snprintf(name, sizeof(name), DRV_MODULE_NAME ".%d", id);
542 misc_device = &test->miscdev;
543 misc_device->minor = MISC_DYNAMIC_MINOR;
544 misc_device->name = name;
545 misc_device->fops = &pci_endpoint_test_fops,
547 err = misc_register(misc_device);
549 dev_err(dev, "failed to register device\n");
556 ida_simple_remove(&pci_endpoint_test_ida, id);
559 for (bar = BAR_0; bar <= BAR_5; bar++) {
561 pci_iounmap(pdev, test->bar[bar]);
565 pci_disable_msi(pdev);
566 pci_release_regions(pdev);
569 pci_disable_device(pdev);
574 static void pci_endpoint_test_remove(struct pci_dev *pdev)
578 struct pci_endpoint_test *test = pci_get_drvdata(pdev);
579 struct miscdevice *misc_device = &test->miscdev;
581 if (sscanf(misc_device->name, DRV_MODULE_NAME ".%d", &id) != 1)
584 misc_deregister(&test->miscdev);
585 ida_simple_remove(&pci_endpoint_test_ida, id);
586 for (bar = BAR_0; bar <= BAR_5; bar++) {
588 pci_iounmap(pdev, test->bar[bar]);
590 pci_disable_msi(pdev);
591 pci_release_regions(pdev);
592 pci_disable_device(pdev);
595 static const struct pci_device_id pci_endpoint_test_tbl[] = {
596 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x) },
597 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x) },
600 MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);
602 static struct pci_driver pci_endpoint_test_driver = {
603 .name = DRV_MODULE_NAME,
604 .id_table = pci_endpoint_test_tbl,
605 .probe = pci_endpoint_test_probe,
606 .remove = pci_endpoint_test_remove,
608 module_pci_driver(pci_endpoint_test_driver);
610 MODULE_DESCRIPTION("PCI ENDPOINT TEST HOST DRIVER");
611 MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
612 MODULE_LICENSE("GPL v2");