1 // SPDX-License-Identifier: GPL-2.0-only
3 * Host side test driver to test endpoint functionality
5 * Copyright (C) 2017 Texas Instruments
6 * Author: Kishon Vijay Abraham I <kishon@ti.com>
9 #include <linux/crc32.h>
10 #include <linux/delay.h>
13 #include <linux/interrupt.h>
14 #include <linux/irq.h>
15 #include <linux/miscdevice.h>
16 #include <linux/module.h>
17 #include <linux/mutex.h>
18 #include <linux/random.h>
19 #include <linux/slab.h>
20 #include <linux/uaccess.h>
21 #include <linux/pci.h>
22 #include <linux/pci_ids.h>
24 #include <linux/pci_regs.h>
26 #include <uapi/linux/pcitest.h>
28 #define DRV_MODULE_NAME "pci-endpoint-test"
30 #define IRQ_TYPE_UNDEFINED -1
31 #define IRQ_TYPE_INTX 0
32 #define IRQ_TYPE_MSI 1
33 #define IRQ_TYPE_MSIX 2
35 #define PCI_ENDPOINT_TEST_MAGIC 0x0
37 #define PCI_ENDPOINT_TEST_COMMAND 0x4
38 #define COMMAND_RAISE_INTX_IRQ BIT(0)
39 #define COMMAND_RAISE_MSI_IRQ BIT(1)
40 #define COMMAND_RAISE_MSIX_IRQ BIT(2)
41 #define COMMAND_READ BIT(3)
42 #define COMMAND_WRITE BIT(4)
43 #define COMMAND_COPY BIT(5)
45 #define PCI_ENDPOINT_TEST_STATUS 0x8
46 #define STATUS_READ_SUCCESS BIT(0)
47 #define STATUS_READ_FAIL BIT(1)
48 #define STATUS_WRITE_SUCCESS BIT(2)
49 #define STATUS_WRITE_FAIL BIT(3)
50 #define STATUS_COPY_SUCCESS BIT(4)
51 #define STATUS_COPY_FAIL BIT(5)
52 #define STATUS_IRQ_RAISED BIT(6)
53 #define STATUS_SRC_ADDR_INVALID BIT(7)
54 #define STATUS_DST_ADDR_INVALID BIT(8)
56 #define PCI_ENDPOINT_TEST_LOWER_SRC_ADDR 0x0c
57 #define PCI_ENDPOINT_TEST_UPPER_SRC_ADDR 0x10
59 #define PCI_ENDPOINT_TEST_LOWER_DST_ADDR 0x14
60 #define PCI_ENDPOINT_TEST_UPPER_DST_ADDR 0x18
62 #define PCI_ENDPOINT_TEST_SIZE 0x1c
63 #define PCI_ENDPOINT_TEST_CHECKSUM 0x20
65 #define PCI_ENDPOINT_TEST_IRQ_TYPE 0x24
66 #define PCI_ENDPOINT_TEST_IRQ_NUMBER 0x28
68 #define PCI_ENDPOINT_TEST_FLAGS 0x2c
69 #define FLAG_USE_DMA BIT(0)
71 #define PCI_DEVICE_ID_TI_AM654 0xb00c
72 #define PCI_DEVICE_ID_TI_J7200 0xb00f
73 #define PCI_DEVICE_ID_TI_AM64 0xb010
74 #define PCI_DEVICE_ID_TI_J721S2 0xb013
75 #define PCI_DEVICE_ID_LS1088A 0x80c0
76 #define PCI_DEVICE_ID_IMX8 0x0808
78 #define is_am654_pci_dev(pdev) \
79 ((pdev)->device == PCI_DEVICE_ID_TI_AM654)
81 #define PCI_DEVICE_ID_RENESAS_R8A774A1 0x0028
82 #define PCI_DEVICE_ID_RENESAS_R8A774B1 0x002b
83 #define PCI_DEVICE_ID_RENESAS_R8A774C0 0x002d
84 #define PCI_DEVICE_ID_RENESAS_R8A774E1 0x0025
85 #define PCI_DEVICE_ID_RENESAS_R8A779F0 0x0031
87 static DEFINE_IDA(pci_endpoint_test_ida);
89 #define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \
93 module_param(no_msi, bool, 0444);
94 MODULE_PARM_DESC(no_msi, "Disable MSI interrupt in pci_endpoint_test");
96 static int irq_type = IRQ_TYPE_MSI;
97 module_param(irq_type, int, 0444);
98 MODULE_PARM_DESC(irq_type, "IRQ mode selection in pci_endpoint_test (0 - Legacy, 1 - MSI, 2 - MSI-X)");
109 struct pci_endpoint_test {
110 struct pci_dev *pdev;
112 void __iomem *bar[PCI_STD_NUM_BARS];
113 struct completion irq_raised;
117 /* mutex to protect the ioctls */
119 struct miscdevice miscdev;
120 enum pci_barno test_reg_bar;
125 struct pci_endpoint_test_data {
126 enum pci_barno test_reg_bar;
131 static inline u32 pci_endpoint_test_readl(struct pci_endpoint_test *test,
134 return readl(test->base + offset);
137 static inline void pci_endpoint_test_writel(struct pci_endpoint_test *test,
138 u32 offset, u32 value)
140 writel(value, test->base + offset);
143 static inline u32 pci_endpoint_test_bar_readl(struct pci_endpoint_test *test,
146 return readl(test->bar[bar] + offset);
149 static inline void pci_endpoint_test_bar_writel(struct pci_endpoint_test *test,
150 int bar, u32 offset, u32 value)
152 writel(value, test->bar[bar] + offset);
155 static irqreturn_t pci_endpoint_test_irqhandler(int irq, void *dev_id)
157 struct pci_endpoint_test *test = dev_id;
160 reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS);
161 if (reg & STATUS_IRQ_RAISED) {
162 test->last_irq = irq;
163 complete(&test->irq_raised);
169 static void pci_endpoint_test_free_irq_vectors(struct pci_endpoint_test *test)
171 struct pci_dev *pdev = test->pdev;
173 pci_free_irq_vectors(pdev);
174 test->irq_type = IRQ_TYPE_UNDEFINED;
177 static bool pci_endpoint_test_alloc_irq_vectors(struct pci_endpoint_test *test,
181 struct pci_dev *pdev = test->pdev;
182 struct device *dev = &pdev->dev;
187 irq = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_INTX);
189 dev_err(dev, "Failed to get Legacy interrupt\n");
192 irq = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI);
194 dev_err(dev, "Failed to get MSI interrupts\n");
197 irq = pci_alloc_irq_vectors(pdev, 1, 2048, PCI_IRQ_MSIX);
199 dev_err(dev, "Failed to get MSI-X interrupts\n");
202 dev_err(dev, "Invalid IRQ type selected\n");
210 test->irq_type = type;
211 test->num_irqs = irq;
216 static void pci_endpoint_test_release_irq(struct pci_endpoint_test *test)
219 struct pci_dev *pdev = test->pdev;
220 struct device *dev = &pdev->dev;
222 for (i = 0; i < test->num_irqs; i++)
223 devm_free_irq(dev, pci_irq_vector(pdev, i), test);
228 static bool pci_endpoint_test_request_irq(struct pci_endpoint_test *test)
232 struct pci_dev *pdev = test->pdev;
233 struct device *dev = &pdev->dev;
235 for (i = 0; i < test->num_irqs; i++) {
236 err = devm_request_irq(dev, pci_irq_vector(pdev, i),
237 pci_endpoint_test_irqhandler,
238 IRQF_SHARED, test->name, test);
248 dev_err(dev, "Failed to request IRQ %d for Legacy\n",
249 pci_irq_vector(pdev, i));
252 dev_err(dev, "Failed to request IRQ %d for MSI %d\n",
253 pci_irq_vector(pdev, i),
257 dev_err(dev, "Failed to request IRQ %d for MSI-X %d\n",
258 pci_irq_vector(pdev, i),
266 static const u32 bar_test_pattern[] = {
275 static bool pci_endpoint_test_bar(struct pci_endpoint_test *test,
276 enum pci_barno barno)
281 struct pci_dev *pdev = test->pdev;
283 if (!test->bar[barno])
286 size = pci_resource_len(pdev, barno);
288 if (barno == test->test_reg_bar)
291 for (j = 0; j < size; j += 4)
292 pci_endpoint_test_bar_writel(test, barno, j,
293 bar_test_pattern[barno]);
295 for (j = 0; j < size; j += 4) {
296 val = pci_endpoint_test_bar_readl(test, barno, j);
297 if (val != bar_test_pattern[barno])
304 static bool pci_endpoint_test_intx_irq(struct pci_endpoint_test *test)
308 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
310 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 0);
311 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
312 COMMAND_RAISE_INTX_IRQ);
313 val = wait_for_completion_timeout(&test->irq_raised,
314 msecs_to_jiffies(1000));
321 static bool pci_endpoint_test_msi_irq(struct pci_endpoint_test *test,
322 u16 msi_num, bool msix)
325 struct pci_dev *pdev = test->pdev;
327 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
328 msix ? IRQ_TYPE_MSIX : IRQ_TYPE_MSI);
329 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, msi_num);
330 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
331 msix ? COMMAND_RAISE_MSIX_IRQ :
332 COMMAND_RAISE_MSI_IRQ);
333 val = wait_for_completion_timeout(&test->irq_raised,
334 msecs_to_jiffies(1000));
338 return pci_irq_vector(pdev, msi_num - 1) == test->last_irq;
341 static int pci_endpoint_test_validate_xfer_params(struct device *dev,
342 struct pci_endpoint_test_xfer_param *param, size_t alignment)
345 dev_dbg(dev, "Data size is zero\n");
349 if (param->size > SIZE_MAX - alignment) {
350 dev_dbg(dev, "Maximum transfer data size exceeded\n");
357 static bool pci_endpoint_test_copy(struct pci_endpoint_test *test,
360 struct pci_endpoint_test_xfer_param param;
367 dma_addr_t src_phys_addr;
368 dma_addr_t dst_phys_addr;
369 struct pci_dev *pdev = test->pdev;
370 struct device *dev = &pdev->dev;
372 dma_addr_t orig_src_phys_addr;
374 dma_addr_t orig_dst_phys_addr;
376 size_t alignment = test->alignment;
377 int irq_type = test->irq_type;
382 err = copy_from_user(¶m, (void __user *)arg, sizeof(param));
384 dev_err(dev, "Failed to get transfer param\n");
388 err = pci_endpoint_test_validate_xfer_params(dev, ¶m, alignment);
394 use_dma = !!(param.flags & PCITEST_FLAGS_USE_DMA);
396 flags |= FLAG_USE_DMA;
398 if (irq_type < IRQ_TYPE_INTX || irq_type > IRQ_TYPE_MSIX) {
399 dev_err(dev, "Invalid IRQ type option\n");
403 orig_src_addr = kzalloc(size + alignment, GFP_KERNEL);
404 if (!orig_src_addr) {
405 dev_err(dev, "Failed to allocate source buffer\n");
410 get_random_bytes(orig_src_addr, size + alignment);
411 orig_src_phys_addr = dma_map_single(dev, orig_src_addr,
412 size + alignment, DMA_TO_DEVICE);
413 if (dma_mapping_error(dev, orig_src_phys_addr)) {
414 dev_err(dev, "failed to map source buffer address\n");
416 goto err_src_phys_addr;
419 if (alignment && !IS_ALIGNED(orig_src_phys_addr, alignment)) {
420 src_phys_addr = PTR_ALIGN(orig_src_phys_addr, alignment);
421 offset = src_phys_addr - orig_src_phys_addr;
422 src_addr = orig_src_addr + offset;
424 src_phys_addr = orig_src_phys_addr;
425 src_addr = orig_src_addr;
428 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR,
429 lower_32_bits(src_phys_addr));
431 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR,
432 upper_32_bits(src_phys_addr));
434 src_crc32 = crc32_le(~0, src_addr, size);
436 orig_dst_addr = kzalloc(size + alignment, GFP_KERNEL);
437 if (!orig_dst_addr) {
438 dev_err(dev, "Failed to allocate destination address\n");
443 orig_dst_phys_addr = dma_map_single(dev, orig_dst_addr,
444 size + alignment, DMA_FROM_DEVICE);
445 if (dma_mapping_error(dev, orig_dst_phys_addr)) {
446 dev_err(dev, "failed to map destination buffer address\n");
448 goto err_dst_phys_addr;
451 if (alignment && !IS_ALIGNED(orig_dst_phys_addr, alignment)) {
452 dst_phys_addr = PTR_ALIGN(orig_dst_phys_addr, alignment);
453 offset = dst_phys_addr - orig_dst_phys_addr;
454 dst_addr = orig_dst_addr + offset;
456 dst_phys_addr = orig_dst_phys_addr;
457 dst_addr = orig_dst_addr;
460 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR,
461 lower_32_bits(dst_phys_addr));
462 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR,
463 upper_32_bits(dst_phys_addr));
465 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE,
468 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_FLAGS, flags);
469 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
470 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
471 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
474 wait_for_completion(&test->irq_raised);
476 dma_unmap_single(dev, orig_dst_phys_addr, size + alignment,
479 dst_crc32 = crc32_le(~0, dst_addr, size);
480 if (dst_crc32 == src_crc32)
484 kfree(orig_dst_addr);
487 dma_unmap_single(dev, orig_src_phys_addr, size + alignment,
491 kfree(orig_src_addr);
497 static bool pci_endpoint_test_write(struct pci_endpoint_test *test,
500 struct pci_endpoint_test_xfer_param param;
506 dma_addr_t phys_addr;
507 struct pci_dev *pdev = test->pdev;
508 struct device *dev = &pdev->dev;
510 dma_addr_t orig_phys_addr;
512 size_t alignment = test->alignment;
513 int irq_type = test->irq_type;
518 err = copy_from_user(¶m, (void __user *)arg, sizeof(param));
520 dev_err(dev, "Failed to get transfer param\n");
524 err = pci_endpoint_test_validate_xfer_params(dev, ¶m, alignment);
530 use_dma = !!(param.flags & PCITEST_FLAGS_USE_DMA);
532 flags |= FLAG_USE_DMA;
534 if (irq_type < IRQ_TYPE_INTX || irq_type > IRQ_TYPE_MSIX) {
535 dev_err(dev, "Invalid IRQ type option\n");
539 orig_addr = kzalloc(size + alignment, GFP_KERNEL);
541 dev_err(dev, "Failed to allocate address\n");
546 get_random_bytes(orig_addr, size + alignment);
548 orig_phys_addr = dma_map_single(dev, orig_addr, size + alignment,
550 if (dma_mapping_error(dev, orig_phys_addr)) {
551 dev_err(dev, "failed to map source buffer address\n");
556 if (alignment && !IS_ALIGNED(orig_phys_addr, alignment)) {
557 phys_addr = PTR_ALIGN(orig_phys_addr, alignment);
558 offset = phys_addr - orig_phys_addr;
559 addr = orig_addr + offset;
561 phys_addr = orig_phys_addr;
565 crc32 = crc32_le(~0, addr, size);
566 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_CHECKSUM,
569 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR,
570 lower_32_bits(phys_addr));
571 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR,
572 upper_32_bits(phys_addr));
574 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
576 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_FLAGS, flags);
577 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
578 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
579 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
582 wait_for_completion(&test->irq_raised);
584 reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS);
585 if (reg & STATUS_READ_SUCCESS)
588 dma_unmap_single(dev, orig_phys_addr, size + alignment,
598 static bool pci_endpoint_test_read(struct pci_endpoint_test *test,
601 struct pci_endpoint_test_xfer_param param;
607 dma_addr_t phys_addr;
608 struct pci_dev *pdev = test->pdev;
609 struct device *dev = &pdev->dev;
611 dma_addr_t orig_phys_addr;
613 size_t alignment = test->alignment;
614 int irq_type = test->irq_type;
618 err = copy_from_user(¶m, (void __user *)arg, sizeof(param));
620 dev_err(dev, "Failed to get transfer param\n");
624 err = pci_endpoint_test_validate_xfer_params(dev, ¶m, alignment);
630 use_dma = !!(param.flags & PCITEST_FLAGS_USE_DMA);
632 flags |= FLAG_USE_DMA;
634 if (irq_type < IRQ_TYPE_INTX || irq_type > IRQ_TYPE_MSIX) {
635 dev_err(dev, "Invalid IRQ type option\n");
639 orig_addr = kzalloc(size + alignment, GFP_KERNEL);
641 dev_err(dev, "Failed to allocate destination address\n");
646 orig_phys_addr = dma_map_single(dev, orig_addr, size + alignment,
648 if (dma_mapping_error(dev, orig_phys_addr)) {
649 dev_err(dev, "failed to map source buffer address\n");
654 if (alignment && !IS_ALIGNED(orig_phys_addr, alignment)) {
655 phys_addr = PTR_ALIGN(orig_phys_addr, alignment);
656 offset = phys_addr - orig_phys_addr;
657 addr = orig_addr + offset;
659 phys_addr = orig_phys_addr;
663 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR,
664 lower_32_bits(phys_addr));
665 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR,
666 upper_32_bits(phys_addr));
668 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
670 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_FLAGS, flags);
671 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
672 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
673 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
676 wait_for_completion(&test->irq_raised);
678 dma_unmap_single(dev, orig_phys_addr, size + alignment,
681 crc32 = crc32_le(~0, addr, size);
682 if (crc32 == pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_CHECKSUM))
691 static bool pci_endpoint_test_clear_irq(struct pci_endpoint_test *test)
693 pci_endpoint_test_release_irq(test);
694 pci_endpoint_test_free_irq_vectors(test);
698 static bool pci_endpoint_test_set_irq(struct pci_endpoint_test *test,
701 struct pci_dev *pdev = test->pdev;
702 struct device *dev = &pdev->dev;
704 if (req_irq_type < IRQ_TYPE_INTX || req_irq_type > IRQ_TYPE_MSIX) {
705 dev_err(dev, "Invalid IRQ type option\n");
709 if (test->irq_type == req_irq_type)
712 pci_endpoint_test_release_irq(test);
713 pci_endpoint_test_free_irq_vectors(test);
715 if (!pci_endpoint_test_alloc_irq_vectors(test, req_irq_type))
718 if (!pci_endpoint_test_request_irq(test))
724 pci_endpoint_test_free_irq_vectors(test);
728 static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd,
733 struct pci_endpoint_test *test = to_endpoint_test(file->private_data);
734 struct pci_dev *pdev = test->pdev;
736 mutex_lock(&test->mutex);
738 reinit_completion(&test->irq_raised);
739 test->last_irq = -ENODATA;
746 if (is_am654_pci_dev(pdev) && bar == BAR_0)
748 ret = pci_endpoint_test_bar(test, bar);
750 case PCITEST_INTX_IRQ:
751 ret = pci_endpoint_test_intx_irq(test);
755 ret = pci_endpoint_test_msi_irq(test, arg, cmd == PCITEST_MSIX);
758 ret = pci_endpoint_test_write(test, arg);
761 ret = pci_endpoint_test_read(test, arg);
764 ret = pci_endpoint_test_copy(test, arg);
766 case PCITEST_SET_IRQTYPE:
767 ret = pci_endpoint_test_set_irq(test, arg);
769 case PCITEST_GET_IRQTYPE:
772 case PCITEST_CLEAR_IRQ:
773 ret = pci_endpoint_test_clear_irq(test);
778 mutex_unlock(&test->mutex);
782 static const struct file_operations pci_endpoint_test_fops = {
783 .owner = THIS_MODULE,
784 .unlocked_ioctl = pci_endpoint_test_ioctl,
787 static int pci_endpoint_test_probe(struct pci_dev *pdev,
788 const struct pci_device_id *ent)
795 struct device *dev = &pdev->dev;
796 struct pci_endpoint_test *test;
797 struct pci_endpoint_test_data *data;
798 enum pci_barno test_reg_bar = BAR_0;
799 struct miscdevice *misc_device;
801 if (pci_is_bridge(pdev))
804 test = devm_kzalloc(dev, sizeof(*test), GFP_KERNEL);
808 test->test_reg_bar = 0;
811 test->irq_type = IRQ_TYPE_UNDEFINED;
814 irq_type = IRQ_TYPE_INTX;
816 data = (struct pci_endpoint_test_data *)ent->driver_data;
818 test_reg_bar = data->test_reg_bar;
819 test->test_reg_bar = test_reg_bar;
820 test->alignment = data->alignment;
821 irq_type = data->irq_type;
824 init_completion(&test->irq_raised);
825 mutex_init(&test->mutex);
827 if ((dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(48)) != 0) &&
828 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
829 dev_err(dev, "Cannot set DMA mask\n");
833 err = pci_enable_device(pdev);
835 dev_err(dev, "Cannot enable PCI device\n");
839 err = pci_request_regions(pdev, DRV_MODULE_NAME);
841 dev_err(dev, "Cannot obtain PCI resources\n");
842 goto err_disable_pdev;
845 pci_set_master(pdev);
847 if (!pci_endpoint_test_alloc_irq_vectors(test, irq_type)) {
849 goto err_disable_irq;
852 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
853 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
854 base = pci_ioremap_bar(pdev, bar);
856 dev_err(dev, "Failed to read BAR%d\n", bar);
857 WARN_ON(bar == test_reg_bar);
859 test->bar[bar] = base;
863 test->base = test->bar[test_reg_bar];
866 dev_err(dev, "Cannot perform PCI test without BAR%d\n",
871 pci_set_drvdata(pdev, test);
873 id = ida_alloc(&pci_endpoint_test_ida, GFP_KERNEL);
876 dev_err(dev, "Unable to get id\n");
880 snprintf(name, sizeof(name), DRV_MODULE_NAME ".%d", id);
881 test->name = kstrdup(name, GFP_KERNEL);
887 if (!pci_endpoint_test_request_irq(test)) {
889 goto err_kfree_test_name;
892 misc_device = &test->miscdev;
893 misc_device->minor = MISC_DYNAMIC_MINOR;
894 misc_device->name = kstrdup(name, GFP_KERNEL);
895 if (!misc_device->name) {
897 goto err_release_irq;
899 misc_device->parent = &pdev->dev;
900 misc_device->fops = &pci_endpoint_test_fops;
902 err = misc_register(misc_device);
904 dev_err(dev, "Failed to register device\n");
911 kfree(misc_device->name);
914 pci_endpoint_test_release_irq(test);
920 ida_free(&pci_endpoint_test_ida, id);
923 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
925 pci_iounmap(pdev, test->bar[bar]);
929 pci_endpoint_test_free_irq_vectors(test);
930 pci_release_regions(pdev);
933 pci_disable_device(pdev);
938 static void pci_endpoint_test_remove(struct pci_dev *pdev)
942 struct pci_endpoint_test *test = pci_get_drvdata(pdev);
943 struct miscdevice *misc_device = &test->miscdev;
945 if (sscanf(misc_device->name, DRV_MODULE_NAME ".%d", &id) != 1)
950 pci_endpoint_test_release_irq(test);
951 pci_endpoint_test_free_irq_vectors(test);
953 misc_deregister(&test->miscdev);
954 kfree(misc_device->name);
956 ida_free(&pci_endpoint_test_ida, id);
957 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
959 pci_iounmap(pdev, test->bar[bar]);
962 pci_release_regions(pdev);
963 pci_disable_device(pdev);
966 static const struct pci_endpoint_test_data default_data = {
967 .test_reg_bar = BAR_0,
969 .irq_type = IRQ_TYPE_MSI,
972 static const struct pci_endpoint_test_data am654_data = {
973 .test_reg_bar = BAR_2,
975 .irq_type = IRQ_TYPE_MSI,
978 static const struct pci_endpoint_test_data j721e_data = {
980 .irq_type = IRQ_TYPE_MSI,
983 static const struct pci_device_id pci_endpoint_test_tbl[] = {
984 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x),
985 .driver_data = (kernel_ulong_t)&default_data,
987 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x),
988 .driver_data = (kernel_ulong_t)&default_data,
990 { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0x81c0),
991 .driver_data = (kernel_ulong_t)&default_data,
993 { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_IMX8),},
994 { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_LS1088A),
995 .driver_data = (kernel_ulong_t)&default_data,
997 { PCI_DEVICE_DATA(SYNOPSYS, EDDA, NULL) },
998 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654),
999 .driver_data = (kernel_ulong_t)&am654_data
1001 { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774A1),},
1002 { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774B1),},
1003 { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774C0),},
1004 { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774E1),},
1005 { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A779F0),
1006 .driver_data = (kernel_ulong_t)&default_data,
1008 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J721E),
1009 .driver_data = (kernel_ulong_t)&j721e_data,
1011 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J7200),
1012 .driver_data = (kernel_ulong_t)&j721e_data,
1014 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM64),
1015 .driver_data = (kernel_ulong_t)&j721e_data,
1017 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J721S2),
1018 .driver_data = (kernel_ulong_t)&j721e_data,
1022 MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);
1024 static struct pci_driver pci_endpoint_test_driver = {
1025 .name = DRV_MODULE_NAME,
1026 .id_table = pci_endpoint_test_tbl,
1027 .probe = pci_endpoint_test_probe,
1028 .remove = pci_endpoint_test_remove,
1029 .sriov_configure = pci_sriov_configure_simple,
1031 module_pci_driver(pci_endpoint_test_driver);
1033 MODULE_DESCRIPTION("PCI ENDPOINT TEST HOST DRIVER");
1034 MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
1035 MODULE_LICENSE("GPL v2");