drivers/misc/mei/pci-me.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2003-2022, Intel Corporation. All rights reserved.
   4  * Intel Management Engine Interface (Intel MEI) Linux driver
   5  */
   6
   7 #include <linux/module.h>
   8 #include <linux/kernel.h>
   9 #include <linux/device.h>
  10 #include <linux/errno.h>
  11 #include <linux/types.h>
  12 #include <linux/pci.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/sched.h>
  15 #include <linux/interrupt.h>
  16
  17 #include <linux/pm_domain.h>
  18 #include <linux/pm_runtime.h>
  19
  20 #include <linux/mei.h>
  21
  22 #include "mei_dev.h"
  23 #include "client.h"
  24 #include "hw-me-regs.h"
  25 #include "hw-me.h"
  26
  27 /* mei_pci_tbl - PCI Device ID Table */
  28 static const struct pci_device_id mei_me_pci_tbl[] = {
  29         {MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)},
  30         {MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)},
  31         {MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)},
  32         {MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)},
  33         {MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)},
  34         {MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)},
  35         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)},
  36         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)},
  37         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)},
  38         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)},
  39         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)},
  40
  41         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)},
  42         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)},
  43         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)},
  44         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)},
  45         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)},
  46         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)},
  47         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)},
  48         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)},
  49         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)},
  50
  51         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)},
  52         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)},
  53         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)},
  54         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)},
  55
  56         {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH6_CFG)},
  57         {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH6_CFG)},
  58         {MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)},
  59         {MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)},
  60         {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH7_CFG)},
  61         {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH7_CFG)},
  62         {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH7_CFG)},
  63         {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_4_CFG)},
  64         {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_4_CFG)},
  65         {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)},
  66         {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_4_CFG)},
  67         {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)},
  68         {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)},
  69
  70         {MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)},
  71         {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)},
  72         {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_3, MEI_ME_PCH8_ITOUCH_CFG)},
  73         {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_4_CFG)},
  74         {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_4_CFG)},
  75         {MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_SPS_4_CFG)},
  76
  77         {MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)},
  78         {MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)},
  79
  80         {MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE, MEI_ME_PCH8_CFG)},
  81
  82         {MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)},
  83
  84         {MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)},
  85         {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)},
  86         {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_3, MEI_ME_PCH8_CFG)},
  87
  88         {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)},
  89         {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)},
  90         {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_SPS_CFG)},
  91         {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_3, MEI_ME_PCH12_SPS_ITOUCH_CFG)},
  92
  93         {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP, MEI_ME_PCH12_CFG)},
  94         {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)},
  95         {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_V, MEI_ME_PCH12_CFG)},
  96         {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H, MEI_ME_PCH12_CFG)},
  97         {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H_3, MEI_ME_PCH8_ITOUCH_CFG)},
  98
  99         {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)},
 100         {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_N, MEI_ME_PCH12_CFG)},
 101
 102         {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH15_CFG)},
 103         {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_H, MEI_ME_PCH15_SPS_CFG)},
 104
 105         {MEI_PCI_DEVICE(MEI_DEV_ID_JSP_N, MEI_ME_PCH15_CFG)},
 106
 107         {MEI_PCI_DEVICE(MEI_DEV_ID_MCC, MEI_ME_PCH15_CFG)},
 108         {MEI_PCI_DEVICE(MEI_DEV_ID_MCC_4, MEI_ME_PCH8_CFG)},
 109
 110         {MEI_PCI_DEVICE(MEI_DEV_ID_CDF, MEI_ME_PCH8_CFG)},
 111
 112         {MEI_PCI_DEVICE(MEI_DEV_ID_EBG, MEI_ME_PCH15_SPS_CFG)},
 113
 114         {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_S, MEI_ME_PCH15_CFG)},
 115         {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_LP, MEI_ME_PCH15_CFG)},
 116         {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_P, MEI_ME_PCH15_CFG)},
 117         {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_N, MEI_ME_PCH15_CFG)},
 118
 119         {MEI_PCI_DEVICE(MEI_DEV_ID_RPL_S, MEI_ME_PCH15_CFG)},
 120
 121         {MEI_PCI_DEVICE(MEI_DEV_ID_MTL_M, MEI_ME_PCH15_CFG)},
 122         {MEI_PCI_DEVICE(MEI_DEV_ID_ARL_S, MEI_ME_PCH15_CFG)},
 123         {MEI_PCI_DEVICE(MEI_DEV_ID_ARL_H, MEI_ME_PCH15_CFG)},
 124
 125         /* required last entry */
 126         {0, }
 127 };
 128
 129 MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);
 130
 131 #ifdef CONFIG_PM
 132 static inline void mei_me_set_pm_domain(struct mei_device *dev);
 133 static inline void mei_me_unset_pm_domain(struct mei_device *dev);
 134 #else
 135 static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
 136 static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
 137 #endif /* CONFIG_PM */
 138
 139 static int mei_me_read_fws(const struct mei_device *dev, int where, u32 *val)
 140 {
 141         struct pci_dev *pdev = to_pci_dev(dev->dev);
 142
 143         return pci_read_config_dword(pdev, where, val);
 144 }
 145
 146 /**
 147  * mei_me_quirk_probe - probe for devices that doesn't valid ME interface
 148  *
 149  * @pdev: PCI device structure
 150  * @cfg: per generation config
 151  *
 152  * Return: true if ME Interface is valid, false otherwise
 153  */
 154 static bool mei_me_quirk_probe(struct pci_dev *pdev,
 155                                 const struct mei_cfg *cfg)
 156 {
 157         if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
 158                 dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
 159                 return false;
 160         }
 161
 162         return true;
 163 }
 164
 165 /**
 166  * mei_me_probe - Device Initialization Routine
 167  *
 168  * @pdev: PCI device structure
 169  * @ent: entry in kcs_pci_tbl
 170  *
 171  * Return: 0 on success, <0 on failure.
 172  */
 173 static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 174 {
 175         const struct mei_cfg *cfg;
 176         struct mei_device *dev;
 177         struct mei_me_hw *hw;
 178         unsigned int irqflags;
 179         int err;
 180
 181         cfg = mei_me_get_cfg(ent->driver_data);
 182         if (!cfg)
 183                 return -ENODEV;
 184
 185         if (!mei_me_quirk_probe(pdev, cfg))
 186                 return -ENODEV;
 187
 188         /* enable pci dev */
 189         err = pcim_enable_device(pdev);
 190         if (err) {
 191                 dev_err(&pdev->dev, "failed to enable pci device.\n");
 192                 goto end;
 193         }
 194         /* set PCI host mastering  */
 195         pci_set_master(pdev);
 196         /* pci request regions and mapping IO device memory for mei driver */
 197         err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME);
 198         if (err) {
 199                 dev_err(&pdev->dev, "failed to get pci regions.\n");
 200                 goto end;
 201         }
 202
 203         err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
 204         if (err) {
 205                 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
 206                 goto end;
 207         }
 208
 209         /* allocates and initializes the mei dev structure */
 210         dev = mei_me_dev_init(&pdev->dev, cfg, false);
 211         if (!dev) {
 212                 err = -ENOMEM;
 213                 goto end;
 214         }
 215         hw = to_me_hw(dev);
 216         hw->mem_addr = pcim_iomap_table(pdev)[0];
 217         hw->read_fws = mei_me_read_fws;
 218
 219         pci_enable_msi(pdev);
 220
 221         hw->irq = pdev->irq;
 222
 223          /* request and enable interrupt */
 224         irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
 225
 226         err = request_threaded_irq(pdev->irq,
 227                         mei_me_irq_quick_handler,
 228                         mei_me_irq_thread_handler,
 229                         irqflags, KBUILD_MODNAME, dev);
 230         if (err) {
 231                 dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
 232                        pdev->irq);
 233                 goto end;
 234         }
 235
 236         if (mei_start(dev)) {
 237                 dev_err(&pdev->dev, "init hw failure.\n");
 238                 err = -ENODEV;
 239                 goto release_irq;
 240         }
 241
 242         pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
 243         pm_runtime_use_autosuspend(&pdev->dev);
 244
 245         err = mei_register(dev, &pdev->dev);
 246         if (err)
 247                 goto stop;
 248
 249         pci_set_drvdata(pdev, dev);
 250
 251         /*
 252          * MEI requires to resume from runtime suspend mode
 253          * in order to perform link reset flow upon system suspend.
 254          */
 255         dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
 256
 257         /*
 258          * ME maps runtime suspend/resume to D0i states,
 259          * hence we need to go around native PCI runtime service which
 260          * eventually brings the device into D3cold/hot state,
 261          * but the mei device cannot wake up from D3 unlike from D0i3.
 262          * To get around the PCI device native runtime pm,
 263          * ME uses runtime pm domain handlers which take precedence
 264          * over the driver's pm handlers.
 265          */
 266         mei_me_set_pm_domain(dev);
 267
 268         if (mei_pg_is_enabled(dev)) {
 269                 pm_runtime_put_noidle(&pdev->dev);
 270                 if (hw->d0i3_supported)
 271                         pm_runtime_allow(&pdev->dev);
 272         }
 273
 274         dev_dbg(&pdev->dev, "initialization successful.\n");
 275
 276         return 0;
 277
 278 stop:
 279         mei_stop(dev);
 280 release_irq:
 281         mei_cancel_work(dev);
 282         mei_disable_interrupts(dev);
 283         free_irq(pdev->irq, dev);
 284 end:
 285         dev_err(&pdev->dev, "initialization failed.\n");
 286         return err;
 287 }
 288
 289 /**
 290  * mei_me_shutdown - Device Removal Routine
 291  *
 292  * @pdev: PCI device structure
 293  *
 294  * mei_me_shutdown is called from the reboot notifier
 295  * it's a simplified version of remove so we go down
 296  * faster.
 297  */
 298 static void mei_me_shutdown(struct pci_dev *pdev)
 299 {
 300         struct mei_device *dev = pci_get_drvdata(pdev);
 301
 302         dev_dbg(&pdev->dev, "shutdown\n");
 303         mei_stop(dev);
 304
 305         mei_me_unset_pm_domain(dev);
 306
 307         mei_disable_interrupts(dev);
 308         free_irq(pdev->irq, dev);
 309 }
 310
 311 /**
 312  * mei_me_remove - Device Removal Routine
 313  *
 314  * @pdev: PCI device structure
 315  *
 316  * mei_me_remove is called by the PCI subsystem to alert the driver
 317  * that it should release a PCI device.
 318  */
 319 static void mei_me_remove(struct pci_dev *pdev)
 320 {
 321         struct mei_device *dev = pci_get_drvdata(pdev);
 322
 323         if (mei_pg_is_enabled(dev))
 324                 pm_runtime_get_noresume(&pdev->dev);
 325
 326         dev_dbg(&pdev->dev, "stop\n");
 327         mei_stop(dev);
 328
 329         mei_me_unset_pm_domain(dev);
 330
 331         mei_disable_interrupts(dev);
 332
 333         free_irq(pdev->irq, dev);
 334
 335         mei_deregister(dev);
 336 }
 337
 338 #ifdef CONFIG_PM_SLEEP
 339 static int mei_me_pci_prepare(struct device *device)
 340 {
 341         pm_runtime_resume(device);
 342         return 0;
 343 }
 344
 345 static int mei_me_pci_suspend(struct device *device)
 346 {
 347         struct pci_dev *pdev = to_pci_dev(device);
 348         struct mei_device *dev = pci_get_drvdata(pdev);
 349
 350         dev_dbg(&pdev->dev, "suspend\n");
 351
 352         mei_stop(dev);
 353
 354         mei_disable_interrupts(dev);
 355
 356         free_irq(pdev->irq, dev);
 357         pci_disable_msi(pdev);
 358
 359         return 0;
 360 }
 361
 362 static int mei_me_pci_resume(struct device *device)
 363 {
 364         struct pci_dev *pdev = to_pci_dev(device);
 365         struct mei_device *dev = pci_get_drvdata(pdev);
 366         unsigned int irqflags;
 367         int err;
 368
 369         pci_enable_msi(pdev);
 370
 371         irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
 372
 373         /* request and enable interrupt */
 374         err = request_threaded_irq(pdev->irq,
 375                         mei_me_irq_quick_handler,
 376                         mei_me_irq_thread_handler,
 377                         irqflags, KBUILD_MODNAME, dev);
 378
 379         if (err) {
 380                 dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
 381                                 pdev->irq);
 382                 return err;
 383         }
 384
 385         err = mei_restart(dev);
 386         if (err)
 387                 return err;
 388
 389         /* Start timer if stopped in suspend */
 390         schedule_delayed_work(&dev->timer_work, HZ);
 391
 392         return 0;
 393 }
 394
 395 static void mei_me_pci_complete(struct device *device)
 396 {
 397         pm_runtime_suspend(device);
 398 }
 399 #else /* CONFIG_PM_SLEEP */
 400
 401 #define mei_me_pci_prepare NULL
 402 #define mei_me_pci_complete NULL
 403
 404 #endif /* !CONFIG_PM_SLEEP */
 405
 406 #ifdef CONFIG_PM
 407 static int mei_me_pm_runtime_idle(struct device *device)
 408 {
 409         struct mei_device *dev = dev_get_drvdata(device);
 410
 411         dev_dbg(device, "rpm: me: runtime_idle\n");
 412
 413         if (mei_write_is_idle(dev))
 414                 pm_runtime_autosuspend(device);
 415
 416         return -EBUSY;
 417 }
 418
 419 static int mei_me_pm_runtime_suspend(struct device *device)
 420 {
 421         struct mei_device *dev = dev_get_drvdata(device);
 422         int ret;
 423
 424         dev_dbg(device, "rpm: me: runtime suspend\n");
 425
 426         mutex_lock(&dev->device_lock);
 427
 428         if (mei_write_is_idle(dev))
 429                 ret = mei_me_pg_enter_sync(dev);
 430         else
 431                 ret = -EAGAIN;
 432
 433         mutex_unlock(&dev->device_lock);
 434
 435         dev_dbg(device, "rpm: me: runtime suspend ret=%d\n", ret);
 436
 437         if (ret && ret != -EAGAIN)
 438                 schedule_work(&dev->reset_work);
 439
 440         return ret;
 441 }
 442
 443 static int mei_me_pm_runtime_resume(struct device *device)
 444 {
 445         struct mei_device *dev = dev_get_drvdata(device);
 446         int ret;
 447
 448         dev_dbg(device, "rpm: me: runtime resume\n");
 449
 450         mutex_lock(&dev->device_lock);
 451
 452         ret = mei_me_pg_exit_sync(dev);
 453
 454         mutex_unlock(&dev->device_lock);
 455
 456         dev_dbg(device, "rpm: me: runtime resume ret = %d\n", ret);
 457
 458         if (ret)
 459                 schedule_work(&dev->reset_work);
 460
 461         return ret;
 462 }
 463
 464 /**
 465  * mei_me_set_pm_domain - fill and set pm domain structure for device
 466  *
 467  * @dev: mei_device
 468  */
 469 static inline void mei_me_set_pm_domain(struct mei_device *dev)
 470 {
 471         struct pci_dev *pdev  = to_pci_dev(dev->dev);
 472
 473         if (pdev->dev.bus && pdev->dev.bus->pm) {
 474                 dev->pg_domain.ops = *pdev->dev.bus->pm;
 475
 476                 dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
 477                 dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
 478                 dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;
 479
 480                 dev_pm_domain_set(&pdev->dev, &dev->pg_domain);
 481         }
 482 }
 483
 484 /**
 485  * mei_me_unset_pm_domain - clean pm domain structure for device
 486  *
 487  * @dev: mei_device
 488  */
 489 static inline void mei_me_unset_pm_domain(struct mei_device *dev)
 490 {
 491         /* stop using pm callbacks if any */
 492         dev_pm_domain_set(dev->dev, NULL);
 493 }
 494
 495 static const struct dev_pm_ops mei_me_pm_ops = {
 496         .prepare = mei_me_pci_prepare,
 497         .complete = mei_me_pci_complete,
 498         SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
 499                                 mei_me_pci_resume)
 500         SET_RUNTIME_PM_OPS(
 501                 mei_me_pm_runtime_suspend,
 502                 mei_me_pm_runtime_resume,
 503                 mei_me_pm_runtime_idle)
 504 };
 505
 506 #define MEI_ME_PM_OPS   (&mei_me_pm_ops)
 507 #else
 508 #define MEI_ME_PM_OPS   NULL
 509 #endif /* CONFIG_PM */
 510 /*
 511  *  PCI driver structure
 512  */
 513 static struct pci_driver mei_me_driver = {
 514         .name = KBUILD_MODNAME,
 515         .id_table = mei_me_pci_tbl,
 516         .probe = mei_me_probe,
 517         .remove = mei_me_remove,
 518         .shutdown = mei_me_shutdown,
 519         .driver.pm = MEI_ME_PM_OPS,
 520         .driver.probe_type = PROBE_PREFER_ASYNCHRONOUS,
 521 };
 522
 523 module_pci_driver(mei_me_driver);
 524
 525 MODULE_AUTHOR("Intel Corporation");
 526 MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
 527 MODULE_LICENSE("GPL v2");