3 * Intel Management Engine Interface (Intel MEI) Linux driver
4 * Copyright (c) 2003-2012, Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 #include <linux/pci.h>
19 #include <linux/kthread.h>
20 #include <linux/interrupt.h>
26 #include "hw-me-regs.h"
29 * mei_me_reg_read - Reads 32bit data from the mei device
31 * @hw: the me hardware structure
32 * @offset: offset from which to read the data
34 * Return: register value (u32)
36 static inline u32 mei_me_reg_read(const struct mei_me_hw *hw,
39 return ioread32(hw->mem_addr + offset);
44 * mei_me_reg_write - Writes 32bit data to the mei device
46 * @hw: the me hardware structure
47 * @offset: offset from which to write the data
48 * @value: register value to write (u32)
50 static inline void mei_me_reg_write(const struct mei_me_hw *hw,
51 unsigned long offset, u32 value)
53 iowrite32(value, hw->mem_addr + offset);
57 * mei_me_mecbrw_read - Reads 32bit data from ME circular buffer
58 * read window register
60 * @dev: the device structure
62 * Return: ME_CB_RW register value (u32)
64 static u32 mei_me_mecbrw_read(const struct mei_device *dev)
66 return mei_me_reg_read(to_me_hw(dev), ME_CB_RW);
69 * mei_me_mecsr_read - Reads 32bit data from the ME CSR
71 * @hw: the me hardware structure
73 * Return: ME_CSR_HA register value (u32)
75 static inline u32 mei_me_mecsr_read(const struct mei_me_hw *hw)
77 return mei_me_reg_read(hw, ME_CSR_HA);
81 * mei_hcsr_read - Reads 32bit data from the host CSR
83 * @hw: the me hardware structure
85 * Return: H_CSR register value (u32)
87 static inline u32 mei_hcsr_read(const struct mei_me_hw *hw)
89 return mei_me_reg_read(hw, H_CSR);
93 * mei_hcsr_set - writes H_CSR register to the mei device,
94 * and ignores the H_IS bit for it is write-one-to-zero.
96 * @hw: the me hardware structure
97 * @hcsr: new register value
99 static inline void mei_hcsr_set(struct mei_me_hw *hw, u32 hcsr)
102 mei_me_reg_write(hw, H_CSR, hcsr);
106 * mei_me_fw_status - read fw status register from pci config space
109 * @fw_status: fw status register values
111 * Return: 0 on success, error otherwise
113 static int mei_me_fw_status(struct mei_device *dev,
114 struct mei_fw_status *fw_status)
116 struct pci_dev *pdev = to_pci_dev(dev->dev);
117 struct mei_me_hw *hw = to_me_hw(dev);
118 const struct mei_fw_status *fw_src = &hw->cfg->fw_status;
125 fw_status->count = fw_src->count;
126 for (i = 0; i < fw_src->count && i < MEI_FW_STATUS_MAX; i++) {
127 ret = pci_read_config_dword(pdev,
128 fw_src->status[i], &fw_status->status[i]);
137 * mei_me_hw_config - configure hw dependent settings
141 static void mei_me_hw_config(struct mei_device *dev)
143 struct mei_me_hw *hw = to_me_hw(dev);
144 u32 hcsr = mei_hcsr_read(to_me_hw(dev));
145 /* Doesn't change in runtime */
146 dev->hbuf_depth = (hcsr & H_CBD) >> 24;
148 hw->pg_state = MEI_PG_OFF;
152 * mei_me_pg_state - translate internal pg state
153 * to the mei power gating state
157 * Return: MEI_PG_OFF if aliveness is on and MEI_PG_ON otherwise
159 static inline enum mei_pg_state mei_me_pg_state(struct mei_device *dev)
161 struct mei_me_hw *hw = to_me_hw(dev);
167 * mei_me_intr_clear - clear and stop interrupts
169 * @dev: the device structure
171 static void mei_me_intr_clear(struct mei_device *dev)
173 struct mei_me_hw *hw = to_me_hw(dev);
174 u32 hcsr = mei_hcsr_read(hw);
176 if ((hcsr & H_IS) == H_IS)
177 mei_me_reg_write(hw, H_CSR, hcsr);
180 * mei_me_intr_enable - enables mei device interrupts
182 * @dev: the device structure
184 static void mei_me_intr_enable(struct mei_device *dev)
186 struct mei_me_hw *hw = to_me_hw(dev);
187 u32 hcsr = mei_hcsr_read(hw);
190 mei_hcsr_set(hw, hcsr);
194 * mei_me_intr_disable - disables mei device interrupts
196 * @dev: the device structure
198 static void mei_me_intr_disable(struct mei_device *dev)
200 struct mei_me_hw *hw = to_me_hw(dev);
201 u32 hcsr = mei_hcsr_read(hw);
204 mei_hcsr_set(hw, hcsr);
208 * mei_me_hw_reset_release - release device from the reset
210 * @dev: the device structure
212 static void mei_me_hw_reset_release(struct mei_device *dev)
214 struct mei_me_hw *hw = to_me_hw(dev);
215 u32 hcsr = mei_hcsr_read(hw);
219 mei_hcsr_set(hw, hcsr);
221 /* complete this write before we set host ready on another CPU */
225 * mei_me_hw_reset - resets fw via mei csr register.
227 * @dev: the device structure
228 * @intr_enable: if interrupt should be enabled after reset.
232 static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable)
234 struct mei_me_hw *hw = to_me_hw(dev);
235 u32 hcsr = mei_hcsr_read(hw);
237 /* H_RST may be found lit before reset is started,
238 * for example if preceding reset flow hasn't completed.
239 * In that case asserting H_RST will be ignored, therefore
240 * we need to clean H_RST bit to start a successful reset sequence.
242 if ((hcsr & H_RST) == H_RST) {
243 dev_warn(dev->dev, "H_RST is set = 0x%08X", hcsr);
245 mei_me_reg_write(hw, H_CSR, hcsr);
246 hcsr = mei_hcsr_read(hw);
249 hcsr |= H_RST | H_IG | H_IS;
256 dev->recvd_hw_ready = false;
257 mei_me_reg_write(hw, H_CSR, hcsr);
260 * Host reads the H_CSR once to ensure that the
261 * posted write to H_CSR completes.
263 hcsr = mei_hcsr_read(hw);
265 if ((hcsr & H_RST) == 0)
266 dev_warn(dev->dev, "H_RST is not set = 0x%08X", hcsr);
268 if ((hcsr & H_RDY) == H_RDY)
269 dev_warn(dev->dev, "H_RDY is not cleared 0x%08X", hcsr);
271 if (intr_enable == false)
272 mei_me_hw_reset_release(dev);
278 * mei_me_host_set_ready - enable device
282 static void mei_me_host_set_ready(struct mei_device *dev)
284 struct mei_me_hw *hw = to_me_hw(dev);
285 u32 hcsr = mei_hcsr_read(hw);
287 hcsr |= H_IE | H_IG | H_RDY;
288 mei_hcsr_set(hw, hcsr);
292 * mei_me_host_is_ready - check whether the host has turned ready
297 static bool mei_me_host_is_ready(struct mei_device *dev)
299 struct mei_me_hw *hw = to_me_hw(dev);
300 u32 hcsr = mei_hcsr_read(hw);
302 return (hcsr & H_RDY) == H_RDY;
306 * mei_me_hw_is_ready - check whether the me(hw) has turned ready
311 static bool mei_me_hw_is_ready(struct mei_device *dev)
313 struct mei_me_hw *hw = to_me_hw(dev);
314 u32 mecsr = mei_me_mecsr_read(hw);
316 return (mecsr & ME_RDY_HRA) == ME_RDY_HRA;
320 * mei_me_hw_ready_wait - wait until the me(hw) has turned ready
321 * or timeout is reached
324 * Return: 0 on success, error otherwise
326 static int mei_me_hw_ready_wait(struct mei_device *dev)
328 mutex_unlock(&dev->device_lock);
329 wait_event_timeout(dev->wait_hw_ready,
331 mei_secs_to_jiffies(MEI_HW_READY_TIMEOUT));
332 mutex_lock(&dev->device_lock);
333 if (!dev->recvd_hw_ready) {
334 dev_err(dev->dev, "wait hw ready failed\n");
338 dev->recvd_hw_ready = false;
343 * mei_me_hw_start - hw start routine
346 * Return: 0 on success, error otherwise
348 static int mei_me_hw_start(struct mei_device *dev)
350 int ret = mei_me_hw_ready_wait(dev);
354 dev_dbg(dev->dev, "hw is ready\n");
356 mei_me_host_set_ready(dev);
362 * mei_hbuf_filled_slots - gets number of device filled buffer slots
364 * @dev: the device structure
366 * Return: number of filled slots
368 static unsigned char mei_hbuf_filled_slots(struct mei_device *dev)
370 struct mei_me_hw *hw = to_me_hw(dev);
372 char read_ptr, write_ptr;
374 hcsr = mei_hcsr_read(hw);
376 read_ptr = (char) ((hcsr & H_CBRP) >> 8);
377 write_ptr = (char) ((hcsr & H_CBWP) >> 16);
379 return (unsigned char) (write_ptr - read_ptr);
383 * mei_me_hbuf_is_empty - checks if host buffer is empty.
385 * @dev: the device structure
387 * Return: true if empty, false - otherwise.
389 static bool mei_me_hbuf_is_empty(struct mei_device *dev)
391 return mei_hbuf_filled_slots(dev) == 0;
395 * mei_me_hbuf_empty_slots - counts write empty slots.
397 * @dev: the device structure
399 * Return: -EOVERFLOW if overflow, otherwise empty slots count
401 static int mei_me_hbuf_empty_slots(struct mei_device *dev)
403 unsigned char filled_slots, empty_slots;
405 filled_slots = mei_hbuf_filled_slots(dev);
406 empty_slots = dev->hbuf_depth - filled_slots;
408 /* check for overflow */
409 if (filled_slots > dev->hbuf_depth)
416 * mei_me_hbuf_max_len - returns size of hw buffer.
418 * @dev: the device structure
420 * Return: size of hw buffer in bytes
422 static size_t mei_me_hbuf_max_len(const struct mei_device *dev)
424 return dev->hbuf_depth * sizeof(u32) - sizeof(struct mei_msg_hdr);
429 * mei_me_write_message - writes a message to mei device.
431 * @dev: the device structure
432 * @header: mei HECI header of message
433 * @buf: message payload will be written
435 * Return: -EIO if write has failed
437 static int mei_me_write_message(struct mei_device *dev,
438 struct mei_msg_hdr *header,
441 struct mei_me_hw *hw = to_me_hw(dev);
443 unsigned long length = header->length;
444 u32 *reg_buf = (u32 *)buf;
450 dev_dbg(dev->dev, MEI_HDR_FMT, MEI_HDR_PRM(header));
452 empty_slots = mei_hbuf_empty_slots(dev);
453 dev_dbg(dev->dev, "empty slots = %hu.\n", empty_slots);
455 dw_cnt = mei_data2slots(length);
456 if (empty_slots < 0 || dw_cnt > empty_slots)
459 mei_me_reg_write(hw, H_CB_WW, *((u32 *) header));
461 for (i = 0; i < length / 4; i++)
462 mei_me_reg_write(hw, H_CB_WW, reg_buf[i]);
468 memcpy(®, &buf[length - rem], rem);
469 mei_me_reg_write(hw, H_CB_WW, reg);
472 hcsr = mei_hcsr_read(hw) | H_IG;
473 mei_hcsr_set(hw, hcsr);
474 if (!mei_me_hw_is_ready(dev))
481 * mei_me_count_full_read_slots - counts read full slots.
483 * @dev: the device structure
485 * Return: -EOVERFLOW if overflow, otherwise filled slots count
487 static int mei_me_count_full_read_slots(struct mei_device *dev)
489 struct mei_me_hw *hw = to_me_hw(dev);
491 char read_ptr, write_ptr;
492 unsigned char buffer_depth, filled_slots;
494 me_csr = mei_me_mecsr_read(hw);
495 buffer_depth = (unsigned char)((me_csr & ME_CBD_HRA) >> 24);
496 read_ptr = (char) ((me_csr & ME_CBRP_HRA) >> 8);
497 write_ptr = (char) ((me_csr & ME_CBWP_HRA) >> 16);
498 filled_slots = (unsigned char) (write_ptr - read_ptr);
500 /* check for overflow */
501 if (filled_slots > buffer_depth)
504 dev_dbg(dev->dev, "filled_slots =%08x\n", filled_slots);
505 return (int)filled_slots;
509 * mei_me_read_slots - reads a message from mei device.
511 * @dev: the device structure
512 * @buffer: message buffer will be written
513 * @buffer_length: message size will be read
517 static int mei_me_read_slots(struct mei_device *dev, unsigned char *buffer,
518 unsigned long buffer_length)
520 struct mei_me_hw *hw = to_me_hw(dev);
521 u32 *reg_buf = (u32 *)buffer;
524 for (; buffer_length >= sizeof(u32); buffer_length -= sizeof(u32))
525 *reg_buf++ = mei_me_mecbrw_read(dev);
527 if (buffer_length > 0) {
528 u32 reg = mei_me_mecbrw_read(dev);
530 memcpy(reg_buf, ®, buffer_length);
533 hcsr = mei_hcsr_read(hw) | H_IG;
534 mei_hcsr_set(hw, hcsr);
539 * mei_me_pg_enter - write pg enter register
541 * @dev: the device structure
543 static void mei_me_pg_enter(struct mei_device *dev)
545 struct mei_me_hw *hw = to_me_hw(dev);
546 u32 reg = mei_me_reg_read(hw, H_HPG_CSR);
548 reg |= H_HPG_CSR_PGI;
549 mei_me_reg_write(hw, H_HPG_CSR, reg);
553 * mei_me_pg_exit - write pg exit register
555 * @dev: the device structure
557 static void mei_me_pg_exit(struct mei_device *dev)
559 struct mei_me_hw *hw = to_me_hw(dev);
560 u32 reg = mei_me_reg_read(hw, H_HPG_CSR);
562 WARN(!(reg & H_HPG_CSR_PGI), "PGI is not set\n");
564 reg |= H_HPG_CSR_PGIHEXR;
565 mei_me_reg_write(hw, H_HPG_CSR, reg);
569 * mei_me_pg_set_sync - perform pg entry procedure
571 * @dev: the device structure
573 * Return: 0 on success an error code otherwise
575 int mei_me_pg_set_sync(struct mei_device *dev)
577 struct mei_me_hw *hw = to_me_hw(dev);
578 unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT);
581 dev->pg_event = MEI_PG_EVENT_WAIT;
583 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD);
587 mutex_unlock(&dev->device_lock);
588 wait_event_timeout(dev->wait_pg,
589 dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout);
590 mutex_lock(&dev->device_lock);
592 if (dev->pg_event == MEI_PG_EVENT_RECEIVED) {
593 mei_me_pg_enter(dev);
599 dev->pg_event = MEI_PG_EVENT_IDLE;
600 hw->pg_state = MEI_PG_ON;
606 * mei_me_pg_unset_sync - perform pg exit procedure
608 * @dev: the device structure
610 * Return: 0 on success an error code otherwise
612 int mei_me_pg_unset_sync(struct mei_device *dev)
614 struct mei_me_hw *hw = to_me_hw(dev);
615 unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT);
618 if (dev->pg_event == MEI_PG_EVENT_RECEIVED)
621 dev->pg_event = MEI_PG_EVENT_WAIT;
625 mutex_unlock(&dev->device_lock);
626 wait_event_timeout(dev->wait_pg,
627 dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout);
628 mutex_lock(&dev->device_lock);
631 if (dev->pg_event == MEI_PG_EVENT_RECEIVED)
632 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_EXIT_RES_CMD);
636 dev->pg_event = MEI_PG_EVENT_IDLE;
637 hw->pg_state = MEI_PG_OFF;
643 * mei_me_pg_is_enabled - detect if PG is supported by HW
645 * @dev: the device structure
647 * Return: true is pg supported, false otherwise
649 static bool mei_me_pg_is_enabled(struct mei_device *dev)
651 struct mei_me_hw *hw = to_me_hw(dev);
652 u32 reg = mei_me_reg_read(hw, ME_CSR_HA);
654 if ((reg & ME_PGIC_HRA) == 0)
657 if (!dev->hbm_f_pg_supported)
663 dev_dbg(dev->dev, "pg: not supported: HGP = %d hbm version %d.%d ?= %d.%d\n",
664 !!(reg & ME_PGIC_HRA),
665 dev->version.major_version,
666 dev->version.minor_version,
667 HBM_MAJOR_VERSION_PGI,
668 HBM_MINOR_VERSION_PGI);
674 * mei_me_irq_quick_handler - The ISR of the MEI device
676 * @irq: The irq number
677 * @dev_id: pointer to the device structure
679 * Return: irqreturn_t
682 irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id)
684 struct mei_device *dev = (struct mei_device *) dev_id;
685 struct mei_me_hw *hw = to_me_hw(dev);
686 u32 csr_reg = mei_hcsr_read(hw);
688 if ((csr_reg & H_IS) != H_IS)
691 /* clear H_IS bit in H_CSR */
692 mei_me_reg_write(hw, H_CSR, csr_reg);
694 return IRQ_WAKE_THREAD;
698 * mei_me_irq_thread_handler - function called after ISR to handle the interrupt
701 * @irq: The irq number
702 * @dev_id: pointer to the device structure
704 * Return: irqreturn_t
707 irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id)
709 struct mei_device *dev = (struct mei_device *) dev_id;
710 struct mei_cl_cb complete_list;
714 dev_dbg(dev->dev, "function called after ISR to handle the interrupt processing.\n");
715 /* initialize our complete list */
716 mutex_lock(&dev->device_lock);
717 mei_io_list_init(&complete_list);
719 /* Ack the interrupt here
720 * In case of MSI we don't go through the quick handler */
721 if (pci_dev_msi_enabled(to_pci_dev(dev->dev)))
722 mei_clear_interrupts(dev);
724 /* check if ME wants a reset */
725 if (!mei_hw_is_ready(dev) && dev->dev_state != MEI_DEV_RESETTING) {
726 dev_warn(dev->dev, "FW not ready: resetting.\n");
727 schedule_work(&dev->reset_work);
731 /* check if we need to start the dev */
732 if (!mei_host_is_ready(dev)) {
733 if (mei_hw_is_ready(dev)) {
734 mei_me_hw_reset_release(dev);
735 dev_dbg(dev->dev, "we need to start the dev.\n");
737 dev->recvd_hw_ready = true;
738 wake_up(&dev->wait_hw_ready);
740 dev_dbg(dev->dev, "Spurious Interrupt\n");
744 /* check slots available for reading */
745 slots = mei_count_full_read_slots(dev);
747 dev_dbg(dev->dev, "slots to read = %08x\n", slots);
748 rets = mei_irq_read_handler(dev, &complete_list, &slots);
749 /* There is a race between ME write and interrupt delivery:
750 * Not all data is always available immediately after the
751 * interrupt, so try to read again on the next interrupt.
753 if (rets == -ENODATA)
756 if (rets && dev->dev_state != MEI_DEV_RESETTING) {
757 dev_err(dev->dev, "mei_irq_read_handler ret = %d.\n",
759 schedule_work(&dev->reset_work);
764 dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
767 * During PG handshake only allowed write is the replay to the
768 * PG exit message, so block calling write function
769 * if the pg state is not idle
771 if (dev->pg_event == MEI_PG_EVENT_IDLE) {
772 rets = mei_irq_write_handler(dev, &complete_list);
773 dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
776 mei_irq_compl_handler(dev, &complete_list);
779 dev_dbg(dev->dev, "interrupt thread end ret = %d\n", rets);
780 mutex_unlock(&dev->device_lock);
784 static const struct mei_hw_ops mei_me_hw_ops = {
786 .fw_status = mei_me_fw_status,
787 .pg_state = mei_me_pg_state,
789 .host_is_ready = mei_me_host_is_ready,
791 .hw_is_ready = mei_me_hw_is_ready,
792 .hw_reset = mei_me_hw_reset,
793 .hw_config = mei_me_hw_config,
794 .hw_start = mei_me_hw_start,
796 .pg_is_enabled = mei_me_pg_is_enabled,
798 .intr_clear = mei_me_intr_clear,
799 .intr_enable = mei_me_intr_enable,
800 .intr_disable = mei_me_intr_disable,
802 .hbuf_free_slots = mei_me_hbuf_empty_slots,
803 .hbuf_is_ready = mei_me_hbuf_is_empty,
804 .hbuf_max_len = mei_me_hbuf_max_len,
806 .write = mei_me_write_message,
808 .rdbuf_full_slots = mei_me_count_full_read_slots,
809 .read_hdr = mei_me_mecbrw_read,
810 .read = mei_me_read_slots
813 static bool mei_me_fw_type_nm(struct pci_dev *pdev)
817 pci_read_config_dword(pdev, PCI_CFG_HFS_2, ®);
818 /* make sure that bit 9 (NM) is up and bit 10 (DM) is down */
819 return (reg & 0x600) == 0x200;
822 #define MEI_CFG_FW_NM \
823 .quirk_probe = mei_me_fw_type_nm
825 static bool mei_me_fw_type_sps(struct pci_dev *pdev)
828 /* Read ME FW Status check for SPS Firmware */
829 pci_read_config_dword(pdev, PCI_CFG_HFS_1, ®);
830 /* if bits [19:16] = 15, running SPS Firmware */
831 return (reg & 0xf0000) == 0xf0000;
834 #define MEI_CFG_FW_SPS \
835 .quirk_probe = mei_me_fw_type_sps
838 #define MEI_CFG_LEGACY_HFS \
841 #define MEI_CFG_ICH_HFS \
842 .fw_status.count = 1, \
843 .fw_status.status[0] = PCI_CFG_HFS_1
845 #define MEI_CFG_PCH_HFS \
846 .fw_status.count = 2, \
847 .fw_status.status[0] = PCI_CFG_HFS_1, \
848 .fw_status.status[1] = PCI_CFG_HFS_2
850 #define MEI_CFG_PCH8_HFS \
851 .fw_status.count = 6, \
852 .fw_status.status[0] = PCI_CFG_HFS_1, \
853 .fw_status.status[1] = PCI_CFG_HFS_2, \
854 .fw_status.status[2] = PCI_CFG_HFS_3, \
855 .fw_status.status[3] = PCI_CFG_HFS_4, \
856 .fw_status.status[4] = PCI_CFG_HFS_5, \
857 .fw_status.status[5] = PCI_CFG_HFS_6
859 /* ICH Legacy devices */
860 const struct mei_cfg mei_me_legacy_cfg = {
865 const struct mei_cfg mei_me_ich_cfg = {
870 const struct mei_cfg mei_me_pch_cfg = {
875 /* PCH Cougar Point and Patsburg with quirk for Node Manager exclusion */
876 const struct mei_cfg mei_me_pch_cpt_pbg_cfg = {
881 /* PCH8 Lynx Point and newer devices */
882 const struct mei_cfg mei_me_pch8_cfg = {
886 /* PCH8 Lynx Point with quirk for SPS Firmware exclusion */
887 const struct mei_cfg mei_me_pch8_sps_cfg = {
893 * mei_me_dev_init - allocates and initializes the mei device structure
895 * @pdev: The pci device structure
896 * @cfg: per device generation config
898 * Return: The mei_device_device pointer on success, NULL on failure.
900 struct mei_device *mei_me_dev_init(struct pci_dev *pdev,
901 const struct mei_cfg *cfg)
903 struct mei_device *dev;
904 struct mei_me_hw *hw;
906 dev = kzalloc(sizeof(struct mei_device) +
907 sizeof(struct mei_me_hw), GFP_KERNEL);
912 mei_device_init(dev, &pdev->dev, &mei_me_hw_ops);