1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright 2019-2020 HabanaLabs, Ltd.
11 #include <uapi/misc/habanalabs.h>
12 #include "habanalabs.h"
13 #include "include/common/hl_boot_if.h"
14 #include "include/gaudi/gaudi_packets.h"
15 #include "include/gaudi/gaudi.h"
16 #include "include/gaudi/gaudi_async_events.h"
18 #define NUMBER_OF_EXT_HW_QUEUES 12
19 #define NUMBER_OF_CMPLT_QUEUES NUMBER_OF_EXT_HW_QUEUES
20 #define NUMBER_OF_CPU_HW_QUEUES 1
21 #define NUMBER_OF_INT_HW_QUEUES 100
22 #define NUMBER_OF_HW_QUEUES (NUMBER_OF_EXT_HW_QUEUES + \
23 NUMBER_OF_CPU_HW_QUEUES + \
24 NUMBER_OF_INT_HW_QUEUES)
27 * Number of MSI interrupts IDS:
28 * Each completion queue has 1 ID
29 * The event queue has 1 ID
31 #define NUMBER_OF_INTERRUPTS (NUMBER_OF_CMPLT_QUEUES + \
32 NUMBER_OF_CPU_HW_QUEUES)
34 #if (NUMBER_OF_INTERRUPTS > GAUDI_MSI_ENTRIES)
35 #error "Number of MSI interrupts must be smaller or equal to GAUDI_MSI_ENTRIES"
38 #define QMAN_FENCE_TIMEOUT_USEC 10000 /* 10 ms */
40 #define CORESIGHT_TIMEOUT_USEC 100000 /* 100 ms */
42 #define GAUDI_MAX_CLK_FREQ 2200000000ull /* 2200 MHz */
44 #define MAX_POWER_DEFAULT 200000 /* 200W */
46 #define GAUDI_CPU_TIMEOUT_USEC 15000000 /* 15s */
48 #define TPC_ENABLED_MASK 0xFF
50 #define GAUDI_HBM_SIZE_32GB 0x800000000ull
51 #define GAUDI_HBM_DEVICES 4
52 #define GAUDI_HBM_CHANNELS 8
53 #define GAUDI_HBM_CFG_BASE (mmHBM0_BASE - CFG_BASE)
54 #define GAUDI_HBM_CFG_OFFSET (mmHBM1_BASE - mmHBM0_BASE)
56 #define DMA_MAX_TRANSFER_SIZE U32_MAX
58 #define GAUDI_DEFAULT_CARD_NAME "HL2000"
60 #define GAUDI_MAX_PENDING_CS 1024
62 #if !IS_MAX_PENDING_CS_VALID(GAUDI_MAX_PENDING_CS)
63 #error "GAUDI_MAX_PENDING_CS must be power of 2 and greater than 1"
66 #define PCI_DMA_NUMBER_OF_CHNLS 3
67 #define HBM_DMA_NUMBER_OF_CHNLS 5
68 #define DMA_NUMBER_OF_CHNLS (PCI_DMA_NUMBER_OF_CHNLS + \
69 HBM_DMA_NUMBER_OF_CHNLS)
71 #define MME_NUMBER_OF_SLAVE_ENGINES 2
72 #define MME_NUMBER_OF_ENGINES (MME_NUMBER_OF_MASTER_ENGINES + \
73 MME_NUMBER_OF_SLAVE_ENGINES)
74 #define MME_NUMBER_OF_QMANS (MME_NUMBER_OF_MASTER_ENGINES * \
77 #define QMAN_STREAMS 4
79 #define DMA_QMAN_OFFSET (mmDMA1_QM_BASE - mmDMA0_QM_BASE)
80 #define TPC_QMAN_OFFSET (mmTPC1_QM_BASE - mmTPC0_QM_BASE)
81 #define MME_QMAN_OFFSET (mmMME1_QM_BASE - mmMME0_QM_BASE)
82 #define NIC_MACRO_QMAN_OFFSET (mmNIC1_QM0_BASE - mmNIC0_QM0_BASE)
84 #define TPC_CFG_OFFSET (mmTPC1_CFG_BASE - mmTPC0_CFG_BASE)
86 #define DMA_CORE_OFFSET (mmDMA1_CORE_BASE - mmDMA0_CORE_BASE)
88 #define SIF_RTR_CTRL_OFFSET (mmSIF_RTR_CTRL_1_BASE - mmSIF_RTR_CTRL_0_BASE)
90 #define NIF_RTR_CTRL_OFFSET (mmNIF_RTR_CTRL_1_BASE - mmNIF_RTR_CTRL_0_BASE)
92 #define MME_ACC_OFFSET (mmMME1_ACC_BASE - mmMME0_ACC_BASE)
93 #define SRAM_BANK_OFFSET (mmSRAM_Y0_X1_RTR_BASE - mmSRAM_Y0_X0_RTR_BASE)
95 #define NUM_OF_SOB_IN_BLOCK \
96 (((mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_2047 - \
97 mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0) + 4) >> 2)
99 #define NUM_OF_MONITORS_IN_BLOCK \
100 (((mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_511 - \
101 mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_0) + 4) >> 2)
104 /* DRAM Memory Map */
106 #define CPU_FW_IMAGE_SIZE 0x10000000 /* 256MB */
107 #define MMU_PAGE_TABLES_SIZE 0x0BF00000 /* 191MB */
108 #define MMU_CACHE_MNG_SIZE 0x00100000 /* 1MB */
109 #define RESERVED 0x04000000 /* 64MB */
111 #define CPU_FW_IMAGE_ADDR DRAM_PHYS_BASE
112 #define MMU_PAGE_TABLES_ADDR (CPU_FW_IMAGE_ADDR + CPU_FW_IMAGE_SIZE)
113 #define MMU_CACHE_MNG_ADDR (MMU_PAGE_TABLES_ADDR + MMU_PAGE_TABLES_SIZE)
115 #define DRAM_DRIVER_END_ADDR (MMU_CACHE_MNG_ADDR + MMU_CACHE_MNG_SIZE +\
118 #define DRAM_BASE_ADDR_USER 0x20000000
120 #if (DRAM_DRIVER_END_ADDR > DRAM_BASE_ADDR_USER)
121 #error "Driver must reserve no more than 512MB"
124 /* Internal QMANs PQ sizes */
126 #define MME_QMAN_LENGTH 1024
127 #define MME_QMAN_SIZE_IN_BYTES (MME_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE)
129 #define HBM_DMA_QMAN_LENGTH 1024
130 #define HBM_DMA_QMAN_SIZE_IN_BYTES \
131 (HBM_DMA_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE)
133 #define TPC_QMAN_LENGTH 1024
134 #define TPC_QMAN_SIZE_IN_BYTES (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE)
136 #define SRAM_USER_BASE_OFFSET GAUDI_DRIVER_SRAM_RESERVED_SIZE_FROM_START
138 /* Virtual address space */
139 #define VA_HOST_SPACE_START 0x1000000000000ull /* 256TB */
140 #define VA_HOST_SPACE_END 0x3FF8000000000ull /* 1PB - 1TB */
141 #define VA_HOST_SPACE_SIZE (VA_HOST_SPACE_END - \
142 VA_HOST_SPACE_START) /* 767TB */
144 #define HW_CAP_PLL 0x00000001
145 #define HW_CAP_HBM 0x00000002
146 #define HW_CAP_MMU 0x00000004
147 #define HW_CAP_MME 0x00000008
148 #define HW_CAP_CPU 0x00000010
149 #define HW_CAP_PCI_DMA 0x00000020
150 #define HW_CAP_MSI 0x00000040
151 #define HW_CAP_CPU_Q 0x00000080
152 #define HW_CAP_HBM_DMA 0x00000100
153 #define HW_CAP_CLK_GATE 0x00000200
154 #define HW_CAP_SRAM_SCRAMBLER 0x00000400
155 #define HW_CAP_HBM_SCRAMBLER 0x00000800
157 #define HW_CAP_TPC0 0x01000000
158 #define HW_CAP_TPC1 0x02000000
159 #define HW_CAP_TPC2 0x04000000
160 #define HW_CAP_TPC3 0x08000000
161 #define HW_CAP_TPC4 0x10000000
162 #define HW_CAP_TPC5 0x20000000
163 #define HW_CAP_TPC6 0x40000000
164 #define HW_CAP_TPC7 0x80000000
165 #define HW_CAP_TPC_MASK 0xFF000000
166 #define HW_CAP_TPC_SHIFT 24
168 #define GAUDI_CPU_PCI_MSB_ADDR(addr) (((addr) & GENMASK_ULL(49, 39)) >> 39)
169 #define GAUDI_PCI_TO_CPU_ADDR(addr) \
171 (addr) &= ~GENMASK_ULL(49, 39); \
172 (addr) |= BIT_ULL(39); \
174 #define GAUDI_CPU_TO_PCI_ADDR(addr, extension) \
176 (addr) &= ~GENMASK_ULL(49, 39); \
177 (addr) |= (u64) (extension) << 39; \
180 enum gaudi_dma_channels {
192 enum gaudi_tpc_mask {
193 GAUDI_TPC_MASK_TPC0 = 0x01,
194 GAUDI_TPC_MASK_TPC1 = 0x02,
195 GAUDI_TPC_MASK_TPC2 = 0x04,
196 GAUDI_TPC_MASK_TPC3 = 0x08,
197 GAUDI_TPC_MASK_TPC4 = 0x10,
198 GAUDI_TPC_MASK_TPC5 = 0x20,
199 GAUDI_TPC_MASK_TPC6 = 0x40,
200 GAUDI_TPC_MASK_TPC7 = 0x80,
201 GAUDI_TPC_MASK_ALL = 0xFF
205 * struct gaudi_internal_qman_info - Internal QMAN information.
206 * @pq_kernel_addr: Kernel address of the PQ memory area in the host.
207 * @pq_dma_addr: DMA address of the PQ memory area in the host.
208 * @pq_size: Size of allocated host memory for PQ.
210 struct gaudi_internal_qman_info {
211 void *pq_kernel_addr;
212 dma_addr_t pq_dma_addr;
217 * struct gaudi_device - ASIC specific manage structure.
218 * @armcp_info_get: get information on device from ArmCP
219 * @hw_queues_lock: protects the H/W queues from concurrent access.
220 * @clk_gate_mutex: protects code areas that require clock gating to be disabled
222 * @internal_qmans: Internal QMANs information. The array size is larger than
223 * the actual number of internal queues because they are not in
225 * @hbm_bar_cur_addr: current address of HBM PCI bar.
226 * @max_freq_value: current max clk frequency.
227 * @events: array that holds all event id's
228 * @events_stat: array that holds histogram of all received events.
229 * @events_stat_aggregate: same as events_stat but doesn't get cleared on reset
230 * @hw_cap_initialized: This field contains a bit per H/W engine. When that
231 * engine is initialized, that bit is set by the driver to
232 * signal we can use this engine in later code paths.
233 * Each bit is cleared upon reset of its corresponding H/W
235 * @multi_msi_mode: whether we are working in multi MSI single MSI mode.
236 * Multi MSI is possible only with IOMMU enabled.
237 * @mmu_cache_inv_pi: PI for MMU cache invalidation flow. The H/W expects an
238 * 8-bit value so use u8.
240 struct gaudi_device {
241 int (*armcp_info_get)(struct hl_device *hdev);
243 /* TODO: remove hw_queues_lock after moving to scheduler code */
244 spinlock_t hw_queues_lock;
245 struct mutex clk_gate_mutex;
247 struct gaudi_internal_qman_info internal_qmans[GAUDI_QUEUE_ID_SIZE];
249 u64 hbm_bar_cur_addr;
252 u32 events[GAUDI_EVENT_SIZE];
253 u32 events_stat[GAUDI_EVENT_SIZE];
254 u32 events_stat_aggregate[GAUDI_EVENT_SIZE];
255 u32 hw_cap_initialized;
260 void gaudi_init_security(struct hl_device *hdev);
261 void gaudi_add_device_attr(struct hl_device *hdev,
262 struct attribute_group *dev_attr_grp);
263 void gaudi_set_pll_profile(struct hl_device *hdev, enum hl_pll_frequency freq);
264 int gaudi_debug_coresight(struct hl_device *hdev, void *data);
265 void gaudi_halt_coresight(struct hl_device *hdev);
266 int gaudi_get_clk_rate(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk);
268 #endif /* GAUDIP_H_ */