1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for most of the SPI EEPROMs, such as Atmel AT25 models
4 * and Cypress FRAMs FM25 models.
6 * Copyright (C) 2006 David Brownell
9 #include <linux/bits.h>
10 #include <linux/delay.h>
11 #include <linux/device.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/property.h>
15 #include <linux/sched.h>
16 #include <linux/slab.h>
18 #include <linux/spi/eeprom.h>
19 #include <linux/spi/spi.h>
21 #include <linux/nvmem-provider.h>
24 * NOTE: this is an *EEPROM* driver. The vagaries of product naming
25 * mean that some AT25 products are EEPROMs, and others are FLASH.
26 * Handle FLASH chips with the drivers/mtd/devices/m25p80.c driver,
29 * EEPROMs that can be used with this driver include, for example:
33 #define FM25_SN_LEN 8 /* serial number length */
34 #define EE_MAXADDRLEN 3 /* 24 bit addresses, up to 2 MBytes */
37 struct spi_eeprom chip;
38 struct spi_device *spi;
41 struct nvmem_config nvmem_config;
42 struct nvmem_device *nvmem;
43 u8 sernum[FM25_SN_LEN];
44 u8 command[EE_MAXADDRLEN + 1];
47 #define AT25_WREN 0x06 /* latch the write enable */
48 #define AT25_WRDI 0x04 /* reset the write enable */
49 #define AT25_RDSR 0x05 /* read status register */
50 #define AT25_WRSR 0x01 /* write status register */
51 #define AT25_READ 0x03 /* read byte(s) */
52 #define AT25_WRITE 0x02 /* write byte(s)/sector */
53 #define FM25_SLEEP 0xb9 /* enter sleep mode */
54 #define FM25_RDID 0x9f /* read device ID */
55 #define FM25_RDSN 0xc3 /* read S/N */
57 #define AT25_SR_nRDY 0x01 /* nRDY = write-in-progress */
58 #define AT25_SR_WEN 0x02 /* write enable (latched) */
59 #define AT25_SR_BP0 0x04 /* BP for software writeprotect */
60 #define AT25_SR_BP1 0x08
61 #define AT25_SR_WPEN 0x80 /* writeprotect enable */
63 #define AT25_INSTR_BIT3 0x08 /* additional address bit in instr */
65 #define FM25_ID_LEN 9 /* ID length */
68 * Specs often allow 5ms for a page write, sometimes 20ms;
69 * it's important to recover from write timeouts.
73 /*-------------------------------------------------------------------------*/
75 #define io_limit PAGE_SIZE /* bytes */
77 static int at25_ee_read(void *priv, unsigned int offset,
78 void *val, size_t count)
80 struct at25_data *at25 = priv;
82 size_t max_chunk = spi_max_transfer_size(at25->spi);
83 size_t num_msgs = DIV_ROUND_UP(count, max_chunk);
85 unsigned int msg_offset;
89 struct spi_transfer t[2];
93 if (unlikely(offset >= at25->chip.byte_len))
95 if ((offset + count) > at25->chip.byte_len)
96 count = at25->chip.byte_len - offset;
100 msg_offset = (unsigned int)offset;
101 msg_count = min(count, max_chunk);
106 if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR)
107 if (msg_offset >= BIT(at25->addrlen * 8))
108 instr |= AT25_INSTR_BIT3;
110 mutex_lock(&at25->lock);
114 /* 8/16/24-bit address is written MSB first */
115 switch (at25->addrlen) {
116 default: /* case 3 */
117 *cp++ = msg_offset >> 16;
120 *cp++ = msg_offset >> 8;
123 case 0: /* can't happen: for better code generation */
124 *cp++ = msg_offset >> 0;
127 spi_message_init(&m);
128 memset(t, 0, sizeof(t));
130 t[0].tx_buf = at25->command;
131 t[0].len = at25->addrlen + 1;
132 spi_message_add_tail(&t[0], &m);
134 t[1].rx_buf = buf + nr_bytes;
135 t[1].len = msg_count;
136 spi_message_add_tail(&t[1], &m);
138 status = spi_sync(at25->spi, &m);
140 mutex_unlock(&at25->lock);
146 msg_offset += msg_count;
147 nr_bytes += msg_count;
150 dev_dbg(&at25->spi->dev, "read %zu bytes at %d\n",
155 /* Read extra registers as ID or serial number */
156 static int fm25_aux_read(struct at25_data *at25, u8 *buf, uint8_t command,
160 struct spi_transfer t[2];
161 struct spi_message m;
163 spi_message_init(&m);
164 memset(t, 0, sizeof(t));
166 t[0].tx_buf = at25->command;
168 spi_message_add_tail(&t[0], &m);
172 spi_message_add_tail(&t[1], &m);
174 mutex_lock(&at25->lock);
176 at25->command[0] = command;
178 status = spi_sync(at25->spi, &m);
179 dev_dbg(&at25->spi->dev, "read %d aux bytes --> %d\n", len, status);
181 mutex_unlock(&at25->lock);
185 static ssize_t sernum_show(struct device *dev, struct device_attribute *attr, char *buf)
187 struct at25_data *at25;
189 at25 = dev_get_drvdata(dev);
190 return sysfs_emit(buf, "%*ph\n", (int)sizeof(at25->sernum), at25->sernum);
192 static DEVICE_ATTR_RO(sernum);
194 static struct attribute *sernum_attrs[] = {
195 &dev_attr_sernum.attr,
198 ATTRIBUTE_GROUPS(sernum);
200 static int at25_ee_write(void *priv, unsigned int off, void *val, size_t count)
202 struct at25_data *at25 = priv;
203 size_t maxsz = spi_max_transfer_size(at25->spi);
204 const char *buf = val;
209 if (unlikely(off >= at25->chip.byte_len))
211 if ((off + count) > at25->chip.byte_len)
212 count = at25->chip.byte_len - off;
213 if (unlikely(!count))
216 /* Temp buffer starts with command and address */
217 buf_size = at25->chip.page_size;
218 if (buf_size > io_limit)
220 bounce = kmalloc(buf_size + at25->addrlen + 1, GFP_KERNEL);
225 * For write, rollover is within the page ... so we write at
226 * most one page, then manually roll over to the next page.
228 mutex_lock(&at25->lock);
230 unsigned long timeout, retries;
232 unsigned offset = (unsigned) off;
238 status = spi_write(at25->spi, cp, 1);
240 dev_dbg(&at25->spi->dev, "WREN --> %d\n", status);
245 if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR)
246 if (offset >= BIT(at25->addrlen * 8))
247 instr |= AT25_INSTR_BIT3;
250 /* 8/16/24-bit address is written MSB first */
251 switch (at25->addrlen) {
252 default: /* case 3 */
253 *cp++ = offset >> 16;
259 case 0: /* can't happen: for better code generation */
263 /* Write as much of a page as we can */
264 segment = buf_size - (offset % buf_size);
269 memcpy(cp, buf, segment);
270 status = spi_write(at25->spi, bounce,
271 segment + at25->addrlen + 1);
272 dev_dbg(&at25->spi->dev, "write %u bytes at %u --> %d\n",
273 segment, offset, status);
278 * REVISIT this should detect (or prevent) failed writes
279 * to read-only sections of the EEPROM...
282 /* Wait for non-busy status */
283 timeout = jiffies + msecs_to_jiffies(EE_TIMEOUT);
287 sr = spi_w8r8(at25->spi, AT25_RDSR);
288 if (sr < 0 || (sr & AT25_SR_nRDY)) {
289 dev_dbg(&at25->spi->dev,
290 "rdsr --> %d (%02x)\n", sr, sr);
291 /* at HZ=100, this is sloooow */
295 if (!(sr & AT25_SR_nRDY))
297 } while (retries++ < 3 || time_before_eq(jiffies, timeout));
299 if ((sr < 0) || (sr & AT25_SR_nRDY)) {
300 dev_err(&at25->spi->dev,
301 "write %u bytes offset %u, timeout after %u msecs\n",
303 jiffies_to_msecs(jiffies -
304 (timeout - EE_TIMEOUT)));
315 mutex_unlock(&at25->lock);
321 /*-------------------------------------------------------------------------*/
323 static int at25_fw_to_chip(struct device *dev, struct spi_eeprom *chip)
328 strscpy(chip->name, "at25", sizeof(chip->name));
330 err = device_property_read_u32(dev, "size", &val);
332 err = device_property_read_u32(dev, "at25,byte-len", &val);
334 dev_err(dev, "Error: missing \"size\" property\n");
337 chip->byte_len = val;
339 err = device_property_read_u32(dev, "pagesize", &val);
341 err = device_property_read_u32(dev, "at25,page-size", &val);
343 dev_err(dev, "Error: missing \"pagesize\" property\n");
346 chip->page_size = val;
348 err = device_property_read_u32(dev, "address-width", &val);
350 err = device_property_read_u32(dev, "at25,addr-mode", &val);
352 dev_err(dev, "Error: missing \"address-width\" property\n");
355 chip->flags = (u16)val;
359 chip->flags |= EE_INSTR_BIT3_IS_ADDR;
362 chip->flags |= EE_ADDR1;
365 chip->flags |= EE_ADDR2;
368 chip->flags |= EE_ADDR3;
372 "Error: bad \"address-width\" property: %u\n",
376 if (device_property_present(dev, "read-only"))
377 chip->flags |= EE_READONLY;
382 static int at25_fram_to_chip(struct device *dev, struct spi_eeprom *chip)
384 struct at25_data *at25 = container_of(chip, struct at25_data, chip);
385 u8 sernum[FM25_SN_LEN];
389 strscpy(chip->name, "fm25", sizeof(chip->name));
392 fm25_aux_read(at25, id, FM25_RDID, FM25_ID_LEN);
394 dev_err(dev, "Error: no Cypress FRAM (id %02x)\n", id[6]);
397 /* Set size found in ID */
398 if (id[7] < 0x21 || id[7] > 0x26) {
399 dev_err(dev, "Error: unsupported size (id %02x)\n", id[7]);
403 chip->byte_len = BIT(id[7] - 0x21 + 4) * 1024;
404 if (chip->byte_len > 64 * 1024)
405 chip->flags |= EE_ADDR3;
407 chip->flags |= EE_ADDR2;
410 fm25_aux_read(at25, sernum, FM25_RDSN, FM25_SN_LEN);
411 /* Swap byte order */
412 for (i = 0; i < FM25_SN_LEN; i++)
413 at25->sernum[i] = sernum[FM25_SN_LEN - 1 - i];
416 chip->page_size = PAGE_SIZE;
420 static const struct of_device_id at25_of_match[] = {
421 { .compatible = "atmel,at25" },
422 { .compatible = "cypress,fm25" },
425 MODULE_DEVICE_TABLE(of, at25_of_match);
427 static const struct spi_device_id at25_spi_ids[] = {
432 MODULE_DEVICE_TABLE(spi, at25_spi_ids);
434 static int at25_probe(struct spi_device *spi)
436 struct at25_data *at25 = NULL;
439 struct spi_eeprom *pdata;
442 err = device_property_match_string(&spi->dev, "compatible", "cypress,fm25");
449 * Ping the chip ... the status register is pretty portable,
450 * unlike probing manufacturer IDs. We do expect that system
451 * firmware didn't write it in the past few milliseconds!
453 sr = spi_w8r8(spi, AT25_RDSR);
454 if (sr < 0 || sr & AT25_SR_nRDY) {
455 dev_dbg(&spi->dev, "rdsr --> %d (%02x)\n", sr, sr);
459 at25 = devm_kzalloc(&spi->dev, sizeof(*at25), GFP_KERNEL);
463 mutex_init(&at25->lock);
465 spi_set_drvdata(spi, at25);
467 /* Chip description */
468 pdata = dev_get_platdata(&spi->dev);
473 err = at25_fram_to_chip(&spi->dev, &at25->chip);
475 err = at25_fw_to_chip(&spi->dev, &at25->chip);
480 /* For now we only support 8/16/24 bit addressing */
481 if (at25->chip.flags & EE_ADDR1)
483 else if (at25->chip.flags & EE_ADDR2)
485 else if (at25->chip.flags & EE_ADDR3)
488 dev_dbg(&spi->dev, "unsupported address type\n");
492 at25->nvmem_config.type = is_fram ? NVMEM_TYPE_FRAM : NVMEM_TYPE_EEPROM;
493 at25->nvmem_config.name = dev_name(&spi->dev);
494 at25->nvmem_config.dev = &spi->dev;
495 at25->nvmem_config.read_only = at25->chip.flags & EE_READONLY;
496 at25->nvmem_config.root_only = true;
497 at25->nvmem_config.owner = THIS_MODULE;
498 at25->nvmem_config.compat = true;
499 at25->nvmem_config.base_dev = &spi->dev;
500 at25->nvmem_config.reg_read = at25_ee_read;
501 at25->nvmem_config.reg_write = at25_ee_write;
502 at25->nvmem_config.priv = at25;
503 at25->nvmem_config.stride = 1;
504 at25->nvmem_config.word_size = 1;
505 at25->nvmem_config.size = at25->chip.byte_len;
507 at25->nvmem = devm_nvmem_register(&spi->dev, &at25->nvmem_config);
508 if (IS_ERR(at25->nvmem))
509 return PTR_ERR(at25->nvmem);
511 dev_info(&spi->dev, "%d %s %s %s%s, pagesize %u\n",
512 (at25->chip.byte_len < 1024) ?
513 at25->chip.byte_len : (at25->chip.byte_len / 1024),
514 (at25->chip.byte_len < 1024) ? "Byte" : "KByte",
515 at25->chip.name, is_fram ? "fram" : "eeprom",
516 (at25->chip.flags & EE_READONLY) ? " (readonly)" : "",
517 at25->chip.page_size);
521 /*-------------------------------------------------------------------------*/
523 static struct spi_driver at25_driver = {
526 .of_match_table = at25_of_match,
527 .dev_groups = sernum_groups,
530 .id_table = at25_spi_ids,
533 module_spi_driver(at25_driver);
535 MODULE_DESCRIPTION("Driver for most SPI EEPROMs");
536 MODULE_AUTHOR("David Brownell");
537 MODULE_LICENSE("GPL");
538 MODULE_ALIAS("spi:at25");