2 * Copyright 2014 IBM Corp.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
10 #include <linux/pci.h>
14 static int cxl_pci_probe_mode(struct pci_bus *bus)
16 return PCI_PROBE_NORMAL;
19 static int cxl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
24 static void cxl_teardown_msi_irqs(struct pci_dev *pdev)
27 * MSI should never be set but need still need to provide this call
32 static bool cxl_pci_enable_device_hook(struct pci_dev *dev)
34 struct pci_controller *phb;
36 struct cxl_context *ctx;
38 phb = pci_bus_to_host(dev->bus);
39 afu = (struct cxl_afu *)phb->private_data;
41 if (!cxl_ops->link_ok(afu->adapter, afu)) {
42 dev_warn(&dev->dev, "%s: Device link is down, refusing to enable AFU\n", __func__);
46 dev->dev.archdata.dma_offset = PAGE_OFFSET;
49 * Allocate a context to do cxl things too. If we eventually do real
50 * DMA ops, we'll need a default context to attach them to
52 ctx = cxl_dev_context_init(dev);
55 dev->dev.archdata.cxl_ctx = ctx;
57 return (cxl_ops->afu_check_and_enable(afu) == 0);
60 static void cxl_pci_disable_device(struct pci_dev *dev)
62 struct cxl_context *ctx = cxl_get_context(dev);
65 if (ctx->status == STARTED) {
66 dev_err(&dev->dev, "Default context started\n");
69 dev->dev.archdata.cxl_ctx = NULL;
70 cxl_release_context(ctx);
74 static resource_size_t cxl_pci_window_alignment(struct pci_bus *bus,
80 static void cxl_pci_reset_secondary_bus(struct pci_dev *dev)
82 /* Should we do an AFU reset here ? */
85 static int cxl_pcie_cfg_record(u8 bus, u8 devfn)
87 return (bus << 8) + devfn;
90 static inline struct cxl_afu *pci_bus_to_afu(struct pci_bus *bus)
92 struct pci_controller *phb = bus ? pci_bus_to_host(bus) : NULL;
94 return phb ? phb->private_data : NULL;
97 static void cxl_afu_configured_put(struct cxl_afu *afu)
99 atomic_dec_if_positive(&afu->configured_state);
102 static bool cxl_afu_configured_get(struct cxl_afu *afu)
104 return atomic_inc_unless_negative(&afu->configured_state);
107 static inline int cxl_pcie_config_info(struct pci_bus *bus, unsigned int devfn,
108 struct cxl_afu *afu, int *_record)
112 record = cxl_pcie_cfg_record(bus->number, devfn);
113 if (record > afu->crs_num)
114 return PCIBIOS_DEVICE_NOT_FOUND;
120 static int cxl_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
121 int offset, int len, u32 *val)
129 afu = pci_bus_to_afu(bus);
130 /* Grab a reader lock on afu. */
131 if (afu == NULL || !cxl_afu_configured_get(afu))
132 return PCIBIOS_DEVICE_NOT_FOUND;
134 rc = cxl_pcie_config_info(bus, devfn, afu, &record);
140 rc = cxl_ops->afu_cr_read8(afu, record, offset, &val8);
144 rc = cxl_ops->afu_cr_read16(afu, record, offset, &val16);
148 rc = cxl_ops->afu_cr_read32(afu, record, offset, &val32);
156 cxl_afu_configured_put(afu);
157 return rc ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
160 static int cxl_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
161 int offset, int len, u32 val)
166 afu = pci_bus_to_afu(bus);
167 /* Grab a reader lock on afu. */
168 if (afu == NULL || !cxl_afu_configured_get(afu))
169 return PCIBIOS_DEVICE_NOT_FOUND;
171 rc = cxl_pcie_config_info(bus, devfn, afu, &record);
177 rc = cxl_ops->afu_cr_write8(afu, record, offset, val & 0xff);
180 rc = cxl_ops->afu_cr_write16(afu, record, offset, val & 0xffff);
183 rc = cxl_ops->afu_cr_write32(afu, record, offset, val);
190 cxl_afu_configured_put(afu);
191 return rc ? PCIBIOS_SET_FAILED : PCIBIOS_SUCCESSFUL;
194 static struct pci_ops cxl_pcie_pci_ops =
196 .read = cxl_pcie_read_config,
197 .write = cxl_pcie_write_config,
201 static struct pci_controller_ops cxl_pci_controller_ops =
203 .probe_mode = cxl_pci_probe_mode,
204 .enable_device_hook = cxl_pci_enable_device_hook,
205 .disable_device = cxl_pci_disable_device,
206 .release_device = cxl_pci_disable_device,
207 .window_alignment = cxl_pci_window_alignment,
208 .reset_secondary_bus = cxl_pci_reset_secondary_bus,
209 .setup_msi_irqs = cxl_setup_msi_irqs,
210 .teardown_msi_irqs = cxl_teardown_msi_irqs,
213 int cxl_pci_vphb_add(struct cxl_afu *afu)
215 struct pci_controller *phb;
216 struct device_node *vphb_dn;
217 struct device *parent;
220 * If there are no AFU configuration records we won't have anything to
221 * expose under the vPHB, so skip creating one, returning success since
222 * this is still a valid case. This will also opt us out of EEH
223 * handling since we won't have anything special to do if there are no
224 * kernel drivers attached to the vPHB, and EEH handling is not yet
225 * supported in the peer model.
230 /* The parent device is the adapter. Reuse the device node of
232 * We don't seem to care what device node is used for the vPHB,
233 * but tools such as lsvpd walk up the device parents looking
234 * for a valid location code, so we might as well show devices
235 * attached to the adapter as being located on that adapter.
237 parent = afu->adapter->dev.parent;
238 vphb_dn = parent->of_node;
240 /* Alloc and setup PHB data structure */
241 phb = pcibios_alloc_controller(vphb_dn);
245 /* Setup parent in sysfs */
246 phb->parent = parent;
248 /* Setup the PHB using arch provided callback */
249 phb->ops = &cxl_pcie_pci_ops;
250 phb->cfg_addr = NULL;
251 phb->cfg_data = NULL;
252 phb->private_data = afu;
253 phb->controller_ops = cxl_pci_controller_ops;
256 pcibios_scan_phb(phb);
257 if (phb->bus == NULL)
260 /* Set release hook on root bus */
261 pci_set_host_bridge_release(to_pci_host_bridge(phb->bus->bridge),
262 pcibios_free_controller_deferred,
265 /* Claim resources. This might need some rework as well depending
266 * whether we are doing probe-only or not, like assigning unassigned
269 pcibios_claim_one_bus(phb->bus);
271 /* Add probed PCI devices to the device model */
272 pci_bus_add_devices(phb->bus);
279 void cxl_pci_vphb_remove(struct cxl_afu *afu)
281 struct pci_controller *phb;
283 /* If there is no configuration record we won't have one of these */
284 if (!afu || !afu->phb)
290 pci_remove_root_bus(phb->bus);
292 * We don't free phb here - that's handled by
293 * pcibios_free_controller_deferred()
297 bool cxl_pci_is_vphb_device(struct pci_dev *dev)
299 struct pci_controller *phb;
301 phb = pci_bus_to_host(dev->bus);
303 return (phb->ops == &cxl_pcie_pci_ops);
306 struct cxl_afu *cxl_pci_to_afu(struct pci_dev *dev)
308 struct pci_controller *phb;
310 phb = pci_bus_to_host(dev->bus);
312 return (struct cxl_afu *)phb->private_data;
314 EXPORT_SYMBOL_GPL(cxl_pci_to_afu);
316 unsigned int cxl_pci_to_cfg_record(struct pci_dev *dev)
318 return cxl_pcie_cfg_record(dev->bus->number, dev->devfn);
320 EXPORT_SYMBOL_GPL(cxl_pci_to_cfg_record);