2 * CARMA Board DATA-FPGA Programmer
4 * Copyright (c) 2009-2011 Ira W. Snyder <iws@ovro.caltech.edu>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
12 #include <linux/dma-mapping.h>
13 #include <linux/of_address.h>
14 #include <linux/of_irq.h>
15 #include <linux/of_platform.h>
16 #include <linux/completion.h>
17 #include <linux/miscdevice.h>
18 #include <linux/dmaengine.h>
19 #include <linux/fsldma.h>
20 #include <linux/interrupt.h>
21 #include <linux/highmem.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/mutex.h>
25 #include <linux/delay.h>
26 #include <linux/init.h>
27 #include <linux/leds.h>
28 #include <linux/slab.h>
29 #include <linux/kref.h>
33 #include <media/videobuf-dma-sg.h>
35 /* MPC8349EMDS specific get_immrbase() */
36 #include <sysdev/fsl_soc.h>
38 static const char drv_name[] = "carma-fpga-program";
41 * Firmware images are always this exact size
43 * 12849552 bytes for a CARMA Digitizer Board (EP2S90 FPGAs)
44 * 18662880 bytes for a CARMA Correlator Board (EP2S130 FPGAs)
46 #define FW_SIZE_EP2S90 12849552
47 #define FW_SIZE_EP2S130 18662880
50 struct miscdevice miscdev;
55 /* Device Registers */
60 /* Freescale DMA Device */
61 struct dma_chan *chan;
65 struct completion completion;
70 struct videobuf_dmabuf vb;
73 /* max size and written bytes */
79 * FPGA Bitfile Helpers
83 * fpga_drop_firmware_data() - drop the bitfile image from memory
84 * @priv: the driver's private data structure
86 * LOCKING: must hold priv->lock
88 static void fpga_drop_firmware_data(struct fpga_dev *priv)
90 videobuf_dma_free(&priv->vb);
91 priv->vb_allocated = false;
96 * Private Data Reference Count
99 static void fpga_dev_remove(struct kref *ref)
101 struct fpga_dev *priv = container_of(ref, struct fpga_dev, ref);
103 /* free any firmware image that was not programmed */
104 fpga_drop_firmware_data(priv);
106 mutex_destroy(&priv->lock);
111 * LED Trigger (could be a seperate module)
115 * NOTE: this whole thing does have the problem that whenever the led's are
116 * NOTE: first set to use the fpga trigger, they could be in the wrong state
119 DEFINE_LED_TRIGGER(ledtrig_fpga);
121 static void ledtrig_fpga_programmed(bool enabled)
124 led_trigger_event(ledtrig_fpga, LED_FULL);
126 led_trigger_event(ledtrig_fpga, LED_OFF);
130 * FPGA Register Helpers
133 /* Register Definitions */
134 #define FPGA_CONFIG_CONTROL 0x40
135 #define FPGA_CONFIG_STATUS 0x44
136 #define FPGA_CONFIG_FIFO_SIZE 0x48
137 #define FPGA_CONFIG_FIFO_USED 0x4C
138 #define FPGA_CONFIG_TOTAL_BYTE_COUNT 0x50
139 #define FPGA_CONFIG_CUR_BYTE_COUNT 0x54
141 #define FPGA_FIFO_ADDRESS 0x3000
143 static int fpga_fifo_size(void __iomem *regs)
145 return ioread32be(regs + FPGA_CONFIG_FIFO_SIZE);
148 #define CFG_STATUS_ERR_MASK 0xfffe
150 static int fpga_config_error(void __iomem *regs)
152 return ioread32be(regs + FPGA_CONFIG_STATUS) & CFG_STATUS_ERR_MASK;
155 static int fpga_fifo_empty(void __iomem *regs)
157 return ioread32be(regs + FPGA_CONFIG_FIFO_USED) == 0;
160 static void fpga_fifo_write(void __iomem *regs, u32 val)
162 iowrite32be(val, regs + FPGA_FIFO_ADDRESS);
165 static void fpga_set_byte_count(void __iomem *regs, u32 count)
167 iowrite32be(count, regs + FPGA_CONFIG_TOTAL_BYTE_COUNT);
170 #define CFG_CTL_ENABLE (1 << 0)
171 #define CFG_CTL_RESET (1 << 1)
172 #define CFG_CTL_DMA (1 << 2)
174 static void fpga_programmer_enable(struct fpga_dev *priv, bool dma)
178 val = (dma) ? (CFG_CTL_ENABLE | CFG_CTL_DMA) : CFG_CTL_ENABLE;
179 iowrite32be(val, priv->regs + FPGA_CONFIG_CONTROL);
182 static void fpga_programmer_disable(struct fpga_dev *priv)
184 iowrite32be(0x0, priv->regs + FPGA_CONFIG_CONTROL);
187 static void fpga_dump_registers(struct fpga_dev *priv)
189 u32 control, status, size, used, total, curr;
191 /* good status: do nothing */
192 if (priv->status == 0)
195 /* Dump all status registers */
196 control = ioread32be(priv->regs + FPGA_CONFIG_CONTROL);
197 status = ioread32be(priv->regs + FPGA_CONFIG_STATUS);
198 size = ioread32be(priv->regs + FPGA_CONFIG_FIFO_SIZE);
199 used = ioread32be(priv->regs + FPGA_CONFIG_FIFO_USED);
200 total = ioread32be(priv->regs + FPGA_CONFIG_TOTAL_BYTE_COUNT);
201 curr = ioread32be(priv->regs + FPGA_CONFIG_CUR_BYTE_COUNT);
203 dev_err(priv->dev, "Configuration failed, dumping status registers\n");
204 dev_err(priv->dev, "Control: 0x%.8x\n", control);
205 dev_err(priv->dev, "Status: 0x%.8x\n", status);
206 dev_err(priv->dev, "FIFO Size: 0x%.8x\n", size);
207 dev_err(priv->dev, "FIFO Used: 0x%.8x\n", used);
208 dev_err(priv->dev, "FIFO Total: 0x%.8x\n", total);
209 dev_err(priv->dev, "FIFO Curr: 0x%.8x\n", curr);
213 * FPGA Power Supply Code
216 #define CTL_PWR_CONTROL 0x2006
217 #define CTL_PWR_STATUS 0x200A
218 #define CTL_PWR_FAIL 0x200B
220 #define PWR_CONTROL_ENABLE 0x01
222 #define PWR_STATUS_ERROR_MASK 0x10
223 #define PWR_STATUS_GOOD 0x0f
226 * Determine if the FPGA power is good for all supplies
228 static bool fpga_power_good(struct fpga_dev *priv)
232 val = ioread8(priv->regs + CTL_PWR_STATUS);
233 if (val & PWR_STATUS_ERROR_MASK)
236 return val == PWR_STATUS_GOOD;
240 * Disable the FPGA power supplies
242 static void fpga_disable_power_supplies(struct fpga_dev *priv)
247 iowrite8(0x0, priv->regs + CTL_PWR_CONTROL);
250 * Wait 500ms for the power rails to discharge
252 * Without this delay, the CTL-CPLD state machine can get into a
253 * state where it is waiting for the power-goods to assert, but they
254 * never do. This only happens when enabling and disabling the
255 * power sequencer very rapidly.
257 * The loop below will also wait for the power goods to de-assert,
258 * but testing has shown that they are always disabled by the time
259 * the sleep completes. However, omitting the sleep and only waiting
260 * for the power-goods to de-assert was not sufficient to ensure
261 * that the power sequencer would not wedge itself.
266 while (time_before(jiffies, start + HZ)) {
267 val = ioread8(priv->regs + CTL_PWR_STATUS);
268 if (!(val & PWR_STATUS_GOOD))
271 usleep_range(5000, 10000);
274 val = ioread8(priv->regs + CTL_PWR_STATUS);
275 if (val & PWR_STATUS_GOOD) {
276 dev_err(priv->dev, "power disable failed: "
277 "power goods: status 0x%.2x\n", val);
280 if (val & PWR_STATUS_ERROR_MASK) {
281 dev_err(priv->dev, "power disable failed: "
282 "alarm bit set: status 0x%.2x\n", val);
287 * fpga_enable_power_supplies() - enable the DATA-FPGA power supplies
288 * @priv: the driver's private data structure
290 * Enable the DATA-FPGA power supplies, waiting up to 1 second for
291 * them to enable successfully.
293 * Returns 0 on success, -ERRNO otherwise
295 static int fpga_enable_power_supplies(struct fpga_dev *priv)
297 unsigned long start = jiffies;
299 if (fpga_power_good(priv)) {
300 dev_dbg(priv->dev, "power was already good\n");
304 iowrite8(PWR_CONTROL_ENABLE, priv->regs + CTL_PWR_CONTROL);
305 while (time_before(jiffies, start + HZ)) {
306 if (fpga_power_good(priv))
309 usleep_range(5000, 10000);
312 return fpga_power_good(priv) ? 0 : -ETIMEDOUT;
316 * Determine if the FPGA power supplies are all enabled
318 static bool fpga_power_enabled(struct fpga_dev *priv)
322 val = ioread8(priv->regs + CTL_PWR_CONTROL);
323 if (val & PWR_CONTROL_ENABLE)
330 * Determine if the FPGA's are programmed and running correctly
332 static bool fpga_running(struct fpga_dev *priv)
334 if (!fpga_power_good(priv))
337 /* Check the config done bit */
338 return ioread32be(priv->regs + FPGA_CONFIG_STATUS) & (1 << 18);
342 * FPGA Programming Code
346 * fpga_program_block() - put a block of data into the programmer's FIFO
347 * @priv: the driver's private data structure
348 * @buf: the data to program
349 * @count: the length of data to program (must be a multiple of 4 bytes)
351 * Returns 0 on success, -ERRNO otherwise
353 static int fpga_program_block(struct fpga_dev *priv, void *buf, size_t count)
356 int size = fpga_fifo_size(priv->regs);
358 unsigned long timeout;
360 /* enforce correct data length for the FIFO */
361 BUG_ON(count % 4 != 0);
365 /* Get the size of the block to write (maximum is FIFO_SIZE) */
366 len = min_t(size_t, count, size);
367 timeout = jiffies + HZ / 4;
369 /* Write the block */
370 for (i = 0; i < len / 4; i++)
371 fpga_fifo_write(priv->regs, data[i]);
373 /* Update the amounts left */
377 /* Wait for the fifo to empty */
380 if (fpga_fifo_empty(priv->regs)) {
383 dev_dbg(priv->dev, "Fifo not empty\n");
387 if (fpga_config_error(priv->regs)) {
388 dev_err(priv->dev, "Error detected\n");
392 if (time_after(jiffies, timeout)) {
393 dev_err(priv->dev, "Fifo drain timeout\n");
397 usleep_range(5000, 10000);
405 * fpga_program_cpu() - program the DATA-FPGA's using the CPU
406 * @priv: the driver's private data structure
408 * This is useful when the DMA programming method fails. It is possible to
409 * wedge the Freescale DMA controller such that the DMA programming method
410 * always fails. This method has always succeeded.
412 * Returns 0 on success, -ERRNO otherwise
414 static noinline int fpga_program_cpu(struct fpga_dev *priv)
418 /* Disable the programmer */
419 fpga_programmer_disable(priv);
421 /* Set the total byte count */
422 fpga_set_byte_count(priv->regs, priv->bytes);
423 dev_dbg(priv->dev, "total byte count %u bytes\n", priv->bytes);
425 /* Enable the controller for programming */
426 fpga_programmer_enable(priv, false);
427 dev_dbg(priv->dev, "enabled the controller\n");
429 /* Write each chunk of the FPGA bitfile to FPGA programmer */
430 ret = fpga_program_block(priv, priv->vb.vaddr, priv->bytes);
432 goto out_disable_controller;
434 /* Wait for the interrupt handler to signal that programming finished */
435 ret = wait_for_completion_timeout(&priv->completion, 2 * HZ);
437 dev_err(priv->dev, "Timed out waiting for completion\n");
439 goto out_disable_controller;
442 /* Retrieve the status from the interrupt handler */
445 out_disable_controller:
446 fpga_programmer_disable(priv);
450 #define FIFO_DMA_ADDRESS 0xf0003000
451 #define FIFO_MAX_LEN 4096
454 * fpga_program_dma() - program the DATA-FPGA's using the DMA engine
455 * @priv: the driver's private data structure
457 * Program the DATA-FPGA's using the Freescale DMA engine. This requires that
458 * the engine is programmed such that the hardware DMA request lines can
459 * control the entire DMA transaction. The system controller FPGA then
460 * completely offloads the programming from the CPU.
462 * Returns 0 on success, -ERRNO otherwise
464 static noinline int fpga_program_dma(struct fpga_dev *priv)
466 struct videobuf_dmabuf *vb = &priv->vb;
467 struct dma_chan *chan = priv->chan;
468 struct dma_async_tx_descriptor *tx;
469 size_t num_pages, len, avail = 0;
470 struct dma_slave_config config;
471 struct scatterlist *sg;
472 struct sg_table table;
476 /* Disable the programmer */
477 fpga_programmer_disable(priv);
479 /* Allocate a scatterlist for the DMA destination */
480 num_pages = DIV_ROUND_UP(priv->bytes, FIFO_MAX_LEN);
481 ret = sg_alloc_table(&table, num_pages, GFP_KERNEL);
483 dev_err(priv->dev, "Unable to allocate dst scatterlist\n");
489 * This is an ugly hack
491 * We fill in a scatterlist as if it were mapped for DMA. This is
492 * necessary because there exists no better structure for this
493 * inside the kernel code.
495 * As an added bonus, we can use the DMAEngine API for all of this,
496 * rather than inventing another extremely similar API.
499 for_each_sg(table.sgl, sg, num_pages, i) {
500 len = min_t(size_t, avail, FIFO_MAX_LEN);
501 sg_dma_address(sg) = FIFO_DMA_ADDRESS;
502 sg_dma_len(sg) = len;
507 /* Map the buffer for DMA */
508 ret = videobuf_dma_map(priv->dev, &priv->vb);
510 dev_err(priv->dev, "Unable to map buffer for DMA\n");
515 * Configure the DMA channel to transfer FIFO_SIZE / 2 bytes per
516 * transaction, and then put it under external control
518 memset(&config, 0, sizeof(config));
519 config.direction = DMA_MEM_TO_DEV;
520 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
521 config.dst_maxburst = fpga_fifo_size(priv->regs) / 2 / 4;
522 ret = dmaengine_slave_config(chan, &config);
524 dev_err(priv->dev, "DMA slave configuration failed\n");
528 ret = fsl_dma_external_start(chan, 1)
530 dev_err(priv->dev, "DMA external control setup failed\n");
534 /* setup and submit the DMA transaction */
536 tx = dmaengine_prep_dma_sg(chan, table.sgl, num_pages,
537 vb->sglist, vb->sglen, 0);
539 dev_err(priv->dev, "Unable to prep DMA transaction\n");
544 cookie = tx->tx_submit(tx);
545 if (dma_submit_error(cookie)) {
546 dev_err(priv->dev, "Unable to submit DMA transaction\n");
551 dma_async_issue_pending(chan);
553 /* Set the total byte count */
554 fpga_set_byte_count(priv->regs, priv->bytes);
555 dev_dbg(priv->dev, "total byte count %u bytes\n", priv->bytes);
557 /* Enable the controller for DMA programming */
558 fpga_programmer_enable(priv, true);
559 dev_dbg(priv->dev, "enabled the controller\n");
561 /* Wait for the interrupt handler to signal that programming finished */
562 ret = wait_for_completion_timeout(&priv->completion, 2 * HZ);
564 dev_err(priv->dev, "Timed out waiting for completion\n");
566 goto out_disable_controller;
569 /* Retrieve the status from the interrupt handler */
572 out_disable_controller:
573 fpga_programmer_disable(priv);
575 videobuf_dma_unmap(priv->dev, vb);
577 sg_free_table(&table);
586 static irqreturn_t fpga_irq(int irq, void *dev_id)
588 struct fpga_dev *priv = dev_id;
590 /* Save the status */
591 priv->status = fpga_config_error(priv->regs) ? -EIO : 0;
592 dev_dbg(priv->dev, "INTERRUPT status %d\n", priv->status);
593 fpga_dump_registers(priv);
595 /* Disabling the programmer clears the interrupt */
596 fpga_programmer_disable(priv);
598 /* Notify any waiters */
599 complete(&priv->completion);
609 * fpga_do_stop() - deconfigure (reset) the DATA-FPGA's
610 * @priv: the driver's private data structure
612 * LOCKING: must hold priv->lock
614 static int fpga_do_stop(struct fpga_dev *priv)
618 /* Set the led to unprogrammed */
619 ledtrig_fpga_programmed(false);
621 /* Pulse the config line to reset the FPGA's */
622 val = CFG_CTL_ENABLE | CFG_CTL_RESET;
623 iowrite32be(val, priv->regs + FPGA_CONFIG_CONTROL);
624 iowrite32be(0x0, priv->regs + FPGA_CONFIG_CONTROL);
629 static noinline int fpga_do_program(struct fpga_dev *priv)
633 if (priv->bytes != priv->fw_size) {
634 dev_err(priv->dev, "Incorrect bitfile size: got %zu bytes, "
635 "should be %zu bytes\n",
636 priv->bytes, priv->fw_size);
640 if (!fpga_power_enabled(priv)) {
641 dev_err(priv->dev, "Power not enabled\n");
645 if (!fpga_power_good(priv)) {
646 dev_err(priv->dev, "Power not good\n");
650 /* Set the LED to unprogrammed */
651 ledtrig_fpga_programmed(false);
653 /* Try to program the FPGA's using DMA */
654 ret = fpga_program_dma(priv);
656 /* If DMA failed or doesn't exist, try with CPU */
658 dev_warn(priv->dev, "Falling back to CPU programming\n");
659 ret = fpga_program_cpu(priv);
663 dev_err(priv->dev, "Unable to program FPGA's\n");
667 /* Drop the firmware bitfile from memory */
668 fpga_drop_firmware_data(priv);
670 dev_dbg(priv->dev, "FPGA programming successful\n");
671 ledtrig_fpga_programmed(true);
680 static int fpga_open(struct inode *inode, struct file *filp)
683 * The miscdevice layer puts our struct miscdevice into the
684 * filp->private_data field. We use this to find our private
685 * data and then overwrite it with our own private structure.
687 struct fpga_dev *priv = container_of(filp->private_data,
688 struct fpga_dev, miscdev);
689 unsigned int nr_pages;
692 /* We only allow one process at a time */
693 ret = mutex_lock_interruptible(&priv->lock);
697 filp->private_data = priv;
698 kref_get(&priv->ref);
700 /* Truncation: drop any existing data */
701 if (filp->f_flags & O_TRUNC)
704 /* Check if we have already allocated a buffer */
705 if (priv->vb_allocated)
708 /* Allocate a buffer to hold enough data for the bitfile */
709 nr_pages = DIV_ROUND_UP(priv->fw_size, PAGE_SIZE);
710 ret = videobuf_dma_init_kernel(&priv->vb, DMA_TO_DEVICE, nr_pages);
712 dev_err(priv->dev, "unable to allocate data buffer\n");
713 mutex_unlock(&priv->lock);
714 kref_put(&priv->ref, fpga_dev_remove);
718 priv->vb_allocated = true;
722 static int fpga_release(struct inode *inode, struct file *filp)
724 struct fpga_dev *priv = filp->private_data;
726 mutex_unlock(&priv->lock);
727 kref_put(&priv->ref, fpga_dev_remove);
731 static ssize_t fpga_write(struct file *filp, const char __user *buf,
732 size_t count, loff_t *f_pos)
734 struct fpga_dev *priv = filp->private_data;
736 /* FPGA bitfiles have an exact size: disallow anything else */
737 if (priv->bytes >= priv->fw_size)
740 count = min_t(size_t, priv->fw_size - priv->bytes, count);
741 if (copy_from_user(priv->vb.vaddr + priv->bytes, buf, count))
744 priv->bytes += count;
748 static ssize_t fpga_read(struct file *filp, char __user *buf, size_t count,
751 struct fpga_dev *priv = filp->private_data;
752 return simple_read_from_buffer(buf, count, ppos,
753 priv->vb.vaddr, priv->bytes);
756 static loff_t fpga_llseek(struct file *filp, loff_t offset, int origin)
758 struct fpga_dev *priv = filp->private_data;
761 /* only read-only opens are allowed to seek */
762 if ((filp->f_flags & O_ACCMODE) != O_RDONLY)
765 return fixed_size_llseek(file, offset, origin, priv->fw_size);
768 static const struct file_operations fpga_fops = {
770 .release = fpga_release,
773 .llseek = fpga_llseek,
780 static ssize_t pfail_show(struct device *dev, struct device_attribute *attr,
783 struct fpga_dev *priv = dev_get_drvdata(dev);
786 val = ioread8(priv->regs + CTL_PWR_FAIL);
787 return snprintf(buf, PAGE_SIZE, "0x%.2x\n", val);
790 static ssize_t pgood_show(struct device *dev, struct device_attribute *attr,
793 struct fpga_dev *priv = dev_get_drvdata(dev);
794 return snprintf(buf, PAGE_SIZE, "%d\n", fpga_power_good(priv));
797 static ssize_t penable_show(struct device *dev, struct device_attribute *attr,
800 struct fpga_dev *priv = dev_get_drvdata(dev);
801 return snprintf(buf, PAGE_SIZE, "%d\n", fpga_power_enabled(priv));
804 static ssize_t penable_store(struct device *dev, struct device_attribute *attr,
805 const char *buf, size_t count)
807 struct fpga_dev *priv = dev_get_drvdata(dev);
811 ret = kstrtoul(buf, 0, &val);
816 ret = fpga_enable_power_supplies(priv);
821 fpga_disable_power_supplies(priv);
827 static ssize_t program_show(struct device *dev, struct device_attribute *attr,
830 struct fpga_dev *priv = dev_get_drvdata(dev);
831 return snprintf(buf, PAGE_SIZE, "%d\n", fpga_running(priv));
834 static ssize_t program_store(struct device *dev, struct device_attribute *attr,
835 const char *buf, size_t count)
837 struct fpga_dev *priv = dev_get_drvdata(dev);
841 ret = kstrtoul(buf, 0, &val);
845 /* We can't have an image writer and be programming simultaneously */
846 if (mutex_lock_interruptible(&priv->lock))
849 /* Program or Reset the FPGA's */
850 ret = val ? fpga_do_program(priv) : fpga_do_stop(priv);
858 mutex_unlock(&priv->lock);
862 static DEVICE_ATTR(power_fail, S_IRUGO, pfail_show, NULL);
863 static DEVICE_ATTR(power_good, S_IRUGO, pgood_show, NULL);
864 static DEVICE_ATTR(power_enable, S_IRUGO | S_IWUSR,
865 penable_show, penable_store);
867 static DEVICE_ATTR(program, S_IRUGO | S_IWUSR,
868 program_show, program_store);
870 static struct attribute *fpga_attributes[] = {
871 &dev_attr_power_fail.attr,
872 &dev_attr_power_good.attr,
873 &dev_attr_power_enable.attr,
874 &dev_attr_program.attr,
878 static const struct attribute_group fpga_attr_group = {
879 .attrs = fpga_attributes,
883 * OpenFirmware Device Subsystem
886 #define SYS_REG_VERSION 0x00
887 #define SYS_REG_GEOGRAPHIC 0x10
889 static bool dma_filter(struct dma_chan *chan, void *data)
892 * DMA Channel #0 is the only acceptable device
894 * This probably won't survive an unload/load cycle of the Freescale
895 * DMAEngine driver, but that won't be a problem
897 return chan->chan_id == 0 && chan->device->dev_id == 0;
900 static int fpga_of_remove(struct platform_device *op)
902 struct fpga_dev *priv = platform_get_drvdata(op);
903 struct device *this_device = priv->miscdev.this_device;
905 sysfs_remove_group(&this_device->kobj, &fpga_attr_group);
906 misc_deregister(&priv->miscdev);
908 free_irq(priv->irq, priv);
909 irq_dispose_mapping(priv->irq);
911 /* make sure the power supplies are off */
912 fpga_disable_power_supplies(priv);
914 /* unmap registers */
918 dma_release_channel(priv->chan);
920 /* drop our reference to the private data structure */
921 kref_put(&priv->ref, fpga_dev_remove);
925 /* CTL-CPLD Version Register */
926 #define CTL_CPLD_VERSION 0x2000
928 static int fpga_of_probe(struct platform_device *op)
930 struct device_node *of_node = op->dev.of_node;
931 struct device *this_device;
932 struct fpga_dev *priv;
937 /* Allocate private data */
938 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
940 dev_err(&op->dev, "Unable to allocate private data\n");
945 /* Setup the miscdevice */
946 priv->miscdev.minor = MISC_DYNAMIC_MINOR;
947 priv->miscdev.name = drv_name;
948 priv->miscdev.fops = &fpga_fops;
950 kref_init(&priv->ref);
952 platform_set_drvdata(op, priv);
953 priv->dev = &op->dev;
954 mutex_init(&priv->lock);
955 init_completion(&priv->completion);
956 videobuf_dma_init(&priv->vb);
958 dev_set_drvdata(priv->dev, priv);
960 dma_cap_set(DMA_MEMCPY, mask);
961 dma_cap_set(DMA_SLAVE, mask);
962 dma_cap_set(DMA_SG, mask);
964 /* Get control of DMA channel #0 */
965 priv->chan = dma_request_channel(mask, dma_filter, NULL);
967 dev_err(&op->dev, "Unable to acquire DMA channel #0\n");
972 /* Remap the registers for use */
973 priv->regs = of_iomap(of_node, 0);
975 dev_err(&op->dev, "Unable to ioremap registers\n");
977 goto out_dma_release_channel;
980 /* Remap the IMMR for use */
981 priv->immr = ioremap(get_immrbase(), 0x100000);
983 dev_err(&op->dev, "Unable to ioremap IMMR\n");
989 * Check that external DMA is configured
991 * U-Boot does this for us, but we should check it and bail out if
992 * there is a problem. Failing to have this register setup correctly
993 * will cause the DMA controller to transfer a single cacheline
994 * worth of data, then wedge itself.
996 if ((ioread32be(priv->immr + 0x114) & 0xE00) != 0xE00) {
997 dev_err(&op->dev, "External DMA control not configured\n");
1003 * Check the CTL-CPLD version
1005 * This driver uses the CTL-CPLD DATA-FPGA power sequencer, and we
1006 * don't want to run on any version of the CTL-CPLD that does not use
1007 * a compatible register layout.
1009 * v2: changed register layout, added power sequencer
1010 * v3: added glitch filter on the i2c overcurrent/overtemp outputs
1012 ver = ioread8(priv->regs + CTL_CPLD_VERSION);
1013 if (ver != 0x02 && ver != 0x03) {
1014 dev_err(&op->dev, "CTL-CPLD is not version 0x02 or 0x03!\n");
1016 goto out_unmap_immr;
1019 /* Set the exact size that the firmware image should be */
1020 ver = ioread32be(priv->regs + SYS_REG_VERSION);
1021 priv->fw_size = (ver & (1 << 18)) ? FW_SIZE_EP2S130 : FW_SIZE_EP2S90;
1023 /* Find the correct IRQ number */
1024 priv->irq = irq_of_parse_and_map(of_node, 0);
1025 if (priv->irq == NO_IRQ) {
1026 dev_err(&op->dev, "Unable to find IRQ line\n");
1028 goto out_unmap_immr;
1031 /* Request the IRQ */
1032 ret = request_irq(priv->irq, fpga_irq, IRQF_SHARED, drv_name, priv);
1034 dev_err(&op->dev, "Unable to request IRQ %d\n", priv->irq);
1036 goto out_irq_dispose_mapping;
1039 /* Reset and stop the FPGA's, just in case */
1042 /* Register the miscdevice */
1043 ret = misc_register(&priv->miscdev);
1045 dev_err(&op->dev, "Unable to register miscdevice\n");
1049 /* Create the sysfs files */
1050 this_device = priv->miscdev.this_device;
1051 dev_set_drvdata(this_device, priv);
1052 ret = sysfs_create_group(&this_device->kobj, &fpga_attr_group);
1054 dev_err(&op->dev, "Unable to create sysfs files\n");
1055 goto out_misc_deregister;
1058 dev_info(priv->dev, "CARMA FPGA Programmer: %s rev%s with %s FPGAs\n",
1059 (ver & (1 << 17)) ? "Correlator" : "Digitizer",
1060 (ver & (1 << 16)) ? "B" : "A",
1061 (ver & (1 << 18)) ? "EP2S130" : "EP2S90");
1065 out_misc_deregister:
1066 misc_deregister(&priv->miscdev);
1068 free_irq(priv->irq, priv);
1069 out_irq_dispose_mapping:
1070 irq_dispose_mapping(priv->irq);
1072 iounmap(priv->immr);
1074 iounmap(priv->regs);
1075 out_dma_release_channel:
1076 dma_release_channel(priv->chan);
1078 kref_put(&priv->ref, fpga_dev_remove);
1083 static struct of_device_id fpga_of_match[] = {
1084 { .compatible = "carma,fpga-programmer", },
1088 static struct platform_driver fpga_of_driver = {
1089 .probe = fpga_of_probe,
1090 .remove = fpga_of_remove,
1093 .of_match_table = fpga_of_match,
1094 .owner = THIS_MODULE,
1099 * Module Init / Exit
1102 static int __init fpga_init(void)
1104 led_trigger_register_simple("fpga", &ledtrig_fpga);
1105 return platform_driver_register(&fpga_of_driver);
1108 static void __exit fpga_exit(void)
1110 platform_driver_unregister(&fpga_of_driver);
1111 led_trigger_unregister_simple(ledtrig_fpga);
1114 MODULE_AUTHOR("Ira W. Snyder <iws@ovro.caltech.edu>");
1115 MODULE_DESCRIPTION("CARMA Board DATA-FPGA Programmer");
1116 MODULE_LICENSE("GPL");
1118 module_init(fpga_init);
1119 module_exit(fpga_exit);