1 // SPDX-License-Identifier: GPL-2.0-only
3 * Intel Sunrisepoint LPSS core support.
5 * Copyright (C) 2015, Intel Corporation
7 * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
8 * Mika Westerberg <mika.westerberg@linux.intel.com>
9 * Heikki Krogerus <heikki.krogerus@linux.intel.com>
10 * Jarkko Nikula <jarkko.nikula@linux.intel.com>
13 #include <linux/clk.h>
14 #include <linux/clkdev.h>
15 #include <linux/clk-provider.h>
16 #include <linux/debugfs.h>
17 #include <linux/idr.h>
19 #include <linux/ioport.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/mfd/core.h>
23 #include <linux/pm_qos.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/property.h>
26 #include <linux/seq_file.h>
27 #include <linux/io-64-nonatomic-lo-hi.h>
29 #include <linux/dma/idma64.h>
31 #include "intel-lpss.h"
33 #define LPSS_DEV_OFFSET 0x000
34 #define LPSS_DEV_SIZE 0x200
35 #define LPSS_PRIV_OFFSET 0x200
36 #define LPSS_PRIV_SIZE 0x100
37 #define LPSS_PRIV_REG_COUNT (LPSS_PRIV_SIZE / 4)
38 #define LPSS_IDMA64_OFFSET 0x800
39 #define LPSS_IDMA64_SIZE 0x800
41 /* Offsets from lpss->priv */
42 #define LPSS_PRIV_RESETS 0x04
43 #define LPSS_PRIV_RESETS_IDMA BIT(2)
44 #define LPSS_PRIV_RESETS_FUNC 0x3
46 #define LPSS_PRIV_ACTIVELTR 0x10
47 #define LPSS_PRIV_IDLELTR 0x14
49 #define LPSS_PRIV_LTR_REQ BIT(15)
50 #define LPSS_PRIV_LTR_SCALE_MASK 0xc00
51 #define LPSS_PRIV_LTR_SCALE_1US 0x800
52 #define LPSS_PRIV_LTR_SCALE_32US 0xc00
53 #define LPSS_PRIV_LTR_VALUE_MASK 0x3ff
55 #define LPSS_PRIV_SSP_REG 0x20
56 #define LPSS_PRIV_SSP_REG_DIS_DMA_FIN BIT(0)
58 #define LPSS_PRIV_REMAP_ADDR 0x40
60 #define LPSS_PRIV_CAPS 0xfc
61 #define LPSS_PRIV_CAPS_NO_IDMA BIT(8)
62 #define LPSS_PRIV_CAPS_TYPE_SHIFT 4
63 #define LPSS_PRIV_CAPS_TYPE_MASK (0xf << LPSS_PRIV_CAPS_TYPE_SHIFT)
65 /* This matches the type field in CAPS register */
66 enum intel_lpss_dev_type {
73 const struct intel_lpss_platform_info *info;
74 enum intel_lpss_dev_type type;
76 struct clk_lookup *clock;
77 struct mfd_cell *cell;
80 u32 priv_ctx[LPSS_PRIV_REG_COUNT];
85 struct dentry *debugfs;
88 static const struct resource intel_lpss_dev_resources[] = {
89 DEFINE_RES_MEM_NAMED(LPSS_DEV_OFFSET, LPSS_DEV_SIZE, "lpss_dev"),
90 DEFINE_RES_MEM_NAMED(LPSS_PRIV_OFFSET, LPSS_PRIV_SIZE, "lpss_priv"),
94 static const struct resource intel_lpss_idma64_resources[] = {
95 DEFINE_RES_MEM(LPSS_IDMA64_OFFSET, LPSS_IDMA64_SIZE),
100 * Cells needs to be ordered so that the iDMA is created first. This is
101 * because we need to be sure the DMA is available when the host controller
104 static const struct mfd_cell intel_lpss_idma64_cell = {
105 .name = LPSS_IDMA64_DRIVER_NAME,
106 .num_resources = ARRAY_SIZE(intel_lpss_idma64_resources),
107 .resources = intel_lpss_idma64_resources,
110 static const struct mfd_cell intel_lpss_i2c_cell = {
111 .name = "i2c_designware",
112 .num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
113 .resources = intel_lpss_dev_resources,
116 static const struct mfd_cell intel_lpss_uart_cell = {
117 .name = "dw-apb-uart",
118 .num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
119 .resources = intel_lpss_dev_resources,
122 static const struct mfd_cell intel_lpss_spi_cell = {
123 .name = "pxa2xx-spi",
124 .num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
125 .resources = intel_lpss_dev_resources,
128 static DEFINE_IDA(intel_lpss_devid_ida);
129 static struct dentry *intel_lpss_debugfs;
131 static int intel_lpss_request_dma_module(const char *name)
133 static bool intel_lpss_dma_requested;
135 if (intel_lpss_dma_requested)
138 intel_lpss_dma_requested = true;
139 return request_module("%s", name);
142 static void intel_lpss_cache_ltr(struct intel_lpss *lpss)
144 lpss->active_ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);
145 lpss->idle_ltr = readl(lpss->priv + LPSS_PRIV_IDLELTR);
148 static int intel_lpss_debugfs_add(struct intel_lpss *lpss)
152 dir = debugfs_create_dir(dev_name(lpss->dev), intel_lpss_debugfs);
156 /* Cache the values into lpss structure */
157 intel_lpss_cache_ltr(lpss);
159 debugfs_create_x32("capabilities", S_IRUGO, dir, &lpss->caps);
160 debugfs_create_x32("active_ltr", S_IRUGO, dir, &lpss->active_ltr);
161 debugfs_create_x32("idle_ltr", S_IRUGO, dir, &lpss->idle_ltr);
167 static void intel_lpss_debugfs_remove(struct intel_lpss *lpss)
169 debugfs_remove_recursive(lpss->debugfs);
172 static void intel_lpss_ltr_set(struct device *dev, s32 val)
174 struct intel_lpss *lpss = dev_get_drvdata(dev);
178 * Program latency tolerance (LTR) accordingly what has been asked
179 * by the PM QoS layer or disable it in case we were passed
180 * negative value or PM_QOS_LATENCY_ANY.
182 ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);
184 if (val == PM_QOS_LATENCY_ANY || val < 0) {
185 ltr &= ~LPSS_PRIV_LTR_REQ;
187 ltr |= LPSS_PRIV_LTR_REQ;
188 ltr &= ~LPSS_PRIV_LTR_SCALE_MASK;
189 ltr &= ~LPSS_PRIV_LTR_VALUE_MASK;
191 if (val > LPSS_PRIV_LTR_VALUE_MASK)
192 ltr |= LPSS_PRIV_LTR_SCALE_32US | val >> 5;
194 ltr |= LPSS_PRIV_LTR_SCALE_1US | val;
197 if (ltr == lpss->active_ltr)
200 writel(ltr, lpss->priv + LPSS_PRIV_ACTIVELTR);
201 writel(ltr, lpss->priv + LPSS_PRIV_IDLELTR);
203 /* Cache the values into lpss structure */
204 intel_lpss_cache_ltr(lpss);
207 static void intel_lpss_ltr_expose(struct intel_lpss *lpss)
209 lpss->dev->power.set_latency_tolerance = intel_lpss_ltr_set;
210 dev_pm_qos_expose_latency_tolerance(lpss->dev);
213 static void intel_lpss_ltr_hide(struct intel_lpss *lpss)
215 dev_pm_qos_hide_latency_tolerance(lpss->dev);
216 lpss->dev->power.set_latency_tolerance = NULL;
219 static int intel_lpss_assign_devs(struct intel_lpss *lpss)
221 const struct mfd_cell *cell;
224 type = lpss->caps & LPSS_PRIV_CAPS_TYPE_MASK;
225 type >>= LPSS_PRIV_CAPS_TYPE_SHIFT;
229 cell = &intel_lpss_i2c_cell;
232 cell = &intel_lpss_uart_cell;
235 cell = &intel_lpss_spi_cell;
241 lpss->cell = devm_kmemdup(lpss->dev, cell, sizeof(*cell), GFP_KERNEL);
250 static bool intel_lpss_has_idma(const struct intel_lpss *lpss)
252 return (lpss->caps & LPSS_PRIV_CAPS_NO_IDMA) == 0;
255 static void intel_lpss_set_remap_addr(const struct intel_lpss *lpss)
257 resource_size_t addr = lpss->info->mem->start;
259 lo_hi_writeq(addr, lpss->priv + LPSS_PRIV_REMAP_ADDR);
262 static void intel_lpss_deassert_reset(const struct intel_lpss *lpss)
264 u32 value = LPSS_PRIV_RESETS_FUNC | LPSS_PRIV_RESETS_IDMA;
266 /* Bring out the device from reset */
267 writel(value, lpss->priv + LPSS_PRIV_RESETS);
270 static void intel_lpss_init_dev(const struct intel_lpss *lpss)
272 u32 value = LPSS_PRIV_SSP_REG_DIS_DMA_FIN;
274 /* Set the device in reset state */
275 writel(0, lpss->priv + LPSS_PRIV_RESETS);
277 intel_lpss_deassert_reset(lpss);
279 intel_lpss_set_remap_addr(lpss);
281 if (!intel_lpss_has_idma(lpss))
284 /* Make sure that SPI multiblock DMA transfers are re-enabled */
285 if (lpss->type == LPSS_DEV_SPI)
286 writel(value, lpss->priv + LPSS_PRIV_SSP_REG);
289 static void intel_lpss_unregister_clock_tree(struct clk *clk)
294 parent = clk_get_parent(clk);
300 static int intel_lpss_register_clock_divider(struct intel_lpss *lpss,
305 struct clk *tmp = *clk;
307 snprintf(name, sizeof(name), "%s-enable", devname);
308 tmp = clk_register_gate(NULL, name, __clk_get_name(tmp), 0,
309 lpss->priv, 0, 0, NULL);
313 snprintf(name, sizeof(name), "%s-div", devname);
314 tmp = clk_register_fractional_divider(NULL, name, __clk_get_name(tmp),
315 0, lpss->priv, 1, 15, 16, 15, 0,
321 snprintf(name, sizeof(name), "%s-update", devname);
322 tmp = clk_register_gate(NULL, name, __clk_get_name(tmp),
323 CLK_SET_RATE_PARENT, lpss->priv, 31, 0, NULL);
331 static int intel_lpss_register_clock(struct intel_lpss *lpss)
333 const struct mfd_cell *cell = lpss->cell;
338 if (!lpss->info->clk_rate)
342 clk = clk_register_fixed_rate(NULL, dev_name(lpss->dev), NULL, 0,
343 lpss->info->clk_rate);
347 snprintf(devname, sizeof(devname), "%s.%d", cell->name, lpss->devid);
350 * Support for clock divider only if it has some preset value.
351 * Otherwise we assume that the divider is not used.
353 if (lpss->type != LPSS_DEV_I2C) {
354 ret = intel_lpss_register_clock_divider(lpss, devname, &clk);
356 goto err_clk_register;
361 /* Clock for the host controller */
362 lpss->clock = clkdev_create(clk, lpss->info->clk_con_id, "%s", devname);
364 goto err_clk_register;
371 intel_lpss_unregister_clock_tree(clk);
376 static void intel_lpss_unregister_clock(struct intel_lpss *lpss)
378 if (IS_ERR_OR_NULL(lpss->clk))
381 clkdev_drop(lpss->clock);
382 intel_lpss_unregister_clock_tree(lpss->clk);
385 int intel_lpss_probe(struct device *dev,
386 const struct intel_lpss_platform_info *info)
388 struct intel_lpss *lpss;
391 if (!info || !info->mem || info->irq <= 0)
394 lpss = devm_kzalloc(dev, sizeof(*lpss), GFP_KERNEL);
398 lpss->priv = devm_ioremap(dev, info->mem->start + LPSS_PRIV_OFFSET,
405 lpss->caps = readl(lpss->priv + LPSS_PRIV_CAPS);
407 dev_set_drvdata(dev, lpss);
409 ret = intel_lpss_assign_devs(lpss);
413 lpss->cell->properties = info->properties;
415 intel_lpss_init_dev(lpss);
417 lpss->devid = ida_simple_get(&intel_lpss_devid_ida, 0, 0, GFP_KERNEL);
421 ret = intel_lpss_register_clock(lpss);
423 goto err_clk_register;
425 intel_lpss_ltr_expose(lpss);
427 ret = intel_lpss_debugfs_add(lpss);
429 dev_warn(dev, "Failed to create debugfs entries\n");
431 if (intel_lpss_has_idma(lpss)) {
433 * Ensure the DMA driver is loaded before the host
434 * controller device appears, so that the host controller
435 * driver can request its DMA channels as early as
438 * If the DMA module is not there that's OK as well.
440 intel_lpss_request_dma_module(LPSS_IDMA64_DRIVER_NAME);
442 ret = mfd_add_devices(dev, lpss->devid, &intel_lpss_idma64_cell,
443 1, info->mem, info->irq, NULL);
445 dev_warn(dev, "Failed to add %s, fallback to PIO\n",
446 LPSS_IDMA64_DRIVER_NAME);
449 ret = mfd_add_devices(dev, lpss->devid, lpss->cell,
450 1, info->mem, info->irq, NULL);
454 dev_pm_set_driver_flags(dev, DPM_FLAG_SMART_SUSPEND);
459 intel_lpss_debugfs_remove(lpss);
460 intel_lpss_ltr_hide(lpss);
461 intel_lpss_unregister_clock(lpss);
464 ida_simple_remove(&intel_lpss_devid_ida, lpss->devid);
468 EXPORT_SYMBOL_GPL(intel_lpss_probe);
470 void intel_lpss_remove(struct device *dev)
472 struct intel_lpss *lpss = dev_get_drvdata(dev);
474 mfd_remove_devices(dev);
475 intel_lpss_debugfs_remove(lpss);
476 intel_lpss_ltr_hide(lpss);
477 intel_lpss_unregister_clock(lpss);
478 ida_simple_remove(&intel_lpss_devid_ida, lpss->devid);
480 EXPORT_SYMBOL_GPL(intel_lpss_remove);
482 static int resume_lpss_device(struct device *dev, void *data)
484 if (!dev_pm_test_driver_flags(dev, DPM_FLAG_SMART_SUSPEND))
485 pm_runtime_resume(dev);
490 int intel_lpss_prepare(struct device *dev)
493 * Resume both child devices before entering system sleep. This
494 * ensures that they are in proper state before they get suspended.
496 device_for_each_child_reverse(dev, NULL, resume_lpss_device);
499 EXPORT_SYMBOL_GPL(intel_lpss_prepare);
501 int intel_lpss_suspend(struct device *dev)
503 struct intel_lpss *lpss = dev_get_drvdata(dev);
506 /* Save device context */
507 for (i = 0; i < LPSS_PRIV_REG_COUNT; i++)
508 lpss->priv_ctx[i] = readl(lpss->priv + i * 4);
511 * If the device type is not UART, then put the controller into
512 * reset. UART cannot be put into reset since S3/S0ix fail when
513 * no_console_suspend flag is enabled.
515 if (lpss->type != LPSS_DEV_UART)
516 writel(0, lpss->priv + LPSS_PRIV_RESETS);
520 EXPORT_SYMBOL_GPL(intel_lpss_suspend);
522 int intel_lpss_resume(struct device *dev)
524 struct intel_lpss *lpss = dev_get_drvdata(dev);
527 intel_lpss_deassert_reset(lpss);
529 /* Restore device context */
530 for (i = 0; i < LPSS_PRIV_REG_COUNT; i++)
531 writel(lpss->priv_ctx[i], lpss->priv + i * 4);
535 EXPORT_SYMBOL_GPL(intel_lpss_resume);
537 static int __init intel_lpss_init(void)
539 intel_lpss_debugfs = debugfs_create_dir("intel_lpss", NULL);
542 module_init(intel_lpss_init);
544 static void __exit intel_lpss_exit(void)
546 debugfs_remove(intel_lpss_debugfs);
548 module_exit(intel_lpss_exit);
550 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
551 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
552 MODULE_AUTHOR("Heikki Krogerus <heikki.krogerus@linux.intel.com>");
553 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@linux.intel.com>");
554 MODULE_DESCRIPTION("Intel LPSS core driver");
555 MODULE_LICENSE("GPL v2");