drivers/mfd/db8500-prcmu.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * DB8500 PRCM Unit driver
   4  *
   5  * Copyright (C) STMicroelectronics 2009
   6  * Copyright (C) ST-Ericsson SA 2010
   7  *
   8  * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
   9  * Author: Sundar Iyer <sundar.iyer@stericsson.com>
  10  * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
  11  *
  12  * U8500 PRCM Unit interface driver
  13  */
  14 #include <linux/init.h>
  15 #include <linux/export.h>
  16 #include <linux/kernel.h>
  17 #include <linux/delay.h>
  18 #include <linux/errno.h>
  19 #include <linux/err.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/io.h>
  22 #include <linux/slab.h>
  23 #include <linux/mutex.h>
  24 #include <linux/completion.h>
  25 #include <linux/irq.h>
  26 #include <linux/jiffies.h>
  27 #include <linux/bitops.h>
  28 #include <linux/fs.h>
  29 #include <linux/of.h>
  30 #include <linux/of_irq.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/uaccess.h>
  33 #include <linux/mfd/core.h>
  34 #include <linux/mfd/dbx500-prcmu.h>
  35 #include <linux/mfd/abx500/ab8500.h>
  36 #include <linux/regulator/db8500-prcmu.h>
  37 #include <linux/regulator/machine.h>
  38 #include <linux/platform_data/ux500_wdt.h>
  39 #include <linux/platform_data/db8500_thermal.h>
  40 #include "dbx500-prcmu-regs.h"
  41
  42 /* Index of different voltages to be used when accessing AVSData */
  43 #define PRCM_AVS_BASE           0x2FC
  44 #define PRCM_AVS_VBB_RET        (PRCM_AVS_BASE + 0x0)
  45 #define PRCM_AVS_VBB_MAX_OPP    (PRCM_AVS_BASE + 0x1)
  46 #define PRCM_AVS_VBB_100_OPP    (PRCM_AVS_BASE + 0x2)
  47 #define PRCM_AVS_VBB_50_OPP     (PRCM_AVS_BASE + 0x3)
  48 #define PRCM_AVS_VARM_MAX_OPP   (PRCM_AVS_BASE + 0x4)
  49 #define PRCM_AVS_VARM_100_OPP   (PRCM_AVS_BASE + 0x5)
  50 #define PRCM_AVS_VARM_50_OPP    (PRCM_AVS_BASE + 0x6)
  51 #define PRCM_AVS_VARM_RET       (PRCM_AVS_BASE + 0x7)
  52 #define PRCM_AVS_VAPE_100_OPP   (PRCM_AVS_BASE + 0x8)
  53 #define PRCM_AVS_VAPE_50_OPP    (PRCM_AVS_BASE + 0x9)
  54 #define PRCM_AVS_VMOD_100_OPP   (PRCM_AVS_BASE + 0xA)
  55 #define PRCM_AVS_VMOD_50_OPP    (PRCM_AVS_BASE + 0xB)
  56 #define PRCM_AVS_VSAFE          (PRCM_AVS_BASE + 0xC)
  57
  58 #define PRCM_AVS_VOLTAGE                0
  59 #define PRCM_AVS_VOLTAGE_MASK           0x3f
  60 #define PRCM_AVS_ISSLOWSTARTUP          6
  61 #define PRCM_AVS_ISSLOWSTARTUP_MASK     (1 << PRCM_AVS_ISSLOWSTARTUP)
  62 #define PRCM_AVS_ISMODEENABLE           7
  63 #define PRCM_AVS_ISMODEENABLE_MASK      (1 << PRCM_AVS_ISMODEENABLE)
  64
  65 #define PRCM_BOOT_STATUS        0xFFF
  66 #define PRCM_ROMCODE_A2P        0xFFE
  67 #define PRCM_ROMCODE_P2A        0xFFD
  68 #define PRCM_XP70_CUR_PWR_STATE 0xFFC      /* 4 BYTES */
  69
  70 #define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */
  71
  72 #define _PRCM_MBOX_HEADER               0xFE8 /* 16 bytes */
  73 #define PRCM_MBOX_HEADER_REQ_MB0        (_PRCM_MBOX_HEADER + 0x0)
  74 #define PRCM_MBOX_HEADER_REQ_MB1        (_PRCM_MBOX_HEADER + 0x1)
  75 #define PRCM_MBOX_HEADER_REQ_MB2        (_PRCM_MBOX_HEADER + 0x2)
  76 #define PRCM_MBOX_HEADER_REQ_MB3        (_PRCM_MBOX_HEADER + 0x3)
  77 #define PRCM_MBOX_HEADER_REQ_MB4        (_PRCM_MBOX_HEADER + 0x4)
  78 #define PRCM_MBOX_HEADER_REQ_MB5        (_PRCM_MBOX_HEADER + 0x5)
  79 #define PRCM_MBOX_HEADER_ACK_MB0        (_PRCM_MBOX_HEADER + 0x8)
  80
  81 /* Req Mailboxes */
  82 #define PRCM_REQ_MB0 0xFDC /* 12 bytes  */
  83 #define PRCM_REQ_MB1 0xFD0 /* 12 bytes  */
  84 #define PRCM_REQ_MB2 0xFC0 /* 16 bytes  */
  85 #define PRCM_REQ_MB3 0xE4C /* 372 bytes  */
  86 #define PRCM_REQ_MB4 0xE48 /* 4 bytes  */
  87 #define PRCM_REQ_MB5 0xE44 /* 4 bytes  */
  88
  89 /* Ack Mailboxes */
  90 #define PRCM_ACK_MB0 0xE08 /* 52 bytes  */
  91 #define PRCM_ACK_MB1 0xE04 /* 4 bytes */
  92 #define PRCM_ACK_MB2 0xE00 /* 4 bytes */
  93 #define PRCM_ACK_MB3 0xDFC /* 4 bytes */
  94 #define PRCM_ACK_MB4 0xDF8 /* 4 bytes */
  95 #define PRCM_ACK_MB5 0xDF4 /* 4 bytes */
  96
  97 /* Mailbox 0 headers */
  98 #define MB0H_POWER_STATE_TRANS          0
  99 #define MB0H_CONFIG_WAKEUPS_EXE         1
 100 #define MB0H_READ_WAKEUP_ACK            3
 101 #define MB0H_CONFIG_WAKEUPS_SLEEP       4
 102
 103 #define MB0H_WAKEUP_EXE 2
 104 #define MB0H_WAKEUP_SLEEP 5
 105
 106 /* Mailbox 0 REQs */
 107 #define PRCM_REQ_MB0_AP_POWER_STATE     (PRCM_REQ_MB0 + 0x0)
 108 #define PRCM_REQ_MB0_AP_PLL_STATE       (PRCM_REQ_MB0 + 0x1)
 109 #define PRCM_REQ_MB0_ULP_CLOCK_STATE    (PRCM_REQ_MB0 + 0x2)
 110 #define PRCM_REQ_MB0_DO_NOT_WFI         (PRCM_REQ_MB0 + 0x3)
 111 #define PRCM_REQ_MB0_WAKEUP_8500        (PRCM_REQ_MB0 + 0x4)
 112 #define PRCM_REQ_MB0_WAKEUP_4500        (PRCM_REQ_MB0 + 0x8)
 113
 114 /* Mailbox 0 ACKs */
 115 #define PRCM_ACK_MB0_AP_PWRSTTR_STATUS  (PRCM_ACK_MB0 + 0x0)
 116 #define PRCM_ACK_MB0_READ_POINTER       (PRCM_ACK_MB0 + 0x1)
 117 #define PRCM_ACK_MB0_WAKEUP_0_8500      (PRCM_ACK_MB0 + 0x4)
 118 #define PRCM_ACK_MB0_WAKEUP_0_4500      (PRCM_ACK_MB0 + 0x8)
 119 #define PRCM_ACK_MB0_WAKEUP_1_8500      (PRCM_ACK_MB0 + 0x1C)
 120 #define PRCM_ACK_MB0_WAKEUP_1_4500      (PRCM_ACK_MB0 + 0x20)
 121 #define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20
 122
 123 /* Mailbox 1 headers */
 124 #define MB1H_ARM_APE_OPP 0x0
 125 #define MB1H_RESET_MODEM 0x2
 126 #define MB1H_REQUEST_APE_OPP_100_VOLT 0x3
 127 #define MB1H_RELEASE_APE_OPP_100_VOLT 0x4
 128 #define MB1H_RELEASE_USB_WAKEUP 0x5
 129 #define MB1H_PLL_ON_OFF 0x6
 130
 131 /* Mailbox 1 Requests */
 132 #define PRCM_REQ_MB1_ARM_OPP                    (PRCM_REQ_MB1 + 0x0)
 133 #define PRCM_REQ_MB1_APE_OPP                    (PRCM_REQ_MB1 + 0x1)
 134 #define PRCM_REQ_MB1_PLL_ON_OFF                 (PRCM_REQ_MB1 + 0x4)
 135 #define PLL_SOC0_OFF    0x1
 136 #define PLL_SOC0_ON     0x2
 137 #define PLL_SOC1_OFF    0x4
 138 #define PLL_SOC1_ON     0x8
 139
 140 /* Mailbox 1 ACKs */
 141 #define PRCM_ACK_MB1_CURRENT_ARM_OPP    (PRCM_ACK_MB1 + 0x0)
 142 #define PRCM_ACK_MB1_CURRENT_APE_OPP    (PRCM_ACK_MB1 + 0x1)
 143 #define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2)
 144 #define PRCM_ACK_MB1_DVFS_STATUS        (PRCM_ACK_MB1 + 0x3)
 145
 146 /* Mailbox 2 headers */
 147 #define MB2H_DPS        0x0
 148 #define MB2H_AUTO_PWR   0x1
 149
 150 /* Mailbox 2 REQs */
 151 #define PRCM_REQ_MB2_SVA_MMDSP          (PRCM_REQ_MB2 + 0x0)
 152 #define PRCM_REQ_MB2_SVA_PIPE           (PRCM_REQ_MB2 + 0x1)
 153 #define PRCM_REQ_MB2_SIA_MMDSP          (PRCM_REQ_MB2 + 0x2)
 154 #define PRCM_REQ_MB2_SIA_PIPE           (PRCM_REQ_MB2 + 0x3)
 155 #define PRCM_REQ_MB2_SGA                (PRCM_REQ_MB2 + 0x4)
 156 #define PRCM_REQ_MB2_B2R2_MCDE          (PRCM_REQ_MB2 + 0x5)
 157 #define PRCM_REQ_MB2_ESRAM12            (PRCM_REQ_MB2 + 0x6)
 158 #define PRCM_REQ_MB2_ESRAM34            (PRCM_REQ_MB2 + 0x7)
 159 #define PRCM_REQ_MB2_AUTO_PM_SLEEP      (PRCM_REQ_MB2 + 0x8)
 160 #define PRCM_REQ_MB2_AUTO_PM_IDLE       (PRCM_REQ_MB2 + 0xC)
 161
 162 /* Mailbox 2 ACKs */
 163 #define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0)
 164 #define HWACC_PWR_ST_OK 0xFE
 165
 166 /* Mailbox 3 headers */
 167 #define MB3H_ANC        0x0
 168 #define MB3H_SIDETONE   0x1
 169 #define MB3H_SYSCLK     0xE
 170
 171 /* Mailbox 3 Requests */
 172 #define PRCM_REQ_MB3_ANC_FIR_COEFF      (PRCM_REQ_MB3 + 0x0)
 173 #define PRCM_REQ_MB3_ANC_IIR_COEFF      (PRCM_REQ_MB3 + 0x20)
 174 #define PRCM_REQ_MB3_ANC_SHIFTER        (PRCM_REQ_MB3 + 0x60)
 175 #define PRCM_REQ_MB3_ANC_WARP           (PRCM_REQ_MB3 + 0x64)
 176 #define PRCM_REQ_MB3_SIDETONE_FIR_GAIN  (PRCM_REQ_MB3 + 0x68)
 177 #define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C)
 178 #define PRCM_REQ_MB3_SYSCLK_MGT         (PRCM_REQ_MB3 + 0x16C)
 179
 180 /* Mailbox 4 headers */
 181 #define MB4H_DDR_INIT   0x0
 182 #define MB4H_MEM_ST     0x1
 183 #define MB4H_HOTDOG     0x12
 184 #define MB4H_HOTMON     0x13
 185 #define MB4H_HOT_PERIOD 0x14
 186 #define MB4H_A9WDOG_CONF 0x16
 187 #define MB4H_A9WDOG_EN   0x17
 188 #define MB4H_A9WDOG_DIS  0x18
 189 #define MB4H_A9WDOG_LOAD 0x19
 190 #define MB4H_A9WDOG_KICK 0x20
 191
 192 /* Mailbox 4 Requests */
 193 #define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE       (PRCM_REQ_MB4 + 0x0)
 194 #define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE        (PRCM_REQ_MB4 + 0x1)
 195 #define PRCM_REQ_MB4_ESRAM0_ST                  (PRCM_REQ_MB4 + 0x3)
 196 #define PRCM_REQ_MB4_HOTDOG_THRESHOLD           (PRCM_REQ_MB4 + 0x0)
 197 #define PRCM_REQ_MB4_HOTMON_LOW                 (PRCM_REQ_MB4 + 0x0)
 198 #define PRCM_REQ_MB4_HOTMON_HIGH                (PRCM_REQ_MB4 + 0x1)
 199 #define PRCM_REQ_MB4_HOTMON_CONFIG              (PRCM_REQ_MB4 + 0x2)
 200 #define PRCM_REQ_MB4_HOT_PERIOD                 (PRCM_REQ_MB4 + 0x0)
 201 #define HOTMON_CONFIG_LOW                       BIT(0)
 202 #define HOTMON_CONFIG_HIGH                      BIT(1)
 203 #define PRCM_REQ_MB4_A9WDOG_0                   (PRCM_REQ_MB4 + 0x0)
 204 #define PRCM_REQ_MB4_A9WDOG_1                   (PRCM_REQ_MB4 + 0x1)
 205 #define PRCM_REQ_MB4_A9WDOG_2                   (PRCM_REQ_MB4 + 0x2)
 206 #define PRCM_REQ_MB4_A9WDOG_3                   (PRCM_REQ_MB4 + 0x3)
 207 #define A9WDOG_AUTO_OFF_EN                      BIT(7)
 208 #define A9WDOG_AUTO_OFF_DIS                     0
 209 #define A9WDOG_ID_MASK                          0xf
 210
 211 /* Mailbox 5 Requests */
 212 #define PRCM_REQ_MB5_I2C_SLAVE_OP       (PRCM_REQ_MB5 + 0x0)
 213 #define PRCM_REQ_MB5_I2C_HW_BITS        (PRCM_REQ_MB5 + 0x1)
 214 #define PRCM_REQ_MB5_I2C_REG            (PRCM_REQ_MB5 + 0x2)
 215 #define PRCM_REQ_MB5_I2C_VAL            (PRCM_REQ_MB5 + 0x3)
 216 #define PRCMU_I2C_WRITE(slave) (((slave) << 1) | BIT(6))
 217 #define PRCMU_I2C_READ(slave) (((slave) << 1) | BIT(0) | BIT(6))
 218 #define PRCMU_I2C_STOP_EN               BIT(3)
 219
 220 /* Mailbox 5 ACKs */
 221 #define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1)
 222 #define PRCM_ACK_MB5_I2C_VAL    (PRCM_ACK_MB5 + 0x3)
 223 #define I2C_WR_OK 0x1
 224 #define I2C_RD_OK 0x2
 225
 226 #define NUM_MB 8
 227 #define MBOX_BIT BIT
 228 #define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1)
 229
 230 /*
 231  * Wakeups/IRQs
 232  */
 233
 234 #define WAKEUP_BIT_RTC BIT(0)
 235 #define WAKEUP_BIT_RTT0 BIT(1)
 236 #define WAKEUP_BIT_RTT1 BIT(2)
 237 #define WAKEUP_BIT_HSI0 BIT(3)
 238 #define WAKEUP_BIT_HSI1 BIT(4)
 239 #define WAKEUP_BIT_CA_WAKE BIT(5)
 240 #define WAKEUP_BIT_USB BIT(6)
 241 #define WAKEUP_BIT_ABB BIT(7)
 242 #define WAKEUP_BIT_ABB_FIFO BIT(8)
 243 #define WAKEUP_BIT_SYSCLK_OK BIT(9)
 244 #define WAKEUP_BIT_CA_SLEEP BIT(10)
 245 #define WAKEUP_BIT_AC_WAKE_ACK BIT(11)
 246 #define WAKEUP_BIT_SIDE_TONE_OK BIT(12)
 247 #define WAKEUP_BIT_ANC_OK BIT(13)
 248 #define WAKEUP_BIT_SW_ERROR BIT(14)
 249 #define WAKEUP_BIT_AC_SLEEP_ACK BIT(15)
 250 #define WAKEUP_BIT_ARM BIT(17)
 251 #define WAKEUP_BIT_HOTMON_LOW BIT(18)
 252 #define WAKEUP_BIT_HOTMON_HIGH BIT(19)
 253 #define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20)
 254 #define WAKEUP_BIT_GPIO0 BIT(23)
 255 #define WAKEUP_BIT_GPIO1 BIT(24)
 256 #define WAKEUP_BIT_GPIO2 BIT(25)
 257 #define WAKEUP_BIT_GPIO3 BIT(26)
 258 #define WAKEUP_BIT_GPIO4 BIT(27)
 259 #define WAKEUP_BIT_GPIO5 BIT(28)
 260 #define WAKEUP_BIT_GPIO6 BIT(29)
 261 #define WAKEUP_BIT_GPIO7 BIT(30)
 262 #define WAKEUP_BIT_GPIO8 BIT(31)
 263
 264 static struct {
 265         bool valid;
 266         struct prcmu_fw_version version;
 267 } fw_info;
 268
 269 static struct irq_domain *db8500_irq_domain;
 270
 271 /*
 272  * This vector maps irq numbers to the bits in the bit field used in
 273  * communication with the PRCMU firmware.
 274  *
 275  * The reason for having this is to keep the irq numbers contiguous even though
 276  * the bits in the bit field are not. (The bits also have a tendency to move
 277  * around, to further complicate matters.)
 278  */
 279 #define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name))
 280 #define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name)
 281
 282 #define IRQ_PRCMU_RTC 0
 283 #define IRQ_PRCMU_RTT0 1
 284 #define IRQ_PRCMU_RTT1 2
 285 #define IRQ_PRCMU_HSI0 3
 286 #define IRQ_PRCMU_HSI1 4
 287 #define IRQ_PRCMU_CA_WAKE 5
 288 #define IRQ_PRCMU_USB 6
 289 #define IRQ_PRCMU_ABB 7
 290 #define IRQ_PRCMU_ABB_FIFO 8
 291 #define IRQ_PRCMU_ARM 9
 292 #define IRQ_PRCMU_MODEM_SW_RESET_REQ 10
 293 #define IRQ_PRCMU_GPIO0 11
 294 #define IRQ_PRCMU_GPIO1 12
 295 #define IRQ_PRCMU_GPIO2 13
 296 #define IRQ_PRCMU_GPIO3 14
 297 #define IRQ_PRCMU_GPIO4 15
 298 #define IRQ_PRCMU_GPIO5 16
 299 #define IRQ_PRCMU_GPIO6 17
 300 #define IRQ_PRCMU_GPIO7 18
 301 #define IRQ_PRCMU_GPIO8 19
 302 #define IRQ_PRCMU_CA_SLEEP 20
 303 #define IRQ_PRCMU_HOTMON_LOW 21
 304 #define IRQ_PRCMU_HOTMON_HIGH 22
 305 #define NUM_PRCMU_WAKEUPS 23
 306
 307 static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = {
 308         IRQ_ENTRY(RTC),
 309         IRQ_ENTRY(RTT0),
 310         IRQ_ENTRY(RTT1),
 311         IRQ_ENTRY(HSI0),
 312         IRQ_ENTRY(HSI1),
 313         IRQ_ENTRY(CA_WAKE),
 314         IRQ_ENTRY(USB),
 315         IRQ_ENTRY(ABB),
 316         IRQ_ENTRY(ABB_FIFO),
 317         IRQ_ENTRY(CA_SLEEP),
 318         IRQ_ENTRY(ARM),
 319         IRQ_ENTRY(HOTMON_LOW),
 320         IRQ_ENTRY(HOTMON_HIGH),
 321         IRQ_ENTRY(MODEM_SW_RESET_REQ),
 322         IRQ_ENTRY(GPIO0),
 323         IRQ_ENTRY(GPIO1),
 324         IRQ_ENTRY(GPIO2),
 325         IRQ_ENTRY(GPIO3),
 326         IRQ_ENTRY(GPIO4),
 327         IRQ_ENTRY(GPIO5),
 328         IRQ_ENTRY(GPIO6),
 329         IRQ_ENTRY(GPIO7),
 330         IRQ_ENTRY(GPIO8)
 331 };
 332
 333 #define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1)
 334 #define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name)
 335 static u32 prcmu_wakeup_bit[NUM_PRCMU_WAKEUP_INDICES] = {
 336         WAKEUP_ENTRY(RTC),
 337         WAKEUP_ENTRY(RTT0),
 338         WAKEUP_ENTRY(RTT1),
 339         WAKEUP_ENTRY(HSI0),
 340         WAKEUP_ENTRY(HSI1),
 341         WAKEUP_ENTRY(USB),
 342         WAKEUP_ENTRY(ABB),
 343         WAKEUP_ENTRY(ABB_FIFO),
 344         WAKEUP_ENTRY(ARM)
 345 };
 346
 347 /*
 348  * mb0_transfer - state needed for mailbox 0 communication.
 349  * @lock:               The transaction lock.
 350  * @dbb_events_lock:    A lock used to handle concurrent access to (parts of)
 351  *                      the request data.
 352  * @mask_work:          Work structure used for (un)masking wakeup interrupts.
 353  * @req:                Request data that need to persist between requests.
 354  */
 355 static struct {
 356         spinlock_t lock;
 357         spinlock_t dbb_irqs_lock;
 358         struct work_struct mask_work;
 359         struct mutex ac_wake_lock;
 360         struct completion ac_wake_work;
 361         struct {
 362                 u32 dbb_irqs;
 363                 u32 dbb_wakeups;
 364                 u32 abb_events;
 365         } req;
 366 } mb0_transfer;
 367
 368 /*
 369  * mb1_transfer - state needed for mailbox 1 communication.
 370  * @lock:       The transaction lock.
 371  * @work:       The transaction completion structure.
 372  * @ape_opp:    The current APE OPP.
 373  * @ack:        Reply ("acknowledge") data.
 374  */
 375 static struct {
 376         struct mutex lock;
 377         struct completion work;
 378         u8 ape_opp;
 379         struct {
 380                 u8 header;
 381                 u8 arm_opp;
 382                 u8 ape_opp;
 383                 u8 ape_voltage_status;
 384         } ack;
 385 } mb1_transfer;
 386
 387 /*
 388  * mb2_transfer - state needed for mailbox 2 communication.
 389  * @lock:            The transaction lock.
 390  * @work:            The transaction completion structure.
 391  * @auto_pm_lock:    The autonomous power management configuration lock.
 392  * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled.
 393  * @req:             Request data that need to persist between requests.
 394  * @ack:             Reply ("acknowledge") data.
 395  */
 396 static struct {
 397         struct mutex lock;
 398         struct completion work;
 399         spinlock_t auto_pm_lock;
 400         bool auto_pm_enabled;
 401         struct {
 402                 u8 status;
 403         } ack;
 404 } mb2_transfer;
 405
 406 /*
 407  * mb3_transfer - state needed for mailbox 3 communication.
 408  * @lock:               The request lock.
 409  * @sysclk_lock:        A lock used to handle concurrent sysclk requests.
 410  * @sysclk_work:        Work structure used for sysclk requests.
 411  */
 412 static struct {
 413         spinlock_t lock;
 414         struct mutex sysclk_lock;
 415         struct completion sysclk_work;
 416 } mb3_transfer;
 417
 418 /*
 419  * mb4_transfer - state needed for mailbox 4 communication.
 420  * @lock:       The transaction lock.
 421  * @work:       The transaction completion structure.
 422  */
 423 static struct {
 424         struct mutex lock;
 425         struct completion work;
 426 } mb4_transfer;
 427
 428 /*
 429  * mb5_transfer - state needed for mailbox 5 communication.
 430  * @lock:       The transaction lock.
 431  * @work:       The transaction completion structure.
 432  * @ack:        Reply ("acknowledge") data.
 433  */
 434 static struct {
 435         struct mutex lock;
 436         struct completion work;
 437         struct {
 438                 u8 status;
 439                 u8 value;
 440         } ack;
 441 } mb5_transfer;
 442
 443 static atomic_t ac_wake_req_state = ATOMIC_INIT(0);
 444
 445 /* Spinlocks */
 446 static DEFINE_SPINLOCK(prcmu_lock);
 447 static DEFINE_SPINLOCK(clkout_lock);
 448
 449 /* Global var to runtime determine TCDM base for v2 or v1 */
 450 static __iomem void *tcdm_base;
 451 static __iomem void *prcmu_base;
 452
 453 struct clk_mgt {
 454         u32 offset;
 455         u32 pllsw;
 456         int branch;
 457         bool clk38div;
 458 };
 459
 460 enum {
 461         PLL_RAW,
 462         PLL_FIX,
 463         PLL_DIV
 464 };
 465
 466 static DEFINE_SPINLOCK(clk_mgt_lock);
 467
 468 #define CLK_MGT_ENTRY(_name, _branch, _clk38div)[PRCMU_##_name] = \
 469         { (PRCM_##_name##_MGT), 0 , _branch, _clk38div}
 470 static struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = {
 471         CLK_MGT_ENTRY(SGACLK, PLL_DIV, false),
 472         CLK_MGT_ENTRY(UARTCLK, PLL_FIX, true),
 473         CLK_MGT_ENTRY(MSP02CLK, PLL_FIX, true),
 474         CLK_MGT_ENTRY(MSP1CLK, PLL_FIX, true),
 475         CLK_MGT_ENTRY(I2CCLK, PLL_FIX, true),
 476         CLK_MGT_ENTRY(SDMMCCLK, PLL_DIV, true),
 477         CLK_MGT_ENTRY(SLIMCLK, PLL_FIX, true),
 478         CLK_MGT_ENTRY(PER1CLK, PLL_DIV, true),
 479         CLK_MGT_ENTRY(PER2CLK, PLL_DIV, true),
 480         CLK_MGT_ENTRY(PER3CLK, PLL_DIV, true),
 481         CLK_MGT_ENTRY(PER5CLK, PLL_DIV, true),
 482         CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true),
 483         CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true),
 484         CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true),
 485         CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true),
 486         CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true),
 487         CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true),
 488         CLK_MGT_ENTRY(HDMICLK, PLL_FIX, false),
 489         CLK_MGT_ENTRY(APEATCLK, PLL_DIV, true),
 490         CLK_MGT_ENTRY(APETRACECLK, PLL_DIV, true),
 491         CLK_MGT_ENTRY(MCDECLK, PLL_DIV, true),
 492         CLK_MGT_ENTRY(IPI2CCLK, PLL_FIX, true),
 493         CLK_MGT_ENTRY(DSIALTCLK, PLL_FIX, false),
 494         CLK_MGT_ENTRY(DMACLK, PLL_DIV, true),
 495         CLK_MGT_ENTRY(B2R2CLK, PLL_DIV, true),
 496         CLK_MGT_ENTRY(TVCLK, PLL_FIX, true),
 497         CLK_MGT_ENTRY(SSPCLK, PLL_FIX, true),
 498         CLK_MGT_ENTRY(RNGCLK, PLL_FIX, true),
 499         CLK_MGT_ENTRY(UICCCLK, PLL_FIX, false),
 500 };
 501
 502 struct dsiclk {
 503         u32 divsel_mask;
 504         u32 divsel_shift;
 505         u32 divsel;
 506 };
 507
 508 static struct dsiclk dsiclk[2] = {
 509         {
 510                 .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK,
 511                 .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT,
 512                 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
 513         },
 514         {
 515                 .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK,
 516                 .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT,
 517                 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
 518         }
 519 };
 520
 521 struct dsiescclk {
 522         u32 en;
 523         u32 div_mask;
 524         u32 div_shift;
 525 };
 526
 527 static struct dsiescclk dsiescclk[3] = {
 528         {
 529                 .en = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN,
 530                 .div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK,
 531                 .div_shift = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT,
 532         },
 533         {
 534                 .en = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN,
 535                 .div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK,
 536                 .div_shift = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT,
 537         },
 538         {
 539                 .en = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN,
 540                 .div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK,
 541                 .div_shift = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT,
 542         }
 543 };
 544
 545
 546 /*
 547 * Used by MCDE to setup all necessary PRCMU registers
 548 */
 549 #define PRCMU_RESET_DSIPLL              0x00004000
 550 #define PRCMU_UNCLAMP_DSIPLL            0x00400800
 551
 552 #define PRCMU_CLK_PLL_DIV_SHIFT         0
 553 #define PRCMU_CLK_PLL_SW_SHIFT          5
 554 #define PRCMU_CLK_38                    (1 << 9)
 555 #define PRCMU_CLK_38_SRC                (1 << 10)
 556 #define PRCMU_CLK_38_DIV                (1 << 11)
 557
 558 /* PLLDIV=12, PLLSW=4 (PLLDDR) */
 559 #define PRCMU_DSI_CLOCK_SETTING         0x0000008C
 560
 561 /* DPI 50000000 Hz */
 562 #define PRCMU_DPI_CLOCK_SETTING         ((1 << PRCMU_CLK_PLL_SW_SHIFT) | \
 563                                           (16 << PRCMU_CLK_PLL_DIV_SHIFT))
 564 #define PRCMU_DSI_LP_CLOCK_SETTING      0x00000E00
 565
 566 /* D=101, N=1, R=4, SELDIV2=0 */
 567 #define PRCMU_PLLDSI_FREQ_SETTING       0x00040165
 568
 569 #define PRCMU_ENABLE_PLLDSI             0x00000001
 570 #define PRCMU_DISABLE_PLLDSI            0x00000000
 571 #define PRCMU_RELEASE_RESET_DSS         0x0000400C
 572 #define PRCMU_DSI_PLLOUT_SEL_SETTING    0x00000202
 573 /* ESC clk, div0=1, div1=1, div2=3 */
 574 #define PRCMU_ENABLE_ESCAPE_CLOCK_DIV   0x07030101
 575 #define PRCMU_DISABLE_ESCAPE_CLOCK_DIV  0x00030101
 576 #define PRCMU_DSI_RESET_SW              0x00000007
 577
 578 #define PRCMU_PLLDSI_LOCKP_LOCKED       0x3
 579
 580 int db8500_prcmu_enable_dsipll(void)
 581 {
 582         int i;
 583
 584         /* Clear DSIPLL_RESETN */
 585         writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR);
 586         /* Unclamp DSIPLL in/out */
 587         writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR);
 588
 589         /* Set DSI PLL FREQ */
 590         writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ);
 591         writel(PRCMU_DSI_PLLOUT_SEL_SETTING, PRCM_DSI_PLLOUT_SEL);
 592         /* Enable Escape clocks */
 593         writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
 594
 595         /* Start DSI PLL */
 596         writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
 597         /* Reset DSI PLL */
 598         writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET);
 599         for (i = 0; i < 10; i++) {
 600                 if ((readl(PRCM_PLLDSI_LOCKP) & PRCMU_PLLDSI_LOCKP_LOCKED)
 601                                         == PRCMU_PLLDSI_LOCKP_LOCKED)
 602                         break;
 603                 udelay(100);
 604         }
 605         /* Set DSIPLL_RESETN */
 606         writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET);
 607         return 0;
 608 }
 609
 610 int db8500_prcmu_disable_dsipll(void)
 611 {
 612         /* Disable dsi pll */
 613         writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
 614         /* Disable  escapeclock */
 615         writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
 616         return 0;
 617 }
 618
 619 int db8500_prcmu_set_display_clocks(void)
 620 {
 621         unsigned long flags;
 622
 623         spin_lock_irqsave(&clk_mgt_lock, flags);
 624
 625         /* Grab the HW semaphore. */
 626         while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
 627                 cpu_relax();
 628
 629         writel(PRCMU_DSI_CLOCK_SETTING, prcmu_base + PRCM_HDMICLK_MGT);
 630         writel(PRCMU_DSI_LP_CLOCK_SETTING, prcmu_base + PRCM_TVCLK_MGT);
 631         writel(PRCMU_DPI_CLOCK_SETTING, prcmu_base + PRCM_LCDCLK_MGT);
 632
 633         /* Release the HW semaphore. */
 634         writel(0, PRCM_SEM);
 635
 636         spin_unlock_irqrestore(&clk_mgt_lock, flags);
 637
 638         return 0;
 639 }
 640
 641 u32 db8500_prcmu_read(unsigned int reg)
 642 {
 643         return readl(prcmu_base + reg);
 644 }
 645
 646 void db8500_prcmu_write(unsigned int reg, u32 value)
 647 {
 648         unsigned long flags;
 649
 650         spin_lock_irqsave(&prcmu_lock, flags);
 651         writel(value, (prcmu_base + reg));
 652         spin_unlock_irqrestore(&prcmu_lock, flags);
 653 }
 654
 655 void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
 656 {
 657         u32 val;
 658         unsigned long flags;
 659
 660         spin_lock_irqsave(&prcmu_lock, flags);
 661         val = readl(prcmu_base + reg);
 662         val = ((val & ~mask) | (value & mask));
 663         writel(val, (prcmu_base + reg));
 664         spin_unlock_irqrestore(&prcmu_lock, flags);
 665 }
 666
 667 struct prcmu_fw_version *prcmu_get_fw_version(void)
 668 {
 669         return fw_info.valid ? &fw_info.version : NULL;
 670 }
 671
 672 bool prcmu_has_arm_maxopp(void)
 673 {
 674         return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) &
 675                 PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK;
 676 }
 677
 678 /**
 679  * prcmu_set_rc_a2p - This function is used to run few power state sequences
 680  * @val: Value to be set, i.e. transition requested
 681  * Returns: 0 on success, -EINVAL on invalid argument
 682  *
 683  * This function is used to run the following power state sequences -
 684  * any state to ApReset,  ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
 685  */
 686 int prcmu_set_rc_a2p(enum romcode_write val)
 687 {
 688         if (val < RDY_2_DS || val > RDY_2_XP70_RST)
 689                 return -EINVAL;
 690         writeb(val, (tcdm_base + PRCM_ROMCODE_A2P));
 691         return 0;
 692 }
 693
 694 /**
 695  * prcmu_get_rc_p2a - This function is used to get power state sequences
 696  * Returns: the power transition that has last happened
 697  *
 698  * This function can return the following transitions-
 699  * any state to ApReset,  ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
 700  */
 701 enum romcode_read prcmu_get_rc_p2a(void)
 702 {
 703         return readb(tcdm_base + PRCM_ROMCODE_P2A);
 704 }
 705
 706 /**
 707  * prcmu_get_current_mode - Return the current XP70 power mode
 708  * Returns: Returns the current AP(ARM) power mode: init,
 709  * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset
 710  */
 711 enum ap_pwrst prcmu_get_xp70_current_state(void)
 712 {
 713         return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE);
 714 }
 715
 716 /**
 717  * prcmu_config_clkout - Configure one of the programmable clock outputs.
 718  * @clkout:     The CLKOUT number (0 or 1).
 719  * @source:     The clock to be used (one of the PRCMU_CLKSRC_*).
 720  * @div:        The divider to be applied.
 721  *
 722  * Configures one of the programmable clock outputs (CLKOUTs).
 723  * @div should be in the range [1,63] to request a configuration, or 0 to
 724  * inform that the configuration is no longer requested.
 725  */
 726 int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
 727 {
 728         static int requests[2];
 729         int r = 0;
 730         unsigned long flags;
 731         u32 val;
 732         u32 bits;
 733         u32 mask;
 734         u32 div_mask;
 735
 736         BUG_ON(clkout > 1);
 737         BUG_ON(div > 63);
 738         BUG_ON((clkout == 0) && (source > PRCMU_CLKSRC_CLK009));
 739
 740         if (!div && !requests[clkout])
 741                 return -EINVAL;
 742
 743         if (clkout == 0) {
 744                 div_mask = PRCM_CLKOCR_CLKODIV0_MASK;
 745                 mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK);
 746                 bits = ((source << PRCM_CLKOCR_CLKOSEL0_SHIFT) |
 747                         (div << PRCM_CLKOCR_CLKODIV0_SHIFT));
 748         } else {
 749                 div_mask = PRCM_CLKOCR_CLKODIV1_MASK;
 750                 mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK |
 751                         PRCM_CLKOCR_CLK1TYPE);
 752                 bits = ((source << PRCM_CLKOCR_CLKOSEL1_SHIFT) |
 753                         (div << PRCM_CLKOCR_CLKODIV1_SHIFT));
 754         }
 755         bits &= mask;
 756
 757         spin_lock_irqsave(&clkout_lock, flags);
 758
 759         val = readl(PRCM_CLKOCR);
 760         if (val & div_mask) {
 761                 if (div) {
 762                         if ((val & mask) != bits) {
 763                                 r = -EBUSY;
 764                                 goto unlock_and_return;
 765                         }
 766                 } else {
 767                         if ((val & mask & ~div_mask) != bits) {
 768                                 r = -EINVAL;
 769                                 goto unlock_and_return;
 770                         }
 771                 }
 772         }
 773         writel((bits | (val & ~mask)), PRCM_CLKOCR);
 774         requests[clkout] += (div ? 1 : -1);
 775
 776 unlock_and_return:
 777         spin_unlock_irqrestore(&clkout_lock, flags);
 778
 779         return r;
 780 }
 781
 782 int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll)
 783 {
 784         unsigned long flags;
 785
 786         BUG_ON((state < PRCMU_AP_SLEEP) || (PRCMU_AP_DEEP_IDLE < state));
 787
 788         spin_lock_irqsave(&mb0_transfer.lock, flags);
 789
 790         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
 791                 cpu_relax();
 792
 793         writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
 794         writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE));
 795         writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE));
 796         writeb((keep_ulp_clk ? 1 : 0),
 797                 (tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE));
 798         writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI));
 799         writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
 800
 801         spin_unlock_irqrestore(&mb0_transfer.lock, flags);
 802
 803         return 0;
 804 }
 805
 806 u8 db8500_prcmu_get_power_state_result(void)
 807 {
 808         return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS);
 809 }
 810
 811 /* This function should only be called while mb0_transfer.lock is held. */
 812 static void config_wakeups(void)
 813 {
 814         const u8 header[2] = {
 815                 MB0H_CONFIG_WAKEUPS_EXE,
 816                 MB0H_CONFIG_WAKEUPS_SLEEP
 817         };
 818         static u32 last_dbb_events;
 819         static u32 last_abb_events;
 820         u32 dbb_events;
 821         u32 abb_events;
 822         unsigned int i;
 823
 824         dbb_events = mb0_transfer.req.dbb_irqs | mb0_transfer.req.dbb_wakeups;
 825         dbb_events |= (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK);
 826
 827         abb_events = mb0_transfer.req.abb_events;
 828
 829         if ((dbb_events == last_dbb_events) && (abb_events == last_abb_events))
 830                 return;
 831
 832         for (i = 0; i < 2; i++) {
 833                 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
 834                         cpu_relax();
 835                 writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500));
 836                 writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500));
 837                 writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
 838                 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
 839         }
 840         last_dbb_events = dbb_events;
 841         last_abb_events = abb_events;
 842 }
 843
 844 void db8500_prcmu_enable_wakeups(u32 wakeups)
 845 {
 846         unsigned long flags;
 847         u32 bits;
 848         int i;
 849
 850         BUG_ON(wakeups != (wakeups & VALID_WAKEUPS));
 851
 852         for (i = 0, bits = 0; i < NUM_PRCMU_WAKEUP_INDICES; i++) {
 853                 if (wakeups & BIT(i))
 854                         bits |= prcmu_wakeup_bit[i];
 855         }
 856
 857         spin_lock_irqsave(&mb0_transfer.lock, flags);
 858
 859         mb0_transfer.req.dbb_wakeups = bits;
 860         config_wakeups();
 861
 862         spin_unlock_irqrestore(&mb0_transfer.lock, flags);
 863 }
 864
 865 void db8500_prcmu_config_abb_event_readout(u32 abb_events)
 866 {
 867         unsigned long flags;
 868
 869         spin_lock_irqsave(&mb0_transfer.lock, flags);
 870
 871         mb0_transfer.req.abb_events = abb_events;
 872         config_wakeups();
 873
 874         spin_unlock_irqrestore(&mb0_transfer.lock, flags);
 875 }
 876
 877 void db8500_prcmu_get_abb_event_buffer(void __iomem **buf)
 878 {
 879         if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
 880                 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500);
 881         else
 882                 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500);
 883 }
 884
 885 /**
 886  * db8500_prcmu_set_arm_opp - set the appropriate ARM OPP
 887  * @opp: The new ARM operating point to which transition is to be made
 888  * Returns: 0 on success, non-zero on failure
 889  *
 890  * This function sets the the operating point of the ARM.
 891  */
 892 int db8500_prcmu_set_arm_opp(u8 opp)
 893 {
 894         int r;
 895
 896         if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK)
 897                 return -EINVAL;
 898
 899         r = 0;
 900
 901         mutex_lock(&mb1_transfer.lock);
 902
 903         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
 904                 cpu_relax();
 905
 906         writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
 907         writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
 908         writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP));
 909
 910         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
 911         wait_for_completion(&mb1_transfer.work);
 912
 913         if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
 914                 (mb1_transfer.ack.arm_opp != opp))
 915                 r = -EIO;
 916
 917         mutex_unlock(&mb1_transfer.lock);
 918
 919         return r;
 920 }
 921
 922 /**
 923  * db8500_prcmu_get_arm_opp - get the current ARM OPP
 924  *
 925  * Returns: the current ARM OPP
 926  */
 927 int db8500_prcmu_get_arm_opp(void)
 928 {
 929         return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP);
 930 }
 931
 932 /**
 933  * db8500_prcmu_get_ddr_opp - get the current DDR OPP
 934  *
 935  * Returns: the current DDR OPP
 936  */
 937 int db8500_prcmu_get_ddr_opp(void)
 938 {
 939         return readb(PRCM_DDR_SUBSYS_APE_MINBW);
 940 }
 941
 942 /* Divide the frequency of certain clocks by 2 for APE_50_PARTLY_25_OPP. */
 943 static void request_even_slower_clocks(bool enable)
 944 {
 945         u32 clock_reg[] = {
 946                 PRCM_ACLK_MGT,
 947                 PRCM_DMACLK_MGT
 948         };
 949         unsigned long flags;
 950         unsigned int i;
 951
 952         spin_lock_irqsave(&clk_mgt_lock, flags);
 953
 954         /* Grab the HW semaphore. */
 955         while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
 956                 cpu_relax();
 957
 958         for (i = 0; i < ARRAY_SIZE(clock_reg); i++) {
 959                 u32 val;
 960                 u32 div;
 961
 962                 val = readl(prcmu_base + clock_reg[i]);
 963                 div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK);
 964                 if (enable) {
 965                         if ((div <= 1) || (div > 15)) {
 966                                 pr_err("prcmu: Bad clock divider %d in %s\n",
 967                                         div, __func__);
 968                                 goto unlock_and_return;
 969                         }
 970                         div <<= 1;
 971                 } else {
 972                         if (div <= 2)
 973                                 goto unlock_and_return;
 974                         div >>= 1;
 975                 }
 976                 val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) |
 977                         (div & PRCM_CLK_MGT_CLKPLLDIV_MASK));
 978                 writel(val, prcmu_base + clock_reg[i]);
 979         }
 980
 981 unlock_and_return:
 982         /* Release the HW semaphore. */
 983         writel(0, PRCM_SEM);
 984
 985         spin_unlock_irqrestore(&clk_mgt_lock, flags);
 986 }
 987
 988 /**
 989  * db8500_set_ape_opp - set the appropriate APE OPP
 990  * @opp: The new APE operating point to which transition is to be made
 991  * Returns: 0 on success, non-zero on failure
 992  *
 993  * This function sets the operating point of the APE.
 994  */
 995 int db8500_prcmu_set_ape_opp(u8 opp)
 996 {
 997         int r = 0;
 998
 999         if (opp == mb1_transfer.ape_opp)
1000                 return 0;
1001
1002         mutex_lock(&mb1_transfer.lock);
1003
1004         if (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)
1005                 request_even_slower_clocks(false);
1006
1007         if ((opp != APE_100_OPP) && (mb1_transfer.ape_opp != APE_100_OPP))
1008                 goto skip_message;
1009
1010         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1011                 cpu_relax();
1012
1013         writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1014         writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
1015         writeb(((opp == APE_50_PARTLY_25_OPP) ? APE_50_OPP : opp),
1016                 (tcdm_base + PRCM_REQ_MB1_APE_OPP));
1017
1018         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1019         wait_for_completion(&mb1_transfer.work);
1020
1021         if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
1022                 (mb1_transfer.ack.ape_opp != opp))
1023                 r = -EIO;
1024
1025 skip_message:
1026         if ((!r && (opp == APE_50_PARTLY_25_OPP)) ||
1027                 (r && (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)))
1028                 request_even_slower_clocks(true);
1029         if (!r)
1030                 mb1_transfer.ape_opp = opp;
1031
1032         mutex_unlock(&mb1_transfer.lock);
1033
1034         return r;
1035 }
1036
1037 /**
1038  * db8500_prcmu_get_ape_opp - get the current APE OPP
1039  *
1040  * Returns: the current APE OPP
1041  */
1042 int db8500_prcmu_get_ape_opp(void)
1043 {
1044         return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP);
1045 }
1046
1047 /**
1048  * db8500_prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage
1049  * @enable: true to request the higher voltage, false to drop a request.
1050  *
1051  * Calls to this function to enable and disable requests must be balanced.
1052  */
1053 int db8500_prcmu_request_ape_opp_100_voltage(bool enable)
1054 {
1055         int r = 0;
1056         u8 header;
1057         static unsigned int requests;
1058
1059         mutex_lock(&mb1_transfer.lock);
1060
1061         if (enable) {
1062                 if (0 != requests++)
1063                         goto unlock_and_return;
1064                 header = MB1H_REQUEST_APE_OPP_100_VOLT;
1065         } else {
1066                 if (requests == 0) {
1067                         r = -EIO;
1068                         goto unlock_and_return;
1069                 } else if (1 != requests--) {
1070                         goto unlock_and_return;
1071                 }
1072                 header = MB1H_RELEASE_APE_OPP_100_VOLT;
1073         }
1074
1075         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1076                 cpu_relax();
1077
1078         writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1079
1080         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1081         wait_for_completion(&mb1_transfer.work);
1082
1083         if ((mb1_transfer.ack.header != header) ||
1084                 ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
1085                 r = -EIO;
1086
1087 unlock_and_return:
1088         mutex_unlock(&mb1_transfer.lock);
1089
1090         return r;
1091 }
1092
1093 /**
1094  * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup
1095  *
1096  * This function releases the power state requirements of a USB wakeup.
1097  */
1098 int prcmu_release_usb_wakeup_state(void)
1099 {
1100         int r = 0;
1101
1102         mutex_lock(&mb1_transfer.lock);
1103
1104         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1105                 cpu_relax();
1106
1107         writeb(MB1H_RELEASE_USB_WAKEUP,
1108                 (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1109
1110         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1111         wait_for_completion(&mb1_transfer.work);
1112
1113         if ((mb1_transfer.ack.header != MB1H_RELEASE_USB_WAKEUP) ||
1114                 ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
1115                 r = -EIO;
1116
1117         mutex_unlock(&mb1_transfer.lock);
1118
1119         return r;
1120 }
1121
1122 static int request_pll(u8 clock, bool enable)
1123 {
1124         int r = 0;
1125
1126         if (clock == PRCMU_PLLSOC0)
1127                 clock = (enable ? PLL_SOC0_ON : PLL_SOC0_OFF);
1128         else if (clock == PRCMU_PLLSOC1)
1129                 clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF);
1130         else
1131                 return -EINVAL;
1132
1133         mutex_lock(&mb1_transfer.lock);
1134
1135         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1136                 cpu_relax();
1137
1138         writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1139         writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF));
1140
1141         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1142         wait_for_completion(&mb1_transfer.work);
1143
1144         if (mb1_transfer.ack.header != MB1H_PLL_ON_OFF)
1145                 r = -EIO;
1146
1147         mutex_unlock(&mb1_transfer.lock);
1148
1149         return r;
1150 }
1151
1152 /**
1153  * db8500_prcmu_set_epod - set the state of a EPOD (power domain)
1154  * @epod_id: The EPOD to set
1155  * @epod_state: The new EPOD state
1156  *
1157  * This function sets the state of a EPOD (power domain). It may not be called
1158  * from interrupt context.
1159  */
1160 int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
1161 {
1162         int r = 0;
1163         bool ram_retention = false;
1164         int i;
1165
1166         /* check argument */
1167         BUG_ON(epod_id >= NUM_EPOD_ID);
1168
1169         /* set flag if retention is possible */
1170         switch (epod_id) {
1171         case EPOD_ID_SVAMMDSP:
1172         case EPOD_ID_SIAMMDSP:
1173         case EPOD_ID_ESRAM12:
1174         case EPOD_ID_ESRAM34:
1175                 ram_retention = true;
1176                 break;
1177         }
1178
1179         /* check argument */
1180         BUG_ON(epod_state > EPOD_STATE_ON);
1181         BUG_ON(epod_state == EPOD_STATE_RAMRET && !ram_retention);
1182
1183         /* get lock */
1184         mutex_lock(&mb2_transfer.lock);
1185
1186         /* wait for mailbox */
1187         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2))
1188                 cpu_relax();
1189
1190         /* fill in mailbox */
1191         for (i = 0; i < NUM_EPOD_ID; i++)
1192                 writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i));
1193         writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id));
1194
1195         writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2));
1196
1197         writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET);
1198
1199         /*
1200          * The current firmware version does not handle errors correctly,
1201          * and we cannot recover if there is an error.
1202          * This is expected to change when the firmware is updated.
1203          */
1204         if (!wait_for_completion_timeout(&mb2_transfer.work,
1205                         msecs_to_jiffies(20000))) {
1206                 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1207                         __func__);
1208                 r = -EIO;
1209                 goto unlock_and_return;
1210         }
1211
1212         if (mb2_transfer.ack.status != HWACC_PWR_ST_OK)
1213                 r = -EIO;
1214
1215 unlock_and_return:
1216         mutex_unlock(&mb2_transfer.lock);
1217         return r;
1218 }
1219
1220 /**
1221  * prcmu_configure_auto_pm - Configure autonomous power management.
1222  * @sleep: Configuration for ApSleep.
1223  * @idle:  Configuration for ApIdle.
1224  */
1225 void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
1226         struct prcmu_auto_pm_config *idle)
1227 {
1228         u32 sleep_cfg;
1229         u32 idle_cfg;
1230         unsigned long flags;
1231
1232         BUG_ON((sleep == NULL) || (idle == NULL));
1233
1234         sleep_cfg = (sleep->sva_auto_pm_enable & 0xF);
1235         sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_auto_pm_enable & 0xF));
1236         sleep_cfg = ((sleep_cfg << 8) | (sleep->sva_power_on & 0xFF));
1237         sleep_cfg = ((sleep_cfg << 8) | (sleep->sia_power_on & 0xFF));
1238         sleep_cfg = ((sleep_cfg << 4) | (sleep->sva_policy & 0xF));
1239         sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_policy & 0xF));
1240
1241         idle_cfg = (idle->sva_auto_pm_enable & 0xF);
1242         idle_cfg = ((idle_cfg << 4) | (idle->sia_auto_pm_enable & 0xF));
1243         idle_cfg = ((idle_cfg << 8) | (idle->sva_power_on & 0xFF));
1244         idle_cfg = ((idle_cfg << 8) | (idle->sia_power_on & 0xFF));
1245         idle_cfg = ((idle_cfg << 4) | (idle->sva_policy & 0xF));
1246         idle_cfg = ((idle_cfg << 4) | (idle->sia_policy & 0xF));
1247
1248         spin_lock_irqsave(&mb2_transfer.auto_pm_lock, flags);
1249
1250         /*
1251          * The autonomous power management configuration is done through
1252          * fields in mailbox 2, but these fields are only used as shared
1253          * variables - i.e. there is no need to send a message.
1254          */
1255         writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP));
1256         writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE));
1257
1258         mb2_transfer.auto_pm_enabled =
1259                 ((sleep->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1260                  (sleep->sia_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1261                  (idle->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1262                  (idle->sia_auto_pm_enable == PRCMU_AUTO_PM_ON));
1263
1264         spin_unlock_irqrestore(&mb2_transfer.auto_pm_lock, flags);
1265 }
1266 EXPORT_SYMBOL(prcmu_configure_auto_pm);
1267
1268 bool prcmu_is_auto_pm_enabled(void)
1269 {
1270         return mb2_transfer.auto_pm_enabled;
1271 }
1272
1273 static int request_sysclk(bool enable)
1274 {
1275         int r;
1276         unsigned long flags;
1277
1278         r = 0;
1279
1280         mutex_lock(&mb3_transfer.sysclk_lock);
1281
1282         spin_lock_irqsave(&mb3_transfer.lock, flags);
1283
1284         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3))
1285                 cpu_relax();
1286
1287         writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT));
1288
1289         writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3));
1290         writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET);
1291
1292         spin_unlock_irqrestore(&mb3_transfer.lock, flags);
1293
1294         /*
1295          * The firmware only sends an ACK if we want to enable the
1296          * SysClk, and it succeeds.
1297          */
1298         if (enable && !wait_for_completion_timeout(&mb3_transfer.sysclk_work,
1299                         msecs_to_jiffies(20000))) {
1300                 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1301                         __func__);
1302                 r = -EIO;
1303         }
1304
1305         mutex_unlock(&mb3_transfer.sysclk_lock);
1306
1307         return r;
1308 }
1309
1310 static int request_timclk(bool enable)
1311 {
1312         u32 val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK);
1313
1314         if (!enable)
1315                 val |= PRCM_TCR_STOP_TIMERS;
1316         writel(val, PRCM_TCR);
1317
1318         return 0;
1319 }
1320
1321 static int request_clock(u8 clock, bool enable)
1322 {
1323         u32 val;
1324         unsigned long flags;
1325
1326         spin_lock_irqsave(&clk_mgt_lock, flags);
1327
1328         /* Grab the HW semaphore. */
1329         while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1330                 cpu_relax();
1331
1332         val = readl(prcmu_base + clk_mgt[clock].offset);
1333         if (enable) {
1334                 val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw);
1335         } else {
1336                 clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1337                 val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK);
1338         }
1339         writel(val, prcmu_base + clk_mgt[clock].offset);
1340
1341         /* Release the HW semaphore. */
1342         writel(0, PRCM_SEM);
1343
1344         spin_unlock_irqrestore(&clk_mgt_lock, flags);
1345
1346         return 0;
1347 }
1348
1349 static int request_sga_clock(u8 clock, bool enable)
1350 {
1351         u32 val;
1352         int ret;
1353
1354         if (enable) {
1355                 val = readl(PRCM_CGATING_BYPASS);
1356                 writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1357         }
1358
1359         ret = request_clock(clock, enable);
1360
1361         if (!ret && !enable) {
1362                 val = readl(PRCM_CGATING_BYPASS);
1363                 writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1364         }
1365
1366         return ret;
1367 }
1368
1369 static inline bool plldsi_locked(void)
1370 {
1371         return (readl(PRCM_PLLDSI_LOCKP) &
1372                 (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
1373                  PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3)) ==
1374                 (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
1375                  PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3);
1376 }
1377
1378 static int request_plldsi(bool enable)
1379 {
1380         int r = 0;
1381         u32 val;
1382
1383         writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
1384                 PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), (enable ?
1385                 PRCM_MMIP_LS_CLAMP_CLR : PRCM_MMIP_LS_CLAMP_SET));
1386
1387         val = readl(PRCM_PLLDSI_ENABLE);
1388         if (enable)
1389                 val |= PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1390         else
1391                 val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1392         writel(val, PRCM_PLLDSI_ENABLE);
1393
1394         if (enable) {
1395                 unsigned int i;
1396                 bool locked = plldsi_locked();
1397
1398                 for (i = 10; !locked && (i > 0); --i) {
1399                         udelay(100);
1400                         locked = plldsi_locked();
1401                 }
1402                 if (locked) {
1403                         writel(PRCM_APE_RESETN_DSIPLL_RESETN,
1404                                 PRCM_APE_RESETN_SET);
1405                 } else {
1406                         writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
1407                                 PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI),
1408                                 PRCM_MMIP_LS_CLAMP_SET);
1409                         val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1410                         writel(val, PRCM_PLLDSI_ENABLE);
1411                         r = -EAGAIN;
1412                 }
1413         } else {
1414                 writel(PRCM_APE_RESETN_DSIPLL_RESETN, PRCM_APE_RESETN_CLR);
1415         }
1416         return r;
1417 }
1418
1419 static int request_dsiclk(u8 n, bool enable)
1420 {
1421         u32 val;
1422
1423         val = readl(PRCM_DSI_PLLOUT_SEL);
1424         val &= ~dsiclk[n].divsel_mask;
1425         val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) <<
1426                 dsiclk[n].divsel_shift);
1427         writel(val, PRCM_DSI_PLLOUT_SEL);
1428         return 0;
1429 }
1430
1431 static int request_dsiescclk(u8 n, bool enable)
1432 {
1433         u32 val;
1434
1435         val = readl(PRCM_DSITVCLK_DIV);
1436         enable ? (val |= dsiescclk[n].en) : (val &= ~dsiescclk[n].en);
1437         writel(val, PRCM_DSITVCLK_DIV);
1438         return 0;
1439 }
1440
1441 /**
1442  * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled.
1443  * @clock:      The clock for which the request is made.
1444  * @enable:     Whether the clock should be enabled (true) or disabled (false).
1445  *
1446  * This function should only be used by the clock implementation.
1447  * Do not use it from any other place!
1448  */
1449 int db8500_prcmu_request_clock(u8 clock, bool enable)
1450 {
1451         if (clock == PRCMU_SGACLK)
1452                 return request_sga_clock(clock, enable);
1453         else if (clock < PRCMU_NUM_REG_CLOCKS)
1454                 return request_clock(clock, enable);
1455         else if (clock == PRCMU_TIMCLK)
1456                 return request_timclk(enable);
1457         else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1458                 return request_dsiclk((clock - PRCMU_DSI0CLK), enable);
1459         else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1460                 return request_dsiescclk((clock - PRCMU_DSI0ESCCLK), enable);
1461         else if (clock == PRCMU_PLLDSI)
1462                 return request_plldsi(enable);
1463         else if (clock == PRCMU_SYSCLK)
1464                 return request_sysclk(enable);
1465         else if ((clock == PRCMU_PLLSOC0) || (clock == PRCMU_PLLSOC1))
1466                 return request_pll(clock, enable);
1467         else
1468                 return -EINVAL;
1469 }
1470
1471 static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate,
1472         int branch)
1473 {
1474         u64 rate;
1475         u32 val;
1476         u32 d;
1477         u32 div = 1;
1478
1479         val = readl(reg);
1480
1481         rate = src_rate;
1482         rate *= ((val & PRCM_PLL_FREQ_D_MASK) >> PRCM_PLL_FREQ_D_SHIFT);
1483
1484         d = ((val & PRCM_PLL_FREQ_N_MASK) >> PRCM_PLL_FREQ_N_SHIFT);
1485         if (d > 1)
1486                 div *= d;
1487
1488         d = ((val & PRCM_PLL_FREQ_R_MASK) >> PRCM_PLL_FREQ_R_SHIFT);
1489         if (d > 1)
1490                 div *= d;
1491
1492         if (val & PRCM_PLL_FREQ_SELDIV2)
1493                 div *= 2;
1494
1495         if ((branch == PLL_FIX) || ((branch == PLL_DIV) &&
1496                 (val & PRCM_PLL_FREQ_DIV2EN) &&
1497                 ((reg == PRCM_PLLSOC0_FREQ) ||
1498                  (reg == PRCM_PLLARM_FREQ) ||
1499                  (reg == PRCM_PLLDDR_FREQ))))
1500                 div *= 2;
1501
1502         (void)do_div(rate, div);
1503
1504         return (unsigned long)rate;
1505 }
1506
1507 #define ROOT_CLOCK_RATE 38400000
1508
1509 static unsigned long clock_rate(u8 clock)
1510 {
1511         u32 val;
1512         u32 pllsw;
1513         unsigned long rate = ROOT_CLOCK_RATE;
1514
1515         val = readl(prcmu_base + clk_mgt[clock].offset);
1516
1517         if (val & PRCM_CLK_MGT_CLK38) {
1518                 if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV))
1519                         rate /= 2;
1520                 return rate;
1521         }
1522
1523         val |= clk_mgt[clock].pllsw;
1524         pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1525
1526         if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC0)
1527                 rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch);
1528         else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC1)
1529                 rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch);
1530         else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_DDR)
1531                 rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch);
1532         else
1533                 return 0;
1534
1535         if ((clock == PRCMU_SGACLK) &&
1536                 (val & PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN)) {
1537                 u64 r = (rate * 10);
1538
1539                 (void)do_div(r, 25);
1540                 return (unsigned long)r;
1541         }
1542         val &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
1543         if (val)
1544                 return rate / val;
1545         else
1546                 return 0;
1547 }
1548
1549 static unsigned long armss_rate(void)
1550 {
1551         u32 r;
1552         unsigned long rate;
1553
1554         r = readl(PRCM_ARM_CHGCLKREQ);
1555
1556         if (r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ) {
1557                 /* External ARMCLKFIX clock */
1558
1559                 rate = pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_FIX);
1560
1561                 /* Check PRCM_ARM_CHGCLKREQ divider */
1562                 if (!(r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL))
1563                         rate /= 2;
1564
1565                 /* Check PRCM_ARMCLKFIX_MGT divider */
1566                 r = readl(PRCM_ARMCLKFIX_MGT);
1567                 r &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
1568                 rate /= r;
1569
1570         } else {/* ARM PLL */
1571                 rate = pll_rate(PRCM_PLLARM_FREQ, ROOT_CLOCK_RATE, PLL_DIV);
1572         }
1573
1574         return rate;
1575 }
1576
1577 static unsigned long dsiclk_rate(u8 n)
1578 {
1579         u32 divsel;
1580         u32 div = 1;
1581
1582         divsel = readl(PRCM_DSI_PLLOUT_SEL);
1583         divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift);
1584
1585         if (divsel == PRCM_DSI_PLLOUT_SEL_OFF)
1586                 divsel = dsiclk[n].divsel;
1587         else
1588                 dsiclk[n].divsel = divsel;
1589
1590         switch (divsel) {
1591         case PRCM_DSI_PLLOUT_SEL_PHI_4:
1592                 div *= 2;
1593                 /* Fall through */
1594         case PRCM_DSI_PLLOUT_SEL_PHI_2:
1595                 div *= 2;
1596                 /* Fall through */
1597         case PRCM_DSI_PLLOUT_SEL_PHI:
1598                 return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1599                         PLL_RAW) / div;
1600         default:
1601                 return 0;
1602         }
1603 }
1604
1605 static unsigned long dsiescclk_rate(u8 n)
1606 {
1607         u32 div;
1608
1609         div = readl(PRCM_DSITVCLK_DIV);
1610         div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift));
1611         return clock_rate(PRCMU_TVCLK) / max((u32)1, div);
1612 }
1613
1614 unsigned long prcmu_clock_rate(u8 clock)
1615 {
1616         if (clock < PRCMU_NUM_REG_CLOCKS)
1617                 return clock_rate(clock);
1618         else if (clock == PRCMU_TIMCLK)
1619                 return ROOT_CLOCK_RATE / 16;
1620         else if (clock == PRCMU_SYSCLK)
1621                 return ROOT_CLOCK_RATE;
1622         else if (clock == PRCMU_PLLSOC0)
1623                 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1624         else if (clock == PRCMU_PLLSOC1)
1625                 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1626         else if (clock == PRCMU_ARMSS)
1627                 return armss_rate();
1628         else if (clock == PRCMU_PLLDDR)
1629                 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1630         else if (clock == PRCMU_PLLDSI)
1631                 return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1632                         PLL_RAW);
1633         else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1634                 return dsiclk_rate(clock - PRCMU_DSI0CLK);
1635         else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1636                 return dsiescclk_rate(clock - PRCMU_DSI0ESCCLK);
1637         else
1638                 return 0;
1639 }
1640
1641 static unsigned long clock_source_rate(u32 clk_mgt_val, int branch)
1642 {
1643         if (clk_mgt_val & PRCM_CLK_MGT_CLK38)
1644                 return ROOT_CLOCK_RATE;
1645         clk_mgt_val &= PRCM_CLK_MGT_CLKPLLSW_MASK;
1646         if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC0)
1647                 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, branch);
1648         else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC1)
1649                 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, branch);
1650         else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_DDR)
1651                 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, branch);
1652         else
1653                 return 0;
1654 }
1655
1656 static u32 clock_divider(unsigned long src_rate, unsigned long rate)
1657 {
1658         u32 div;
1659
1660         div = (src_rate / rate);
1661         if (div == 0)
1662                 return 1;
1663         if (rate < (src_rate / div))
1664                 div++;
1665         return div;
1666 }
1667
1668 static long round_clock_rate(u8 clock, unsigned long rate)
1669 {
1670         u32 val;
1671         u32 div;
1672         unsigned long src_rate;
1673         long rounded_rate;
1674
1675         val = readl(prcmu_base + clk_mgt[clock].offset);
1676         src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1677                 clk_mgt[clock].branch);
1678         div = clock_divider(src_rate, rate);
1679         if (val & PRCM_CLK_MGT_CLK38) {
1680                 if (clk_mgt[clock].clk38div) {
1681                         if (div > 2)
1682                                 div = 2;
1683                 } else {
1684                         div = 1;
1685                 }
1686         } else if ((clock == PRCMU_SGACLK) && (div == 3)) {
1687                 u64 r = (src_rate * 10);
1688
1689                 (void)do_div(r, 25);
1690                 if (r <= rate)
1691                         return (unsigned long)r;
1692         }
1693         rounded_rate = (src_rate / min(div, (u32)31));
1694
1695         return rounded_rate;
1696 }
1697
1698 static const unsigned long db8500_armss_freqs[] = {
1699         200000000,
1700         400000000,
1701         800000000,
1702         998400000
1703 };
1704
1705 /* The DB8520 has slightly higher ARMSS max frequency */
1706 static const unsigned long db8520_armss_freqs[] = {
1707         200000000,
1708         400000000,
1709         800000000,
1710         1152000000
1711 };
1712
1713
1714
1715 static long round_armss_rate(unsigned long rate)
1716 {
1717         unsigned long freq = 0;
1718         const unsigned long *freqs;
1719         int nfreqs;
1720         int i;
1721
1722         if (fw_info.version.project == PRCMU_FW_PROJECT_U8520) {
1723                 freqs = db8520_armss_freqs;
1724                 nfreqs = ARRAY_SIZE(db8520_armss_freqs);
1725         } else {
1726                 freqs = db8500_armss_freqs;
1727                 nfreqs = ARRAY_SIZE(db8500_armss_freqs);
1728         }
1729
1730         /* Find the corresponding arm opp from the cpufreq table. */
1731         for (i = 0; i < nfreqs; i++) {
1732                 freq = freqs[i];
1733                 if (rate <= freq)
1734                         break;
1735         }
1736
1737         /* Return the last valid value, even if a match was not found. */
1738         return freq;
1739 }
1740
1741 #define MIN_PLL_VCO_RATE 600000000ULL
1742 #define MAX_PLL_VCO_RATE 1680640000ULL
1743
1744 static long round_plldsi_rate(unsigned long rate)
1745 {
1746         long rounded_rate = 0;
1747         unsigned long src_rate;
1748         unsigned long rem;
1749         u32 r;
1750
1751         src_rate = clock_rate(PRCMU_HDMICLK);
1752         rem = rate;
1753
1754         for (r = 7; (rem > 0) && (r > 0); r--) {
1755                 u64 d;
1756
1757                 d = (r * rate);
1758                 (void)do_div(d, src_rate);
1759                 if (d < 6)
1760                         d = 6;
1761                 else if (d > 255)
1762                         d = 255;
1763                 d *= src_rate;
1764                 if (((2 * d) < (r * MIN_PLL_VCO_RATE)) ||
1765                         ((r * MAX_PLL_VCO_RATE) < (2 * d)))
1766                         continue;
1767                 (void)do_div(d, r);
1768                 if (rate < d) {
1769                         if (rounded_rate == 0)
1770                                 rounded_rate = (long)d;
1771                         break;
1772                 }
1773                 if ((rate - d) < rem) {
1774                         rem = (rate - d);
1775                         rounded_rate = (long)d;
1776                 }
1777         }
1778         return rounded_rate;
1779 }
1780
1781 static long round_dsiclk_rate(unsigned long rate)
1782 {
1783         u32 div;
1784         unsigned long src_rate;
1785         long rounded_rate;
1786
1787         src_rate = pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1788                 PLL_RAW);
1789         div = clock_divider(src_rate, rate);
1790         rounded_rate = (src_rate / ((div > 2) ? 4 : div));
1791
1792         return rounded_rate;
1793 }
1794
1795 static long round_dsiescclk_rate(unsigned long rate)
1796 {
1797         u32 div;
1798         unsigned long src_rate;
1799         long rounded_rate;
1800
1801         src_rate = clock_rate(PRCMU_TVCLK);
1802         div = clock_divider(src_rate, rate);
1803         rounded_rate = (src_rate / min(div, (u32)255));
1804
1805         return rounded_rate;
1806 }
1807
1808 long prcmu_round_clock_rate(u8 clock, unsigned long rate)
1809 {
1810         if (clock < PRCMU_NUM_REG_CLOCKS)
1811                 return round_clock_rate(clock, rate);
1812         else if (clock == PRCMU_ARMSS)
1813                 return round_armss_rate(rate);
1814         else if (clock == PRCMU_PLLDSI)
1815                 return round_plldsi_rate(rate);
1816         else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1817                 return round_dsiclk_rate(rate);
1818         else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1819                 return round_dsiescclk_rate(rate);
1820         else
1821                 return (long)prcmu_clock_rate(clock);
1822 }
1823
1824 static void set_clock_rate(u8 clock, unsigned long rate)
1825 {
1826         u32 val;
1827         u32 div;
1828         unsigned long src_rate;
1829         unsigned long flags;
1830
1831         spin_lock_irqsave(&clk_mgt_lock, flags);
1832
1833         /* Grab the HW semaphore. */
1834         while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1835                 cpu_relax();
1836
1837         val = readl(prcmu_base + clk_mgt[clock].offset);
1838         src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1839                 clk_mgt[clock].branch);
1840         div = clock_divider(src_rate, rate);
1841         if (val & PRCM_CLK_MGT_CLK38) {
1842                 if (clk_mgt[clock].clk38div) {
1843                         if (div > 1)
1844                                 val |= PRCM_CLK_MGT_CLK38DIV;
1845                         else
1846                                 val &= ~PRCM_CLK_MGT_CLK38DIV;
1847                 }
1848         } else if (clock == PRCMU_SGACLK) {
1849                 val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK |
1850                         PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN);
1851                 if (div == 3) {
1852                         u64 r = (src_rate * 10);
1853
1854                         (void)do_div(r, 25);
1855                         if (r <= rate) {
1856                                 val |= PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN;
1857                                 div = 0;
1858                         }
1859                 }
1860                 val |= min(div, (u32)31);
1861         } else {
1862                 val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK;
1863                 val |= min(div, (u32)31);
1864         }
1865         writel(val, prcmu_base + clk_mgt[clock].offset);
1866
1867         /* Release the HW semaphore. */
1868         writel(0, PRCM_SEM);
1869
1870         spin_unlock_irqrestore(&clk_mgt_lock, flags);
1871 }
1872
1873 static int set_armss_rate(unsigned long rate)
1874 {
1875         unsigned long freq;
1876         u8 opps[] = { ARM_EXTCLK, ARM_50_OPP, ARM_100_OPP, ARM_MAX_OPP };
1877         const unsigned long *freqs;
1878         int nfreqs;
1879         int i;
1880
1881         if (fw_info.version.project == PRCMU_FW_PROJECT_U8520) {
1882                 freqs = db8520_armss_freqs;
1883                 nfreqs = ARRAY_SIZE(db8520_armss_freqs);
1884         } else {
1885                 freqs = db8500_armss_freqs;
1886                 nfreqs = ARRAY_SIZE(db8500_armss_freqs);
1887         }
1888
1889         /* Find the corresponding arm opp from the cpufreq table. */
1890         for (i = 0; i < nfreqs; i++) {
1891                 freq = freqs[i];
1892                 if (rate == freq)
1893                         break;
1894         }
1895
1896         if (rate != freq)
1897                 return -EINVAL;
1898
1899         /* Set the new arm opp. */
1900         pr_debug("SET ARM OPP 0x%02x\n", opps[i]);
1901         return db8500_prcmu_set_arm_opp(opps[i]);
1902 }
1903
1904 static int set_plldsi_rate(unsigned long rate)
1905 {
1906         unsigned long src_rate;
1907         unsigned long rem;
1908         u32 pll_freq = 0;
1909         u32 r;
1910
1911         src_rate = clock_rate(PRCMU_HDMICLK);
1912         rem = rate;
1913
1914         for (r = 7; (rem > 0) && (r > 0); r--) {
1915                 u64 d;
1916                 u64 hwrate;
1917
1918                 d = (r * rate);
1919                 (void)do_div(d, src_rate);
1920                 if (d < 6)
1921                         d = 6;
1922                 else if (d > 255)
1923                         d = 255;
1924                 hwrate = (d * src_rate);
1925                 if (((2 * hwrate) < (r * MIN_PLL_VCO_RATE)) ||
1926                         ((r * MAX_PLL_VCO_RATE) < (2 * hwrate)))
1927                         continue;
1928                 (void)do_div(hwrate, r);
1929                 if (rate < hwrate) {
1930                         if (pll_freq == 0)
1931                                 pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
1932                                         (r << PRCM_PLL_FREQ_R_SHIFT));
1933                         break;
1934                 }
1935                 if ((rate - hwrate) < rem) {
1936                         rem = (rate - hwrate);
1937                         pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
1938                                 (r << PRCM_PLL_FREQ_R_SHIFT));
1939                 }
1940         }
1941         if (pll_freq == 0)
1942                 return -EINVAL;
1943
1944         pll_freq |= (1 << PRCM_PLL_FREQ_N_SHIFT);
1945         writel(pll_freq, PRCM_PLLDSI_FREQ);
1946
1947         return 0;
1948 }
1949
1950 static void set_dsiclk_rate(u8 n, unsigned long rate)
1951 {
1952         u32 val;
1953         u32 div;
1954
1955         div = clock_divider(pll_rate(PRCM_PLLDSI_FREQ,
1956                         clock_rate(PRCMU_HDMICLK), PLL_RAW), rate);
1957
1958         dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI :
1959                            (div == 2) ? PRCM_DSI_PLLOUT_SEL_PHI_2 :
1960                            /* else */   PRCM_DSI_PLLOUT_SEL_PHI_4;
1961
1962         val = readl(PRCM_DSI_PLLOUT_SEL);
1963         val &= ~dsiclk[n].divsel_mask;
1964         val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift);
1965         writel(val, PRCM_DSI_PLLOUT_SEL);
1966 }
1967
1968 static void set_dsiescclk_rate(u8 n, unsigned long rate)
1969 {
1970         u32 val;
1971         u32 div;
1972
1973         div = clock_divider(clock_rate(PRCMU_TVCLK), rate);
1974         val = readl(PRCM_DSITVCLK_DIV);
1975         val &= ~dsiescclk[n].div_mask;
1976         val |= (min(div, (u32)255) << dsiescclk[n].div_shift);
1977         writel(val, PRCM_DSITVCLK_DIV);
1978 }
1979
1980 int prcmu_set_clock_rate(u8 clock, unsigned long rate)
1981 {
1982         if (clock < PRCMU_NUM_REG_CLOCKS)
1983                 set_clock_rate(clock, rate);
1984         else if (clock == PRCMU_ARMSS)
1985                 return set_armss_rate(rate);
1986         else if (clock == PRCMU_PLLDSI)
1987                 return set_plldsi_rate(rate);
1988         else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1989                 set_dsiclk_rate((clock - PRCMU_DSI0CLK), rate);
1990         else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1991                 set_dsiescclk_rate((clock - PRCMU_DSI0ESCCLK), rate);
1992         return 0;
1993 }
1994
1995 int db8500_prcmu_config_esram0_deep_sleep(u8 state)
1996 {
1997         if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) ||
1998             (state < ESRAM0_DEEP_SLEEP_STATE_OFF))
1999                 return -EINVAL;
2000
2001         mutex_lock(&mb4_transfer.lock);
2002
2003         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2004                 cpu_relax();
2005
2006         writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2007         writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON),
2008                (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE));
2009         writeb(DDR_PWR_STATE_ON,
2010                (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE));
2011         writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST));
2012
2013         writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2014         wait_for_completion(&mb4_transfer.work);
2015
2016         mutex_unlock(&mb4_transfer.lock);
2017
2018         return 0;
2019 }
2020
2021 int db8500_prcmu_config_hotdog(u8 threshold)
2022 {
2023         mutex_lock(&mb4_transfer.lock);
2024
2025         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2026                 cpu_relax();
2027
2028         writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD));
2029         writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2030
2031         writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2032         wait_for_completion(&mb4_transfer.work);
2033
2034         mutex_unlock(&mb4_transfer.lock);
2035
2036         return 0;
2037 }
2038
2039 int db8500_prcmu_config_hotmon(u8 low, u8 high)
2040 {
2041         mutex_lock(&mb4_transfer.lock);
2042
2043         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2044                 cpu_relax();
2045
2046         writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW));
2047         writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH));
2048         writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH),
2049                 (tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG));
2050         writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2051
2052         writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2053         wait_for_completion(&mb4_transfer.work);
2054
2055         mutex_unlock(&mb4_transfer.lock);
2056
2057         return 0;
2058 }
2059 EXPORT_SYMBOL_GPL(db8500_prcmu_config_hotmon);
2060
2061 static int config_hot_period(u16 val)
2062 {
2063         mutex_lock(&mb4_transfer.lock);
2064
2065         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2066                 cpu_relax();
2067
2068         writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD));
2069         writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2070
2071         writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2072         wait_for_completion(&mb4_transfer.work);
2073
2074         mutex_unlock(&mb4_transfer.lock);
2075
2076         return 0;
2077 }
2078
2079 int db8500_prcmu_start_temp_sense(u16 cycles32k)
2080 {
2081         if (cycles32k == 0xFFFF)
2082                 return -EINVAL;
2083
2084         return config_hot_period(cycles32k);
2085 }
2086 EXPORT_SYMBOL_GPL(db8500_prcmu_start_temp_sense);
2087
2088 int db8500_prcmu_stop_temp_sense(void)
2089 {
2090         return config_hot_period(0xFFFF);
2091 }
2092 EXPORT_SYMBOL_GPL(db8500_prcmu_stop_temp_sense);
2093
2094 static int prcmu_a9wdog(u8 cmd, u8 d0, u8 d1, u8 d2, u8 d3)
2095 {
2096
2097         mutex_lock(&mb4_transfer.lock);
2098
2099         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2100                 cpu_relax();
2101
2102         writeb(d0, (tcdm_base + PRCM_REQ_MB4_A9WDOG_0));
2103         writeb(d1, (tcdm_base + PRCM_REQ_MB4_A9WDOG_1));
2104         writeb(d2, (tcdm_base + PRCM_REQ_MB4_A9WDOG_2));
2105         writeb(d3, (tcdm_base + PRCM_REQ_MB4_A9WDOG_3));
2106
2107         writeb(cmd, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2108
2109         writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2110         wait_for_completion(&mb4_transfer.work);
2111
2112         mutex_unlock(&mb4_transfer.lock);
2113
2114         return 0;
2115
2116 }
2117
2118 int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
2119 {
2120         BUG_ON(num == 0 || num > 0xf);
2121         return prcmu_a9wdog(MB4H_A9WDOG_CONF, num, 0, 0,
2122                             sleep_auto_off ? A9WDOG_AUTO_OFF_EN :
2123                             A9WDOG_AUTO_OFF_DIS);
2124 }
2125 EXPORT_SYMBOL(db8500_prcmu_config_a9wdog);
2126
2127 int db8500_prcmu_enable_a9wdog(u8 id)
2128 {
2129         return prcmu_a9wdog(MB4H_A9WDOG_EN, id, 0, 0, 0);
2130 }
2131 EXPORT_SYMBOL(db8500_prcmu_enable_a9wdog);
2132
2133 int db8500_prcmu_disable_a9wdog(u8 id)
2134 {
2135         return prcmu_a9wdog(MB4H_A9WDOG_DIS, id, 0, 0, 0);
2136 }
2137 EXPORT_SYMBOL(db8500_prcmu_disable_a9wdog);
2138
2139 int db8500_prcmu_kick_a9wdog(u8 id)
2140 {
2141         return prcmu_a9wdog(MB4H_A9WDOG_KICK, id, 0, 0, 0);
2142 }
2143 EXPORT_SYMBOL(db8500_prcmu_kick_a9wdog);
2144
2145 /*
2146  * timeout is 28 bit, in ms.
2147  */
2148 int db8500_prcmu_load_a9wdog(u8 id, u32 timeout)
2149 {
2150         return prcmu_a9wdog(MB4H_A9WDOG_LOAD,
2151                             (id & A9WDOG_ID_MASK) |
2152                             /*
2153                              * Put the lowest 28 bits of timeout at
2154                              * offset 4. Four first bits are used for id.
2155                              */
2156                             (u8)((timeout << 4) & 0xf0),
2157                             (u8)((timeout >> 4) & 0xff),
2158                             (u8)((timeout >> 12) & 0xff),
2159                             (u8)((timeout >> 20) & 0xff));
2160 }
2161 EXPORT_SYMBOL(db8500_prcmu_load_a9wdog);
2162
2163 /**
2164  * prcmu_abb_read() - Read register value(s) from the ABB.
2165  * @slave:      The I2C slave address.
2166  * @reg:        The (start) register address.
2167  * @value:      The read out value(s).
2168  * @size:       The number of registers to read.
2169  *
2170  * Reads register value(s) from the ABB.
2171  * @size has to be 1 for the current firmware version.
2172  */
2173 int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
2174 {
2175         int r;
2176
2177         if (size != 1)
2178                 return -EINVAL;
2179
2180         mutex_lock(&mb5_transfer.lock);
2181
2182         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
2183                 cpu_relax();
2184
2185         writeb(0, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
2186         writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
2187         writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
2188         writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
2189         writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
2190
2191         writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
2192
2193         if (!wait_for_completion_timeout(&mb5_transfer.work,
2194                                 msecs_to_jiffies(20000))) {
2195                 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
2196                         __func__);
2197                 r = -EIO;
2198         } else {
2199                 r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO);
2200         }
2201
2202         if (!r)
2203                 *value = mb5_transfer.ack.value;
2204
2205         mutex_unlock(&mb5_transfer.lock);
2206
2207         return r;
2208 }
2209
2210 /**
2211  * prcmu_abb_write_masked() - Write masked register value(s) to the ABB.
2212  * @slave:      The I2C slave address.
2213  * @reg:        The (start) register address.
2214  * @value:      The value(s) to write.
2215  * @mask:       The mask(s) to use.
2216  * @size:       The number of registers to write.
2217  *
2218  * Writes masked register value(s) to the ABB.
2219  * For each @value, only the bits set to 1 in the corresponding @mask
2220  * will be written. The other bits are not changed.
2221  * @size has to be 1 for the current firmware version.
2222  */
2223 int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size)
2224 {
2225         int r;
2226
2227         if (size != 1)
2228                 return -EINVAL;
2229
2230         mutex_lock(&mb5_transfer.lock);
2231
2232         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
2233                 cpu_relax();
2234
2235         writeb(~*mask, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
2236         writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
2237         writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
2238         writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
2239         writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
2240
2241         writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
2242
2243         if (!wait_for_completion_timeout(&mb5_transfer.work,
2244                                 msecs_to_jiffies(20000))) {
2245                 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
2246                         __func__);
2247                 r = -EIO;
2248         } else {
2249                 r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO);
2250         }
2251
2252         mutex_unlock(&mb5_transfer.lock);
2253
2254         return r;
2255 }
2256
2257 /**
2258  * prcmu_abb_write() - Write register value(s) to the ABB.
2259  * @slave:      The I2C slave address.
2260  * @reg:        The (start) register address.
2261  * @value:      The value(s) to write.
2262  * @size:       The number of registers to write.
2263  *
2264  * Writes register value(s) to the ABB.
2265  * @size has to be 1 for the current firmware version.
2266  */
2267 int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
2268 {
2269         u8 mask = ~0;
2270
2271         return prcmu_abb_write_masked(slave, reg, value, &mask, size);
2272 }
2273
2274 /**
2275  * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem
2276  */
2277 int prcmu_ac_wake_req(void)
2278 {
2279         u32 val;
2280         int ret = 0;
2281
2282         mutex_lock(&mb0_transfer.ac_wake_lock);
2283
2284         val = readl(PRCM_HOSTACCESS_REQ);
2285         if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)
2286                 goto unlock_and_return;
2287
2288         atomic_set(&ac_wake_req_state, 1);
2289
2290         /*
2291          * Force Modem Wake-up before hostaccess_req ping-pong.
2292          * It prevents Modem to enter in Sleep while acking the hostaccess
2293          * request. The 31us delay has been calculated by HWI.
2294          */
2295         val |= PRCM_HOSTACCESS_REQ_WAKE_REQ;
2296         writel(val, PRCM_HOSTACCESS_REQ);
2297
2298         udelay(31);
2299
2300         val |= PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ;
2301         writel(val, PRCM_HOSTACCESS_REQ);
2302
2303         if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
2304                         msecs_to_jiffies(5000))) {
2305                 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
2306                         __func__);
2307                 ret = -EFAULT;
2308         }
2309
2310 unlock_and_return:
2311         mutex_unlock(&mb0_transfer.ac_wake_lock);
2312         return ret;
2313 }
2314
2315 /**
2316  * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem
2317  */
2318 void prcmu_ac_sleep_req(void)
2319 {
2320         u32 val;
2321
2322         mutex_lock(&mb0_transfer.ac_wake_lock);
2323
2324         val = readl(PRCM_HOSTACCESS_REQ);
2325         if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ))
2326                 goto unlock_and_return;
2327
2328         writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ),
2329                 PRCM_HOSTACCESS_REQ);
2330
2331         if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
2332                         msecs_to_jiffies(5000))) {
2333                 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
2334                         __func__);
2335         }
2336
2337         atomic_set(&ac_wake_req_state, 0);
2338
2339 unlock_and_return:
2340         mutex_unlock(&mb0_transfer.ac_wake_lock);
2341 }
2342
2343 bool db8500_prcmu_is_ac_wake_requested(void)
2344 {
2345         return (atomic_read(&ac_wake_req_state) != 0);
2346 }
2347
2348 /**
2349  * db8500_prcmu_system_reset - System reset
2350  *
2351  * Saves the reset reason code and then sets the APE_SOFTRST register which
2352  * fires interrupt to fw
2353  */
2354 void db8500_prcmu_system_reset(u16 reset_code)
2355 {
2356         writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON));
2357         writel(1, PRCM_APE_SOFTRST);
2358 }
2359
2360 /**
2361  * db8500_prcmu_get_reset_code - Retrieve SW reset reason code
2362  *
2363  * Retrieves the reset reason code stored by prcmu_system_reset() before
2364  * last restart.
2365  */
2366 u16 db8500_prcmu_get_reset_code(void)
2367 {
2368         return readw(tcdm_base + PRCM_SW_RST_REASON);
2369 }
2370
2371 /**
2372  * db8500_prcmu_reset_modem - ask the PRCMU to reset modem
2373  */
2374 void db8500_prcmu_modem_reset(void)
2375 {
2376         mutex_lock(&mb1_transfer.lock);
2377
2378         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
2379                 cpu_relax();
2380
2381         writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
2382         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
2383         wait_for_completion(&mb1_transfer.work);
2384
2385         /*
2386          * No need to check return from PRCMU as modem should go in reset state
2387          * This state is already managed by upper layer
2388          */
2389
2390         mutex_unlock(&mb1_transfer.lock);
2391 }
2392
2393 static void ack_dbb_wakeup(void)
2394 {
2395         unsigned long flags;
2396
2397         spin_lock_irqsave(&mb0_transfer.lock, flags);
2398
2399         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
2400                 cpu_relax();
2401
2402         writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
2403         writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
2404
2405         spin_unlock_irqrestore(&mb0_transfer.lock, flags);
2406 }
2407
2408 static inline void print_unknown_header_warning(u8 n, u8 header)
2409 {
2410         pr_warn("prcmu: Unknown message header (%d) in mailbox %d\n",
2411                 header, n);
2412 }
2413
2414 static bool read_mailbox_0(void)
2415 {
2416         bool r;
2417         u32 ev;
2418         unsigned int n;
2419         u8 header;
2420
2421         header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0);
2422         switch (header) {
2423         case MB0H_WAKEUP_EXE:
2424         case MB0H_WAKEUP_SLEEP:
2425                 if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
2426                         ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500);
2427                 else
2428                         ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500);
2429
2430                 if (ev & (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK))
2431                         complete(&mb0_transfer.ac_wake_work);
2432                 if (ev & WAKEUP_BIT_SYSCLK_OK)
2433                         complete(&mb3_transfer.sysclk_work);
2434
2435                 ev &= mb0_transfer.req.dbb_irqs;
2436
2437                 for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) {
2438                         if (ev & prcmu_irq_bit[n])
2439                                 generic_handle_irq(irq_find_mapping(db8500_irq_domain, n));
2440                 }
2441                 r = true;
2442                 break;
2443         default:
2444                 print_unknown_header_warning(0, header);
2445                 r = false;
2446                 break;
2447         }
2448         writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR);
2449         return r;
2450 }
2451
2452 static bool read_mailbox_1(void)
2453 {
2454         mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1);
2455         mb1_transfer.ack.arm_opp = readb(tcdm_base +
2456                 PRCM_ACK_MB1_CURRENT_ARM_OPP);
2457         mb1_transfer.ack.ape_opp = readb(tcdm_base +
2458                 PRCM_ACK_MB1_CURRENT_APE_OPP);
2459         mb1_transfer.ack.ape_voltage_status = readb(tcdm_base +
2460                 PRCM_ACK_MB1_APE_VOLTAGE_STATUS);
2461         writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR);
2462         complete(&mb1_transfer.work);
2463         return false;
2464 }
2465
2466 static bool read_mailbox_2(void)
2467 {
2468         mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS);
2469         writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR);
2470         complete(&mb2_transfer.work);
2471         return false;
2472 }
2473
2474 static bool read_mailbox_3(void)
2475 {
2476         writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR);
2477         return false;
2478 }
2479
2480 static bool read_mailbox_4(void)
2481 {
2482         u8 header;
2483         bool do_complete = true;
2484
2485         header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4);
2486         switch (header) {
2487         case MB4H_MEM_ST:
2488         case MB4H_HOTDOG:
2489         case MB4H_HOTMON:
2490         case MB4H_HOT_PERIOD:
2491         case MB4H_A9WDOG_CONF:
2492         case MB4H_A9WDOG_EN:
2493         case MB4H_A9WDOG_DIS:
2494         case MB4H_A9WDOG_LOAD:
2495         case MB4H_A9WDOG_KICK:
2496                 break;
2497         default:
2498                 print_unknown_header_warning(4, header);
2499                 do_complete = false;
2500                 break;
2501         }
2502
2503         writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR);
2504
2505         if (do_complete)
2506                 complete(&mb4_transfer.work);
2507
2508         return false;
2509 }
2510
2511 static bool read_mailbox_5(void)
2512 {
2513         mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS);
2514         mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL);
2515         writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR);
2516         complete(&mb5_transfer.work);
2517         return false;
2518 }
2519
2520 static bool read_mailbox_6(void)
2521 {
2522         writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR);
2523         return false;
2524 }
2525
2526 static bool read_mailbox_7(void)
2527 {
2528         writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR);
2529         return false;
2530 }
2531
2532 static bool (* const read_mailbox[NUM_MB])(void) = {
2533         read_mailbox_0,
2534         read_mailbox_1,
2535         read_mailbox_2,
2536         read_mailbox_3,
2537         read_mailbox_4,
2538         read_mailbox_5,
2539         read_mailbox_6,
2540         read_mailbox_7
2541 };
2542
2543 static irqreturn_t prcmu_irq_handler(int irq, void *data)
2544 {
2545         u32 bits;
2546         u8 n;
2547         irqreturn_t r;
2548
2549         bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS);
2550         if (unlikely(!bits))
2551                 return IRQ_NONE;
2552
2553         r = IRQ_HANDLED;
2554         for (n = 0; bits; n++) {
2555                 if (bits & MBOX_BIT(n)) {
2556                         bits -= MBOX_BIT(n);
2557                         if (read_mailbox[n]())
2558                                 r = IRQ_WAKE_THREAD;
2559                 }
2560         }
2561         return r;
2562 }
2563
2564 static irqreturn_t prcmu_irq_thread_fn(int irq, void *data)
2565 {
2566         ack_dbb_wakeup();
2567         return IRQ_HANDLED;
2568 }
2569
2570 static void prcmu_mask_work(struct work_struct *work)
2571 {
2572         unsigned long flags;
2573
2574         spin_lock_irqsave(&mb0_transfer.lock, flags);
2575
2576         config_wakeups();
2577
2578         spin_unlock_irqrestore(&mb0_transfer.lock, flags);
2579 }
2580
2581 static void prcmu_irq_mask(struct irq_data *d)
2582 {
2583         unsigned long flags;
2584
2585         spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
2586
2587         mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->hwirq];
2588
2589         spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
2590
2591         if (d->irq != IRQ_PRCMU_CA_SLEEP)
2592                 schedule_work(&mb0_transfer.mask_work);
2593 }
2594
2595 static void prcmu_irq_unmask(struct irq_data *d)
2596 {
2597         unsigned long flags;
2598
2599         spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
2600
2601         mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->hwirq];
2602
2603         spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
2604
2605         if (d->irq != IRQ_PRCMU_CA_SLEEP)
2606                 schedule_work(&mb0_transfer.mask_work);
2607 }
2608
2609 static void noop(struct irq_data *d)
2610 {
2611 }
2612
2613 static struct irq_chip prcmu_irq_chip = {
2614         .name           = "prcmu",
2615         .irq_disable    = prcmu_irq_mask,
2616         .irq_ack        = noop,
2617         .irq_mask       = prcmu_irq_mask,
2618         .irq_unmask     = prcmu_irq_unmask,
2619 };
2620
2621 static char *fw_project_name(u32 project)
2622 {
2623         switch (project) {
2624         case PRCMU_FW_PROJECT_U8500:
2625                 return "U8500";
2626         case PRCMU_FW_PROJECT_U8400:
2627                 return "U8400";
2628         case PRCMU_FW_PROJECT_U9500:
2629                 return "U9500";
2630         case PRCMU_FW_PROJECT_U8500_MBB:
2631                 return "U8500 MBB";
2632         case PRCMU_FW_PROJECT_U8500_C1:
2633                 return "U8500 C1";
2634         case PRCMU_FW_PROJECT_U8500_C2:
2635                 return "U8500 C2";
2636         case PRCMU_FW_PROJECT_U8500_C3:
2637                 return "U8500 C3";
2638         case PRCMU_FW_PROJECT_U8500_C4:
2639                 return "U8500 C4";
2640         case PRCMU_FW_PROJECT_U9500_MBL:
2641                 return "U9500 MBL";
2642         case PRCMU_FW_PROJECT_U8500_MBL:
2643                 return "U8500 MBL";
2644         case PRCMU_FW_PROJECT_U8500_MBL2:
2645                 return "U8500 MBL2";
2646         case PRCMU_FW_PROJECT_U8520:
2647                 return "U8520 MBL";
2648         case PRCMU_FW_PROJECT_U8420:
2649                 return "U8420";
2650         case PRCMU_FW_PROJECT_U9540:
2651                 return "U9540";
2652         case PRCMU_FW_PROJECT_A9420:
2653                 return "A9420";
2654         case PRCMU_FW_PROJECT_L8540:
2655                 return "L8540";
2656         case PRCMU_FW_PROJECT_L8580:
2657                 return "L8580";
2658         default:
2659                 return "Unknown";
2660         }
2661 }
2662
2663 static int db8500_irq_map(struct irq_domain *d, unsigned int virq,
2664                                 irq_hw_number_t hwirq)
2665 {
2666         irq_set_chip_and_handler(virq, &prcmu_irq_chip,
2667                                 handle_simple_irq);
2668
2669         return 0;
2670 }
2671
2672 static const struct irq_domain_ops db8500_irq_ops = {
2673         .map    = db8500_irq_map,
2674         .xlate  = irq_domain_xlate_twocell,
2675 };
2676
2677 static int db8500_irq_init(struct device_node *np)
2678 {
2679         int i;
2680
2681         db8500_irq_domain = irq_domain_add_simple(
2682                 np, NUM_PRCMU_WAKEUPS, 0,
2683                 &db8500_irq_ops, NULL);
2684
2685         if (!db8500_irq_domain) {
2686                 pr_err("Failed to create irqdomain\n");
2687                 return -ENOSYS;
2688         }
2689
2690         /* All wakeups will be used, so create mappings for all */
2691         for (i = 0; i < NUM_PRCMU_WAKEUPS; i++)
2692                 irq_create_mapping(db8500_irq_domain, i);
2693
2694         return 0;
2695 }
2696
2697 static void dbx500_fw_version_init(struct platform_device *pdev,
2698                             u32 version_offset)
2699 {
2700         struct resource *res;
2701         void __iomem *tcpm_base;
2702         u32 version;
2703
2704         res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2705                                            "prcmu-tcpm");
2706         if (!res) {
2707                 dev_err(&pdev->dev,
2708                         "Error: no prcmu tcpm memory region provided\n");
2709                 return;
2710         }
2711         tcpm_base = ioremap(res->start, resource_size(res));
2712         if (!tcpm_base) {
2713                 dev_err(&pdev->dev, "no prcmu tcpm mem region provided\n");
2714                 return;
2715         }
2716
2717         version = readl(tcpm_base + version_offset);
2718         fw_info.version.project = (version & 0xFF);
2719         fw_info.version.api_version = (version >> 8) & 0xFF;
2720         fw_info.version.func_version = (version >> 16) & 0xFF;
2721         fw_info.version.errata = (version >> 24) & 0xFF;
2722         strncpy(fw_info.version.project_name,
2723                 fw_project_name(fw_info.version.project),
2724                 PRCMU_FW_PROJECT_NAME_LEN);
2725         fw_info.valid = true;
2726         pr_info("PRCMU firmware: %s(%d), version %d.%d.%d\n",
2727                 fw_info.version.project_name,
2728                 fw_info.version.project,
2729                 fw_info.version.api_version,
2730                 fw_info.version.func_version,
2731                 fw_info.version.errata);
2732         iounmap(tcpm_base);
2733 }
2734
2735 void __init db8500_prcmu_early_init(u32 phy_base, u32 size)
2736 {
2737         /*
2738          * This is a temporary remap to bring up the clocks. It is
2739          * subsequently replaces with a real remap. After the merge of
2740          * the mailbox subsystem all of this early code goes away, and the
2741          * clock driver can probe independently. An early initcall will
2742          * still be needed, but it can be diverted into drivers/clk/ux500.
2743          */
2744         prcmu_base = ioremap(phy_base, size);
2745         if (!prcmu_base)
2746                 pr_err("%s: ioremap() of prcmu registers failed!\n", __func__);
2747
2748         spin_lock_init(&mb0_transfer.lock);
2749         spin_lock_init(&mb0_transfer.dbb_irqs_lock);
2750         mutex_init(&mb0_transfer.ac_wake_lock);
2751         init_completion(&mb0_transfer.ac_wake_work);
2752         mutex_init(&mb1_transfer.lock);
2753         init_completion(&mb1_transfer.work);
2754         mb1_transfer.ape_opp = APE_NO_CHANGE;
2755         mutex_init(&mb2_transfer.lock);
2756         init_completion(&mb2_transfer.work);
2757         spin_lock_init(&mb2_transfer.auto_pm_lock);
2758         spin_lock_init(&mb3_transfer.lock);
2759         mutex_init(&mb3_transfer.sysclk_lock);
2760         init_completion(&mb3_transfer.sysclk_work);
2761         mutex_init(&mb4_transfer.lock);
2762         init_completion(&mb4_transfer.work);
2763         mutex_init(&mb5_transfer.lock);
2764         init_completion(&mb5_transfer.work);
2765
2766         INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work);
2767 }
2768
2769 static void init_prcm_registers(void)
2770 {
2771         u32 val;
2772
2773         val = readl(PRCM_A9PL_FORCE_CLKEN);
2774         val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN |
2775                 PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN);
2776         writel(val, (PRCM_A9PL_FORCE_CLKEN));
2777 }
2778
2779 /*
2780  * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC
2781  */
2782 static struct regulator_consumer_supply db8500_vape_consumers[] = {
2783         REGULATOR_SUPPLY("v-ape", NULL),
2784         REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"),
2785         REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"),
2786         REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"),
2787         REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"),
2788         REGULATOR_SUPPLY("v-i2c", "nmk-i2c.4"),
2789         /* "v-mmc" changed to "vcore" in the mainline kernel */
2790         REGULATOR_SUPPLY("vcore", "sdi0"),
2791         REGULATOR_SUPPLY("vcore", "sdi1"),
2792         REGULATOR_SUPPLY("vcore", "sdi2"),
2793         REGULATOR_SUPPLY("vcore", "sdi3"),
2794         REGULATOR_SUPPLY("vcore", "sdi4"),
2795         REGULATOR_SUPPLY("v-dma", "dma40.0"),
2796         REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"),
2797         /* "v-uart" changed to "vcore" in the mainline kernel */
2798         REGULATOR_SUPPLY("vcore", "uart0"),
2799         REGULATOR_SUPPLY("vcore", "uart1"),
2800         REGULATOR_SUPPLY("vcore", "uart2"),
2801         REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"),
2802         REGULATOR_SUPPLY("v-hsi", "ste_hsi.0"),
2803         REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
2804 };
2805
2806 static struct regulator_consumer_supply db8500_vsmps2_consumers[] = {
2807         REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"),
2808         /* AV8100 regulator */
2809         REGULATOR_SUPPLY("hdmi_1v8", "0-0070"),
2810 };
2811
2812 static struct regulator_consumer_supply db8500_b2r2_mcde_consumers[] = {
2813         REGULATOR_SUPPLY("vsupply", "b2r2_bus"),
2814         REGULATOR_SUPPLY("vsupply", "mcde"),
2815 };
2816
2817 /* SVA MMDSP regulator switch */
2818 static struct regulator_consumer_supply db8500_svammdsp_consumers[] = {
2819         REGULATOR_SUPPLY("sva-mmdsp", "cm_control"),
2820 };
2821
2822 /* SVA pipe regulator switch */
2823 static struct regulator_consumer_supply db8500_svapipe_consumers[] = {
2824         REGULATOR_SUPPLY("sva-pipe", "cm_control"),
2825 };
2826
2827 /* SIA MMDSP regulator switch */
2828 static struct regulator_consumer_supply db8500_siammdsp_consumers[] = {
2829         REGULATOR_SUPPLY("sia-mmdsp", "cm_control"),
2830 };
2831
2832 /* SIA pipe regulator switch */
2833 static struct regulator_consumer_supply db8500_siapipe_consumers[] = {
2834         REGULATOR_SUPPLY("sia-pipe", "cm_control"),
2835 };
2836
2837 static struct regulator_consumer_supply db8500_sga_consumers[] = {
2838         REGULATOR_SUPPLY("v-mali", NULL),
2839 };
2840
2841 /* ESRAM1 and 2 regulator switch */
2842 static struct regulator_consumer_supply db8500_esram12_consumers[] = {
2843         REGULATOR_SUPPLY("esram12", "cm_control"),
2844 };
2845
2846 /* ESRAM3 and 4 regulator switch */
2847 static struct regulator_consumer_supply db8500_esram34_consumers[] = {
2848         REGULATOR_SUPPLY("v-esram34", "mcde"),
2849         REGULATOR_SUPPLY("esram34", "cm_control"),
2850         REGULATOR_SUPPLY("lcla_esram", "dma40.0"),
2851 };
2852
2853 static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = {
2854         [DB8500_REGULATOR_VAPE] = {
2855                 .constraints = {
2856                         .name = "db8500-vape",
2857                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2858                         .always_on = true,
2859                 },
2860                 .consumer_supplies = db8500_vape_consumers,
2861                 .num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers),
2862         },
2863         [DB8500_REGULATOR_VARM] = {
2864                 .constraints = {
2865                         .name = "db8500-varm",
2866                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2867                 },
2868         },
2869         [DB8500_REGULATOR_VMODEM] = {
2870                 .constraints = {
2871                         .name = "db8500-vmodem",
2872                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2873                 },
2874         },
2875         [DB8500_REGULATOR_VPLL] = {
2876                 .constraints = {
2877                         .name = "db8500-vpll",
2878                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2879                 },
2880         },
2881         [DB8500_REGULATOR_VSMPS1] = {
2882                 .constraints = {
2883                         .name = "db8500-vsmps1",
2884                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2885                 },
2886         },
2887         [DB8500_REGULATOR_VSMPS2] = {
2888                 .constraints = {
2889                         .name = "db8500-vsmps2",
2890                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2891                 },
2892                 .consumer_supplies = db8500_vsmps2_consumers,
2893                 .num_consumer_supplies = ARRAY_SIZE(db8500_vsmps2_consumers),
2894         },
2895         [DB8500_REGULATOR_VSMPS3] = {
2896                 .constraints = {
2897                         .name = "db8500-vsmps3",
2898                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2899                 },
2900         },
2901         [DB8500_REGULATOR_VRF1] = {
2902                 .constraints = {
2903                         .name = "db8500-vrf1",
2904                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2905                 },
2906         },
2907         [DB8500_REGULATOR_SWITCH_SVAMMDSP] = {
2908                 /* dependency to u8500-vape is handled outside regulator framework */
2909                 .constraints = {
2910                         .name = "db8500-sva-mmdsp",
2911                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2912                 },
2913                 .consumer_supplies = db8500_svammdsp_consumers,
2914                 .num_consumer_supplies = ARRAY_SIZE(db8500_svammdsp_consumers),
2915         },
2916         [DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = {
2917                 .constraints = {
2918                         /* "ret" means "retention" */
2919                         .name = "db8500-sva-mmdsp-ret",
2920                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2921                 },
2922         },
2923         [DB8500_REGULATOR_SWITCH_SVAPIPE] = {
2924                 /* dependency to u8500-vape is handled outside regulator framework */
2925                 .constraints = {
2926                         .name = "db8500-sva-pipe",
2927                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2928                 },
2929                 .consumer_supplies = db8500_svapipe_consumers,
2930                 .num_consumer_supplies = ARRAY_SIZE(db8500_svapipe_consumers),
2931         },
2932         [DB8500_REGULATOR_SWITCH_SIAMMDSP] = {
2933                 /* dependency to u8500-vape is handled outside regulator framework */
2934                 .constraints = {
2935                         .name = "db8500-sia-mmdsp",
2936                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2937                 },
2938                 .consumer_supplies = db8500_siammdsp_consumers,
2939                 .num_consumer_supplies = ARRAY_SIZE(db8500_siammdsp_consumers),
2940         },
2941         [DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = {
2942                 .constraints = {
2943                         .name = "db8500-sia-mmdsp-ret",
2944                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2945                 },
2946         },
2947         [DB8500_REGULATOR_SWITCH_SIAPIPE] = {
2948                 /* dependency to u8500-vape is handled outside regulator framework */
2949                 .constraints = {
2950                         .name = "db8500-sia-pipe",
2951                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2952                 },
2953                 .consumer_supplies = db8500_siapipe_consumers,
2954                 .num_consumer_supplies = ARRAY_SIZE(db8500_siapipe_consumers),
2955         },
2956         [DB8500_REGULATOR_SWITCH_SGA] = {
2957                 .supply_regulator = "db8500-vape",
2958                 .constraints = {
2959                         .name = "db8500-sga",
2960                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2961                 },
2962                 .consumer_supplies = db8500_sga_consumers,
2963                 .num_consumer_supplies = ARRAY_SIZE(db8500_sga_consumers),
2964
2965         },
2966         [DB8500_REGULATOR_SWITCH_B2R2_MCDE] = {
2967                 .supply_regulator = "db8500-vape",
2968                 .constraints = {
2969                         .name = "db8500-b2r2-mcde",
2970                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2971                 },
2972                 .consumer_supplies = db8500_b2r2_mcde_consumers,
2973                 .num_consumer_supplies = ARRAY_SIZE(db8500_b2r2_mcde_consumers),
2974         },
2975         [DB8500_REGULATOR_SWITCH_ESRAM12] = {
2976                 /*
2977                  * esram12 is set in retention and supplied by Vsafe when Vape is off,
2978                  * no need to hold Vape
2979                  */
2980                 .constraints = {
2981                         .name = "db8500-esram12",
2982                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2983                 },
2984                 .consumer_supplies = db8500_esram12_consumers,
2985                 .num_consumer_supplies = ARRAY_SIZE(db8500_esram12_consumers),
2986         },
2987         [DB8500_REGULATOR_SWITCH_ESRAM12RET] = {
2988                 .constraints = {
2989                         .name = "db8500-esram12-ret",
2990                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2991                 },
2992         },
2993         [DB8500_REGULATOR_SWITCH_ESRAM34] = {
2994                 /*
2995                  * esram34 is set in retention and supplied by Vsafe when Vape is off,
2996                  * no need to hold Vape
2997                  */
2998                 .constraints = {
2999                         .name = "db8500-esram34",
3000                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3001                 },
3002                 .consumer_supplies = db8500_esram34_consumers,
3003                 .num_consumer_supplies = ARRAY_SIZE(db8500_esram34_consumers),
3004         },
3005         [DB8500_REGULATOR_SWITCH_ESRAM34RET] = {
3006                 .constraints = {
3007                         .name = "db8500-esram34-ret",
3008                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3009                 },
3010         },
3011 };
3012
3013 static struct ux500_wdt_data db8500_wdt_pdata = {
3014         .timeout = 600, /* 10 minutes */
3015         .has_28_bits_resolution = true,
3016 };
3017 /*
3018  * Thermal Sensor
3019  */
3020
3021 static struct resource db8500_thsens_resources[] = {
3022         {
3023                 .name = "IRQ_HOTMON_LOW",
3024                 .start  = IRQ_PRCMU_HOTMON_LOW,
3025                 .end    = IRQ_PRCMU_HOTMON_LOW,
3026                 .flags  = IORESOURCE_IRQ,
3027         },
3028         {
3029                 .name = "IRQ_HOTMON_HIGH",
3030                 .start  = IRQ_PRCMU_HOTMON_HIGH,
3031                 .end    = IRQ_PRCMU_HOTMON_HIGH,
3032                 .flags  = IORESOURCE_IRQ,
3033         },
3034 };
3035
3036 static struct db8500_thsens_platform_data db8500_thsens_data = {
3037         .trip_points[0] = {
3038                 .temp = 70000,
3039                 .type = THERMAL_TRIP_ACTIVE,
3040                 .cdev_name = {
3041                         [0] = "thermal-cpufreq-0",
3042                 },
3043         },
3044         .trip_points[1] = {
3045                 .temp = 75000,
3046                 .type = THERMAL_TRIP_ACTIVE,
3047                 .cdev_name = {
3048                         [0] = "thermal-cpufreq-0",
3049                 },
3050         },
3051         .trip_points[2] = {
3052                 .temp = 80000,
3053                 .type = THERMAL_TRIP_ACTIVE,
3054                 .cdev_name = {
3055                         [0] = "thermal-cpufreq-0",
3056                 },
3057         },
3058         .trip_points[3] = {
3059                 .temp = 85000,
3060                 .type = THERMAL_TRIP_CRITICAL,
3061         },
3062         .num_trips = 4,
3063 };
3064
3065 static const struct mfd_cell common_prcmu_devs[] = {
3066         {
3067                 .name = "ux500_wdt",
3068                 .platform_data = &db8500_wdt_pdata,
3069                 .pdata_size = sizeof(db8500_wdt_pdata),
3070                 .id = -1,
3071         },
3072 };
3073
3074 static const struct mfd_cell db8500_prcmu_devs[] = {
3075         {
3076                 .name = "db8500-prcmu-regulators",
3077                 .of_compatible = "stericsson,db8500-prcmu-regulator",
3078                 .platform_data = &db8500_regulators,
3079                 .pdata_size = sizeof(db8500_regulators),
3080         },
3081         {
3082                 .name = "cpuidle-dbx500",
3083                 .of_compatible = "stericsson,cpuidle-dbx500",
3084         },
3085         {
3086                 .name = "db8500-thermal",
3087                 .num_resources = ARRAY_SIZE(db8500_thsens_resources),
3088                 .resources = db8500_thsens_resources,
3089                 .platform_data = &db8500_thsens_data,
3090                 .pdata_size = sizeof(db8500_thsens_data),
3091         },
3092 };
3093
3094 static int db8500_prcmu_register_ab8500(struct device *parent)
3095 {
3096         struct device_node *np;
3097         struct resource ab8500_resource;
3098         const struct mfd_cell ab8500_cell = {
3099                 .name = "ab8500-core",
3100                 .of_compatible = "stericsson,ab8500",
3101                 .id = AB8500_VERSION_AB8500,
3102                 .resources = &ab8500_resource,
3103                 .num_resources = 1,
3104         };
3105
3106         if (!parent->of_node)
3107                 return -ENODEV;
3108
3109         /* Look up the device node, sneak the IRQ out of it */
3110         for_each_child_of_node(parent->of_node, np) {
3111                 if (of_device_is_compatible(np, ab8500_cell.of_compatible))
3112                         break;
3113         }
3114         if (!np) {
3115                 dev_info(parent, "could not find AB8500 node in the device tree\n");
3116                 return -ENODEV;
3117         }
3118         of_irq_to_resource_table(np, &ab8500_resource, 1);
3119
3120         return mfd_add_devices(parent, 0, &ab8500_cell, 1, NULL, 0, NULL);
3121 }
3122
3123 /**
3124  * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic
3125  *
3126  */
3127 static int db8500_prcmu_probe(struct platform_device *pdev)
3128 {
3129         struct device_node *np = pdev->dev.of_node;
3130         int irq = 0, err = 0;
3131         struct resource *res;
3132
3133         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu");
3134         if (!res) {
3135                 dev_err(&pdev->dev, "no prcmu memory region provided\n");
3136                 return -EINVAL;
3137         }
3138         prcmu_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
3139         if (!prcmu_base) {
3140                 dev_err(&pdev->dev,
3141                         "failed to ioremap prcmu register memory\n");
3142                 return -ENOMEM;
3143         }
3144         init_prcm_registers();
3145         dbx500_fw_version_init(pdev, DB8500_PRCMU_FW_VERSION_OFFSET);
3146         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu-tcdm");
3147         if (!res) {
3148                 dev_err(&pdev->dev, "no prcmu tcdm region provided\n");
3149                 return -EINVAL;
3150         }
3151         tcdm_base = devm_ioremap(&pdev->dev, res->start,
3152                         resource_size(res));
3153         if (!tcdm_base) {
3154                 dev_err(&pdev->dev,
3155                         "failed to ioremap prcmu-tcdm register memory\n");
3156                 return -ENOMEM;
3157         }
3158
3159         /* Clean up the mailbox interrupts after pre-kernel code. */
3160         writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR);
3161
3162         irq = platform_get_irq(pdev, 0);
3163         if (irq <= 0)
3164                 return irq;
3165
3166         err = request_threaded_irq(irq, prcmu_irq_handler,
3167                 prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL);
3168         if (err < 0) {
3169                 pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n");
3170                 return err;
3171         }
3172
3173         db8500_irq_init(np);
3174
3175         prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET);
3176
3177         err = mfd_add_devices(&pdev->dev, 0, common_prcmu_devs,
3178                               ARRAY_SIZE(common_prcmu_devs), NULL, 0, db8500_irq_domain);
3179         if (err) {
3180                 pr_err("prcmu: Failed to add subdevices\n");
3181                 return err;
3182         }
3183
3184         /* TODO: Remove restriction when clk definitions are available. */
3185         if (!of_machine_is_compatible("st-ericsson,u8540")) {
3186                 err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs,
3187                                       ARRAY_SIZE(db8500_prcmu_devs), NULL, 0,
3188                                       db8500_irq_domain);
3189                 if (err) {
3190                         mfd_remove_devices(&pdev->dev);
3191                         pr_err("prcmu: Failed to add subdevices\n");
3192                         return err;
3193                 }
3194         }
3195
3196         err = db8500_prcmu_register_ab8500(&pdev->dev);
3197         if (err) {
3198                 mfd_remove_devices(&pdev->dev);
3199                 pr_err("prcmu: Failed to add ab8500 subdevice\n");
3200                 return err;
3201         }
3202
3203         pr_info("DB8500 PRCMU initialized\n");
3204         return err;
3205 }
3206 static const struct of_device_id db8500_prcmu_match[] = {
3207         { .compatible = "stericsson,db8500-prcmu"},
3208         { },
3209 };
3210
3211 static struct platform_driver db8500_prcmu_driver = {
3212         .driver = {
3213                 .name = "db8500-prcmu",
3214                 .of_match_table = db8500_prcmu_match,
3215         },
3216         .probe = db8500_prcmu_probe,
3217 };
3218
3219 static int __init db8500_prcmu_init(void)
3220 {
3221         return platform_driver_register(&db8500_prcmu_driver);
3222 }
3223 core_initcall(db8500_prcmu_init);