2 * Copyright (C) 2015 NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
12 #include <asm/cacheflush.h>
14 #include <dt-bindings/memory/tegra210-mc.h>
18 static const struct tegra_mc_client tegra210_mc_clients[] = {
22 .swgroup = TEGRA_SWGROUP_PTC,
26 .swgroup = TEGRA_SWGROUP_DC,
40 .swgroup = TEGRA_SWGROUP_DCB,
54 .swgroup = TEGRA_SWGROUP_DC,
68 .swgroup = TEGRA_SWGROUP_DCB,
82 .swgroup = TEGRA_SWGROUP_DC,
96 .swgroup = TEGRA_SWGROUP_DCB,
110 .swgroup = TEGRA_SWGROUP_AFI,
124 .swgroup = TEGRA_SWGROUP_AVPC,
138 .swgroup = TEGRA_SWGROUP_DC,
151 .name = "displayhcb",
152 .swgroup = TEGRA_SWGROUP_DCB,
166 .swgroup = TEGRA_SWGROUP_HDA,
179 .name = "host1xdmar",
180 .swgroup = TEGRA_SWGROUP_HC,
194 .swgroup = TEGRA_SWGROUP_HC,
208 .swgroup = TEGRA_SWGROUP_NVENC,
221 .name = "ppcsahbdmar",
222 .swgroup = TEGRA_SWGROUP_PPCS,
235 .name = "ppcsahbslvr",
236 .swgroup = TEGRA_SWGROUP_PPCS,
250 .swgroup = TEGRA_SWGROUP_SATA,
264 .swgroup = TEGRA_SWGROUP_MPCORE,
274 .swgroup = TEGRA_SWGROUP_NVENC,
288 .swgroup = TEGRA_SWGROUP_AFI,
302 .swgroup = TEGRA_SWGROUP_AVPC,
316 .swgroup = TEGRA_SWGROUP_HDA,
330 .swgroup = TEGRA_SWGROUP_HC,
344 .swgroup = TEGRA_SWGROUP_MPCORE,
353 .name = "ppcsahbdmaw",
354 .swgroup = TEGRA_SWGROUP_PPCS,
367 .name = "ppcsahbslvw",
368 .swgroup = TEGRA_SWGROUP_PPCS,
382 .swgroup = TEGRA_SWGROUP_SATA,
396 .swgroup = TEGRA_SWGROUP_ISP2,
410 .swgroup = TEGRA_SWGROUP_ISP2,
424 .swgroup = TEGRA_SWGROUP_ISP2,
437 .name = "xusb_hostr",
438 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
451 .name = "xusb_hostw",
452 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
466 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
480 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
494 .swgroup = TEGRA_SWGROUP_ISP2B,
508 .swgroup = TEGRA_SWGROUP_ISP2B,
522 .swgroup = TEGRA_SWGROUP_ISP2B,
536 .swgroup = TEGRA_SWGROUP_TSEC,
550 .swgroup = TEGRA_SWGROUP_TSEC,
564 .swgroup = TEGRA_SWGROUP_A9AVP,
578 .swgroup = TEGRA_SWGROUP_A9AVP,
592 .swgroup = TEGRA_SWGROUP_GPU,
607 .swgroup = TEGRA_SWGROUP_GPU,
622 .swgroup = TEGRA_SWGROUP_DC,
636 .swgroup = TEGRA_SWGROUP_SDMMC1A,
650 .swgroup = TEGRA_SWGROUP_SDMMC2A,
664 .swgroup = TEGRA_SWGROUP_SDMMC3A,
677 .swgroup = TEGRA_SWGROUP_SDMMC4A,
692 .swgroup = TEGRA_SWGROUP_SDMMC1A,
706 .swgroup = TEGRA_SWGROUP_SDMMC2A,
720 .swgroup = TEGRA_SWGROUP_SDMMC3A,
734 .swgroup = TEGRA_SWGROUP_SDMMC4A,
748 .swgroup = TEGRA_SWGROUP_VIC,
762 .swgroup = TEGRA_SWGROUP_VIC,
776 .swgroup = TEGRA_SWGROUP_VI,
790 .swgroup = TEGRA_SWGROUP_DC,
804 .swgroup = TEGRA_SWGROUP_NVDEC,
818 .swgroup = TEGRA_SWGROUP_NVDEC,
832 .swgroup = TEGRA_SWGROUP_APE,
846 .swgroup = TEGRA_SWGROUP_APE,
860 .swgroup = TEGRA_SWGROUP_NVJPG,
874 .swgroup = TEGRA_SWGROUP_NVJPG,
888 .swgroup = TEGRA_SWGROUP_SE,
902 .swgroup = TEGRA_SWGROUP_SE,
916 .swgroup = TEGRA_SWGROUP_AXIAP,
930 .swgroup = TEGRA_SWGROUP_AXIAP,
944 .swgroup = TEGRA_SWGROUP_ETR,
958 .swgroup = TEGRA_SWGROUP_ETR,
972 .swgroup = TEGRA_SWGROUP_TSECB,
986 .swgroup = TEGRA_SWGROUP_TSECB,
1000 .swgroup = TEGRA_SWGROUP_GPU,
1015 .swgroup = TEGRA_SWGROUP_GPU,
1030 static const struct tegra_smmu_swgroup tegra210_swgroups[] = {
1031 { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
1032 { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
1033 { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
1034 { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
1035 { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
1036 { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
1037 { .name = "nvenc", .swgroup = TEGRA_SWGROUP_NVENC, .reg = 0x264 },
1038 { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
1039 { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
1040 { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
1041 { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
1042 { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
1043 { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
1044 { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
1045 { .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
1046 { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
1047 { .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
1048 { .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
1049 { .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
1050 { .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
1051 { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
1052 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
1053 { .name = "nvdec", .swgroup = TEGRA_SWGROUP_NVDEC, .reg = 0xab4 },
1054 { .name = "ape", .swgroup = TEGRA_SWGROUP_APE, .reg = 0xab8 },
1055 { .name = "nvjpg", .swgroup = TEGRA_SWGROUP_NVJPG, .reg = 0xac0 },
1056 { .name = "se", .swgroup = TEGRA_SWGROUP_SE, .reg = 0xabc },
1057 { .name = "axiap", .swgroup = TEGRA_SWGROUP_AXIAP, .reg = 0xacc },
1058 { .name = "etr", .swgroup = TEGRA_SWGROUP_ETR, .reg = 0xad0 },
1059 { .name = "tsecb", .swgroup = TEGRA_SWGROUP_TSECB, .reg = 0xad4 },
1062 static const unsigned int tegra210_group_display[] = {
1067 static const struct tegra_smmu_group_soc tegra210_groups[] = {
1070 .swgroups = tegra210_group_display,
1071 .num_swgroups = ARRAY_SIZE(tegra210_group_display),
1075 static const struct tegra_smmu_soc tegra210_smmu_soc = {
1076 .clients = tegra210_mc_clients,
1077 .num_clients = ARRAY_SIZE(tegra210_mc_clients),
1078 .swgroups = tegra210_swgroups,
1079 .num_swgroups = ARRAY_SIZE(tegra210_swgroups),
1080 .groups = tegra210_groups,
1081 .num_groups = ARRAY_SIZE(tegra210_groups),
1082 .supports_round_robin_arbitration = true,
1083 .supports_request_limit = true,
1084 .num_tlb_lines = 32,
1088 const struct tegra_mc_soc tegra210_mc_soc = {
1089 .clients = tegra210_mc_clients,
1090 .num_clients = ARRAY_SIZE(tegra210_mc_clients),
1091 .num_address_bits = 34,
1093 .client_id_mask = 0xff,
1094 .smmu = &tegra210_smmu_soc,