drivers/memory/tegra/tegra186.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2017-2021 NVIDIA CORPORATION.  All rights reserved.
   4  */
   5
   6 #include <linux/io.h>
   7 #include <linux/iommu.h>
   8 #include <linux/module.h>
   9 #include <linux/mod_devicetable.h>
  10 #include <linux/of_device.h>
  11 #include <linux/platform_device.h>
  12
  13 #include <soc/tegra/mc.h>
  14
  15 #if defined(CONFIG_ARCH_TEGRA_186_SOC)
  16 #include <dt-bindings/memory/tegra186-mc.h>
  17 #endif
  18
  19 #include "mc.h"
  20
  21 #define MC_SID_STREAMID_OVERRIDE_MASK GENMASK(7, 0)
  22 #define MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED BIT(16)
  23 #define MC_SID_STREAMID_SECURITY_OVERRIDE BIT(8)
  24
  25 static void tegra186_mc_program_sid(struct tegra_mc *mc)
  26 {
  27         unsigned int i;
  28
  29         for (i = 0; i < mc->soc->num_clients; i++) {
  30                 const struct tegra_mc_client *client = &mc->soc->clients[i];
  31                 u32 override, security;
  32
  33                 override = readl(mc->regs + client->regs.sid.override);
  34                 security = readl(mc->regs + client->regs.sid.security);
  35
  36                 dev_dbg(mc->dev, "client %s: override: %x security: %x\n",
  37                         client->name, override, security);
  38
  39                 dev_dbg(mc->dev, "setting SID %u for %s\n", client->sid,
  40                         client->name);
  41                 writel(client->sid, mc->regs + client->regs.sid.override);
  42
  43                 override = readl(mc->regs + client->regs.sid.override);
  44                 security = readl(mc->regs + client->regs.sid.security);
  45
  46                 dev_dbg(mc->dev, "client %s: override: %x security: %x\n",
  47                         client->name, override, security);
  48         }
  49 }
  50
  51 static int tegra186_mc_probe(struct tegra_mc *mc)
  52 {
  53         struct platform_device *pdev = to_platform_device(mc->dev);
  54         unsigned int i;
  55         char name[8];
  56         int err;
  57
  58         mc->bcast_ch_regs = devm_platform_ioremap_resource_byname(pdev, "broadcast");
  59         if (IS_ERR(mc->bcast_ch_regs)) {
  60                 if (PTR_ERR(mc->bcast_ch_regs) == -EINVAL) {
  61                         dev_warn(&pdev->dev,
  62                                  "Broadcast channel is missing, please update your device-tree\n");
  63                         mc->bcast_ch_regs = NULL;
  64                         goto populate;
  65                 }
  66
  67                 return PTR_ERR(mc->bcast_ch_regs);
  68         }
  69
  70         mc->ch_regs = devm_kcalloc(mc->dev, mc->soc->num_channels, sizeof(*mc->ch_regs),
  71                                    GFP_KERNEL);
  72         if (!mc->ch_regs)
  73                 return -ENOMEM;
  74
  75         for (i = 0; i < mc->soc->num_channels; i++) {
  76                 snprintf(name, sizeof(name), "ch%u", i);
  77
  78                 mc->ch_regs[i] = devm_platform_ioremap_resource_byname(pdev, name);
  79                 if (IS_ERR(mc->ch_regs[i]))
  80                         return PTR_ERR(mc->ch_regs[i]);
  81         }
  82
  83 populate:
  84         err = of_platform_populate(mc->dev->of_node, NULL, NULL, mc->dev);
  85         if (err < 0)
  86                 return err;
  87
  88         tegra186_mc_program_sid(mc);
  89
  90         return 0;
  91 }
  92
  93 static void tegra186_mc_remove(struct tegra_mc *mc)
  94 {
  95         of_platform_depopulate(mc->dev);
  96 }
  97
  98 static int tegra186_mc_resume(struct tegra_mc *mc)
  99 {
 100         tegra186_mc_program_sid(mc);
 101
 102         return 0;
 103 }
 104
 105 #if IS_ENABLED(CONFIG_IOMMU_API)
 106 static void tegra186_mc_client_sid_override(struct tegra_mc *mc,
 107                                             const struct tegra_mc_client *client,
 108                                             unsigned int sid)
 109 {
 110         u32 value, old;
 111
 112         value = readl(mc->regs + client->regs.sid.security);
 113         if ((value & MC_SID_STREAMID_SECURITY_OVERRIDE) == 0) {
 114                 /*
 115                  * If the secure firmware has locked this down the override
 116                  * for this memory client, there's nothing we can do here.
 117                  */
 118                 if (value & MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED)
 119                         return;
 120
 121                 /*
 122                  * Otherwise, try to set the override itself. Typically the
 123                  * secure firmware will never have set this configuration.
 124                  * Instead, it will either have disabled write access to
 125                  * this field, or it will already have set an explicit
 126                  * override itself.
 127                  */
 128                 WARN_ON((value & MC_SID_STREAMID_SECURITY_OVERRIDE) == 0);
 129
 130                 value |= MC_SID_STREAMID_SECURITY_OVERRIDE;
 131                 writel(value, mc->regs + client->regs.sid.security);
 132         }
 133
 134         value = readl(mc->regs + client->regs.sid.override);
 135         old = value & MC_SID_STREAMID_OVERRIDE_MASK;
 136
 137         if (old != sid) {
 138                 dev_dbg(mc->dev, "overriding SID %x for %s with %x\n", old,
 139                         client->name, sid);
 140                 writel(sid, mc->regs + client->regs.sid.override);
 141         }
 142 }
 143 #endif
 144
 145 static int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev)
 146 {
 147 #if IS_ENABLED(CONFIG_IOMMU_API)
 148         struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
 149         struct of_phandle_args args;
 150         unsigned int i, index = 0;
 151
 152         while (!of_parse_phandle_with_args(dev->of_node, "interconnects", "#interconnect-cells",
 153                                            index, &args)) {
 154                 if (args.np == mc->dev->of_node && args.args_count != 0) {
 155                         for (i = 0; i < mc->soc->num_clients; i++) {
 156                                 const struct tegra_mc_client *client = &mc->soc->clients[i];
 157
 158                                 if (client->id == args.args[0]) {
 159                                         u32 sid = fwspec->ids[0] & MC_SID_STREAMID_OVERRIDE_MASK;
 160
 161                                         tegra186_mc_client_sid_override(mc, client, sid);
 162                                 }
 163                         }
 164                 }
 165
 166                 index++;
 167         }
 168 #endif
 169
 170         return 0;
 171 }
 172
 173 const struct tegra_mc_ops tegra186_mc_ops = {
 174         .probe = tegra186_mc_probe,
 175         .remove = tegra186_mc_remove,
 176         .resume = tegra186_mc_resume,
 177         .probe_device = tegra186_mc_probe_device,
 178         .handle_irq = tegra30_mc_handle_irq,
 179 };
 180
 181 #if defined(CONFIG_ARCH_TEGRA_186_SOC)
 182 static const struct tegra_mc_client tegra186_mc_clients[] = {
 183         {
 184                 .id = TEGRA186_MEMORY_CLIENT_PTCR,
 185                 .name = "ptcr",
 186                 .sid = TEGRA186_SID_PASSTHROUGH,
 187                 .regs = {
 188                         .sid = {
 189                                 .override = 0x000,
 190                                 .security = 0x004,
 191                         },
 192                 },
 193         }, {
 194                 .id = TEGRA186_MEMORY_CLIENT_AFIR,
 195                 .name = "afir",
 196                 .sid = TEGRA186_SID_AFI,
 197                 .regs = {
 198                         .sid = {
 199                                 .override = 0x070,
 200                                 .security = 0x074,
 201                         },
 202                 },
 203         }, {
 204                 .id = TEGRA186_MEMORY_CLIENT_HDAR,
 205                 .name = "hdar",
 206                 .sid = TEGRA186_SID_HDA,
 207                 .regs = {
 208                         .sid = {
 209                                 .override = 0x0a8,
 210                                 .security = 0x0ac,
 211                         },
 212                 },
 213         }, {
 214                 .id = TEGRA186_MEMORY_CLIENT_HOST1XDMAR,
 215                 .name = "host1xdmar",
 216                 .sid = TEGRA186_SID_HOST1X,
 217                 .regs = {
 218                         .sid = {
 219                                 .override = 0x0b0,
 220                                 .security = 0x0b4,
 221                         },
 222                 },
 223         }, {
 224                 .id = TEGRA186_MEMORY_CLIENT_NVENCSRD,
 225                 .name = "nvencsrd",
 226                 .sid = TEGRA186_SID_NVENC,
 227                 .regs = {
 228                         .sid = {
 229                                 .override = 0x0e0,
 230                                 .security = 0x0e4,
 231                         },
 232                 },
 233         }, {
 234                 .id = TEGRA186_MEMORY_CLIENT_SATAR,
 235                 .name = "satar",
 236                 .sid = TEGRA186_SID_SATA,
 237                 .regs = {
 238                         .sid = {
 239                                 .override = 0x0f8,
 240                                 .security = 0x0fc,
 241                         },
 242                 },
 243         }, {
 244                 .id = TEGRA186_MEMORY_CLIENT_MPCORER,
 245                 .name = "mpcorer",
 246                 .sid = TEGRA186_SID_PASSTHROUGH,
 247                 .regs = {
 248                         .sid = {
 249                                 .override = 0x138,
 250                                 .security = 0x13c,
 251                         },
 252                 },
 253         }, {
 254                 .id = TEGRA186_MEMORY_CLIENT_NVENCSWR,
 255                 .name = "nvencswr",
 256                 .sid = TEGRA186_SID_NVENC,
 257                 .regs = {
 258                         .sid = {
 259                                 .override = 0x158,
 260                                 .security = 0x15c,
 261                         },
 262                 },
 263         }, {
 264                 .id = TEGRA186_MEMORY_CLIENT_AFIW,
 265                 .name = "afiw",
 266                 .sid = TEGRA186_SID_AFI,
 267                 .regs = {
 268                         .sid = {
 269                                 .override = 0x188,
 270                                 .security = 0x18c,
 271                         },
 272                 },
 273         }, {
 274                 .id = TEGRA186_MEMORY_CLIENT_HDAW,
 275                 .name = "hdaw",
 276                 .sid = TEGRA186_SID_HDA,
 277                 .regs = {
 278                         .sid = {
 279                                 .override = 0x1a8,
 280                                 .security = 0x1ac,
 281                         },
 282                 },
 283         }, {
 284                 .id = TEGRA186_MEMORY_CLIENT_MPCOREW,
 285                 .name = "mpcorew",
 286                 .sid = TEGRA186_SID_PASSTHROUGH,
 287                 .regs = {
 288                         .sid = {
 289                                 .override = 0x1c8,
 290                                 .security = 0x1cc,
 291                         },
 292                 },
 293         }, {
 294                 .id = TEGRA186_MEMORY_CLIENT_SATAW,
 295                 .name = "sataw",
 296                 .sid = TEGRA186_SID_SATA,
 297                 .regs = {
 298                         .sid = {
 299                                 .override = 0x1e8,
 300                                 .security = 0x1ec,
 301                         },
 302                 },
 303         }, {
 304                 .id = TEGRA186_MEMORY_CLIENT_ISPRA,
 305                 .name = "ispra",
 306                 .sid = TEGRA186_SID_ISP,
 307                 .regs = {
 308                         .sid = {
 309                                 .override = 0x220,
 310                                 .security = 0x224,
 311                         },
 312                 },
 313         }, {
 314                 .id = TEGRA186_MEMORY_CLIENT_ISPWA,
 315                 .name = "ispwa",
 316                 .sid = TEGRA186_SID_ISP,
 317                 .regs = {
 318                         .sid = {
 319                                 .override = 0x230,
 320                                 .security = 0x234,
 321                         },
 322                 },
 323         }, {
 324                 .id = TEGRA186_MEMORY_CLIENT_ISPWB,
 325                 .name = "ispwb",
 326                 .sid = TEGRA186_SID_ISP,
 327                 .regs = {
 328                         .sid = {
 329                                 .override = 0x238,
 330                                 .security = 0x23c,
 331                         },
 332                 },
 333         }, {
 334                 .id = TEGRA186_MEMORY_CLIENT_XUSB_HOSTR,
 335                 .name = "xusb_hostr",
 336                 .sid = TEGRA186_SID_XUSB_HOST,
 337                 .regs = {
 338                         .sid = {
 339                                 .override = 0x250,
 340                                 .security = 0x254,
 341                         },
 342                 },
 343         }, {
 344                 .id = TEGRA186_MEMORY_CLIENT_XUSB_HOSTW,
 345                 .name = "xusb_hostw",
 346                 .sid = TEGRA186_SID_XUSB_HOST,
 347                 .regs = {
 348                         .sid = {
 349                                 .override = 0x258,
 350                                 .security = 0x25c,
 351                         },
 352                 },
 353         }, {
 354                 .id = TEGRA186_MEMORY_CLIENT_XUSB_DEVR,
 355                 .name = "xusb_devr",
 356                 .sid = TEGRA186_SID_XUSB_DEV,
 357                 .regs = {
 358                         .sid = {
 359                                 .override = 0x260,
 360                                 .security = 0x264,
 361                         },
 362                 },
 363         }, {
 364                 .id = TEGRA186_MEMORY_CLIENT_XUSB_DEVW,
 365                 .name = "xusb_devw",
 366                 .sid = TEGRA186_SID_XUSB_DEV,
 367                 .regs = {
 368                         .sid = {
 369                                 .override = 0x268,
 370                                 .security = 0x26c,
 371                         },
 372                 },
 373         }, {
 374                 .id = TEGRA186_MEMORY_CLIENT_TSECSRD,
 375                 .name = "tsecsrd",
 376                 .sid = TEGRA186_SID_TSEC,
 377                 .regs = {
 378                         .sid = {
 379                                 .override = 0x2a0,
 380                                 .security = 0x2a4,
 381                         },
 382                 },
 383         }, {
 384                 .id = TEGRA186_MEMORY_CLIENT_TSECSWR,
 385                 .name = "tsecswr",
 386                 .sid = TEGRA186_SID_TSEC,
 387                 .regs = {
 388                         .sid = {
 389                                 .override = 0x2a8,
 390                                 .security = 0x2ac,
 391                         },
 392                 },
 393         }, {
 394                 .id = TEGRA186_MEMORY_CLIENT_GPUSRD,
 395                 .name = "gpusrd",
 396                 .sid = TEGRA186_SID_GPU,
 397                 .regs = {
 398                         .sid = {
 399                                 .override = 0x2c0,
 400                                 .security = 0x2c4,
 401                         },
 402                 },
 403         }, {
 404                 .id = TEGRA186_MEMORY_CLIENT_GPUSWR,
 405                 .name = "gpuswr",
 406                 .sid = TEGRA186_SID_GPU,
 407                 .regs = {
 408                         .sid = {
 409                                 .override = 0x2c8,
 410                                 .security = 0x2cc,
 411                         },
 412                 },
 413         }, {
 414                 .id = TEGRA186_MEMORY_CLIENT_SDMMCRA,
 415                 .name = "sdmmcra",
 416                 .sid = TEGRA186_SID_SDMMC1,
 417                 .regs = {
 418                         .sid = {
 419                                 .override = 0x300,
 420                                 .security = 0x304,
 421                         },
 422                 },
 423         }, {
 424                 .id = TEGRA186_MEMORY_CLIENT_SDMMCRAA,
 425                 .name = "sdmmcraa",
 426                 .sid = TEGRA186_SID_SDMMC2,
 427                 .regs = {
 428                         .sid = {
 429                                 .override = 0x308,
 430                                 .security = 0x30c,
 431                         },
 432                 },
 433         }, {
 434                 .id = TEGRA186_MEMORY_CLIENT_SDMMCR,
 435                 .name = "sdmmcr",
 436                 .sid = TEGRA186_SID_SDMMC3,
 437                 .regs = {
 438                         .sid = {
 439                                 .override = 0x310,
 440                                 .security = 0x314,
 441                         },
 442                 },
 443         }, {
 444                 .id = TEGRA186_MEMORY_CLIENT_SDMMCRAB,
 445                 .name = "sdmmcrab",
 446                 .sid = TEGRA186_SID_SDMMC4,
 447                 .regs = {
 448                         .sid = {
 449                                 .override = 0x318,
 450                                 .security = 0x31c,
 451                         },
 452                 },
 453         }, {
 454                 .id = TEGRA186_MEMORY_CLIENT_SDMMCWA,
 455                 .name = "sdmmcwa",
 456                 .sid = TEGRA186_SID_SDMMC1,
 457                 .regs = {
 458                         .sid = {
 459                                 .override = 0x320,
 460                                 .security = 0x324,
 461                         },
 462                 },
 463         }, {
 464                 .id = TEGRA186_MEMORY_CLIENT_SDMMCWAA,
 465                 .name = "sdmmcwaa",
 466                 .sid = TEGRA186_SID_SDMMC2,
 467                 .regs = {
 468                         .sid = {
 469                                 .override = 0x328,
 470                                 .security = 0x32c,
 471                         },
 472                 },
 473         }, {
 474                 .id = TEGRA186_MEMORY_CLIENT_SDMMCW,
 475                 .name = "sdmmcw",
 476                 .sid = TEGRA186_SID_SDMMC3,
 477                 .regs = {
 478                         .sid = {
 479                                 .override = 0x330,
 480                                 .security = 0x334,
 481                         },
 482                 },
 483         }, {
 484                 .id = TEGRA186_MEMORY_CLIENT_SDMMCWAB,
 485                 .name = "sdmmcwab",
 486                 .sid = TEGRA186_SID_SDMMC4,
 487                 .regs = {
 488                         .sid = {
 489                                 .override = 0x338,
 490                                 .security = 0x33c,
 491                         },
 492                 },
 493         }, {
 494                 .id = TEGRA186_MEMORY_CLIENT_VICSRD,
 495                 .name = "vicsrd",
 496                 .sid = TEGRA186_SID_VIC,
 497                 .regs = {
 498                         .sid = {
 499                                 .override = 0x360,
 500                                 .security = 0x364,
 501                         },
 502                 },
 503         }, {
 504                 .id = TEGRA186_MEMORY_CLIENT_VICSWR,
 505                 .name = "vicswr",
 506                 .sid = TEGRA186_SID_VIC,
 507                 .regs = {
 508                         .sid = {
 509                                 .override = 0x368,
 510                                 .security = 0x36c,
 511                         },
 512                 },
 513         }, {
 514                 .id = TEGRA186_MEMORY_CLIENT_VIW,
 515                 .name = "viw",
 516                 .sid = TEGRA186_SID_VI,
 517                 .regs = {
 518                         .sid = {
 519                                 .override = 0x390,
 520                                 .security = 0x394,
 521                         },
 522                 },
 523         }, {
 524                 .id = TEGRA186_MEMORY_CLIENT_NVDECSRD,
 525                 .name = "nvdecsrd",
 526                 .sid = TEGRA186_SID_NVDEC,
 527                 .regs = {
 528                         .sid = {
 529                                 .override = 0x3c0,
 530                                 .security = 0x3c4,
 531                         },
 532                 },
 533         }, {
 534                 .id = TEGRA186_MEMORY_CLIENT_NVDECSWR,
 535                 .name = "nvdecswr",
 536                 .sid = TEGRA186_SID_NVDEC,
 537                 .regs = {
 538                         .sid = {
 539                                 .override = 0x3c8,
 540                                 .security = 0x3cc,
 541                         },
 542                 },
 543         }, {
 544                 .id = TEGRA186_MEMORY_CLIENT_APER,
 545                 .name = "aper",
 546                 .sid = TEGRA186_SID_APE,
 547                 .regs = {
 548                         .sid = {
 549                                 .override = 0x3d0,
 550                                 .security = 0x3d4,
 551                         },
 552                 },
 553         }, {
 554                 .id = TEGRA186_MEMORY_CLIENT_APEW,
 555                 .name = "apew",
 556                 .sid = TEGRA186_SID_APE,
 557                 .regs = {
 558                         .sid = {
 559                                 .override = 0x3d8,
 560                                 .security = 0x3dc,
 561                         },
 562                 },
 563         }, {
 564                 .id = TEGRA186_MEMORY_CLIENT_NVJPGSRD,
 565                 .name = "nvjpgsrd",
 566                 .sid = TEGRA186_SID_NVJPG,
 567                 .regs = {
 568                         .sid = {
 569                                 .override = 0x3f0,
 570                                 .security = 0x3f4,
 571                         },
 572                 },
 573         }, {
 574                 .id = TEGRA186_MEMORY_CLIENT_NVJPGSWR,
 575                 .name = "nvjpgswr",
 576                 .sid = TEGRA186_SID_NVJPG,
 577                 .regs = {
 578                         .sid = {
 579                                 .override = 0x3f8,
 580                                 .security = 0x3fc,
 581                         },
 582                 },
 583         }, {
 584                 .id = TEGRA186_MEMORY_CLIENT_SESRD,
 585                 .name = "sesrd",
 586                 .sid = TEGRA186_SID_SE,
 587                 .regs = {
 588                         .sid = {
 589                                 .override = 0x400,
 590                                 .security = 0x404,
 591                         },
 592                 },
 593         }, {
 594                 .id = TEGRA186_MEMORY_CLIENT_SESWR,
 595                 .name = "seswr",
 596                 .sid = TEGRA186_SID_SE,
 597                 .regs = {
 598                         .sid = {
 599                                 .override = 0x408,
 600                                 .security = 0x40c,
 601                         },
 602                 },
 603         }, {
 604                 .id = TEGRA186_MEMORY_CLIENT_ETRR,
 605                 .name = "etrr",
 606                 .sid = TEGRA186_SID_ETR,
 607                 .regs = {
 608                         .sid = {
 609                                 .override = 0x420,
 610                                 .security = 0x424,
 611                         },
 612                 },
 613         }, {
 614                 .id = TEGRA186_MEMORY_CLIENT_ETRW,
 615                 .name = "etrw",
 616                 .sid = TEGRA186_SID_ETR,
 617                 .regs = {
 618                         .sid = {
 619                                 .override = 0x428,
 620                                 .security = 0x42c,
 621                         },
 622                 },
 623         }, {
 624                 .id = TEGRA186_MEMORY_CLIENT_TSECSRDB,
 625                 .name = "tsecsrdb",
 626                 .sid = TEGRA186_SID_TSECB,
 627                 .regs = {
 628                         .sid = {
 629                                 .override = 0x430,
 630                                 .security = 0x434,
 631                         },
 632                 },
 633         }, {
 634                 .id = TEGRA186_MEMORY_CLIENT_TSECSWRB,
 635                 .name = "tsecswrb",
 636                 .sid = TEGRA186_SID_TSECB,
 637                 .regs = {
 638                         .sid = {
 639                                 .override = 0x438,
 640                                 .security = 0x43c,
 641                         },
 642                 },
 643         }, {
 644                 .id = TEGRA186_MEMORY_CLIENT_GPUSRD2,
 645                 .name = "gpusrd2",
 646                 .sid = TEGRA186_SID_GPU,
 647                 .regs = {
 648                         .sid = {
 649                                 .override = 0x440,
 650                                 .security = 0x444,
 651                         },
 652                 },
 653         }, {
 654                 .id = TEGRA186_MEMORY_CLIENT_GPUSWR2,
 655                 .name = "gpuswr2",
 656                 .sid = TEGRA186_SID_GPU,
 657                 .regs = {
 658                         .sid = {
 659                                 .override = 0x448,
 660                                 .security = 0x44c,
 661                         },
 662                 },
 663         }, {
 664                 .id = TEGRA186_MEMORY_CLIENT_AXISR,
 665                 .name = "axisr",
 666                 .sid = TEGRA186_SID_GPCDMA_0,
 667                 .regs = {
 668                         .sid = {
 669                                 .override = 0x460,
 670                                 .security = 0x464,
 671                         },
 672                 },
 673         }, {
 674                 .id = TEGRA186_MEMORY_CLIENT_AXISW,
 675                 .name = "axisw",
 676                 .sid = TEGRA186_SID_GPCDMA_0,
 677                 .regs = {
 678                         .sid = {
 679                                 .override = 0x468,
 680                                 .security = 0x46c,
 681                         },
 682                 },
 683         }, {
 684                 .id = TEGRA186_MEMORY_CLIENT_EQOSR,
 685                 .name = "eqosr",
 686                 .sid = TEGRA186_SID_EQOS,
 687                 .regs = {
 688                         .sid = {
 689                                 .override = 0x470,
 690                                 .security = 0x474,
 691                         },
 692                 },
 693         }, {
 694                 .id = TEGRA186_MEMORY_CLIENT_EQOSW,
 695                 .name = "eqosw",
 696                 .sid = TEGRA186_SID_EQOS,
 697                 .regs = {
 698                         .sid = {
 699                                 .override = 0x478,
 700                                 .security = 0x47c,
 701                         },
 702                 },
 703         }, {
 704                 .id = TEGRA186_MEMORY_CLIENT_UFSHCR,
 705                 .name = "ufshcr",
 706                 .sid = TEGRA186_SID_UFSHC,
 707                 .regs = {
 708                         .sid = {
 709                                 .override = 0x480,
 710                                 .security = 0x484,
 711                         },
 712                 },
 713         }, {
 714                 .id = TEGRA186_MEMORY_CLIENT_UFSHCW,
 715                 .name = "ufshcw",
 716                 .sid = TEGRA186_SID_UFSHC,
 717                 .regs = {
 718                         .sid = {
 719                                 .override = 0x488,
 720                                 .security = 0x48c,
 721                         },
 722                 },
 723         }, {
 724                 .id = TEGRA186_MEMORY_CLIENT_NVDISPLAYR,
 725                 .name = "nvdisplayr",
 726                 .sid = TEGRA186_SID_NVDISPLAY,
 727                 .regs = {
 728                         .sid = {
 729                                 .override = 0x490,
 730                                 .security = 0x494,
 731                         },
 732                 },
 733         }, {
 734                 .id = TEGRA186_MEMORY_CLIENT_BPMPR,
 735                 .name = "bpmpr",
 736                 .sid = TEGRA186_SID_BPMP,
 737                 .regs = {
 738                         .sid = {
 739                                 .override = 0x498,
 740                                 .security = 0x49c,
 741                         },
 742                 },
 743         }, {
 744                 .id = TEGRA186_MEMORY_CLIENT_BPMPW,
 745                 .name = "bpmpw",
 746                 .sid = TEGRA186_SID_BPMP,
 747                 .regs = {
 748                         .sid = {
 749                                 .override = 0x4a0,
 750                                 .security = 0x4a4,
 751                         },
 752                 },
 753         }, {
 754                 .id = TEGRA186_MEMORY_CLIENT_BPMPDMAR,
 755                 .name = "bpmpdmar",
 756                 .sid = TEGRA186_SID_BPMP,
 757                 .regs = {
 758                         .sid = {
 759                                 .override = 0x4a8,
 760                                 .security = 0x4ac,
 761                         },
 762                 },
 763         }, {
 764                 .id = TEGRA186_MEMORY_CLIENT_BPMPDMAW,
 765                 .name = "bpmpdmaw",
 766                 .sid = TEGRA186_SID_BPMP,
 767                 .regs = {
 768                         .sid = {
 769                                 .override = 0x4b0,
 770                                 .security = 0x4b4,
 771                         },
 772                 },
 773         }, {
 774                 .id = TEGRA186_MEMORY_CLIENT_AONR,
 775                 .name = "aonr",
 776                 .sid = TEGRA186_SID_AON,
 777                 .regs = {
 778                         .sid = {
 779                                 .override = 0x4b8,
 780                                 .security = 0x4bc,
 781                         },
 782                 },
 783         }, {
 784                 .id = TEGRA186_MEMORY_CLIENT_AONW,
 785                 .name = "aonw",
 786                 .sid = TEGRA186_SID_AON,
 787                 .regs = {
 788                         .sid = {
 789                                 .override = 0x4c0,
 790                                 .security = 0x4c4,
 791                         },
 792                 },
 793         }, {
 794                 .id = TEGRA186_MEMORY_CLIENT_AONDMAR,
 795                 .name = "aondmar",
 796                 .sid = TEGRA186_SID_AON,
 797                 .regs = {
 798                         .sid = {
 799                                 .override = 0x4c8,
 800                                 .security = 0x4cc,
 801                         },
 802                 },
 803         }, {
 804                 .id = TEGRA186_MEMORY_CLIENT_AONDMAW,
 805                 .name = "aondmaw",
 806                 .sid = TEGRA186_SID_AON,
 807                 .regs = {
 808                         .sid = {
 809                                 .override = 0x4d0,
 810                                 .security = 0x4d4,
 811                         },
 812                 },
 813         }, {
 814                 .id = TEGRA186_MEMORY_CLIENT_SCER,
 815                 .name = "scer",
 816                 .sid = TEGRA186_SID_SCE,
 817                 .regs = {
 818                         .sid = {
 819                                 .override = 0x4d8,
 820                                 .security = 0x4dc,
 821                         },
 822                 },
 823         }, {
 824                 .id = TEGRA186_MEMORY_CLIENT_SCEW,
 825                 .name = "scew",
 826                 .sid = TEGRA186_SID_SCE,
 827                 .regs = {
 828                         .sid = {
 829                                 .override = 0x4e0,
 830                                 .security = 0x4e4,
 831                         },
 832                 },
 833         }, {
 834                 .id = TEGRA186_MEMORY_CLIENT_SCEDMAR,
 835                 .name = "scedmar",
 836                 .sid = TEGRA186_SID_SCE,
 837                 .regs = {
 838                         .sid = {
 839                                 .override = 0x4e8,
 840                                 .security = 0x4ec,
 841                         },
 842                 },
 843         }, {
 844                 .id = TEGRA186_MEMORY_CLIENT_SCEDMAW,
 845                 .name = "scedmaw",
 846                 .sid = TEGRA186_SID_SCE,
 847                 .regs = {
 848                         .sid = {
 849                                 .override = 0x4f0,
 850                                 .security = 0x4f4,
 851                         },
 852                 },
 853         }, {
 854                 .id = TEGRA186_MEMORY_CLIENT_APEDMAR,
 855                 .name = "apedmar",
 856                 .sid = TEGRA186_SID_APE,
 857                 .regs = {
 858                         .sid = {
 859                                 .override = 0x4f8,
 860                                 .security = 0x4fc,
 861                         },
 862                 },
 863         }, {
 864                 .id = TEGRA186_MEMORY_CLIENT_APEDMAW,
 865                 .name = "apedmaw",
 866                 .sid = TEGRA186_SID_APE,
 867                 .regs = {
 868                         .sid = {
 869                                 .override = 0x500,
 870                                 .security = 0x504,
 871                         },
 872                 },
 873         }, {
 874                 .id = TEGRA186_MEMORY_CLIENT_NVDISPLAYR1,
 875                 .name = "nvdisplayr1",
 876                 .sid = TEGRA186_SID_NVDISPLAY,
 877                 .regs = {
 878                         .sid = {
 879                                 .override = 0x508,
 880                                 .security = 0x50c,
 881                         },
 882                 },
 883         }, {
 884                 .id = TEGRA186_MEMORY_CLIENT_VICSRD1,
 885                 .name = "vicsrd1",
 886                 .sid = TEGRA186_SID_VIC,
 887                 .regs = {
 888                         .sid = {
 889                                 .override = 0x510,
 890                                 .security = 0x514,
 891                         },
 892                 },
 893         }, {
 894                 .id = TEGRA186_MEMORY_CLIENT_NVDECSRD1,
 895                 .name = "nvdecsrd1",
 896                 .sid = TEGRA186_SID_NVDEC,
 897                 .regs = {
 898                         .sid = {
 899                                 .override = 0x518,
 900                                 .security = 0x51c,
 901                         },
 902                 },
 903         },
 904 };
 905
 906 const struct tegra_mc_soc tegra186_mc_soc = {
 907         .num_clients = ARRAY_SIZE(tegra186_mc_clients),
 908         .clients = tegra186_mc_clients,
 909         .num_address_bits = 40,
 910         .num_channels = 4,
 911         .client_id_mask = 0xff,
 912         .intmask = MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS |
 913                    MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
 914                    MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
 915         .ops = &tegra186_mc_ops,
 916         .ch_intmask = 0x0000000f,
 917         .global_intstatus_channel_shift = 0,
 918 };
 919 #endif