1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
7 #include <linux/of_device.h>
8 #include <linux/slab.h>
10 #include <dt-bindings/memory/tegra124-mc.h>
14 static const struct tegra_mc_client tegra124_mc_clients[] = {
18 .swgroup = TEGRA_SWGROUP_PTC,
30 .swgroup = TEGRA_SWGROUP_DC,
46 .swgroup = TEGRA_SWGROUP_DCB,
62 .swgroup = TEGRA_SWGROUP_DC,
78 .swgroup = TEGRA_SWGROUP_DCB,
94 .swgroup = TEGRA_SWGROUP_DC,
109 .name = "display0cb",
110 .swgroup = TEGRA_SWGROUP_DCB,
126 .swgroup = TEGRA_SWGROUP_AFI,
142 .swgroup = TEGRA_SWGROUP_AVPC,
158 .swgroup = TEGRA_SWGROUP_DC,
173 .name = "displayhcb",
174 .swgroup = TEGRA_SWGROUP_DCB,
190 .swgroup = TEGRA_SWGROUP_HDA,
205 .name = "host1xdmar",
206 .swgroup = TEGRA_SWGROUP_HC,
222 .swgroup = TEGRA_SWGROUP_HC,
238 .swgroup = TEGRA_SWGROUP_MSENC,
253 .name = "ppcsahbdmar",
254 .swgroup = TEGRA_SWGROUP_PPCS,
269 .name = "ppcsahbslvr",
270 .swgroup = TEGRA_SWGROUP_PPCS,
286 .swgroup = TEGRA_SWGROUP_SATA,
302 .swgroup = TEGRA_SWGROUP_VDE,
318 .swgroup = TEGRA_SWGROUP_VDE,
334 .swgroup = TEGRA_SWGROUP_VDE,
350 .swgroup = TEGRA_SWGROUP_VDE,
366 .swgroup = TEGRA_SWGROUP_MPCORELP,
378 .swgroup = TEGRA_SWGROUP_MPCORE,
390 .swgroup = TEGRA_SWGROUP_MSENC,
406 .swgroup = TEGRA_SWGROUP_AFI,
422 .swgroup = TEGRA_SWGROUP_AVPC,
438 .swgroup = TEGRA_SWGROUP_HDA,
454 .swgroup = TEGRA_SWGROUP_HC,
470 .swgroup = TEGRA_SWGROUP_MPCORELP,
482 .swgroup = TEGRA_SWGROUP_MPCORE,
493 .name = "ppcsahbdmaw",
494 .swgroup = TEGRA_SWGROUP_PPCS,
509 .name = "ppcsahbslvw",
510 .swgroup = TEGRA_SWGROUP_PPCS,
526 .swgroup = TEGRA_SWGROUP_SATA,
542 .swgroup = TEGRA_SWGROUP_VDE,
558 .swgroup = TEGRA_SWGROUP_VDE,
574 .swgroup = TEGRA_SWGROUP_VDE,
590 .swgroup = TEGRA_SWGROUP_VDE,
606 .swgroup = TEGRA_SWGROUP_ISP2,
622 .swgroup = TEGRA_SWGROUP_ISP2,
638 .swgroup = TEGRA_SWGROUP_ISP2,
653 .name = "xusb_hostr",
654 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
669 .name = "xusb_hostw",
670 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
686 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
702 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
718 .swgroup = TEGRA_SWGROUP_ISP2B,
734 .swgroup = TEGRA_SWGROUP_ISP2B,
750 .swgroup = TEGRA_SWGROUP_ISP2B,
766 .swgroup = TEGRA_SWGROUP_TSEC,
782 .swgroup = TEGRA_SWGROUP_TSEC,
798 .swgroup = TEGRA_SWGROUP_A9AVP,
814 .swgroup = TEGRA_SWGROUP_A9AVP,
830 .swgroup = TEGRA_SWGROUP_GPU,
847 .swgroup = TEGRA_SWGROUP_GPU,
864 .swgroup = TEGRA_SWGROUP_DC,
880 .swgroup = TEGRA_SWGROUP_SDMMC1A,
896 .swgroup = TEGRA_SWGROUP_SDMMC2A,
912 .swgroup = TEGRA_SWGROUP_SDMMC3A,
927 .swgroup = TEGRA_SWGROUP_SDMMC4A,
944 .swgroup = TEGRA_SWGROUP_SDMMC1A,
960 .swgroup = TEGRA_SWGROUP_SDMMC2A,
976 .swgroup = TEGRA_SWGROUP_SDMMC3A,
992 .swgroup = TEGRA_SWGROUP_SDMMC4A,
1008 .swgroup = TEGRA_SWGROUP_VIC,
1024 .swgroup = TEGRA_SWGROUP_VIC,
1040 .swgroup = TEGRA_SWGROUP_VI,
1056 .swgroup = TEGRA_SWGROUP_DC,
1072 static const struct tegra_smmu_swgroup tegra124_swgroups[] = {
1073 { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
1074 { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
1075 { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
1076 { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
1077 { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
1078 { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
1079 { .name = "msenc", .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 },
1080 { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
1081 { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
1082 { .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
1083 { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
1084 { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
1085 { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
1086 { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
1087 { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
1088 { .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
1089 { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
1090 { .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
1091 { .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
1092 { .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
1093 { .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
1094 { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
1095 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
1098 static const unsigned int tegra124_group_drm[] = {
1104 static const struct tegra_smmu_group_soc tegra124_groups[] = {
1107 .swgroups = tegra124_group_drm,
1108 .num_swgroups = ARRAY_SIZE(tegra124_group_drm),
1112 #define TEGRA124_MC_RESET(_name, _control, _status, _bit) \
1115 .id = TEGRA124_MC_RESET_##_name, \
1116 .control = _control, \
1117 .status = _status, \
1121 static const struct tegra_mc_reset tegra124_mc_resets[] = {
1122 TEGRA124_MC_RESET(AFI, 0x200, 0x204, 0),
1123 TEGRA124_MC_RESET(AVPC, 0x200, 0x204, 1),
1124 TEGRA124_MC_RESET(DC, 0x200, 0x204, 2),
1125 TEGRA124_MC_RESET(DCB, 0x200, 0x204, 3),
1126 TEGRA124_MC_RESET(HC, 0x200, 0x204, 6),
1127 TEGRA124_MC_RESET(HDA, 0x200, 0x204, 7),
1128 TEGRA124_MC_RESET(ISP2, 0x200, 0x204, 8),
1129 TEGRA124_MC_RESET(MPCORE, 0x200, 0x204, 9),
1130 TEGRA124_MC_RESET(MPCORELP, 0x200, 0x204, 10),
1131 TEGRA124_MC_RESET(MSENC, 0x200, 0x204, 11),
1132 TEGRA124_MC_RESET(PPCS, 0x200, 0x204, 14),
1133 TEGRA124_MC_RESET(SATA, 0x200, 0x204, 15),
1134 TEGRA124_MC_RESET(VDE, 0x200, 0x204, 16),
1135 TEGRA124_MC_RESET(VI, 0x200, 0x204, 17),
1136 TEGRA124_MC_RESET(VIC, 0x200, 0x204, 18),
1137 TEGRA124_MC_RESET(XUSB_HOST, 0x200, 0x204, 19),
1138 TEGRA124_MC_RESET(XUSB_DEV, 0x200, 0x204, 20),
1139 TEGRA124_MC_RESET(TSEC, 0x200, 0x204, 21),
1140 TEGRA124_MC_RESET(SDMMC1, 0x200, 0x204, 22),
1141 TEGRA124_MC_RESET(SDMMC2, 0x200, 0x204, 23),
1142 TEGRA124_MC_RESET(SDMMC3, 0x200, 0x204, 25),
1143 TEGRA124_MC_RESET(SDMMC4, 0x970, 0x974, 0),
1144 TEGRA124_MC_RESET(ISP2B, 0x970, 0x974, 1),
1145 TEGRA124_MC_RESET(GPU, 0x970, 0x974, 2),
1148 static int tegra124_mc_icc_set(struct icc_node *src, struct icc_node *dst)
1150 /* TODO: program PTSA */
1154 static int tegra124_mc_icc_aggreate(struct icc_node *node, u32 tag, u32 avg_bw,
1155 u32 peak_bw, u32 *agg_avg, u32 *agg_peak)
1158 * ISO clients need to reserve extra bandwidth up-front because
1159 * there could be high bandwidth pressure during initial filling
1160 * of the client's FIFO buffers. Secondly, we need to take into
1161 * account impurities of the memory subsystem.
1163 if (tag & TEGRA_MC_ICC_TAG_ISO)
1164 peak_bw = tegra_mc_scale_percents(peak_bw, 400);
1167 *agg_peak = max(*agg_peak, peak_bw);
1172 static struct icc_node_data *
1173 tegra124_mc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data)
1175 struct tegra_mc *mc = icc_provider_to_tegra_mc(data);
1176 const struct tegra_mc_client *client;
1177 unsigned int i, idx = spec->args[0];
1178 struct icc_node_data *ndata;
1179 struct icc_node *node;
1181 list_for_each_entry(node, &mc->provider.nodes, node_list) {
1182 if (node->id != idx)
1185 ndata = kzalloc(sizeof(*ndata), GFP_KERNEL);
1187 return ERR_PTR(-ENOMEM);
1189 client = &mc->soc->clients[idx];
1192 switch (client->swgroup) {
1193 case TEGRA_SWGROUP_DC:
1194 case TEGRA_SWGROUP_DCB:
1195 case TEGRA_SWGROUP_PTC:
1196 case TEGRA_SWGROUP_VI:
1197 /* these clients are isochronous by default */
1198 ndata->tag = TEGRA_MC_ICC_TAG_ISO;
1202 ndata->tag = TEGRA_MC_ICC_TAG_DEFAULT;
1209 for (i = 0; i < mc->soc->num_clients; i++) {
1210 if (mc->soc->clients[i].id == idx)
1211 return ERR_PTR(-EPROBE_DEFER);
1214 dev_err(mc->dev, "invalid ICC client ID %u\n", idx);
1216 return ERR_PTR(-EINVAL);
1219 static const struct tegra_mc_icc_ops tegra124_mc_icc_ops = {
1220 .xlate_extended = tegra124_mc_of_icc_xlate_extended,
1221 .aggregate = tegra124_mc_icc_aggreate,
1222 .set = tegra124_mc_icc_set,
1225 #ifdef CONFIG_ARCH_TEGRA_124_SOC
1226 static const unsigned long tegra124_mc_emem_regs[] = {
1228 MC_EMEM_ARB_OUTSTANDING_REQ,
1229 MC_EMEM_ARB_TIMING_RCD,
1230 MC_EMEM_ARB_TIMING_RP,
1231 MC_EMEM_ARB_TIMING_RC,
1232 MC_EMEM_ARB_TIMING_RAS,
1233 MC_EMEM_ARB_TIMING_FAW,
1234 MC_EMEM_ARB_TIMING_RRD,
1235 MC_EMEM_ARB_TIMING_RAP2PRE,
1236 MC_EMEM_ARB_TIMING_WAP2PRE,
1237 MC_EMEM_ARB_TIMING_R2R,
1238 MC_EMEM_ARB_TIMING_W2W,
1239 MC_EMEM_ARB_TIMING_R2W,
1240 MC_EMEM_ARB_TIMING_W2R,
1241 MC_EMEM_ARB_DA_TURNS,
1242 MC_EMEM_ARB_DA_COVERS,
1245 MC_EMEM_ARB_RING1_THROTTLE
1248 static const struct tegra_smmu_soc tegra124_smmu_soc = {
1249 .clients = tegra124_mc_clients,
1250 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1251 .swgroups = tegra124_swgroups,
1252 .num_swgroups = ARRAY_SIZE(tegra124_swgroups),
1253 .groups = tegra124_groups,
1254 .num_groups = ARRAY_SIZE(tegra124_groups),
1255 .supports_round_robin_arbitration = true,
1256 .supports_request_limit = true,
1257 .num_tlb_lines = 32,
1261 const struct tegra_mc_soc tegra124_mc_soc = {
1262 .clients = tegra124_mc_clients,
1263 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1264 .num_address_bits = 34,
1266 .client_id_mask = 0x7f,
1267 .smmu = &tegra124_smmu_soc,
1268 .emem_regs = tegra124_mc_emem_regs,
1269 .num_emem_regs = ARRAY_SIZE(tegra124_mc_emem_regs),
1270 .intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1271 MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1272 MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1273 .reset_ops = &tegra_mc_reset_ops_common,
1274 .resets = tegra124_mc_resets,
1275 .num_resets = ARRAY_SIZE(tegra124_mc_resets),
1276 .icc_ops = &tegra124_mc_icc_ops,
1277 .ops = &tegra30_mc_ops,
1279 #endif /* CONFIG_ARCH_TEGRA_124_SOC */
1281 #ifdef CONFIG_ARCH_TEGRA_132_SOC
1282 static const struct tegra_smmu_soc tegra132_smmu_soc = {
1283 .clients = tegra124_mc_clients,
1284 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1285 .swgroups = tegra124_swgroups,
1286 .num_swgroups = ARRAY_SIZE(tegra124_swgroups),
1287 .groups = tegra124_groups,
1288 .num_groups = ARRAY_SIZE(tegra124_groups),
1289 .supports_round_robin_arbitration = true,
1290 .supports_request_limit = true,
1291 .num_tlb_lines = 32,
1295 const struct tegra_mc_soc tegra132_mc_soc = {
1296 .clients = tegra124_mc_clients,
1297 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1298 .num_address_bits = 34,
1300 .client_id_mask = 0x7f,
1301 .smmu = &tegra132_smmu_soc,
1302 .intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1303 MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1304 MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1305 .reset_ops = &tegra_mc_reset_ops_common,
1306 .resets = tegra124_mc_resets,
1307 .num_resets = ARRAY_SIZE(tegra124_mc_resets),
1308 .icc_ops = &tegra124_mc_icc_ops,
1309 .ops = &tegra30_mc_ops,
1311 #endif /* CONFIG_ARCH_TEGRA_132_SOC */