1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
9 #include <dt-bindings/memory/tegra124-mc.h>
13 #define MC_EMEM_ARB_CFG 0x90
14 #define MC_EMEM_ARB_OUTSTANDING_REQ 0x94
15 #define MC_EMEM_ARB_TIMING_RCD 0x98
16 #define MC_EMEM_ARB_TIMING_RP 0x9c
17 #define MC_EMEM_ARB_TIMING_RC 0xa0
18 #define MC_EMEM_ARB_TIMING_RAS 0xa4
19 #define MC_EMEM_ARB_TIMING_FAW 0xa8
20 #define MC_EMEM_ARB_TIMING_RRD 0xac
21 #define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0
22 #define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4
23 #define MC_EMEM_ARB_TIMING_R2R 0xb8
24 #define MC_EMEM_ARB_TIMING_W2W 0xbc
25 #define MC_EMEM_ARB_TIMING_R2W 0xc0
26 #define MC_EMEM_ARB_TIMING_W2R 0xc4
27 #define MC_EMEM_ARB_DA_TURNS 0xd0
28 #define MC_EMEM_ARB_DA_COVERS 0xd4
29 #define MC_EMEM_ARB_MISC0 0xd8
30 #define MC_EMEM_ARB_MISC1 0xdc
31 #define MC_EMEM_ARB_RING1_THROTTLE 0xe0
33 static const unsigned long tegra124_mc_emem_regs[] = {
35 MC_EMEM_ARB_OUTSTANDING_REQ,
36 MC_EMEM_ARB_TIMING_RCD,
37 MC_EMEM_ARB_TIMING_RP,
38 MC_EMEM_ARB_TIMING_RC,
39 MC_EMEM_ARB_TIMING_RAS,
40 MC_EMEM_ARB_TIMING_FAW,
41 MC_EMEM_ARB_TIMING_RRD,
42 MC_EMEM_ARB_TIMING_RAP2PRE,
43 MC_EMEM_ARB_TIMING_WAP2PRE,
44 MC_EMEM_ARB_TIMING_R2R,
45 MC_EMEM_ARB_TIMING_W2W,
46 MC_EMEM_ARB_TIMING_R2W,
47 MC_EMEM_ARB_TIMING_W2R,
49 MC_EMEM_ARB_DA_COVERS,
52 MC_EMEM_ARB_RING1_THROTTLE
55 static const struct tegra_mc_client tegra124_mc_clients[] = {
59 .swgroup = TEGRA_SWGROUP_PTC,
63 .swgroup = TEGRA_SWGROUP_DC,
77 .swgroup = TEGRA_SWGROUP_DCB,
91 .swgroup = TEGRA_SWGROUP_DC,
104 .name = "display0bb",
105 .swgroup = TEGRA_SWGROUP_DCB,
119 .swgroup = TEGRA_SWGROUP_DC,
132 .name = "display0cb",
133 .swgroup = TEGRA_SWGROUP_DCB,
147 .swgroup = TEGRA_SWGROUP_AFI,
161 .swgroup = TEGRA_SWGROUP_AVPC,
175 .swgroup = TEGRA_SWGROUP_DC,
188 .name = "displayhcb",
189 .swgroup = TEGRA_SWGROUP_DCB,
203 .swgroup = TEGRA_SWGROUP_HDA,
216 .name = "host1xdmar",
217 .swgroup = TEGRA_SWGROUP_HC,
231 .swgroup = TEGRA_SWGROUP_HC,
245 .swgroup = TEGRA_SWGROUP_MSENC,
258 .name = "ppcsahbdmar",
259 .swgroup = TEGRA_SWGROUP_PPCS,
272 .name = "ppcsahbslvr",
273 .swgroup = TEGRA_SWGROUP_PPCS,
287 .swgroup = TEGRA_SWGROUP_SATA,
301 .swgroup = TEGRA_SWGROUP_VDE,
315 .swgroup = TEGRA_SWGROUP_VDE,
329 .swgroup = TEGRA_SWGROUP_VDE,
343 .swgroup = TEGRA_SWGROUP_VDE,
357 .swgroup = TEGRA_SWGROUP_MPCORELP,
367 .swgroup = TEGRA_SWGROUP_MPCORE,
377 .swgroup = TEGRA_SWGROUP_MSENC,
391 .swgroup = TEGRA_SWGROUP_AFI,
405 .swgroup = TEGRA_SWGROUP_AVPC,
419 .swgroup = TEGRA_SWGROUP_HDA,
433 .swgroup = TEGRA_SWGROUP_HC,
447 .swgroup = TEGRA_SWGROUP_MPCORELP,
457 .swgroup = TEGRA_SWGROUP_MPCORE,
466 .name = "ppcsahbdmaw",
467 .swgroup = TEGRA_SWGROUP_PPCS,
480 .name = "ppcsahbslvw",
481 .swgroup = TEGRA_SWGROUP_PPCS,
495 .swgroup = TEGRA_SWGROUP_SATA,
509 .swgroup = TEGRA_SWGROUP_VDE,
523 .swgroup = TEGRA_SWGROUP_VDE,
537 .swgroup = TEGRA_SWGROUP_VDE,
551 .swgroup = TEGRA_SWGROUP_VDE,
565 .swgroup = TEGRA_SWGROUP_ISP2,
579 .swgroup = TEGRA_SWGROUP_ISP2,
593 .swgroup = TEGRA_SWGROUP_ISP2,
606 .name = "xusb_hostr",
607 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
620 .name = "xusb_hostw",
621 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
635 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
649 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
663 .swgroup = TEGRA_SWGROUP_ISP2B,
677 .swgroup = TEGRA_SWGROUP_ISP2B,
691 .swgroup = TEGRA_SWGROUP_ISP2B,
705 .swgroup = TEGRA_SWGROUP_TSEC,
719 .swgroup = TEGRA_SWGROUP_TSEC,
733 .swgroup = TEGRA_SWGROUP_A9AVP,
747 .swgroup = TEGRA_SWGROUP_A9AVP,
761 .swgroup = TEGRA_SWGROUP_GPU,
776 .swgroup = TEGRA_SWGROUP_GPU,
791 .swgroup = TEGRA_SWGROUP_DC,
805 .swgroup = TEGRA_SWGROUP_SDMMC1A,
819 .swgroup = TEGRA_SWGROUP_SDMMC2A,
833 .swgroup = TEGRA_SWGROUP_SDMMC3A,
846 .swgroup = TEGRA_SWGROUP_SDMMC4A,
861 .swgroup = TEGRA_SWGROUP_SDMMC1A,
875 .swgroup = TEGRA_SWGROUP_SDMMC2A,
889 .swgroup = TEGRA_SWGROUP_SDMMC3A,
903 .swgroup = TEGRA_SWGROUP_SDMMC4A,
917 .swgroup = TEGRA_SWGROUP_VIC,
931 .swgroup = TEGRA_SWGROUP_VIC,
945 .swgroup = TEGRA_SWGROUP_VI,
959 .swgroup = TEGRA_SWGROUP_DC,
973 static const struct tegra_smmu_swgroup tegra124_swgroups[] = {
974 { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
975 { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
976 { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
977 { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
978 { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
979 { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
980 { .name = "msenc", .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 },
981 { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
982 { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
983 { .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
984 { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
985 { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
986 { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
987 { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
988 { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
989 { .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
990 { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
991 { .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
992 { .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
993 { .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
994 { .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
995 { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
996 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
999 static const unsigned int tegra124_group_display[] = {
1004 static const struct tegra_smmu_group_soc tegra124_groups[] = {
1007 .swgroups = tegra124_group_display,
1008 .num_swgroups = ARRAY_SIZE(tegra124_group_display),
1012 #define TEGRA124_MC_RESET(_name, _control, _status, _bit) \
1015 .id = TEGRA124_MC_RESET_##_name, \
1016 .control = _control, \
1017 .status = _status, \
1021 static const struct tegra_mc_reset tegra124_mc_resets[] = {
1022 TEGRA124_MC_RESET(AFI, 0x200, 0x204, 0),
1023 TEGRA124_MC_RESET(AVPC, 0x200, 0x204, 1),
1024 TEGRA124_MC_RESET(DC, 0x200, 0x204, 2),
1025 TEGRA124_MC_RESET(DCB, 0x200, 0x204, 3),
1026 TEGRA124_MC_RESET(HC, 0x200, 0x204, 6),
1027 TEGRA124_MC_RESET(HDA, 0x200, 0x204, 7),
1028 TEGRA124_MC_RESET(ISP2, 0x200, 0x204, 8),
1029 TEGRA124_MC_RESET(MPCORE, 0x200, 0x204, 9),
1030 TEGRA124_MC_RESET(MPCORELP, 0x200, 0x204, 10),
1031 TEGRA124_MC_RESET(MSENC, 0x200, 0x204, 11),
1032 TEGRA124_MC_RESET(PPCS, 0x200, 0x204, 14),
1033 TEGRA124_MC_RESET(SATA, 0x200, 0x204, 15),
1034 TEGRA124_MC_RESET(VDE, 0x200, 0x204, 16),
1035 TEGRA124_MC_RESET(VI, 0x200, 0x204, 17),
1036 TEGRA124_MC_RESET(VIC, 0x200, 0x204, 18),
1037 TEGRA124_MC_RESET(XUSB_HOST, 0x200, 0x204, 19),
1038 TEGRA124_MC_RESET(XUSB_DEV, 0x200, 0x204, 20),
1039 TEGRA124_MC_RESET(TSEC, 0x200, 0x204, 21),
1040 TEGRA124_MC_RESET(SDMMC1, 0x200, 0x204, 22),
1041 TEGRA124_MC_RESET(SDMMC2, 0x200, 0x204, 23),
1042 TEGRA124_MC_RESET(SDMMC3, 0x200, 0x204, 25),
1043 TEGRA124_MC_RESET(SDMMC4, 0x970, 0x974, 0),
1044 TEGRA124_MC_RESET(ISP2B, 0x970, 0x974, 1),
1045 TEGRA124_MC_RESET(GPU, 0x970, 0x974, 2),
1048 #ifdef CONFIG_ARCH_TEGRA_124_SOC
1049 static const struct tegra_smmu_soc tegra124_smmu_soc = {
1050 .clients = tegra124_mc_clients,
1051 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1052 .swgroups = tegra124_swgroups,
1053 .num_swgroups = ARRAY_SIZE(tegra124_swgroups),
1054 .groups = tegra124_groups,
1055 .num_groups = ARRAY_SIZE(tegra124_groups),
1056 .supports_round_robin_arbitration = true,
1057 .supports_request_limit = true,
1058 .num_tlb_lines = 32,
1062 const struct tegra_mc_soc tegra124_mc_soc = {
1063 .clients = tegra124_mc_clients,
1064 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1065 .num_address_bits = 34,
1067 .client_id_mask = 0x7f,
1068 .smmu = &tegra124_smmu_soc,
1069 .emem_regs = tegra124_mc_emem_regs,
1070 .num_emem_regs = ARRAY_SIZE(tegra124_mc_emem_regs),
1071 .intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1072 MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1073 MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1074 .reset_ops = &tegra_mc_reset_ops_common,
1075 .resets = tegra124_mc_resets,
1076 .num_resets = ARRAY_SIZE(tegra124_mc_resets),
1078 #endif /* CONFIG_ARCH_TEGRA_124_SOC */
1080 #ifdef CONFIG_ARCH_TEGRA_132_SOC
1081 static const struct tegra_smmu_soc tegra132_smmu_soc = {
1082 .clients = tegra124_mc_clients,
1083 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1084 .swgroups = tegra124_swgroups,
1085 .num_swgroups = ARRAY_SIZE(tegra124_swgroups),
1086 .groups = tegra124_groups,
1087 .num_groups = ARRAY_SIZE(tegra124_groups),
1088 .supports_round_robin_arbitration = true,
1089 .supports_request_limit = true,
1090 .num_tlb_lines = 32,
1094 const struct tegra_mc_soc tegra132_mc_soc = {
1095 .clients = tegra124_mc_clients,
1096 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1097 .num_address_bits = 34,
1099 .client_id_mask = 0x7f,
1100 .smmu = &tegra132_smmu_soc,
1101 .intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1102 MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1103 MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1104 .reset_ops = &tegra_mc_reset_ops_common,
1105 .resets = tegra124_mc_resets,
1106 .num_resets = ARRAY_SIZE(tegra124_mc_resets),
1108 #endif /* CONFIG_ARCH_TEGRA_132_SOC */