drivers/memory/emif.h

   1 /*
   2  * Defines for the EMIF driver
   3  *
   4  * Copyright (C) 2012 Texas Instruments, Inc.
   5  *
   6  * Benoit Cousson (b-cousson@ti.com)
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12 #ifndef __EMIF_H
  13 #define __EMIF_H
  14
  15 /*
  16  * Maximum number of different frequencies supported by EMIF driver
  17  * Determines the number of entries in the pointer array for register
  18  * cache
  19  */
  20 #define EMIF_MAX_NUM_FREQUENCIES                        6
  21
  22 /* Registers offset */
  23 #define EMIF_MODULE_ID_AND_REVISION                     0x0000
  24 #define EMIF_STATUS                                     0x0004
  25 #define EMIF_SDRAM_CONFIG                               0x0008
  26 #define EMIF_SDRAM_CONFIG_2                             0x000c
  27 #define EMIF_SDRAM_REFRESH_CONTROL                      0x0010
  28 #define EMIF_SDRAM_REFRESH_CTRL_SHDW                    0x0014
  29 #define EMIF_SDRAM_TIMING_1                             0x0018
  30 #define EMIF_SDRAM_TIMING_1_SHDW                        0x001c
  31 #define EMIF_SDRAM_TIMING_2                             0x0020
  32 #define EMIF_SDRAM_TIMING_2_SHDW                        0x0024
  33 #define EMIF_SDRAM_TIMING_3                             0x0028
  34 #define EMIF_SDRAM_TIMING_3_SHDW                        0x002c
  35 #define EMIF_LPDDR2_NVM_TIMING                          0x0030
  36 #define EMIF_LPDDR2_NVM_TIMING_SHDW                     0x0034
  37 #define EMIF_POWER_MANAGEMENT_CONTROL                   0x0038
  38 #define EMIF_POWER_MANAGEMENT_CTRL_SHDW                 0x003c
  39 #define EMIF_LPDDR2_MODE_REG_DATA                       0x0040
  40 #define EMIF_LPDDR2_MODE_REG_CONFIG                     0x0050
  41 #define EMIF_OCP_CONFIG                                 0x0054
  42 #define EMIF_OCP_CONFIG_VALUE_1                         0x0058
  43 #define EMIF_OCP_CONFIG_VALUE_2                         0x005c
  44 #define EMIF_IODFT_TEST_LOGIC_GLOBAL_CONTROL            0x0060
  45 #define EMIF_IODFT_TEST_LOGIC_CTRL_MISR_RESULT          0x0064
  46 #define EMIF_IODFT_TEST_LOGIC_ADDRESS_MISR_RESULT       0x0068
  47 #define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_1        0x006c
  48 #define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_2        0x0070
  49 #define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_3        0x0074
  50 #define EMIF_PERFORMANCE_COUNTER_1                      0x0080
  51 #define EMIF_PERFORMANCE_COUNTER_2                      0x0084
  52 #define EMIF_PERFORMANCE_COUNTER_CONFIG                 0x0088
  53 #define EMIF_PERFORMANCE_COUNTER_MASTER_REGION_SELECT   0x008c
  54 #define EMIF_PERFORMANCE_COUNTER_TIME                   0x0090
  55 #define EMIF_MISC_REG                                   0x0094
  56 #define EMIF_DLL_CALIB_CTRL                             0x0098
  57 #define EMIF_DLL_CALIB_CTRL_SHDW                        0x009c
  58 #define EMIF_END_OF_INTERRUPT                           0x00a0
  59 #define EMIF_SYSTEM_OCP_INTERRUPT_RAW_STATUS            0x00a4
  60 #define EMIF_LL_OCP_INTERRUPT_RAW_STATUS                0x00a8
  61 #define EMIF_SYSTEM_OCP_INTERRUPT_STATUS                0x00ac
  62 #define EMIF_LL_OCP_INTERRUPT_STATUS                    0x00b0
  63 #define EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET            0x00b4
  64 #define EMIF_LL_OCP_INTERRUPT_ENABLE_SET                0x00b8
  65 #define EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR          0x00bc
  66 #define EMIF_LL_OCP_INTERRUPT_ENABLE_CLEAR              0x00c0
  67 #define EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG  0x00c8
  68 #define EMIF_TEMPERATURE_ALERT_CONFIG                   0x00cc
  69 #define EMIF_OCP_ERROR_LOG                              0x00d0
  70 #define EMIF_READ_WRITE_LEVELING_RAMP_WINDOW            0x00d4
  71 #define EMIF_READ_WRITE_LEVELING_RAMP_CONTROL           0x00d8
  72 #define EMIF_READ_WRITE_LEVELING_CONTROL                0x00dc
  73 #define EMIF_DDR_PHY_CTRL_1                             0x00e4
  74 #define EMIF_DDR_PHY_CTRL_1_SHDW                        0x00e8
  75 #define EMIF_DDR_PHY_CTRL_2                             0x00ec
  76 #define EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING       0x0100
  77 #define EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING 0x0104
  78 #define EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING 0x0108
  79 #define EMIF_READ_WRITE_EXECUTION_THRESHOLD             0x0120
  80 #define EMIF_COS_CONFIG                                 0x0124
  81 #define EMIF_PHY_STATUS_1                               0x0140
  82 #define EMIF_PHY_STATUS_2                               0x0144
  83 #define EMIF_PHY_STATUS_3                               0x0148
  84 #define EMIF_PHY_STATUS_4                               0x014c
  85 #define EMIF_PHY_STATUS_5                               0x0150
  86 #define EMIF_PHY_STATUS_6                               0x0154
  87 #define EMIF_PHY_STATUS_7                               0x0158
  88 #define EMIF_PHY_STATUS_8                               0x015c
  89 #define EMIF_PHY_STATUS_9                               0x0160
  90 #define EMIF_PHY_STATUS_10                              0x0164
  91 #define EMIF_PHY_STATUS_11                              0x0168
  92 #define EMIF_PHY_STATUS_12                              0x016c
  93 #define EMIF_PHY_STATUS_13                              0x0170
  94 #define EMIF_PHY_STATUS_14                              0x0174
  95 #define EMIF_PHY_STATUS_15                              0x0178
  96 #define EMIF_PHY_STATUS_16                              0x017c
  97 #define EMIF_PHY_STATUS_17                              0x0180
  98 #define EMIF_PHY_STATUS_18                              0x0184
  99 #define EMIF_PHY_STATUS_19                              0x0188
 100 #define EMIF_PHY_STATUS_20                              0x018c
 101 #define EMIF_PHY_STATUS_21                              0x0190
 102 #define EMIF_EXT_PHY_CTRL_1                             0x0200
 103 #define EMIF_EXT_PHY_CTRL_1_SHDW                        0x0204
 104 #define EMIF_EXT_PHY_CTRL_2                             0x0208
 105 #define EMIF_EXT_PHY_CTRL_2_SHDW                        0x020c
 106 #define EMIF_EXT_PHY_CTRL_3                             0x0210
 107 #define EMIF_EXT_PHY_CTRL_3_SHDW                        0x0214
 108 #define EMIF_EXT_PHY_CTRL_4                             0x0218
 109 #define EMIF_EXT_PHY_CTRL_4_SHDW                        0x021c
 110 #define EMIF_EXT_PHY_CTRL_5                             0x0220
 111 #define EMIF_EXT_PHY_CTRL_5_SHDW                        0x0224
 112 #define EMIF_EXT_PHY_CTRL_6                             0x0228
 113 #define EMIF_EXT_PHY_CTRL_6_SHDW                        0x022c
 114 #define EMIF_EXT_PHY_CTRL_7                             0x0230
 115 #define EMIF_EXT_PHY_CTRL_7_SHDW                        0x0234
 116 #define EMIF_EXT_PHY_CTRL_8                             0x0238
 117 #define EMIF_EXT_PHY_CTRL_8_SHDW                        0x023c
 118 #define EMIF_EXT_PHY_CTRL_9                             0x0240
 119 #define EMIF_EXT_PHY_CTRL_9_SHDW                        0x0244
 120 #define EMIF_EXT_PHY_CTRL_10                            0x0248
 121 #define EMIF_EXT_PHY_CTRL_10_SHDW                       0x024c
 122 #define EMIF_EXT_PHY_CTRL_11                            0x0250
 123 #define EMIF_EXT_PHY_CTRL_11_SHDW                       0x0254
 124 #define EMIF_EXT_PHY_CTRL_12                            0x0258
 125 #define EMIF_EXT_PHY_CTRL_12_SHDW                       0x025c
 126 #define EMIF_EXT_PHY_CTRL_13                            0x0260
 127 #define EMIF_EXT_PHY_CTRL_13_SHDW                       0x0264
 128 #define EMIF_EXT_PHY_CTRL_14                            0x0268
 129 #define EMIF_EXT_PHY_CTRL_14_SHDW                       0x026c
 130 #define EMIF_EXT_PHY_CTRL_15                            0x0270
 131 #define EMIF_EXT_PHY_CTRL_15_SHDW                       0x0274
 132 #define EMIF_EXT_PHY_CTRL_16                            0x0278
 133 #define EMIF_EXT_PHY_CTRL_16_SHDW                       0x027c
 134 #define EMIF_EXT_PHY_CTRL_17                            0x0280
 135 #define EMIF_EXT_PHY_CTRL_17_SHDW                       0x0284
 136 #define EMIF_EXT_PHY_CTRL_18                            0x0288
 137 #define EMIF_EXT_PHY_CTRL_18_SHDW                       0x028c
 138 #define EMIF_EXT_PHY_CTRL_19                            0x0290
 139 #define EMIF_EXT_PHY_CTRL_19_SHDW                       0x0294
 140 #define EMIF_EXT_PHY_CTRL_20                            0x0298
 141 #define EMIF_EXT_PHY_CTRL_20_SHDW                       0x029c
 142 #define EMIF_EXT_PHY_CTRL_21                            0x02a0
 143 #define EMIF_EXT_PHY_CTRL_21_SHDW                       0x02a4
 144 #define EMIF_EXT_PHY_CTRL_22                            0x02a8
 145 #define EMIF_EXT_PHY_CTRL_22_SHDW                       0x02ac
 146 #define EMIF_EXT_PHY_CTRL_23                            0x02b0
 147 #define EMIF_EXT_PHY_CTRL_23_SHDW                       0x02b4
 148 #define EMIF_EXT_PHY_CTRL_24                            0x02b8
 149 #define EMIF_EXT_PHY_CTRL_24_SHDW                       0x02bc
 150 #define EMIF_EXT_PHY_CTRL_25                            0x02c0
 151 #define EMIF_EXT_PHY_CTRL_25_SHDW                       0x02c4
 152 #define EMIF_EXT_PHY_CTRL_26                            0x02c8
 153 #define EMIF_EXT_PHY_CTRL_26_SHDW                       0x02cc
 154 #define EMIF_EXT_PHY_CTRL_27                            0x02d0
 155 #define EMIF_EXT_PHY_CTRL_27_SHDW                       0x02d4
 156 #define EMIF_EXT_PHY_CTRL_28                            0x02d8
 157 #define EMIF_EXT_PHY_CTRL_28_SHDW                       0x02dc
 158 #define EMIF_EXT_PHY_CTRL_29                            0x02e0
 159 #define EMIF_EXT_PHY_CTRL_29_SHDW                       0x02e4
 160 #define EMIF_EXT_PHY_CTRL_30                            0x02e8
 161 #define EMIF_EXT_PHY_CTRL_30_SHDW                       0x02ec
 162
 163 /* Registers shifts and masks */
 164
 165 /* EMIF_MODULE_ID_AND_REVISION */
 166 #define SCHEME_SHIFT                                    30
 167 #define SCHEME_MASK                                     (0x3 << 30)
 168 #define MODULE_ID_SHIFT                                 16
 169 #define MODULE_ID_MASK                                  (0xfff << 16)
 170 #define RTL_VERSION_SHIFT                               11
 171 #define RTL_VERSION_MASK                                (0x1f << 11)
 172 #define MAJOR_REVISION_SHIFT                            8
 173 #define MAJOR_REVISION_MASK                             (0x7 << 8)
 174 #define MINOR_REVISION_SHIFT                            0
 175 #define MINOR_REVISION_MASK                             (0x3f << 0)
 176
 177 /* STATUS */
 178 #define BE_SHIFT                                        31
 179 #define BE_MASK                                         (1 << 31)
 180 #define DUAL_CLK_MODE_SHIFT                             30
 181 #define DUAL_CLK_MODE_MASK                              (1 << 30)
 182 #define FAST_INIT_SHIFT                                 29
 183 #define FAST_INIT_MASK                                  (1 << 29)
 184 #define RDLVLGATETO_SHIFT                               6
 185 #define RDLVLGATETO_MASK                                (1 << 6)
 186 #define RDLVLTO_SHIFT                                   5
 187 #define RDLVLTO_MASK                                    (1 << 5)
 188 #define WRLVLTO_SHIFT                                   4
 189 #define WRLVLTO_MASK                                    (1 << 4)
 190 #define PHY_DLL_READY_SHIFT                             2
 191 #define PHY_DLL_READY_MASK                              (1 << 2)
 192
 193 /* SDRAM_CONFIG */
 194 #define SDRAM_TYPE_SHIFT                                29
 195 #define SDRAM_TYPE_MASK                                 (0x7 << 29)
 196 #define IBANK_POS_SHIFT                                 27
 197 #define IBANK_POS_MASK                                  (0x3 << 27)
 198 #define DDR_TERM_SHIFT                                  24
 199 #define DDR_TERM_MASK                                   (0x7 << 24)
 200 #define DDR2_DDQS_SHIFT                                 23
 201 #define DDR2_DDQS_MASK                                  (1 << 23)
 202 #define DYN_ODT_SHIFT                                   21
 203 #define DYN_ODT_MASK                                    (0x3 << 21)
 204 #define DDR_DISABLE_DLL_SHIFT                           20
 205 #define DDR_DISABLE_DLL_MASK                            (1 << 20)
 206 #define SDRAM_DRIVE_SHIFT                               18
 207 #define SDRAM_DRIVE_MASK                                (0x3 << 18)
 208 #define CWL_SHIFT                                       16
 209 #define CWL_MASK                                        (0x3 << 16)
 210 #define NARROW_MODE_SHIFT                               14
 211 #define NARROW_MODE_MASK                                (0x3 << 14)
 212 #define CL_SHIFT                                        10
 213 #define CL_MASK                                         (0xf << 10)
 214 #define ROWSIZE_SHIFT                                   7
 215 #define ROWSIZE_MASK                                    (0x7 << 7)
 216 #define IBANK_SHIFT                                     4
 217 #define IBANK_MASK                                      (0x7 << 4)
 218 #define EBANK_SHIFT                                     3
 219 #define EBANK_MASK                                      (1 << 3)
 220 #define PAGESIZE_SHIFT                                  0
 221 #define PAGESIZE_MASK                                   (0x7 << 0)
 222
 223 /* SDRAM_CONFIG_2 */
 224 #define CS1NVMEN_SHIFT                                  30
 225 #define CS1NVMEN_MASK                                   (1 << 30)
 226 #define EBANK_POS_SHIFT                                 27
 227 #define EBANK_POS_MASK                                  (1 << 27)
 228 #define RDBNUM_SHIFT                                    4
 229 #define RDBNUM_MASK                                     (0x3 << 4)
 230 #define RDBSIZE_SHIFT                                   0
 231 #define RDBSIZE_MASK                                    (0x7 << 0)
 232
 233 /* SDRAM_REFRESH_CONTROL */
 234 #define INITREF_DIS_SHIFT                               31
 235 #define INITREF_DIS_MASK                                (1 << 31)
 236 #define SRT_SHIFT                                       29
 237 #define SRT_MASK                                        (1 << 29)
 238 #define ASR_SHIFT                                       28
 239 #define ASR_MASK                                        (1 << 28)
 240 #define PASR_SHIFT                                      24
 241 #define PASR_MASK                                       (0x7 << 24)
 242 #define REFRESH_RATE_SHIFT                              0
 243 #define REFRESH_RATE_MASK                               (0xffff << 0)
 244
 245 /* SDRAM_TIMING_1 */
 246 #define T_RTW_SHIFT                                     29
 247 #define T_RTW_MASK                                      (0x7 << 29)
 248 #define T_RP_SHIFT                                      25
 249 #define T_RP_MASK                                       (0xf << 25)
 250 #define T_RCD_SHIFT                                     21
 251 #define T_RCD_MASK                                      (0xf << 21)
 252 #define T_WR_SHIFT                                      17
 253 #define T_WR_MASK                                       (0xf << 17)
 254 #define T_RAS_SHIFT                                     12
 255 #define T_RAS_MASK                                      (0x1f << 12)
 256 #define T_RC_SHIFT                                      6
 257 #define T_RC_MASK                                       (0x3f << 6)
 258 #define T_RRD_SHIFT                                     3
 259 #define T_RRD_MASK                                      (0x7 << 3)
 260 #define T_WTR_SHIFT                                     0
 261 #define T_WTR_MASK                                      (0x7 << 0)
 262
 263 /* SDRAM_TIMING_2 */
 264 #define T_XP_SHIFT                                      28
 265 #define T_XP_MASK                                       (0x7 << 28)
 266 #define T_ODT_SHIFT                                     25
 267 #define T_ODT_MASK                                      (0x7 << 25)
 268 #define T_XSNR_SHIFT                                    16
 269 #define T_XSNR_MASK                                     (0x1ff << 16)
 270 #define T_XSRD_SHIFT                                    6
 271 #define T_XSRD_MASK                                     (0x3ff << 6)
 272 #define T_RTP_SHIFT                                     3
 273 #define T_RTP_MASK                                      (0x7 << 3)
 274 #define T_CKE_SHIFT                                     0
 275 #define T_CKE_MASK                                      (0x7 << 0)
 276
 277 /* SDRAM_TIMING_3 */
 278 #define T_PDLL_UL_SHIFT                                 28
 279 #define T_PDLL_UL_MASK                                  (0xf << 28)
 280 #define T_CSTA_SHIFT                                    24
 281 #define T_CSTA_MASK                                     (0xf << 24)
 282 #define T_CKESR_SHIFT                                   21
 283 #define T_CKESR_MASK                                    (0x7 << 21)
 284 #define ZQ_ZQCS_SHIFT                                   15
 285 #define ZQ_ZQCS_MASK                                    (0x3f << 15)
 286 #define T_TDQSCKMAX_SHIFT                               13
 287 #define T_TDQSCKMAX_MASK                                (0x3 << 13)
 288 #define T_RFC_SHIFT                                     4
 289 #define T_RFC_MASK                                      (0x1ff << 4)
 290 #define T_RAS_MAX_SHIFT                                 0
 291 #define T_RAS_MAX_MASK                                  (0xf << 0)
 292
 293 /* POWER_MANAGEMENT_CONTROL */
 294 #define PD_TIM_SHIFT                                    12
 295 #define PD_TIM_MASK                                     (0xf << 12)
 296 #define DPD_EN_SHIFT                                    11
 297 #define DPD_EN_MASK                                     (1 << 11)
 298 #define LP_MODE_SHIFT                                   8
 299 #define LP_MODE_MASK                                    (0x7 << 8)
 300 #define SR_TIM_SHIFT                                    4
 301 #define SR_TIM_MASK                                     (0xf << 4)
 302 #define CS_TIM_SHIFT                                    0
 303 #define CS_TIM_MASK                                     (0xf << 0)
 304
 305 /* LPDDR2_MODE_REG_DATA */
 306 #define VALUE_0_SHIFT                                   0
 307 #define VALUE_0_MASK                                    (0x7f << 0)
 308
 309 /* LPDDR2_MODE_REG_CONFIG */
 310 #define CS_SHIFT                                        31
 311 #define CS_MASK                                         (1 << 31)
 312 #define REFRESH_EN_SHIFT                                30
 313 #define REFRESH_EN_MASK                                 (1 << 30)
 314 #define ADDRESS_SHIFT                                   0
 315 #define ADDRESS_MASK                                    (0xff << 0)
 316
 317 /* OCP_CONFIG */
 318 #define SYS_THRESH_MAX_SHIFT                            24
 319 #define SYS_THRESH_MAX_MASK                             (0xf << 24)
 320 #define MPU_THRESH_MAX_SHIFT                            20
 321 #define MPU_THRESH_MAX_MASK                             (0xf << 20)
 322 #define LL_THRESH_MAX_SHIFT                             16
 323 #define LL_THRESH_MAX_MASK                              (0xf << 16)
 324
 325 /* PERFORMANCE_COUNTER_1 */
 326 #define COUNTER1_SHIFT                                  0
 327 #define COUNTER1_MASK                                   (0xffffffff << 0)
 328
 329 /* PERFORMANCE_COUNTER_2 */
 330 #define COUNTER2_SHIFT                                  0
 331 #define COUNTER2_MASK                                   (0xffffffff << 0)
 332
 333 /* PERFORMANCE_COUNTER_CONFIG */
 334 #define CNTR2_MCONNID_EN_SHIFT                          31
 335 #define CNTR2_MCONNID_EN_MASK                           (1 << 31)
 336 #define CNTR2_REGION_EN_SHIFT                           30
 337 #define CNTR2_REGION_EN_MASK                            (1 << 30)
 338 #define CNTR2_CFG_SHIFT                                 16
 339 #define CNTR2_CFG_MASK                                  (0xf << 16)
 340 #define CNTR1_MCONNID_EN_SHIFT                          15
 341 #define CNTR1_MCONNID_EN_MASK                           (1 << 15)
 342 #define CNTR1_REGION_EN_SHIFT                           14
 343 #define CNTR1_REGION_EN_MASK                            (1 << 14)
 344 #define CNTR1_CFG_SHIFT                                 0
 345 #define CNTR1_CFG_MASK                                  (0xf << 0)
 346
 347 /* PERFORMANCE_COUNTER_MASTER_REGION_SELECT */
 348 #define MCONNID2_SHIFT                                  24
 349 #define MCONNID2_MASK                                   (0xff << 24)
 350 #define REGION_SEL2_SHIFT                               16
 351 #define REGION_SEL2_MASK                                (0x3 << 16)
 352 #define MCONNID1_SHIFT                                  8
 353 #define MCONNID1_MASK                                   (0xff << 8)
 354 #define REGION_SEL1_SHIFT                               0
 355 #define REGION_SEL1_MASK                                (0x3 << 0)
 356
 357 /* PERFORMANCE_COUNTER_TIME */
 358 #define TOTAL_TIME_SHIFT                                0
 359 #define TOTAL_TIME_MASK                                 (0xffffffff << 0)
 360
 361 /* DLL_CALIB_CTRL */
 362 #define ACK_WAIT_SHIFT                                  16
 363 #define ACK_WAIT_MASK                                   (0xf << 16)
 364 #define DLL_CALIB_INTERVAL_SHIFT                        0
 365 #define DLL_CALIB_INTERVAL_MASK                         (0x1ff << 0)
 366
 367 /* END_OF_INTERRUPT */
 368 #define EOI_SHIFT                                       0
 369 #define EOI_MASK                                        (1 << 0)
 370
 371 /* SYSTEM_OCP_INTERRUPT_RAW_STATUS */
 372 #define DNV_SYS_SHIFT                                   2
 373 #define DNV_SYS_MASK                                    (1 << 2)
 374 #define TA_SYS_SHIFT                                    1
 375 #define TA_SYS_MASK                                     (1 << 1)
 376 #define ERR_SYS_SHIFT                                   0
 377 #define ERR_SYS_MASK                                    (1 << 0)
 378
 379 /* LOW_LATENCY_OCP_INTERRUPT_RAW_STATUS */
 380 #define DNV_LL_SHIFT                                    2
 381 #define DNV_LL_MASK                                     (1 << 2)
 382 #define TA_LL_SHIFT                                     1
 383 #define TA_LL_MASK                                      (1 << 1)
 384 #define ERR_LL_SHIFT                                    0
 385 #define ERR_LL_MASK                                     (1 << 0)
 386
 387 /* SYSTEM_OCP_INTERRUPT_ENABLE_SET */
 388 #define EN_DNV_SYS_SHIFT                                2
 389 #define EN_DNV_SYS_MASK                                 (1 << 2)
 390 #define EN_TA_SYS_SHIFT                                 1
 391 #define EN_TA_SYS_MASK                                  (1 << 1)
 392 #define EN_ERR_SYS_SHIFT                                        0
 393 #define EN_ERR_SYS_MASK                                 (1 << 0)
 394
 395 /* LOW_LATENCY_OCP_INTERRUPT_ENABLE_SET */
 396 #define EN_DNV_LL_SHIFT                                 2
 397 #define EN_DNV_LL_MASK                                  (1 << 2)
 398 #define EN_TA_LL_SHIFT                                  1
 399 #define EN_TA_LL_MASK                                   (1 << 1)
 400 #define EN_ERR_LL_SHIFT                                 0
 401 #define EN_ERR_LL_MASK                                  (1 << 0)
 402
 403 /* SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG */
 404 #define ZQ_CS1EN_SHIFT                                  31
 405 #define ZQ_CS1EN_MASK                                   (1 << 31)
 406 #define ZQ_CS0EN_SHIFT                                  30
 407 #define ZQ_CS0EN_MASK                                   (1 << 30)
 408 #define ZQ_DUALCALEN_SHIFT                              29
 409 #define ZQ_DUALCALEN_MASK                               (1 << 29)
 410 #define ZQ_SFEXITEN_SHIFT                               28
 411 #define ZQ_SFEXITEN_MASK                                (1 << 28)
 412 #define ZQ_ZQINIT_MULT_SHIFT                            18
 413 #define ZQ_ZQINIT_MULT_MASK                             (0x3 << 18)
 414 #define ZQ_ZQCL_MULT_SHIFT                              16
 415 #define ZQ_ZQCL_MULT_MASK                               (0x3 << 16)
 416 #define ZQ_REFINTERVAL_SHIFT                            0
 417 #define ZQ_REFINTERVAL_MASK                             (0xffff << 0)
 418
 419 /* TEMPERATURE_ALERT_CONFIG */
 420 #define TA_CS1EN_SHIFT                                  31
 421 #define TA_CS1EN_MASK                                   (1 << 31)
 422 #define TA_CS0EN_SHIFT                                  30
 423 #define TA_CS0EN_MASK                                   (1 << 30)
 424 #define TA_SFEXITEN_SHIFT                               28
 425 #define TA_SFEXITEN_MASK                                (1 << 28)
 426 #define TA_DEVWDT_SHIFT                                 26
 427 #define TA_DEVWDT_MASK                                  (0x3 << 26)
 428 #define TA_DEVCNT_SHIFT                                 24
 429 #define TA_DEVCNT_MASK                                  (0x3 << 24)
 430 #define TA_REFINTERVAL_SHIFT                            0
 431 #define TA_REFINTERVAL_MASK                             (0x3fffff << 0)
 432
 433 /* OCP_ERROR_LOG */
 434 #define MADDRSPACE_SHIFT                                14
 435 #define MADDRSPACE_MASK                                 (0x3 << 14)
 436 #define MBURSTSEQ_SHIFT                                 11
 437 #define MBURSTSEQ_MASK                                  (0x7 << 11)
 438 #define MCMD_SHIFT                                      8
 439 #define MCMD_MASK                                       (0x7 << 8)
 440 #define MCONNID_SHIFT                                   0
 441 #define MCONNID_MASK                                    (0xff << 0)
 442
 443 /* DDR_PHY_CTRL_1 - EMIF4D */
 444 #define DLL_SLAVE_DLY_CTRL_SHIFT_4D                     4
 445 #define DLL_SLAVE_DLY_CTRL_MASK_4D                      (0xFF << 4)
 446 #define READ_LATENCY_SHIFT_4D                           0
 447 #define READ_LATENCY_MASK_4D                            (0xf << 0)
 448
 449 /* DDR_PHY_CTRL_1 - EMIF4D5 */
 450 #define DLL_HALF_DELAY_SHIFT_4D5                        21
 451 #define DLL_HALF_DELAY_MASK_4D5                         (1 << 21)
 452 #define READ_LATENCY_SHIFT_4D5                          0
 453 #define READ_LATENCY_MASK_4D5                           (0x1f << 0)
 454
 455 /* DDR_PHY_CTRL_1_SHDW */
 456 #define DDR_PHY_CTRL_1_SHDW_SHIFT                       5
 457 #define DDR_PHY_CTRL_1_SHDW_MASK                        (0x7ffffff << 5)
 458 #define READ_LATENCY_SHDW_SHIFT                         0
 459 #define READ_LATENCY_SHDW_MASK                          (0x1f << 0)
 460
 461 #endif