1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for Allwinner sunXi IR controller
5 * Copyright (C) 2014 Alexsey Shestacov <wingrime@linux-sunxi.org>
6 * Copyright (C) 2014 Alexander Bersenev <bay@hackerdom.ru>
9 * Copyright (C) 2007-2012 Daniel Wang
10 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
13 #include <linux/clk.h>
14 #include <linux/interrupt.h>
15 #include <linux/module.h>
16 #include <linux/of_platform.h>
17 #include <linux/reset.h>
18 #include <media/rc-core.h>
20 #define SUNXI_IR_DEV "sunxi-ir"
24 #define SUNXI_IR_CTL_REG 0x00
26 #define REG_CTL_GEN BIT(0)
28 #define REG_CTL_RXEN BIT(1)
30 #define REG_CTL_MD (BIT(4) | BIT(5))
33 #define SUNXI_IR_RXCTL_REG 0x10
34 /* Pulse Polarity Invert flag */
35 #define REG_RXCTL_RPPI BIT(2)
38 #define SUNXI_IR_RXFIFO_REG 0x20
40 /* Rx Interrupt Enable */
41 #define SUNXI_IR_RXINT_REG 0x2C
42 /* Rx FIFO Overflow */
43 #define REG_RXINT_ROI_EN BIT(0)
45 #define REG_RXINT_RPEI_EN BIT(1)
46 /* Rx FIFO Data Available */
47 #define REG_RXINT_RAI_EN BIT(4)
49 /* Rx FIFO available byte level */
50 #define REG_RXINT_RAL(val) ((val) << 8)
52 /* Rx Interrupt Status */
53 #define SUNXI_IR_RXSTA_REG 0x30
54 /* RX FIFO Get Available Counter */
55 #define REG_RXSTA_GET_AC(val) (((val) >> 8) & (ir->fifo_size * 2 - 1))
56 /* Clear all interrupt status value */
57 #define REG_RXSTA_CLEARALL 0xff
59 /* IR Sample Config */
60 #define SUNXI_IR_CIR_REG 0x34
61 /* CIR_REG register noise threshold */
62 #define REG_CIR_NTHR(val) (((val) << 2) & (GENMASK(7, 2)))
63 /* CIR_REG register idle threshold */
64 #define REG_CIR_ITHR(val) (((val) << 8) & (GENMASK(15, 8)))
66 /* Required frequency for IR0 or IR1 clock in CIR mode (default) */
67 #define SUNXI_IR_BASE_CLK 8000000
68 /* Noise threshold in samples */
69 #define SUNXI_IR_RXNOISE 1
70 /* Idle Threshold in samples */
71 #define SUNXI_IR_RXIDLE 20
72 /* Time after which device stops sending data in ms */
73 #define SUNXI_IR_TIMEOUT 120
83 struct reset_control *rst;
87 static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id)
92 struct sunxi_ir *ir = dev_id;
93 struct ir_raw_event rawir = {};
95 spin_lock(&ir->ir_lock);
97 status = readl(ir->base + SUNXI_IR_RXSTA_REG);
99 /* clean all pending statuses */
100 writel(status | REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);
102 if (status & (REG_RXINT_RAI_EN | REG_RXINT_RPEI_EN)) {
103 /* How many messages in fifo */
104 rc = REG_RXSTA_GET_AC(status);
106 rc = rc > ir->fifo_size ? ir->fifo_size : rc;
107 /* If we have data */
108 for (cnt = 0; cnt < rc; cnt++) {
109 /* for each bit in fifo */
110 dt = readb(ir->base + SUNXI_IR_RXFIFO_REG);
111 rawir.pulse = (dt & 0x80) != 0;
112 rawir.duration = ((dt & 0x7f) + 1) *
113 ir->rc->rx_resolution;
114 ir_raw_event_store_with_filter(ir->rc, &rawir);
118 if (status & REG_RXINT_ROI_EN) {
119 ir_raw_event_reset(ir->rc);
120 } else if (status & REG_RXINT_RPEI_EN) {
121 ir_raw_event_set_idle(ir->rc, true);
122 ir_raw_event_handle(ir->rc);
125 spin_unlock(&ir->ir_lock);
130 static int sunxi_ir_probe(struct platform_device *pdev)
133 unsigned long tmp = 0;
135 struct device *dev = &pdev->dev;
136 struct device_node *dn = dev->of_node;
137 struct resource *res;
139 u32 b_clk_freq = SUNXI_IR_BASE_CLK;
141 ir = devm_kzalloc(dev, sizeof(struct sunxi_ir), GFP_KERNEL);
145 spin_lock_init(&ir->ir_lock);
147 if (of_device_is_compatible(dn, "allwinner,sun5i-a13-ir"))
153 ir->apb_clk = devm_clk_get(dev, "apb");
154 if (IS_ERR(ir->apb_clk)) {
155 dev_err(dev, "failed to get a apb clock.\n");
156 return PTR_ERR(ir->apb_clk);
158 ir->clk = devm_clk_get(dev, "ir");
159 if (IS_ERR(ir->clk)) {
160 dev_err(dev, "failed to get a ir clock.\n");
161 return PTR_ERR(ir->clk);
164 /* Base clock frequency (optional) */
165 of_property_read_u32(dn, "clock-frequency", &b_clk_freq);
167 /* Reset (optional) */
168 ir->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
170 return PTR_ERR(ir->rst);
171 ret = reset_control_deassert(ir->rst);
175 ret = clk_set_rate(ir->clk, b_clk_freq);
177 dev_err(dev, "set ir base clock failed!\n");
178 goto exit_reset_assert;
180 dev_dbg(dev, "set base clock frequency to %d Hz.\n", b_clk_freq);
182 if (clk_prepare_enable(ir->apb_clk)) {
183 dev_err(dev, "try to enable apb_ir_clk failed\n");
185 goto exit_reset_assert;
188 if (clk_prepare_enable(ir->clk)) {
189 dev_err(dev, "try to enable ir_clk failed\n");
191 goto exit_clkdisable_apb_clk;
195 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
196 ir->base = devm_ioremap_resource(dev, res);
197 if (IS_ERR(ir->base)) {
198 ret = PTR_ERR(ir->base);
199 goto exit_clkdisable_clk;
202 ir->rc = rc_allocate_device(RC_DRIVER_IR_RAW);
204 dev_err(dev, "failed to allocate device\n");
206 goto exit_clkdisable_clk;
210 ir->rc->device_name = SUNXI_IR_DEV;
211 ir->rc->input_phys = "sunxi-ir/input0";
212 ir->rc->input_id.bustype = BUS_HOST;
213 ir->rc->input_id.vendor = 0x0001;
214 ir->rc->input_id.product = 0x0001;
215 ir->rc->input_id.version = 0x0100;
216 ir->map_name = of_get_property(dn, "linux,rc-map-name", NULL);
217 ir->rc->map_name = ir->map_name ?: RC_MAP_EMPTY;
218 ir->rc->dev.parent = dev;
219 ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
220 /* Frequency after IR internal divider with sample period in ns */
221 ir->rc->rx_resolution = (1000000000ul / (b_clk_freq / 64));
222 ir->rc->timeout = MS_TO_NS(SUNXI_IR_TIMEOUT);
223 ir->rc->driver_name = SUNXI_IR_DEV;
225 ret = rc_register_device(ir->rc);
227 dev_err(dev, "failed to register rc device\n");
231 platform_set_drvdata(pdev, ir);
234 ir->irq = platform_get_irq(pdev, 0);
236 dev_err(dev, "no irq resource\n");
241 ret = devm_request_irq(dev, ir->irq, sunxi_ir_irq, 0, SUNXI_IR_DEV, ir);
243 dev_err(dev, "failed request irq\n");
247 /* Enable CIR Mode */
248 writel(REG_CTL_MD, ir->base+SUNXI_IR_CTL_REG);
250 /* Set noise threshold and idle threshold */
251 writel(REG_CIR_NTHR(SUNXI_IR_RXNOISE)|REG_CIR_ITHR(SUNXI_IR_RXIDLE),
252 ir->base + SUNXI_IR_CIR_REG);
254 /* Invert Input Signal */
255 writel(REG_RXCTL_RPPI, ir->base + SUNXI_IR_RXCTL_REG);
257 /* Clear All Rx Interrupt Status */
258 writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);
261 * Enable IRQ on overflow, packet end, FIFO available with trigger
264 writel(REG_RXINT_ROI_EN | REG_RXINT_RPEI_EN |
265 REG_RXINT_RAI_EN | REG_RXINT_RAL(ir->fifo_size / 2 - 1),
266 ir->base + SUNXI_IR_RXINT_REG);
268 /* Enable IR Module */
269 tmp = readl(ir->base + SUNXI_IR_CTL_REG);
270 writel(tmp | REG_CTL_GEN | REG_CTL_RXEN, ir->base + SUNXI_IR_CTL_REG);
272 dev_info(dev, "initialized sunXi IR driver\n");
276 rc_free_device(ir->rc);
278 clk_disable_unprepare(ir->clk);
279 exit_clkdisable_apb_clk:
280 clk_disable_unprepare(ir->apb_clk);
282 reset_control_assert(ir->rst);
287 static int sunxi_ir_remove(struct platform_device *pdev)
290 struct sunxi_ir *ir = platform_get_drvdata(pdev);
292 clk_disable_unprepare(ir->clk);
293 clk_disable_unprepare(ir->apb_clk);
294 reset_control_assert(ir->rst);
296 spin_lock_irqsave(&ir->ir_lock, flags);
298 writel(0, ir->base + SUNXI_IR_RXINT_REG);
299 /* clear All Rx Interrupt Status */
300 writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);
302 writel(0, ir->base + SUNXI_IR_CTL_REG);
303 spin_unlock_irqrestore(&ir->ir_lock, flags);
305 rc_unregister_device(ir->rc);
309 static const struct of_device_id sunxi_ir_match[] = {
310 { .compatible = "allwinner,sun4i-a10-ir", },
311 { .compatible = "allwinner,sun5i-a13-ir", },
314 MODULE_DEVICE_TABLE(of, sunxi_ir_match);
316 static struct platform_driver sunxi_ir_driver = {
317 .probe = sunxi_ir_probe,
318 .remove = sunxi_ir_remove,
320 .name = SUNXI_IR_DEV,
321 .of_match_table = sunxi_ir_match,
325 module_platform_driver(sunxi_ir_driver);
327 MODULE_DESCRIPTION("Allwinner sunXi IR controller driver");
328 MODULE_AUTHOR("Alexsey Shestacov <wingrime@linux-sunxi.org>");
329 MODULE_LICENSE("GPL");