2 * TI CAL camera interface driver
4 * Copyright (c) 2015 Texas Instruments Inc.
5 * Benoit Parrot, <bparrot@ti.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation
12 #include <linux/interrupt.h>
14 #include <linux/ioctl.h>
15 #include <linux/module.h>
16 #include <linux/platform_device.h>
17 #include <linux/delay.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/slab.h>
20 #include <linux/videodev2.h>
21 #include <linux/of_device.h>
22 #include <linux/of_graph.h>
24 #include <media/v4l2-fwnode.h>
25 #include <media/v4l2-async.h>
26 #include <media/v4l2-common.h>
27 #include <media/v4l2-ctrls.h>
28 #include <media/v4l2-device.h>
29 #include <media/v4l2-event.h>
30 #include <media/v4l2-ioctl.h>
31 #include <media/v4l2-fh.h>
32 #include <media/videobuf2-core.h>
33 #include <media/videobuf2-dma-contig.h>
36 #define CAL_MODULE_NAME "cal"
38 #define MAX_WIDTH 1920
39 #define MAX_HEIGHT 1200
41 #define CAL_VERSION "0.1.0"
43 MODULE_DESCRIPTION("TI CAL driver");
44 MODULE_AUTHOR("Benoit Parrot, <bparrot@ti.com>");
45 MODULE_LICENSE("GPL v2");
46 MODULE_VERSION(CAL_VERSION);
48 static unsigned video_nr = -1;
49 module_param(video_nr, uint, 0644);
50 MODULE_PARM_DESC(video_nr, "videoX start number, -1 is autodetect");
52 static unsigned debug;
53 module_param(debug, uint, 0644);
54 MODULE_PARM_DESC(debug, "activates debug info");
56 /* timeperframe: min/max and default */
57 static const struct v4l2_fract
58 tpf_default = {.numerator = 1001, .denominator = 30000};
60 #define cal_dbg(level, caldev, fmt, arg...) \
61 v4l2_dbg(level, debug, &caldev->v4l2_dev, fmt, ##arg)
62 #define cal_info(caldev, fmt, arg...) \
63 v4l2_info(&caldev->v4l2_dev, fmt, ##arg)
64 #define cal_err(caldev, fmt, arg...) \
65 v4l2_err(&caldev->v4l2_dev, fmt, ##arg)
67 #define ctx_dbg(level, ctx, fmt, arg...) \
68 v4l2_dbg(level, debug, &ctx->v4l2_dev, fmt, ##arg)
69 #define ctx_info(ctx, fmt, arg...) \
70 v4l2_info(&ctx->v4l2_dev, fmt, ##arg)
71 #define ctx_err(ctx, fmt, arg...) \
72 v4l2_err(&ctx->v4l2_dev, fmt, ##arg)
74 #define CAL_NUM_INPUT 1
75 #define CAL_NUM_CONTEXT 2
77 #define bytes_per_line(pixel, bpp) (ALIGN(pixel * bpp, 16))
79 #define reg_read(dev, offset) ioread32(dev->base + offset)
80 #define reg_write(dev, offset, val) iowrite32(val, dev->base + offset)
82 #define reg_read_field(dev, offset, mask) get_field(reg_read(dev, offset), \
84 #define reg_write_field(dev, offset, field, mask) { \
85 u32 val = reg_read(dev, offset); \
86 set_field(&val, field, mask); \
87 reg_write(dev, offset, val); }
89 /* ------------------------------------------------------------------
91 * ------------------------------------------------------------------
100 static struct cal_fmt cal_formats[] = {
102 .fourcc = V4L2_PIX_FMT_YUYV,
103 .code = MEDIA_BUS_FMT_YUYV8_2X8,
106 .fourcc = V4L2_PIX_FMT_UYVY,
107 .code = MEDIA_BUS_FMT_UYVY8_2X8,
110 .fourcc = V4L2_PIX_FMT_YVYU,
111 .code = MEDIA_BUS_FMT_YVYU8_2X8,
114 .fourcc = V4L2_PIX_FMT_VYUY,
115 .code = MEDIA_BUS_FMT_VYUY8_2X8,
118 .fourcc = V4L2_PIX_FMT_RGB565, /* gggbbbbb rrrrrggg */
119 .code = MEDIA_BUS_FMT_RGB565_2X8_LE,
122 .fourcc = V4L2_PIX_FMT_RGB565X, /* rrrrrggg gggbbbbb */
123 .code = MEDIA_BUS_FMT_RGB565_2X8_BE,
126 .fourcc = V4L2_PIX_FMT_RGB555, /* gggbbbbb arrrrrgg */
127 .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE,
130 .fourcc = V4L2_PIX_FMT_RGB555X, /* arrrrrgg gggbbbbb */
131 .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE,
134 .fourcc = V4L2_PIX_FMT_RGB24, /* rgb */
135 .code = MEDIA_BUS_FMT_RGB888_2X12_LE,
138 .fourcc = V4L2_PIX_FMT_BGR24, /* bgr */
139 .code = MEDIA_BUS_FMT_RGB888_2X12_BE,
142 .fourcc = V4L2_PIX_FMT_RGB32, /* argb */
143 .code = MEDIA_BUS_FMT_ARGB8888_1X32,
146 .fourcc = V4L2_PIX_FMT_SBGGR8,
147 .code = MEDIA_BUS_FMT_SBGGR8_1X8,
150 .fourcc = V4L2_PIX_FMT_SGBRG8,
151 .code = MEDIA_BUS_FMT_SGBRG8_1X8,
154 .fourcc = V4L2_PIX_FMT_SGRBG8,
155 .code = MEDIA_BUS_FMT_SGRBG8_1X8,
158 .fourcc = V4L2_PIX_FMT_SRGGB8,
159 .code = MEDIA_BUS_FMT_SRGGB8_1X8,
162 .fourcc = V4L2_PIX_FMT_SBGGR10,
163 .code = MEDIA_BUS_FMT_SBGGR10_1X10,
166 .fourcc = V4L2_PIX_FMT_SGBRG10,
167 .code = MEDIA_BUS_FMT_SGBRG10_1X10,
170 .fourcc = V4L2_PIX_FMT_SGRBG10,
171 .code = MEDIA_BUS_FMT_SGRBG10_1X10,
174 .fourcc = V4L2_PIX_FMT_SRGGB10,
175 .code = MEDIA_BUS_FMT_SRGGB10_1X10,
178 .fourcc = V4L2_PIX_FMT_SBGGR12,
179 .code = MEDIA_BUS_FMT_SBGGR12_1X12,
182 .fourcc = V4L2_PIX_FMT_SGBRG12,
183 .code = MEDIA_BUS_FMT_SGBRG12_1X12,
186 .fourcc = V4L2_PIX_FMT_SGRBG12,
187 .code = MEDIA_BUS_FMT_SGRBG12_1X12,
190 .fourcc = V4L2_PIX_FMT_SRGGB12,
191 .code = MEDIA_BUS_FMT_SRGGB12_1X12,
196 /* Print Four-character-code (FOURCC) */
197 static char *fourcc_to_str(u32 fmt)
201 code[0] = (unsigned char)(fmt & 0xff);
202 code[1] = (unsigned char)((fmt >> 8) & 0xff);
203 code[2] = (unsigned char)((fmt >> 16) & 0xff);
204 code[3] = (unsigned char)((fmt >> 24) & 0xff);
210 /* buffer for one video frame */
212 /* common v4l buffer stuff -- must be first */
213 struct vb2_v4l2_buffer vb;
214 struct list_head list;
215 const struct cal_fmt *fmt;
218 struct cal_dmaqueue {
219 struct list_head active;
221 /* Counters to control fps rate */
228 struct resource *res;
230 unsigned int camerrx_control;
232 struct platform_device *pdev;
237 struct resource *res;
239 struct platform_device *pdev;
243 * there is one cal_dev structure in the driver, it is shared by
249 struct resource *res;
250 struct platform_device *pdev;
251 struct v4l2_device v4l2_dev;
253 /* Control Module handle */
255 /* Camera Core Module handle */
256 struct cc_data *cc[CAL_NUM_CSI2_PORTS];
258 struct cal_ctx *ctx[CAL_NUM_CONTEXT];
262 * There is one cal_ctx structure for each camera core context.
265 struct v4l2_device v4l2_dev;
266 struct v4l2_ctrl_handler ctrl_handler;
267 struct video_device vdev;
268 struct v4l2_async_notifier notifier;
269 struct v4l2_subdev *sensor;
270 struct v4l2_fwnode_endpoint endpoint;
272 struct v4l2_async_subdev asd;
278 /* v4l2_ioctl mutex */
280 /* v4l2 buffers lock */
283 /* Several counters */
284 unsigned long jiffies;
286 struct cal_dmaqueue vidq;
292 const struct cal_fmt *fmt;
293 /* Used to store current pixel format */
294 struct v4l2_format v_fmt;
295 /* Used to store current mbus frame format */
296 struct v4l2_mbus_framefmt m_fmt;
298 /* Current subdev enumerated format */
299 struct cal_fmt *active_fmt[ARRAY_SIZE(cal_formats)];
302 struct v4l2_fract timeperframe;
303 unsigned int sequence;
304 unsigned int external_rate;
305 struct vb2_queue vb_vidq;
306 unsigned int seq_count;
307 unsigned int csi2_port;
308 unsigned int virtual_channel;
310 /* Pointer pointing to current v4l2_buffer */
311 struct cal_buffer *cur_frm;
312 /* Pointer pointing to next v4l2_buffer */
313 struct cal_buffer *next_frm;
316 static const struct cal_fmt *find_format_by_pix(struct cal_ctx *ctx,
319 const struct cal_fmt *fmt;
322 for (k = 0; k < ctx->num_active_fmt; k++) {
323 fmt = ctx->active_fmt[k];
324 if (fmt->fourcc == pixelformat)
331 static const struct cal_fmt *find_format_by_code(struct cal_ctx *ctx,
334 const struct cal_fmt *fmt;
337 for (k = 0; k < ctx->num_active_fmt; k++) {
338 fmt = ctx->active_fmt[k];
339 if (fmt->code == code)
346 static inline struct cal_ctx *notifier_to_ctx(struct v4l2_async_notifier *n)
348 return container_of(n, struct cal_ctx, notifier);
351 static inline int get_field(u32 value, u32 mask)
353 return (value & mask) >> __ffs(mask);
356 static inline void set_field(u32 *valp, u32 field, u32 mask)
361 val |= (field << __ffs(mask)) & mask;
366 * Control Module block access
368 static struct cm_data *cm_create(struct cal_dev *dev)
370 struct platform_device *pdev = dev->pdev;
373 cm = devm_kzalloc(&pdev->dev, sizeof(*cm), GFP_KERNEL);
375 return ERR_PTR(-ENOMEM);
377 cm->res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
379 cm->base = devm_ioremap_resource(&pdev->dev, cm->res);
380 if (IS_ERR(cm->base)) {
381 cal_err(dev, "failed to ioremap\n");
382 return ERR_CAST(cm->base);
385 cal_dbg(1, dev, "ioresource %s at %pa - %pa\n",
386 cm->res->name, &cm->res->start, &cm->res->end);
391 static void camerarx_phy_enable(struct cal_ctx *ctx)
395 if (!ctx->dev->cm->base) {
396 ctx_err(ctx, "cm not mapped\n");
400 val = reg_read(ctx->dev->cm, CM_CTRL_CORE_CAMERRX_CONTROL);
401 if (ctx->csi2_port == 1) {
402 set_field(&val, 1, CM_CAMERRX_CTRL_CSI0_CTRLCLKEN_MASK);
403 set_field(&val, 0, CM_CAMERRX_CTRL_CSI0_CAMMODE_MASK);
404 /* enable all lanes by default */
405 set_field(&val, 0xf, CM_CAMERRX_CTRL_CSI0_LANEENABLE_MASK);
406 set_field(&val, 1, CM_CAMERRX_CTRL_CSI0_MODE_MASK);
407 } else if (ctx->csi2_port == 2) {
408 set_field(&val, 1, CM_CAMERRX_CTRL_CSI1_CTRLCLKEN_MASK);
409 set_field(&val, 0, CM_CAMERRX_CTRL_CSI1_CAMMODE_MASK);
410 /* enable all lanes by default */
411 set_field(&val, 0x3, CM_CAMERRX_CTRL_CSI1_LANEENABLE_MASK);
412 set_field(&val, 1, CM_CAMERRX_CTRL_CSI1_MODE_MASK);
414 reg_write(ctx->dev->cm, CM_CTRL_CORE_CAMERRX_CONTROL, val);
417 static void camerarx_phy_disable(struct cal_ctx *ctx)
421 if (!ctx->dev->cm->base) {
422 ctx_err(ctx, "cm not mapped\n");
426 val = reg_read(ctx->dev->cm, CM_CTRL_CORE_CAMERRX_CONTROL);
427 if (ctx->csi2_port == 1)
428 set_field(&val, 0x0, CM_CAMERRX_CTRL_CSI0_CTRLCLKEN_MASK);
429 else if (ctx->csi2_port == 2)
430 set_field(&val, 0x0, CM_CAMERRX_CTRL_CSI1_CTRLCLKEN_MASK);
431 reg_write(ctx->dev->cm, CM_CTRL_CORE_CAMERRX_CONTROL, val);
435 * Camera Instance access block
437 static struct cc_data *cc_create(struct cal_dev *dev, unsigned int core)
439 struct platform_device *pdev = dev->pdev;
442 cc = devm_kzalloc(&pdev->dev, sizeof(*cc), GFP_KERNEL);
444 return ERR_PTR(-ENOMEM);
446 cc->res = platform_get_resource_byname(pdev,
451 cc->base = devm_ioremap_resource(&pdev->dev, cc->res);
452 if (IS_ERR(cc->base)) {
453 cal_err(dev, "failed to ioremap\n");
454 return ERR_CAST(cc->base);
457 cal_dbg(1, dev, "ioresource %s at %pa - %pa\n",
458 cc->res->name, &cc->res->start, &cc->res->end);
464 * Get Revision and HW info
466 static void cal_get_hwinfo(struct cal_dev *dev)
471 revision = reg_read(dev, CAL_HL_REVISION);
472 cal_dbg(3, dev, "CAL_HL_REVISION = 0x%08x (expecting 0x40000200)\n",
475 hwinfo = reg_read(dev, CAL_HL_HWINFO);
476 cal_dbg(3, dev, "CAL_HL_HWINFO = 0x%08x (expecting 0xA3C90469)\n",
480 static inline int cal_runtime_get(struct cal_dev *dev)
482 return pm_runtime_get_sync(&dev->pdev->dev);
485 static inline void cal_runtime_put(struct cal_dev *dev)
487 pm_runtime_put_sync(&dev->pdev->dev);
490 static void cal_quickdump_regs(struct cal_dev *dev)
492 cal_info(dev, "CAL Registers @ 0x%pa:\n", &dev->res->start);
493 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 4,
494 (__force const void *)dev->base,
495 resource_size(dev->res), false);
498 cal_info(dev, "CSI2 Core 0 Registers @ %pa:\n",
499 &dev->ctx[0]->cc->res->start);
500 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 4,
501 (__force const void *)dev->ctx[0]->cc->base,
502 resource_size(dev->ctx[0]->cc->res),
507 cal_info(dev, "CSI2 Core 1 Registers @ %pa:\n",
508 &dev->ctx[1]->cc->res->start);
509 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 4,
510 (__force const void *)dev->ctx[1]->cc->base,
511 resource_size(dev->ctx[1]->cc->res),
515 cal_info(dev, "CAMERRX_Control Registers @ %pa:\n",
516 &dev->cm->res->start);
517 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 4,
518 (__force const void *)dev->cm->base,
519 resource_size(dev->cm->res), false);
523 * Enable the expected IRQ sources
525 static void enable_irqs(struct cal_ctx *ctx)
527 /* Enable IRQ_WDMA_END 0/1 */
528 reg_write_field(ctx->dev,
529 CAL_HL_IRQENABLE_SET(2),
531 CAL_HL_IRQ_MASK(ctx->csi2_port));
532 /* Enable IRQ_WDMA_START 0/1 */
533 reg_write_field(ctx->dev,
534 CAL_HL_IRQENABLE_SET(3),
536 CAL_HL_IRQ_MASK(ctx->csi2_port));
537 /* Todo: Add VC_IRQ and CSI2_COMPLEXIO_IRQ handling */
538 reg_write(ctx->dev, CAL_CSI2_VC_IRQENABLE(1), 0xFF000000);
541 static void disable_irqs(struct cal_ctx *ctx)
543 /* Disable IRQ_WDMA_END 0/1 */
544 reg_write_field(ctx->dev,
545 CAL_HL_IRQENABLE_CLR(2),
547 CAL_HL_IRQ_MASK(ctx->csi2_port));
548 /* Disable IRQ_WDMA_START 0/1 */
549 reg_write_field(ctx->dev,
550 CAL_HL_IRQENABLE_CLR(3),
552 CAL_HL_IRQ_MASK(ctx->csi2_port));
553 /* Todo: Add VC_IRQ and CSI2_COMPLEXIO_IRQ handling */
554 reg_write(ctx->dev, CAL_CSI2_VC_IRQENABLE(1), 0);
557 static void csi2_init(struct cal_ctx *ctx)
562 val = reg_read(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port));
563 set_field(&val, CAL_GEN_ENABLE,
564 CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK);
565 set_field(&val, CAL_GEN_ENABLE,
566 CAL_CSI2_TIMING_STOP_STATE_X16_IO1_MASK);
567 set_field(&val, CAL_GEN_DISABLE,
568 CAL_CSI2_TIMING_STOP_STATE_X4_IO1_MASK);
569 set_field(&val, 407, CAL_CSI2_TIMING_STOP_STATE_COUNTER_IO1_MASK);
570 reg_write(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port), val);
571 ctx_dbg(3, ctx, "CAL_CSI2_TIMING(%d) = 0x%08x\n", ctx->csi2_port,
572 reg_read(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port)));
574 val = reg_read(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port));
575 set_field(&val, CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_OPERATIONAL,
576 CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_MASK);
577 set_field(&val, CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_ON,
578 CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_MASK);
579 reg_write(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port), val);
580 for (i = 0; i < 10; i++) {
581 if (reg_read_field(ctx->dev,
582 CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port),
583 CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_MASK) ==
584 CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_STATE_ON)
586 usleep_range(1000, 1100);
588 ctx_dbg(3, ctx, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x\n", ctx->csi2_port,
589 reg_read(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port)));
591 val = reg_read(ctx->dev, CAL_CTRL);
592 set_field(&val, CAL_CTRL_BURSTSIZE_BURST128, CAL_CTRL_BURSTSIZE_MASK);
593 set_field(&val, 0xF, CAL_CTRL_TAGCNT_MASK);
594 set_field(&val, CAL_CTRL_POSTED_WRITES_NONPOSTED,
595 CAL_CTRL_POSTED_WRITES_MASK);
596 set_field(&val, 0xFF, CAL_CTRL_MFLAGL_MASK);
597 set_field(&val, 0xFF, CAL_CTRL_MFLAGH_MASK);
598 reg_write(ctx->dev, CAL_CTRL, val);
599 ctx_dbg(3, ctx, "CAL_CTRL = 0x%08x\n", reg_read(ctx->dev, CAL_CTRL));
602 static void csi2_lane_config(struct cal_ctx *ctx)
604 u32 val = reg_read(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port));
605 u32 lane_mask = CAL_CSI2_COMPLEXIO_CFG_CLOCK_POSITION_MASK;
606 u32 polarity_mask = CAL_CSI2_COMPLEXIO_CFG_CLOCK_POL_MASK;
607 struct v4l2_fwnode_bus_mipi_csi2 *mipi_csi2 =
608 &ctx->endpoint.bus.mipi_csi2;
611 set_field(&val, mipi_csi2->clock_lane + 1, lane_mask);
612 set_field(&val, mipi_csi2->lane_polarities[0], polarity_mask);
613 for (lane = 0; lane < mipi_csi2->num_data_lanes; lane++) {
615 * Every lane are one nibble apart starting with the
616 * clock followed by the data lanes so shift masks by 4.
620 set_field(&val, mipi_csi2->data_lanes[lane] + 1, lane_mask);
621 set_field(&val, mipi_csi2->lane_polarities[lane + 1],
625 reg_write(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port), val);
626 ctx_dbg(3, ctx, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x\n",
627 ctx->csi2_port, val);
630 static void csi2_ppi_enable(struct cal_ctx *ctx)
632 reg_write_field(ctx->dev, CAL_CSI2_PPI_CTRL(ctx->csi2_port),
633 CAL_GEN_ENABLE, CAL_CSI2_PPI_CTRL_IF_EN_MASK);
636 static void csi2_ppi_disable(struct cal_ctx *ctx)
638 reg_write_field(ctx->dev, CAL_CSI2_PPI_CTRL(ctx->csi2_port),
639 CAL_GEN_DISABLE, CAL_CSI2_PPI_CTRL_IF_EN_MASK);
642 static void csi2_ctx_config(struct cal_ctx *ctx)
646 val = reg_read(ctx->dev, CAL_CSI2_CTX0(ctx->csi2_port));
647 set_field(&val, ctx->csi2_port, CAL_CSI2_CTX_CPORT_MASK);
649 * DT type: MIPI CSI-2 Specs
650 * 0x1: All - DT filter is disabled
651 * 0x24: RGB888 1 pixel = 3 bytes
652 * 0x2B: RAW10 4 pixels = 5 bytes
653 * 0x2A: RAW8 1 pixel = 1 byte
654 * 0x1E: YUV422 2 pixels = 4 bytes
656 set_field(&val, 0x1, CAL_CSI2_CTX_DT_MASK);
657 /* Virtual Channel from the CSI2 sensor usually 0! */
658 set_field(&val, ctx->virtual_channel, CAL_CSI2_CTX_VC_MASK);
659 /* NUM_LINES_PER_FRAME => 0 means auto detect */
660 set_field(&val, 0, CAL_CSI2_CTX_LINES_MASK);
661 set_field(&val, CAL_CSI2_CTX_ATT_PIX, CAL_CSI2_CTX_ATT_MASK);
662 set_field(&val, CAL_CSI2_CTX_PACK_MODE_LINE,
663 CAL_CSI2_CTX_PACK_MODE_MASK);
664 reg_write(ctx->dev, CAL_CSI2_CTX0(ctx->csi2_port), val);
665 ctx_dbg(3, ctx, "CAL_CSI2_CTX0(%d) = 0x%08x\n", ctx->csi2_port,
666 reg_read(ctx->dev, CAL_CSI2_CTX0(ctx->csi2_port)));
669 static void pix_proc_config(struct cal_ctx *ctx)
673 val = reg_read(ctx->dev, CAL_PIX_PROC(ctx->csi2_port));
674 set_field(&val, CAL_PIX_PROC_EXTRACT_B8, CAL_PIX_PROC_EXTRACT_MASK);
675 set_field(&val, CAL_PIX_PROC_DPCMD_BYPASS, CAL_PIX_PROC_DPCMD_MASK);
676 set_field(&val, CAL_PIX_PROC_DPCME_BYPASS, CAL_PIX_PROC_DPCME_MASK);
677 set_field(&val, CAL_PIX_PROC_PACK_B8, CAL_PIX_PROC_PACK_MASK);
678 set_field(&val, ctx->csi2_port, CAL_PIX_PROC_CPORT_MASK);
679 set_field(&val, CAL_GEN_ENABLE, CAL_PIX_PROC_EN_MASK);
680 reg_write(ctx->dev, CAL_PIX_PROC(ctx->csi2_port), val);
681 ctx_dbg(3, ctx, "CAL_PIX_PROC(%d) = 0x%08x\n", ctx->csi2_port,
682 reg_read(ctx->dev, CAL_PIX_PROC(ctx->csi2_port)));
685 static void cal_wr_dma_config(struct cal_ctx *ctx,
690 val = reg_read(ctx->dev, CAL_WR_DMA_CTRL(ctx->csi2_port));
691 set_field(&val, ctx->csi2_port, CAL_WR_DMA_CTRL_CPORT_MASK);
692 set_field(&val, CAL_WR_DMA_CTRL_DTAG_PIX_DAT,
693 CAL_WR_DMA_CTRL_DTAG_MASK);
694 set_field(&val, CAL_WR_DMA_CTRL_MODE_CONST,
695 CAL_WR_DMA_CTRL_MODE_MASK);
696 set_field(&val, CAL_WR_DMA_CTRL_PATTERN_LINEAR,
697 CAL_WR_DMA_CTRL_PATTERN_MASK);
698 set_field(&val, CAL_GEN_ENABLE, CAL_WR_DMA_CTRL_STALL_RD_MASK);
699 reg_write(ctx->dev, CAL_WR_DMA_CTRL(ctx->csi2_port), val);
700 ctx_dbg(3, ctx, "CAL_WR_DMA_CTRL(%d) = 0x%08x\n", ctx->csi2_port,
701 reg_read(ctx->dev, CAL_WR_DMA_CTRL(ctx->csi2_port)));
704 * width/16 not sure but giving it a whirl.
705 * zero does not work right
707 reg_write_field(ctx->dev,
708 CAL_WR_DMA_OFST(ctx->csi2_port),
710 CAL_WR_DMA_OFST_MASK);
711 ctx_dbg(3, ctx, "CAL_WR_DMA_OFST(%d) = 0x%08x\n", ctx->csi2_port,
712 reg_read(ctx->dev, CAL_WR_DMA_OFST(ctx->csi2_port)));
714 val = reg_read(ctx->dev, CAL_WR_DMA_XSIZE(ctx->csi2_port));
715 /* 64 bit word means no skipping */
716 set_field(&val, 0, CAL_WR_DMA_XSIZE_XSKIP_MASK);
718 * (width*8)/64 this should be size of an entire line
719 * in 64bit word but 0 means all data until the end
720 * is detected automagically
722 set_field(&val, (width / 8), CAL_WR_DMA_XSIZE_MASK);
723 reg_write(ctx->dev, CAL_WR_DMA_XSIZE(ctx->csi2_port), val);
724 ctx_dbg(3, ctx, "CAL_WR_DMA_XSIZE(%d) = 0x%08x\n", ctx->csi2_port,
725 reg_read(ctx->dev, CAL_WR_DMA_XSIZE(ctx->csi2_port)));
728 static void cal_wr_dma_addr(struct cal_ctx *ctx, unsigned int dmaaddr)
730 reg_write(ctx->dev, CAL_WR_DMA_ADDR(ctx->csi2_port), dmaaddr);
734 * TCLK values are OK at their reset values
738 #define TCLK_SETTLE 14
739 #define THS_SETTLE 15
741 static void csi2_phy_config(struct cal_ctx *ctx)
743 unsigned int reg0, reg1;
744 unsigned int ths_term, ths_settle;
745 unsigned int ddrclkperiod_us;
748 * THS_TERM: Programmed value = floor(20 ns/DDRClk period) - 2.
750 ddrclkperiod_us = ctx->external_rate / 2000000;
751 ddrclkperiod_us = 1000000 / ddrclkperiod_us;
752 ctx_dbg(1, ctx, "ddrclkperiod_us: %d\n", ddrclkperiod_us);
754 ths_term = 20000 / ddrclkperiod_us;
755 ths_term = (ths_term >= 2) ? ths_term - 2 : ths_term;
756 ctx_dbg(1, ctx, "ths_term: %d (0x%02x)\n", ths_term, ths_term);
759 * THS_SETTLE: Programmed value = floor(176.3 ns/CtrlClk period) - 1.
760 * Since CtrlClk is fixed at 96Mhz then we get
761 * ths_settle = floor(176.3 / 10.416) - 1 = 15
762 * If we ever switch to a dynamic clock then this code might be useful
764 * unsigned int ctrlclkperiod_us;
765 * ctrlclkperiod_us = 96000000 / 1000000;
766 * ctrlclkperiod_us = 1000000 / ctrlclkperiod_us;
767 * ctx_dbg(1, ctx, "ctrlclkperiod_us: %d\n", ctrlclkperiod_us);
769 * ths_settle = 176300 / ctrlclkperiod_us;
770 * ths_settle = (ths_settle > 1) ? ths_settle - 1 : ths_settle;
773 ths_settle = THS_SETTLE;
774 ctx_dbg(1, ctx, "ths_settle: %d (0x%02x)\n", ths_settle, ths_settle);
776 reg0 = reg_read(ctx->cc, CAL_CSI2_PHY_REG0);
777 set_field(®0, CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_DISABLE,
778 CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_MASK);
779 set_field(®0, ths_term, CAL_CSI2_PHY_REG0_THS_TERM_MASK);
780 set_field(®0, ths_settle, CAL_CSI2_PHY_REG0_THS_SETTLE_MASK);
782 ctx_dbg(1, ctx, "CSI2_%d_REG0 = 0x%08x\n", (ctx->csi2_port - 1), reg0);
783 reg_write(ctx->cc, CAL_CSI2_PHY_REG0, reg0);
785 reg1 = reg_read(ctx->cc, CAL_CSI2_PHY_REG1);
786 set_field(®1, TCLK_TERM, CAL_CSI2_PHY_REG1_TCLK_TERM_MASK);
787 set_field(®1, 0xb8, CAL_CSI2_PHY_REG1_DPHY_HS_SYNC_PATTERN_MASK);
788 set_field(®1, TCLK_MISS, CAL_CSI2_PHY_REG1_CTRLCLK_DIV_FACTOR_MASK);
789 set_field(®1, TCLK_SETTLE, CAL_CSI2_PHY_REG1_TCLK_SETTLE_MASK);
791 ctx_dbg(1, ctx, "CSI2_%d_REG1 = 0x%08x\n", (ctx->csi2_port - 1), reg1);
792 reg_write(ctx->cc, CAL_CSI2_PHY_REG1, reg1);
795 static int cal_get_external_info(struct cal_ctx *ctx)
797 struct v4l2_ctrl *ctrl;
802 ctrl = v4l2_ctrl_find(ctx->sensor->ctrl_handler, V4L2_CID_PIXEL_RATE);
804 ctx_err(ctx, "no pixel rate control in subdev: %s\n",
809 ctx->external_rate = v4l2_ctrl_g_ctrl_int64(ctrl);
810 ctx_dbg(3, ctx, "sensor Pixel Rate: %d\n", ctx->external_rate);
815 static inline void cal_schedule_next_buffer(struct cal_ctx *ctx)
817 struct cal_dmaqueue *dma_q = &ctx->vidq;
818 struct cal_buffer *buf;
821 buf = list_entry(dma_q->active.next, struct cal_buffer, list);
823 list_del(&buf->list);
825 addr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);
826 cal_wr_dma_addr(ctx, addr);
829 static inline void cal_process_buffer_complete(struct cal_ctx *ctx)
831 ctx->cur_frm->vb.vb2_buf.timestamp = ktime_get_ns();
832 ctx->cur_frm->vb.field = ctx->m_fmt.field;
833 ctx->cur_frm->vb.sequence = ctx->sequence++;
835 vb2_buffer_done(&ctx->cur_frm->vb.vb2_buf, VB2_BUF_STATE_DONE);
836 ctx->cur_frm = ctx->next_frm;
839 #define isvcirqset(irq, vc, ff) (irq & \
840 (CAL_CSI2_VC_IRQENABLE_ ##ff ##_IRQ_##vc ##_MASK))
842 #define isportirqset(irq, port) (irq & CAL_HL_IRQ_MASK(port))
844 static irqreturn_t cal_irq(int irq_cal, void *data)
846 struct cal_dev *dev = (struct cal_dev *)data;
848 struct cal_dmaqueue *dma_q;
851 /* Check which DMA just finished */
852 irqst2 = reg_read(dev, CAL_HL_IRQSTATUS(2));
854 /* Clear Interrupt status */
855 reg_write(dev, CAL_HL_IRQSTATUS(2), irqst2);
857 /* Need to check both port */
858 if (isportirqset(irqst2, 1)) {
861 if (ctx->cur_frm != ctx->next_frm)
862 cal_process_buffer_complete(ctx);
865 if (isportirqset(irqst2, 2)) {
868 if (ctx->cur_frm != ctx->next_frm)
869 cal_process_buffer_complete(ctx);
873 /* Check which DMA just started */
874 irqst3 = reg_read(dev, CAL_HL_IRQSTATUS(3));
876 /* Clear Interrupt status */
877 reg_write(dev, CAL_HL_IRQSTATUS(3), irqst3);
879 /* Need to check both port */
880 if (isportirqset(irqst3, 1)) {
884 spin_lock(&ctx->slock);
885 if (!list_empty(&dma_q->active) &&
886 ctx->cur_frm == ctx->next_frm)
887 cal_schedule_next_buffer(ctx);
888 spin_unlock(&ctx->slock);
891 if (isportirqset(irqst3, 2)) {
895 spin_lock(&ctx->slock);
896 if (!list_empty(&dma_q->active) &&
897 ctx->cur_frm == ctx->next_frm)
898 cal_schedule_next_buffer(ctx);
899 spin_unlock(&ctx->slock);
909 static int cal_querycap(struct file *file, void *priv,
910 struct v4l2_capability *cap)
912 struct cal_ctx *ctx = video_drvdata(file);
914 strscpy(cap->driver, CAL_MODULE_NAME, sizeof(cap->driver));
915 strscpy(cap->card, CAL_MODULE_NAME, sizeof(cap->card));
917 snprintf(cap->bus_info, sizeof(cap->bus_info),
918 "platform:%s", ctx->v4l2_dev.name);
919 cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING |
921 cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
925 static int cal_enum_fmt_vid_cap(struct file *file, void *priv,
926 struct v4l2_fmtdesc *f)
928 struct cal_ctx *ctx = video_drvdata(file);
929 const struct cal_fmt *fmt = NULL;
931 if (f->index >= ctx->num_active_fmt)
934 fmt = ctx->active_fmt[f->index];
936 f->pixelformat = fmt->fourcc;
937 f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
941 static int __subdev_get_format(struct cal_ctx *ctx,
942 struct v4l2_mbus_framefmt *fmt)
944 struct v4l2_subdev_format sd_fmt;
945 struct v4l2_mbus_framefmt *mbus_fmt = &sd_fmt.format;
948 sd_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
951 ret = v4l2_subdev_call(ctx->sensor, pad, get_fmt, NULL, &sd_fmt);
957 ctx_dbg(1, ctx, "%s %dx%d code:%04X\n", __func__,
958 fmt->width, fmt->height, fmt->code);
963 static int __subdev_set_format(struct cal_ctx *ctx,
964 struct v4l2_mbus_framefmt *fmt)
966 struct v4l2_subdev_format sd_fmt;
967 struct v4l2_mbus_framefmt *mbus_fmt = &sd_fmt.format;
970 sd_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
974 ret = v4l2_subdev_call(ctx->sensor, pad, set_fmt, NULL, &sd_fmt);
978 ctx_dbg(1, ctx, "%s %dx%d code:%04X\n", __func__,
979 fmt->width, fmt->height, fmt->code);
984 static int cal_calc_format_size(struct cal_ctx *ctx,
985 const struct cal_fmt *fmt,
986 struct v4l2_format *f)
989 ctx_dbg(3, ctx, "No cal_fmt provided!\n");
993 v4l_bound_align_image(&f->fmt.pix.width, 48, MAX_WIDTH, 2,
994 &f->fmt.pix.height, 32, MAX_HEIGHT, 0, 0);
995 f->fmt.pix.bytesperline = bytes_per_line(f->fmt.pix.width,
997 f->fmt.pix.sizeimage = f->fmt.pix.height *
998 f->fmt.pix.bytesperline;
1000 ctx_dbg(3, ctx, "%s: fourcc: %s size: %dx%d bpl:%d img_size:%d\n",
1001 __func__, fourcc_to_str(f->fmt.pix.pixelformat),
1002 f->fmt.pix.width, f->fmt.pix.height,
1003 f->fmt.pix.bytesperline, f->fmt.pix.sizeimage);
1008 static int cal_g_fmt_vid_cap(struct file *file, void *priv,
1009 struct v4l2_format *f)
1011 struct cal_ctx *ctx = video_drvdata(file);
1018 static int cal_try_fmt_vid_cap(struct file *file, void *priv,
1019 struct v4l2_format *f)
1021 struct cal_ctx *ctx = video_drvdata(file);
1022 const struct cal_fmt *fmt;
1023 struct v4l2_subdev_frame_size_enum fse;
1026 fmt = find_format_by_pix(ctx, f->fmt.pix.pixelformat);
1028 ctx_dbg(3, ctx, "Fourcc format (0x%08x) not found.\n",
1029 f->fmt.pix.pixelformat);
1031 /* Just get the first one enumerated */
1032 fmt = ctx->active_fmt[0];
1033 f->fmt.pix.pixelformat = fmt->fourcc;
1036 f->fmt.pix.field = ctx->v_fmt.fmt.pix.field;
1038 /* check for/find a valid width/height */
1042 fse.code = fmt->code;
1043 fse.which = V4L2_SUBDEV_FORMAT_ACTIVE;
1044 for (fse.index = 0; ; fse.index++) {
1045 ret = v4l2_subdev_call(ctx->sensor, pad, enum_frame_size,
1050 if ((f->fmt.pix.width == fse.max_width) &&
1051 (f->fmt.pix.height == fse.max_height)) {
1054 } else if ((f->fmt.pix.width >= fse.min_width) &&
1055 (f->fmt.pix.width <= fse.max_width) &&
1056 (f->fmt.pix.height >= fse.min_height) &&
1057 (f->fmt.pix.height <= fse.max_height)) {
1064 /* use existing values as default */
1065 f->fmt.pix.width = ctx->v_fmt.fmt.pix.width;
1066 f->fmt.pix.height = ctx->v_fmt.fmt.pix.height;
1070 * Use current colorspace for now, it will get
1071 * updated properly during s_fmt
1073 f->fmt.pix.colorspace = ctx->v_fmt.fmt.pix.colorspace;
1074 return cal_calc_format_size(ctx, fmt, f);
1077 static int cal_s_fmt_vid_cap(struct file *file, void *priv,
1078 struct v4l2_format *f)
1080 struct cal_ctx *ctx = video_drvdata(file);
1081 struct vb2_queue *q = &ctx->vb_vidq;
1082 const struct cal_fmt *fmt;
1083 struct v4l2_mbus_framefmt mbus_fmt;
1086 if (vb2_is_busy(q)) {
1087 ctx_dbg(3, ctx, "%s device busy\n", __func__);
1091 ret = cal_try_fmt_vid_cap(file, priv, f);
1095 fmt = find_format_by_pix(ctx, f->fmt.pix.pixelformat);
1097 v4l2_fill_mbus_format(&mbus_fmt, &f->fmt.pix, fmt->code);
1099 ret = __subdev_set_format(ctx, &mbus_fmt);
1103 /* Just double check nothing has gone wrong */
1104 if (mbus_fmt.code != fmt->code) {
1106 "%s subdev changed format on us, this should not happen\n",
1111 v4l2_fill_pix_format(&ctx->v_fmt.fmt.pix, &mbus_fmt);
1112 ctx->v_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1113 ctx->v_fmt.fmt.pix.pixelformat = fmt->fourcc;
1114 cal_calc_format_size(ctx, fmt, &ctx->v_fmt);
1116 ctx->m_fmt = mbus_fmt;
1122 static int cal_enum_framesizes(struct file *file, void *fh,
1123 struct v4l2_frmsizeenum *fsize)
1125 struct cal_ctx *ctx = video_drvdata(file);
1126 const struct cal_fmt *fmt;
1127 struct v4l2_subdev_frame_size_enum fse;
1130 /* check for valid format */
1131 fmt = find_format_by_pix(ctx, fsize->pixel_format);
1133 ctx_dbg(3, ctx, "Invalid pixel code: %x\n",
1134 fsize->pixel_format);
1138 fse.index = fsize->index;
1140 fse.code = fmt->code;
1142 ret = v4l2_subdev_call(ctx->sensor, pad, enum_frame_size, NULL, &fse);
1146 ctx_dbg(1, ctx, "%s: index: %d code: %x W:[%d,%d] H:[%d,%d]\n",
1147 __func__, fse.index, fse.code, fse.min_width, fse.max_width,
1148 fse.min_height, fse.max_height);
1150 fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
1151 fsize->discrete.width = fse.max_width;
1152 fsize->discrete.height = fse.max_height;
1157 static int cal_enum_input(struct file *file, void *priv,
1158 struct v4l2_input *inp)
1160 if (inp->index >= CAL_NUM_INPUT)
1163 inp->type = V4L2_INPUT_TYPE_CAMERA;
1164 sprintf(inp->name, "Camera %u", inp->index);
1168 static int cal_g_input(struct file *file, void *priv, unsigned int *i)
1170 struct cal_ctx *ctx = video_drvdata(file);
1176 static int cal_s_input(struct file *file, void *priv, unsigned int i)
1178 struct cal_ctx *ctx = video_drvdata(file);
1180 if (i >= CAL_NUM_INPUT)
1187 /* timeperframe is arbitrary and continuous */
1188 static int cal_enum_frameintervals(struct file *file, void *priv,
1189 struct v4l2_frmivalenum *fival)
1191 struct cal_ctx *ctx = video_drvdata(file);
1192 const struct cal_fmt *fmt;
1193 struct v4l2_subdev_frame_interval_enum fie = {
1194 .index = fival->index,
1195 .width = fival->width,
1196 .height = fival->height,
1197 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1201 fmt = find_format_by_pix(ctx, fival->pixel_format);
1205 fie.code = fmt->code;
1206 ret = v4l2_subdev_call(ctx->sensor, pad, enum_frame_interval,
1210 fival->type = V4L2_FRMIVAL_TYPE_DISCRETE;
1211 fival->discrete = fie.interval;
1217 * Videobuf operations
1219 static int cal_queue_setup(struct vb2_queue *vq,
1220 unsigned int *nbuffers, unsigned int *nplanes,
1221 unsigned int sizes[], struct device *alloc_devs[])
1223 struct cal_ctx *ctx = vb2_get_drv_priv(vq);
1224 unsigned size = ctx->v_fmt.fmt.pix.sizeimage;
1226 if (vq->num_buffers + *nbuffers < 3)
1227 *nbuffers = 3 - vq->num_buffers;
1230 if (sizes[0] < size)
1238 ctx_dbg(3, ctx, "nbuffers=%d, size=%d\n", *nbuffers, sizes[0]);
1243 static int cal_buffer_prepare(struct vb2_buffer *vb)
1245 struct cal_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
1246 struct cal_buffer *buf = container_of(vb, struct cal_buffer,
1250 if (WARN_ON(!ctx->fmt))
1253 size = ctx->v_fmt.fmt.pix.sizeimage;
1254 if (vb2_plane_size(vb, 0) < size) {
1256 "data will not fit into plane (%lu < %lu)\n",
1257 vb2_plane_size(vb, 0), size);
1261 vb2_set_plane_payload(&buf->vb.vb2_buf, 0, size);
1265 static void cal_buffer_queue(struct vb2_buffer *vb)
1267 struct cal_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
1268 struct cal_buffer *buf = container_of(vb, struct cal_buffer,
1270 struct cal_dmaqueue *vidq = &ctx->vidq;
1271 unsigned long flags = 0;
1273 /* recheck locking */
1274 spin_lock_irqsave(&ctx->slock, flags);
1275 list_add_tail(&buf->list, &vidq->active);
1276 spin_unlock_irqrestore(&ctx->slock, flags);
1279 static int cal_start_streaming(struct vb2_queue *vq, unsigned int count)
1281 struct cal_ctx *ctx = vb2_get_drv_priv(vq);
1282 struct cal_dmaqueue *dma_q = &ctx->vidq;
1283 struct cal_buffer *buf, *tmp;
1284 unsigned long addr = 0;
1285 unsigned long flags;
1288 spin_lock_irqsave(&ctx->slock, flags);
1289 if (list_empty(&dma_q->active)) {
1290 spin_unlock_irqrestore(&ctx->slock, flags);
1291 ctx_dbg(3, ctx, "buffer queue is empty\n");
1295 buf = list_entry(dma_q->active.next, struct cal_buffer, list);
1297 ctx->next_frm = buf;
1298 list_del(&buf->list);
1299 spin_unlock_irqrestore(&ctx->slock, flags);
1301 addr = vb2_dma_contig_plane_dma_addr(&ctx->cur_frm->vb.vb2_buf, 0);
1304 ret = cal_get_external_info(ctx);
1308 cal_runtime_get(ctx->dev);
1311 camerarx_phy_enable(ctx);
1313 csi2_phy_config(ctx);
1314 csi2_lane_config(ctx);
1315 csi2_ctx_config(ctx);
1316 pix_proc_config(ctx);
1317 cal_wr_dma_config(ctx, ctx->v_fmt.fmt.pix.bytesperline);
1318 cal_wr_dma_addr(ctx, addr);
1319 csi2_ppi_enable(ctx);
1321 ret = v4l2_subdev_call(ctx->sensor, video, s_stream, 1);
1323 ctx_err(ctx, "stream on failed in subdev\n");
1324 cal_runtime_put(ctx->dev);
1329 cal_quickdump_regs(ctx->dev);
1334 list_for_each_entry_safe(buf, tmp, &dma_q->active, list) {
1335 list_del(&buf->list);
1336 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED);
1341 static void cal_stop_streaming(struct vb2_queue *vq)
1343 struct cal_ctx *ctx = vb2_get_drv_priv(vq);
1344 struct cal_dmaqueue *dma_q = &ctx->vidq;
1345 struct cal_buffer *buf, *tmp;
1346 unsigned long flags;
1348 if (v4l2_subdev_call(ctx->sensor, video, s_stream, 0))
1349 ctx_err(ctx, "stream off failed in subdev\n");
1351 csi2_ppi_disable(ctx);
1354 /* Release all active buffers */
1355 spin_lock_irqsave(&ctx->slock, flags);
1356 list_for_each_entry_safe(buf, tmp, &dma_q->active, list) {
1357 list_del(&buf->list);
1358 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
1361 if (ctx->cur_frm == ctx->next_frm) {
1362 vb2_buffer_done(&ctx->cur_frm->vb.vb2_buf, VB2_BUF_STATE_ERROR);
1364 vb2_buffer_done(&ctx->cur_frm->vb.vb2_buf, VB2_BUF_STATE_ERROR);
1365 vb2_buffer_done(&ctx->next_frm->vb.vb2_buf,
1366 VB2_BUF_STATE_ERROR);
1368 ctx->cur_frm = NULL;
1369 ctx->next_frm = NULL;
1370 spin_unlock_irqrestore(&ctx->slock, flags);
1372 cal_runtime_put(ctx->dev);
1375 static const struct vb2_ops cal_video_qops = {
1376 .queue_setup = cal_queue_setup,
1377 .buf_prepare = cal_buffer_prepare,
1378 .buf_queue = cal_buffer_queue,
1379 .start_streaming = cal_start_streaming,
1380 .stop_streaming = cal_stop_streaming,
1381 .wait_prepare = vb2_ops_wait_prepare,
1382 .wait_finish = vb2_ops_wait_finish,
1385 static const struct v4l2_file_operations cal_fops = {
1386 .owner = THIS_MODULE,
1387 .open = v4l2_fh_open,
1388 .release = vb2_fop_release,
1389 .read = vb2_fop_read,
1390 .poll = vb2_fop_poll,
1391 .unlocked_ioctl = video_ioctl2, /* V4L2 ioctl handler */
1392 .mmap = vb2_fop_mmap,
1395 static const struct v4l2_ioctl_ops cal_ioctl_ops = {
1396 .vidioc_querycap = cal_querycap,
1397 .vidioc_enum_fmt_vid_cap = cal_enum_fmt_vid_cap,
1398 .vidioc_g_fmt_vid_cap = cal_g_fmt_vid_cap,
1399 .vidioc_try_fmt_vid_cap = cal_try_fmt_vid_cap,
1400 .vidioc_s_fmt_vid_cap = cal_s_fmt_vid_cap,
1401 .vidioc_enum_framesizes = cal_enum_framesizes,
1402 .vidioc_reqbufs = vb2_ioctl_reqbufs,
1403 .vidioc_create_bufs = vb2_ioctl_create_bufs,
1404 .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
1405 .vidioc_querybuf = vb2_ioctl_querybuf,
1406 .vidioc_qbuf = vb2_ioctl_qbuf,
1407 .vidioc_dqbuf = vb2_ioctl_dqbuf,
1408 .vidioc_enum_input = cal_enum_input,
1409 .vidioc_g_input = cal_g_input,
1410 .vidioc_s_input = cal_s_input,
1411 .vidioc_enum_frameintervals = cal_enum_frameintervals,
1412 .vidioc_streamon = vb2_ioctl_streamon,
1413 .vidioc_streamoff = vb2_ioctl_streamoff,
1414 .vidioc_log_status = v4l2_ctrl_log_status,
1415 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1416 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1419 static const struct video_device cal_videodev = {
1420 .name = CAL_MODULE_NAME,
1422 .ioctl_ops = &cal_ioctl_ops,
1424 .release = video_device_release_empty,
1427 /* -----------------------------------------------------------------
1428 * Initialization and module stuff
1429 * ------------------------------------------------------------------
1431 static int cal_complete_ctx(struct cal_ctx *ctx);
1433 static int cal_async_bound(struct v4l2_async_notifier *notifier,
1434 struct v4l2_subdev *subdev,
1435 struct v4l2_async_subdev *asd)
1437 struct cal_ctx *ctx = notifier_to_ctx(notifier);
1438 struct v4l2_subdev_mbus_code_enum mbus_code;
1443 ctx_info(ctx, "Rejecting subdev %s (Already set!!)",
1448 ctx->sensor = subdev;
1449 ctx_dbg(1, ctx, "Using sensor %s for capture\n", subdev->name);
1451 /* Enumerate sub device formats and enable all matching local formats */
1452 ctx->num_active_fmt = 0;
1453 for (j = 0, i = 0; ret != -EINVAL; ++j) {
1454 struct cal_fmt *fmt;
1456 memset(&mbus_code, 0, sizeof(mbus_code));
1457 mbus_code.index = j;
1458 ret = v4l2_subdev_call(subdev, pad, enum_mbus_code,
1464 "subdev %s: code: %04x idx: %d\n",
1465 subdev->name, mbus_code.code, j);
1467 for (k = 0; k < ARRAY_SIZE(cal_formats); k++) {
1468 fmt = &cal_formats[k];
1470 if (mbus_code.code == fmt->code) {
1471 ctx->active_fmt[i] = fmt;
1473 "matched fourcc: %s: code: %04x idx: %d\n",
1474 fourcc_to_str(fmt->fourcc),
1476 ctx->num_active_fmt = ++i;
1482 ctx_err(ctx, "No suitable format reported by subdev %s\n",
1487 cal_complete_ctx(ctx);
1492 static int cal_async_complete(struct v4l2_async_notifier *notifier)
1494 struct cal_ctx *ctx = notifier_to_ctx(notifier);
1495 const struct cal_fmt *fmt;
1496 struct v4l2_mbus_framefmt mbus_fmt;
1499 ret = __subdev_get_format(ctx, &mbus_fmt);
1503 fmt = find_format_by_code(ctx, mbus_fmt.code);
1505 ctx_dbg(3, ctx, "mbus code format (0x%08x) not found.\n",
1510 /* Save current subdev format */
1511 v4l2_fill_pix_format(&ctx->v_fmt.fmt.pix, &mbus_fmt);
1512 ctx->v_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1513 ctx->v_fmt.fmt.pix.pixelformat = fmt->fourcc;
1514 cal_calc_format_size(ctx, fmt, &ctx->v_fmt);
1516 ctx->m_fmt = mbus_fmt;
1521 static const struct v4l2_async_notifier_operations cal_async_ops = {
1522 .bound = cal_async_bound,
1523 .complete = cal_async_complete,
1526 static int cal_complete_ctx(struct cal_ctx *ctx)
1528 struct video_device *vfd;
1529 struct vb2_queue *q;
1532 ctx->timeperframe = tpf_default;
1533 ctx->external_rate = 192000000;
1535 /* initialize locks */
1536 spin_lock_init(&ctx->slock);
1537 mutex_init(&ctx->mutex);
1539 /* initialize queue */
1541 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1542 q->io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ;
1544 q->buf_struct_size = sizeof(struct cal_buffer);
1545 q->ops = &cal_video_qops;
1546 q->mem_ops = &vb2_dma_contig_memops;
1547 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1548 q->lock = &ctx->mutex;
1549 q->min_buffers_needed = 3;
1550 q->dev = ctx->v4l2_dev.dev;
1552 ret = vb2_queue_init(q);
1556 /* init video dma queues */
1557 INIT_LIST_HEAD(&ctx->vidq.active);
1560 *vfd = cal_videodev;
1561 vfd->v4l2_dev = &ctx->v4l2_dev;
1565 * Provide a mutex to v4l2 core. It will be used to protect
1566 * all fops and v4l2 ioctls.
1568 vfd->lock = &ctx->mutex;
1569 video_set_drvdata(vfd, ctx);
1571 ret = video_register_device(vfd, VFL_TYPE_GRABBER, video_nr);
1575 v4l2_info(&ctx->v4l2_dev, "V4L2 device registered as %s\n",
1576 video_device_node_name(vfd));
1581 static struct device_node *
1582 of_get_next_port(const struct device_node *parent,
1583 struct device_node *prev)
1585 struct device_node *port = NULL;
1591 struct device_node *ports;
1593 * It's the first call, we have to find a port subnode
1594 * within this node or within an optional 'ports' node.
1596 ports = of_get_child_by_name(parent, "ports");
1600 port = of_get_child_by_name(parent, "port");
1602 /* release the 'ports' node */
1605 struct device_node *ports;
1607 ports = of_get_parent(prev);
1612 port = of_get_next_child(ports, prev);
1618 } while (!of_node_name_eq(port, "port"));
1624 static struct device_node *
1625 of_get_next_endpoint(const struct device_node *parent,
1626 struct device_node *prev)
1628 struct device_node *ep = NULL;
1634 ep = of_get_next_child(parent, prev);
1638 } while (!of_node_name_eq(ep, "endpoint"));
1643 static int of_cal_create_instance(struct cal_ctx *ctx, int inst)
1645 struct platform_device *pdev = ctx->dev->pdev;
1646 struct device_node *ep_node, *port, *sensor_node, *parent;
1647 struct v4l2_fwnode_endpoint *endpoint;
1648 struct v4l2_async_subdev *asd;
1650 int ret, index, found_port = 0, lane;
1652 parent = pdev->dev.of_node;
1655 endpoint = &ctx->endpoint;
1662 ctx_dbg(3, ctx, "Scanning Port node for csi2 port: %d\n", inst);
1663 for (index = 0; index < CAL_NUM_CSI2_PORTS; index++) {
1664 port = of_get_next_port(parent, port);
1666 ctx_dbg(1, ctx, "No port node found for csi2 port:%d\n",
1671 /* Match the slice number with <REG> */
1672 of_property_read_u32(port, "reg", ®val);
1673 ctx_dbg(3, ctx, "port:%d inst:%d <reg>:%d\n",
1674 index, inst, regval);
1675 if ((regval == inst) && (index == inst)) {
1682 ctx_dbg(1, ctx, "No port node matches csi2 port:%d\n",
1687 ctx_dbg(3, ctx, "Scanning sub-device for csi2 port: %d\n",
1690 ep_node = of_get_next_endpoint(port, ep_node);
1692 ctx_dbg(3, ctx, "can't get next endpoint\n");
1696 sensor_node = of_graph_get_remote_port_parent(ep_node);
1698 ctx_dbg(3, ctx, "can't get remote parent\n");
1701 asd->match_type = V4L2_ASYNC_MATCH_FWNODE;
1702 asd->match.fwnode = of_fwnode_handle(sensor_node);
1704 v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep_node), endpoint);
1706 if (endpoint->bus_type != V4L2_MBUS_CSI2_DPHY) {
1707 ctx_err(ctx, "Port:%d sub-device %pOFn is not a CSI2 device\n",
1712 /* Store Virtual Channel number */
1713 ctx->virtual_channel = endpoint->base.id;
1715 ctx_dbg(3, ctx, "Port:%d v4l2-endpoint: CSI2\n", inst);
1716 ctx_dbg(3, ctx, "Virtual Channel=%d\n", ctx->virtual_channel);
1717 ctx_dbg(3, ctx, "flags=0x%08x\n", endpoint->bus.mipi_csi2.flags);
1718 ctx_dbg(3, ctx, "clock_lane=%d\n", endpoint->bus.mipi_csi2.clock_lane);
1719 ctx_dbg(3, ctx, "num_data_lanes=%d\n",
1720 endpoint->bus.mipi_csi2.num_data_lanes);
1721 ctx_dbg(3, ctx, "data_lanes= <\n");
1722 for (lane = 0; lane < endpoint->bus.mipi_csi2.num_data_lanes; lane++)
1723 ctx_dbg(3, ctx, "\t%d\n",
1724 endpoint->bus.mipi_csi2.data_lanes[lane]);
1725 ctx_dbg(3, ctx, "\t>\n");
1727 ctx_dbg(1, ctx, "Port: %d found sub-device %pOFn\n",
1730 v4l2_async_notifier_init(&ctx->notifier);
1732 ret = v4l2_async_notifier_add_subdev(&ctx->notifier, asd);
1734 ctx_err(ctx, "Error adding asd\n");
1738 ctx->notifier.ops = &cal_async_ops;
1739 ret = v4l2_async_notifier_register(&ctx->v4l2_dev,
1742 ctx_err(ctx, "Error registering async notifier\n");
1743 v4l2_async_notifier_cleanup(&ctx->notifier);
1748 * On success we need to keep reference on sensor_node, or
1749 * if notifier_cleanup was called above, sensor_node was
1755 of_node_put(sensor_node);
1756 of_node_put(ep_node);
1762 static struct cal_ctx *cal_create_instance(struct cal_dev *dev, int inst)
1764 struct cal_ctx *ctx;
1765 struct v4l2_ctrl_handler *hdl;
1768 ctx = devm_kzalloc(&dev->pdev->dev, sizeof(*ctx), GFP_KERNEL);
1772 /* save the cal_dev * for future ref */
1775 snprintf(ctx->v4l2_dev.name, sizeof(ctx->v4l2_dev.name),
1776 "%s-%03d", CAL_MODULE_NAME, inst);
1777 ret = v4l2_device_register(&dev->pdev->dev, &ctx->v4l2_dev);
1781 hdl = &ctx->ctrl_handler;
1782 ret = v4l2_ctrl_handler_init(hdl, 11);
1784 ctx_err(ctx, "Failed to init ctrl handler\n");
1787 ctx->v4l2_dev.ctrl_handler = hdl;
1789 /* Make sure Camera Core H/W register area is available */
1790 ctx->cc = dev->cc[inst];
1792 /* Store the instance id */
1793 ctx->csi2_port = inst + 1;
1795 ret = of_cal_create_instance(ctx, inst);
1803 v4l2_ctrl_handler_free(hdl);
1805 v4l2_device_unregister(&ctx->v4l2_dev);
1810 static int cal_probe(struct platform_device *pdev)
1812 struct cal_dev *dev;
1813 struct cal_ctx *ctx;
1818 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
1822 /* set pseudo v4l2 device name so we can use v4l2_printk */
1823 strscpy(dev->v4l2_dev.name, CAL_MODULE_NAME,
1824 sizeof(dev->v4l2_dev.name));
1826 /* save pdev pointer */
1829 dev->res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1831 dev->base = devm_ioremap_resource(&pdev->dev, dev->res);
1832 if (IS_ERR(dev->base))
1833 return PTR_ERR(dev->base);
1835 cal_dbg(1, dev, "ioresource %s at %pa - %pa\n",
1836 dev->res->name, &dev->res->start, &dev->res->end);
1838 irq = platform_get_irq(pdev, 0);
1839 cal_dbg(1, dev, "got irq# %d\n", irq);
1840 ret = devm_request_irq(&pdev->dev, irq, cal_irq, 0, CAL_MODULE_NAME,
1845 platform_set_drvdata(pdev, dev);
1847 dev->cm = cm_create(dev);
1848 if (IS_ERR(dev->cm))
1849 return PTR_ERR(dev->cm);
1851 dev->cc[0] = cc_create(dev, 0);
1852 if (IS_ERR(dev->cc[0]))
1853 return PTR_ERR(dev->cc[0]);
1855 dev->cc[1] = cc_create(dev, 1);
1856 if (IS_ERR(dev->cc[1]))
1857 return PTR_ERR(dev->cc[1]);
1862 dev->ctx[0] = cal_create_instance(dev, 0);
1863 dev->ctx[1] = cal_create_instance(dev, 1);
1864 if (!dev->ctx[0] && !dev->ctx[1]) {
1865 cal_err(dev, "Neither port is configured, no point in staying up\n");
1869 pm_runtime_enable(&pdev->dev);
1871 ret = cal_runtime_get(dev);
1873 goto runtime_disable;
1875 /* Just check we can actually access the module */
1876 cal_get_hwinfo(dev);
1878 cal_runtime_put(dev);
1883 pm_runtime_disable(&pdev->dev);
1884 for (i = 0; i < CAL_NUM_CONTEXT; i++) {
1887 v4l2_async_notifier_unregister(&ctx->notifier);
1888 v4l2_async_notifier_cleanup(&ctx->notifier);
1889 v4l2_ctrl_handler_free(&ctx->ctrl_handler);
1890 v4l2_device_unregister(&ctx->v4l2_dev);
1897 static int cal_remove(struct platform_device *pdev)
1899 struct cal_dev *dev =
1900 (struct cal_dev *)platform_get_drvdata(pdev);
1901 struct cal_ctx *ctx;
1904 cal_dbg(1, dev, "Removing %s\n", CAL_MODULE_NAME);
1906 cal_runtime_get(dev);
1908 for (i = 0; i < CAL_NUM_CONTEXT; i++) {
1911 ctx_dbg(1, ctx, "unregistering %s\n",
1912 video_device_node_name(&ctx->vdev));
1913 camerarx_phy_disable(ctx);
1914 v4l2_async_notifier_unregister(&ctx->notifier);
1915 v4l2_async_notifier_cleanup(&ctx->notifier);
1916 v4l2_ctrl_handler_free(&ctx->ctrl_handler);
1917 v4l2_device_unregister(&ctx->v4l2_dev);
1918 video_unregister_device(&ctx->vdev);
1922 cal_runtime_put(dev);
1923 pm_runtime_disable(&pdev->dev);
1928 #if defined(CONFIG_OF)
1929 static const struct of_device_id cal_of_match[] = {
1930 { .compatible = "ti,dra72-cal", },
1933 MODULE_DEVICE_TABLE(of, cal_of_match);
1936 static struct platform_driver cal_pdrv = {
1938 .remove = cal_remove,
1940 .name = CAL_MODULE_NAME,
1941 .of_match_table = of_match_ptr(cal_of_match),
1945 module_platform_driver(cal_pdrv);