2 * V4L2 Driver for i.MX27 camera host
4 * Copyright (C) 2008, Sascha Hauer, Pengutronix
5 * Copyright (C) 2010, Baruch Siach, Orex Computed Radiography
6 * Copyright (C) 2012, Javier Martin, Vista Silicon S.L.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/init.h>
15 #include <linux/module.h>
17 #include <linux/delay.h>
18 #include <linux/slab.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/errno.h>
22 #include <linux/gcd.h>
23 #include <linux/interrupt.h>
24 #include <linux/kernel.h>
25 #include <linux/math64.h>
27 #include <linux/moduleparam.h>
28 #include <linux/time.h>
29 #include <linux/device.h>
30 #include <linux/platform_device.h>
31 #include <linux/clk.h>
33 #include <media/v4l2-common.h>
34 #include <media/v4l2-dev.h>
35 #include <media/videobuf2-core.h>
36 #include <media/videobuf2-dma-contig.h>
37 #include <media/soc_camera.h>
38 #include <media/soc_mediabus.h>
40 #include <linux/videodev2.h>
42 #include <linux/platform_data/camera-mx2.h>
46 #define MX2_CAM_DRV_NAME "mx2-camera"
47 #define MX2_CAM_VERSION "0.0.6"
48 #define MX2_CAM_DRIVER_DESCRIPTION "i.MX2x_Camera"
51 #define CSICR1_RESET_VAL 0x40000800
52 #define CSICR2_RESET_VAL 0x0
53 #define CSICR3_RESET_VAL 0x0
55 /* csi control reg 1 */
56 #define CSICR1_SWAP16_EN (1 << 31)
57 #define CSICR1_EXT_VSYNC (1 << 30)
58 #define CSICR1_EOF_INTEN (1 << 29)
59 #define CSICR1_PRP_IF_EN (1 << 28)
60 #define CSICR1_CCIR_MODE (1 << 27)
61 #define CSICR1_COF_INTEN (1 << 26)
62 #define CSICR1_SF_OR_INTEN (1 << 25)
63 #define CSICR1_RF_OR_INTEN (1 << 24)
64 #define CSICR1_STATFF_LEVEL (3 << 22)
65 #define CSICR1_STATFF_INTEN (1 << 21)
66 #define CSICR1_RXFF_LEVEL(l) (((l) & 3) << 19)
67 #define CSICR1_RXFF_INTEN (1 << 18)
68 #define CSICR1_SOF_POL (1 << 17)
69 #define CSICR1_SOF_INTEN (1 << 16)
70 #define CSICR1_MCLKDIV(d) (((d) & 0xF) << 12)
71 #define CSICR1_HSYNC_POL (1 << 11)
72 #define CSICR1_CCIR_EN (1 << 10)
73 #define CSICR1_MCLKEN (1 << 9)
74 #define CSICR1_FCC (1 << 8)
75 #define CSICR1_PACK_DIR (1 << 7)
76 #define CSICR1_CLR_STATFIFO (1 << 6)
77 #define CSICR1_CLR_RXFIFO (1 << 5)
78 #define CSICR1_GCLK_MODE (1 << 4)
79 #define CSICR1_INV_DATA (1 << 3)
80 #define CSICR1_INV_PCLK (1 << 2)
81 #define CSICR1_REDGE (1 << 1)
82 #define CSICR1_FMT_MASK (CSICR1_PACK_DIR | CSICR1_SWAP16_EN)
84 #define SHIFT_STATFF_LEVEL 22
85 #define SHIFT_RXFF_LEVEL 19
86 #define SHIFT_MCLKDIV 12
88 #define SHIFT_FRMCNT 16
93 #define CSISTATFIFO 0x0c
97 #define CSIDMASA_STATFIFO 0x20
98 #define CSIDMATA_STATFIFO 0x24
99 #define CSIDMASA_FB1 0x28
100 #define CSIDMASA_FB2 0x2c
101 #define CSIFBUF_PARA 0x30
102 #define CSIIMAG_PARA 0x34
105 #define PRP_CNTL 0x00
106 #define PRP_INTR_CNTL 0x04
107 #define PRP_INTRSTATUS 0x08
108 #define PRP_SOURCE_Y_PTR 0x0c
109 #define PRP_SOURCE_CB_PTR 0x10
110 #define PRP_SOURCE_CR_PTR 0x14
111 #define PRP_DEST_RGB1_PTR 0x18
112 #define PRP_DEST_RGB2_PTR 0x1c
113 #define PRP_DEST_Y_PTR 0x20
114 #define PRP_DEST_CB_PTR 0x24
115 #define PRP_DEST_CR_PTR 0x28
116 #define PRP_SRC_FRAME_SIZE 0x2c
117 #define PRP_DEST_CH1_LINE_STRIDE 0x30
118 #define PRP_SRC_PIXEL_FORMAT_CNTL 0x34
119 #define PRP_CH1_PIXEL_FORMAT_CNTL 0x38
120 #define PRP_CH1_OUT_IMAGE_SIZE 0x3c
121 #define PRP_CH2_OUT_IMAGE_SIZE 0x40
122 #define PRP_SRC_LINE_STRIDE 0x44
123 #define PRP_CSC_COEF_012 0x48
124 #define PRP_CSC_COEF_345 0x4c
125 #define PRP_CSC_COEF_678 0x50
126 #define PRP_CH1_RZ_HORI_COEF1 0x54
127 #define PRP_CH1_RZ_HORI_COEF2 0x58
128 #define PRP_CH1_RZ_HORI_VALID 0x5c
129 #define PRP_CH1_RZ_VERT_COEF1 0x60
130 #define PRP_CH1_RZ_VERT_COEF2 0x64
131 #define PRP_CH1_RZ_VERT_VALID 0x68
132 #define PRP_CH2_RZ_HORI_COEF1 0x6c
133 #define PRP_CH2_RZ_HORI_COEF2 0x70
134 #define PRP_CH2_RZ_HORI_VALID 0x74
135 #define PRP_CH2_RZ_VERT_COEF1 0x78
136 #define PRP_CH2_RZ_VERT_COEF2 0x7c
137 #define PRP_CH2_RZ_VERT_VALID 0x80
139 #define PRP_CNTL_CH1EN (1 << 0)
140 #define PRP_CNTL_CH2EN (1 << 1)
141 #define PRP_CNTL_CSIEN (1 << 2)
142 #define PRP_CNTL_DATA_IN_YUV420 (0 << 3)
143 #define PRP_CNTL_DATA_IN_YUV422 (1 << 3)
144 #define PRP_CNTL_DATA_IN_RGB16 (2 << 3)
145 #define PRP_CNTL_DATA_IN_RGB32 (3 << 3)
146 #define PRP_CNTL_CH1_OUT_RGB8 (0 << 5)
147 #define PRP_CNTL_CH1_OUT_RGB16 (1 << 5)
148 #define PRP_CNTL_CH1_OUT_RGB32 (2 << 5)
149 #define PRP_CNTL_CH1_OUT_YUV422 (3 << 5)
150 #define PRP_CNTL_CH2_OUT_YUV420 (0 << 7)
151 #define PRP_CNTL_CH2_OUT_YUV422 (1 << 7)
152 #define PRP_CNTL_CH2_OUT_YUV444 (2 << 7)
153 #define PRP_CNTL_CH1_LEN (1 << 9)
154 #define PRP_CNTL_CH2_LEN (1 << 10)
155 #define PRP_CNTL_SKIP_FRAME (1 << 11)
156 #define PRP_CNTL_SWRST (1 << 12)
157 #define PRP_CNTL_CLKEN (1 << 13)
158 #define PRP_CNTL_WEN (1 << 14)
159 #define PRP_CNTL_CH1BYP (1 << 15)
160 #define PRP_CNTL_IN_TSKIP(x) ((x) << 16)
161 #define PRP_CNTL_CH1_TSKIP(x) ((x) << 19)
162 #define PRP_CNTL_CH2_TSKIP(x) ((x) << 22)
163 #define PRP_CNTL_INPUT_FIFO_LEVEL(x) ((x) << 25)
164 #define PRP_CNTL_RZ_FIFO_LEVEL(x) ((x) << 27)
165 #define PRP_CNTL_CH2B1EN (1 << 29)
166 #define PRP_CNTL_CH2B2EN (1 << 30)
167 #define PRP_CNTL_CH2FEN (1 << 31)
169 /* IRQ Enable and status register */
170 #define PRP_INTR_RDERR (1 << 0)
171 #define PRP_INTR_CH1WERR (1 << 1)
172 #define PRP_INTR_CH2WERR (1 << 2)
173 #define PRP_INTR_CH1FC (1 << 3)
174 #define PRP_INTR_CH2FC (1 << 5)
175 #define PRP_INTR_LBOVF (1 << 7)
176 #define PRP_INTR_CH2OVF (1 << 8)
178 /* Resizing registers */
179 #define PRP_RZ_VALID_TBL_LEN(x) ((x) << 24)
180 #define PRP_RZ_VALID_BILINEAR (1 << 31)
182 #define MAX_VIDEO_MEM 16
184 #define RESIZE_NUM_MIN 1
185 #define RESIZE_NUM_MAX 20
187 #define SZ_COEF (1 << BC_COEF)
189 #define RESIZE_DIR_H 0
190 #define RESIZE_DIR_V 1
192 #define RESIZE_ALGO_BILINEAR 0
193 #define RESIZE_ALGO_AVERAGING 1
205 /* prp resizing parameters */
206 struct emma_prp_resize {
207 int algo; /* type of algorithm used */
208 int len; /* number of coefficients */
209 unsigned char s[RESIZE_NUM_MAX]; /* table of coefficients */
212 /* prp configuration for a client-host fmt pair */
214 enum v4l2_mbus_pixelcode in_fmt;
216 struct mx2_prp_cfg cfg;
219 struct mx2_buf_internal {
220 struct list_head queue;
225 /* buffer for one video frame */
227 /* common v4l buffer stuff -- must be first */
228 struct vb2_buffer vb;
229 struct mx2_buf_internal internal;
232 enum mx2_camera_type {
236 struct mx2_camera_dev {
238 struct soc_camera_host soc_host;
239 struct clk *clk_emma_ahb, *clk_emma_ipg;
240 struct clk *clk_csi_ahb, *clk_csi_per;
242 void __iomem *base_csi, *base_emma;
244 struct mx2_camera_platform_data *pdata;
245 unsigned long platform_flags;
247 struct list_head capture;
248 struct list_head active_bufs;
249 struct list_head discard;
254 struct mx2_buffer *active;
255 struct mx2_buffer *fb1_active;
256 struct mx2_buffer *fb2_active;
259 enum mx2_camera_type devtype;
261 struct mx2_buf_internal buf_discard[2];
262 void *discard_buffer;
263 dma_addr_t discard_buffer_dma;
265 struct mx2_fmt_cfg *emma_prp;
266 struct emma_prp_resize resizing[2];
267 unsigned int s_width, s_height;
269 struct vb2_alloc_ctx *alloc_ctx;
272 static struct platform_device_id mx2_camera_devtype[] = {
274 .name = "imx27-camera",
275 .driver_data = IMX27_CAMERA,
280 MODULE_DEVICE_TABLE(platform, mx2_camera_devtype);
282 static struct mx2_buffer *mx2_ibuf_to_buf(struct mx2_buf_internal *int_buf)
284 return container_of(int_buf, struct mx2_buffer, internal);
287 static struct mx2_fmt_cfg mx27_emma_prp_table[] = {
289 * This is a generic configuration which is valid for most
290 * prp input-output format combinations.
291 * We set the incoming and outgoing pixelformat to a
292 * 16 Bit wide format and adjust the bytesperline
293 * accordingly. With this configuration the inputdata
294 * will not be changed by the emma and could be any type
295 * of 16 Bit Pixelformat.
302 .in_fmt = PRP_CNTL_DATA_IN_RGB16,
303 .out_fmt = PRP_CNTL_CH1_OUT_RGB16,
304 .src_pixel = 0x2ca00565, /* RGB565 */
305 .ch1_pixel = 0x2ca00565, /* RGB565 */
306 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH1WERR |
307 PRP_INTR_CH1FC | PRP_INTR_LBOVF,
312 .in_fmt = V4L2_MBUS_FMT_UYVY8_2X8,
313 .out_fmt = V4L2_PIX_FMT_YUYV,
316 .in_fmt = PRP_CNTL_DATA_IN_YUV422,
317 .out_fmt = PRP_CNTL_CH1_OUT_YUV422,
318 .src_pixel = 0x22000888, /* YUV422 (YUYV) */
319 .ch1_pixel = 0x62000888, /* YUV422 (YUYV) */
320 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH1WERR |
321 PRP_INTR_CH1FC | PRP_INTR_LBOVF,
322 .csicr1 = CSICR1_SWAP16_EN,
326 .in_fmt = V4L2_MBUS_FMT_YUYV8_2X8,
327 .out_fmt = V4L2_PIX_FMT_YUYV,
330 .in_fmt = PRP_CNTL_DATA_IN_YUV422,
331 .out_fmt = PRP_CNTL_CH1_OUT_YUV422,
332 .src_pixel = 0x22000888, /* YUV422 (YUYV) */
333 .ch1_pixel = 0x62000888, /* YUV422 (YUYV) */
334 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH1WERR |
335 PRP_INTR_CH1FC | PRP_INTR_LBOVF,
336 .csicr1 = CSICR1_PACK_DIR,
340 .in_fmt = V4L2_MBUS_FMT_YUYV8_2X8,
341 .out_fmt = V4L2_PIX_FMT_YUV420,
344 .in_fmt = PRP_CNTL_DATA_IN_YUV422,
345 .out_fmt = PRP_CNTL_CH2_OUT_YUV420,
346 .src_pixel = 0x22000888, /* YUV422 (YUYV) */
347 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH2WERR |
348 PRP_INTR_CH2FC | PRP_INTR_LBOVF |
350 .csicr1 = CSICR1_PACK_DIR,
354 .in_fmt = V4L2_MBUS_FMT_UYVY8_2X8,
355 .out_fmt = V4L2_PIX_FMT_YUV420,
358 .in_fmt = PRP_CNTL_DATA_IN_YUV422,
359 .out_fmt = PRP_CNTL_CH2_OUT_YUV420,
360 .src_pixel = 0x22000888, /* YUV422 (YUYV) */
361 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH2WERR |
362 PRP_INTR_CH2FC | PRP_INTR_LBOVF |
364 .csicr1 = CSICR1_SWAP16_EN,
369 static struct mx2_fmt_cfg *mx27_emma_prp_get_format(
370 enum v4l2_mbus_pixelcode in_fmt,
375 for (i = 1; i < ARRAY_SIZE(mx27_emma_prp_table); i++)
376 if ((mx27_emma_prp_table[i].in_fmt == in_fmt) &&
377 (mx27_emma_prp_table[i].out_fmt == out_fmt)) {
378 return &mx27_emma_prp_table[i];
380 /* If no match return the most generic configuration */
381 return &mx27_emma_prp_table[0];
384 static void mx27_update_emma_buf(struct mx2_camera_dev *pcdev,
385 unsigned long phys, int bufnum)
387 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
389 if (prp->cfg.channel == 1) {
390 writel(phys, pcdev->base_emma +
391 PRP_DEST_RGB1_PTR + 4 * bufnum);
393 writel(phys, pcdev->base_emma +
394 PRP_DEST_Y_PTR - 0x14 * bufnum);
395 if (prp->out_fmt == V4L2_PIX_FMT_YUV420) {
396 u32 imgsize = pcdev->soc_host.icd->user_height *
397 pcdev->soc_host.icd->user_width;
399 writel(phys + imgsize, pcdev->base_emma +
400 PRP_DEST_CB_PTR - 0x14 * bufnum);
401 writel(phys + ((5 * imgsize) / 4), pcdev->base_emma +
402 PRP_DEST_CR_PTR - 0x14 * bufnum);
407 static void mx2_camera_deactivate(struct mx2_camera_dev *pcdev)
409 clk_disable_unprepare(pcdev->clk_csi_ahb);
410 clk_disable_unprepare(pcdev->clk_csi_per);
411 writel(0, pcdev->base_csi + CSICR1);
412 writel(0, pcdev->base_emma + PRP_CNTL);
415 static int mx2_camera_add_device(struct soc_camera_device *icd)
417 dev_info(icd->parent, "Camera driver attached to camera %d\n",
423 static void mx2_camera_remove_device(struct soc_camera_device *icd)
425 dev_info(icd->parent, "Camera driver detached from camera %d\n",
430 * The following two functions absolutely depend on the fact, that
431 * there can be only one camera on mx2 camera sensor interface
433 static int mx2_camera_clock_start(struct soc_camera_host *ici)
435 struct mx2_camera_dev *pcdev = ici->priv;
439 ret = clk_prepare_enable(pcdev->clk_csi_ahb);
443 ret = clk_prepare_enable(pcdev->clk_csi_per);
447 csicr1 = CSICR1_MCLKEN | CSICR1_PRP_IF_EN | CSICR1_FCC |
448 CSICR1_RXFF_LEVEL(0);
450 pcdev->csicr1 = csicr1;
451 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
453 pcdev->frame_count = 0;
458 clk_disable_unprepare(pcdev->clk_csi_ahb);
463 static void mx2_camera_clock_stop(struct soc_camera_host *ici)
465 struct mx2_camera_dev *pcdev = ici->priv;
467 mx2_camera_deactivate(pcdev);
471 * Videobuf operations
473 static int mx2_videobuf_setup(struct vb2_queue *vq,
474 const struct v4l2_format *fmt,
475 unsigned int *count, unsigned int *num_planes,
476 unsigned int sizes[], void *alloc_ctxs[])
478 struct soc_camera_device *icd = soc_camera_from_vb2q(vq);
479 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
480 struct mx2_camera_dev *pcdev = ici->priv;
482 dev_dbg(icd->parent, "count=%d, size=%d\n", *count, sizes[0]);
484 /* TODO: support for VIDIOC_CREATE_BUFS not ready */
488 alloc_ctxs[0] = pcdev->alloc_ctx;
490 sizes[0] = icd->sizeimage;
495 sizes[0] * *count > MAX_VIDEO_MEM * 1024 * 1024)
496 *count = (MAX_VIDEO_MEM * 1024 * 1024) / sizes[0];
503 static int mx2_videobuf_prepare(struct vb2_buffer *vb)
505 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
508 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__,
509 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
513 * This can be useful if you want to see if we actually fill
514 * the buffer with something
516 memset((void *)vb2_plane_vaddr(vb, 0),
517 0xaa, vb2_get_plane_payload(vb, 0));
520 vb2_set_plane_payload(vb, 0, icd->sizeimage);
521 if (vb2_plane_vaddr(vb, 0) &&
522 vb2_get_plane_payload(vb, 0) > vb2_plane_size(vb, 0)) {
533 static void mx2_videobuf_queue(struct vb2_buffer *vb)
535 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
536 struct soc_camera_host *ici =
537 to_soc_camera_host(icd->parent);
538 struct mx2_camera_dev *pcdev = ici->priv;
539 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
542 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__,
543 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
545 spin_lock_irqsave(&pcdev->lock, flags);
547 list_add_tail(&buf->internal.queue, &pcdev->capture);
549 spin_unlock_irqrestore(&pcdev->lock, flags);
552 static void mx27_camera_emma_buf_init(struct soc_camera_device *icd,
555 struct soc_camera_host *ici =
556 to_soc_camera_host(icd->parent);
557 struct mx2_camera_dev *pcdev = ici->priv;
558 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
560 writel((pcdev->s_width << 16) | pcdev->s_height,
561 pcdev->base_emma + PRP_SRC_FRAME_SIZE);
562 writel(prp->cfg.src_pixel,
563 pcdev->base_emma + PRP_SRC_PIXEL_FORMAT_CNTL);
564 if (prp->cfg.channel == 1) {
565 writel((icd->user_width << 16) | icd->user_height,
566 pcdev->base_emma + PRP_CH1_OUT_IMAGE_SIZE);
568 pcdev->base_emma + PRP_DEST_CH1_LINE_STRIDE);
569 writel(prp->cfg.ch1_pixel,
570 pcdev->base_emma + PRP_CH1_PIXEL_FORMAT_CNTL);
571 } else { /* channel 2 */
572 writel((icd->user_width << 16) | icd->user_height,
573 pcdev->base_emma + PRP_CH2_OUT_IMAGE_SIZE);
576 /* Enable interrupts */
577 writel(prp->cfg.irq_flags, pcdev->base_emma + PRP_INTR_CNTL);
580 static void mx2_prp_resize_commit(struct mx2_camera_dev *pcdev)
584 for (dir = RESIZE_DIR_H; dir <= RESIZE_DIR_V; dir++) {
585 unsigned char *s = pcdev->resizing[dir].s;
586 int len = pcdev->resizing[dir].len;
587 unsigned int coeff[2] = {0, 0};
588 unsigned int valid = 0;
594 for (i = RESIZE_NUM_MAX - 1; i >= 0; i--) {
598 coeff[j] = (coeff[j] << BC_COEF) |
599 (s[i] & (SZ_COEF - 1));
601 if (i == 5 || i == 15)
604 valid = (valid << 1) | (s[i] >> BC_COEF);
607 valid |= PRP_RZ_VALID_TBL_LEN(len);
609 if (pcdev->resizing[dir].algo == RESIZE_ALGO_BILINEAR)
610 valid |= PRP_RZ_VALID_BILINEAR;
612 if (pcdev->emma_prp->cfg.channel == 1) {
613 if (dir == RESIZE_DIR_H) {
614 writel(coeff[0], pcdev->base_emma +
615 PRP_CH1_RZ_HORI_COEF1);
616 writel(coeff[1], pcdev->base_emma +
617 PRP_CH1_RZ_HORI_COEF2);
618 writel(valid, pcdev->base_emma +
619 PRP_CH1_RZ_HORI_VALID);
621 writel(coeff[0], pcdev->base_emma +
622 PRP_CH1_RZ_VERT_COEF1);
623 writel(coeff[1], pcdev->base_emma +
624 PRP_CH1_RZ_VERT_COEF2);
625 writel(valid, pcdev->base_emma +
626 PRP_CH1_RZ_VERT_VALID);
629 if (dir == RESIZE_DIR_H) {
630 writel(coeff[0], pcdev->base_emma +
631 PRP_CH2_RZ_HORI_COEF1);
632 writel(coeff[1], pcdev->base_emma +
633 PRP_CH2_RZ_HORI_COEF2);
634 writel(valid, pcdev->base_emma +
635 PRP_CH2_RZ_HORI_VALID);
637 writel(coeff[0], pcdev->base_emma +
638 PRP_CH2_RZ_VERT_COEF1);
639 writel(coeff[1], pcdev->base_emma +
640 PRP_CH2_RZ_VERT_COEF2);
641 writel(valid, pcdev->base_emma +
642 PRP_CH2_RZ_VERT_VALID);
648 static int mx2_start_streaming(struct vb2_queue *q, unsigned int count)
650 struct soc_camera_device *icd = soc_camera_from_vb2q(q);
651 struct soc_camera_host *ici =
652 to_soc_camera_host(icd->parent);
653 struct mx2_camera_dev *pcdev = ici->priv;
654 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
655 struct vb2_buffer *vb;
656 struct mx2_buffer *buf;
664 spin_lock_irqsave(&pcdev->lock, flags);
666 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
668 buf->internal.bufnum = 0;
671 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
672 mx27_update_emma_buf(pcdev, phys, buf->internal.bufnum);
673 list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
675 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
677 buf->internal.bufnum = 1;
680 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
681 mx27_update_emma_buf(pcdev, phys, buf->internal.bufnum);
682 list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
684 bytesperline = soc_mbus_bytes_per_line(icd->user_width,
685 icd->current_fmt->host_fmt);
686 if (bytesperline < 0) {
687 spin_unlock_irqrestore(&pcdev->lock, flags);
692 * I didn't manage to properly enable/disable the prp
693 * on a per frame basis during running transfers,
694 * thus we allocate a buffer here and use it to
695 * discard frames when no buffer is available.
696 * Feel free to work on this ;)
698 pcdev->discard_size = icd->user_height * bytesperline;
699 pcdev->discard_buffer = dma_alloc_coherent(ici->v4l2_dev.dev,
701 &pcdev->discard_buffer_dma, GFP_ATOMIC);
702 if (!pcdev->discard_buffer) {
703 spin_unlock_irqrestore(&pcdev->lock, flags);
707 pcdev->buf_discard[0].discard = true;
708 list_add_tail(&pcdev->buf_discard[0].queue,
711 pcdev->buf_discard[1].discard = true;
712 list_add_tail(&pcdev->buf_discard[1].queue,
715 mx2_prp_resize_commit(pcdev);
717 mx27_camera_emma_buf_init(icd, bytesperline);
719 if (prp->cfg.channel == 1) {
720 writel(PRP_CNTL_CH1EN |
726 PRP_CNTL_CH1_TSKIP(0) |
727 PRP_CNTL_IN_TSKIP(0),
728 pcdev->base_emma + PRP_CNTL);
730 writel(PRP_CNTL_CH2EN |
735 PRP_CNTL_CH2_TSKIP(0) |
736 PRP_CNTL_IN_TSKIP(0),
737 pcdev->base_emma + PRP_CNTL);
739 spin_unlock_irqrestore(&pcdev->lock, flags);
744 static void mx2_stop_streaming(struct vb2_queue *q)
746 struct soc_camera_device *icd = soc_camera_from_vb2q(q);
747 struct soc_camera_host *ici =
748 to_soc_camera_host(icd->parent);
749 struct mx2_camera_dev *pcdev = ici->priv;
750 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
755 spin_lock_irqsave(&pcdev->lock, flags);
757 cntl = readl(pcdev->base_emma + PRP_CNTL);
758 if (prp->cfg.channel == 1) {
759 writel(cntl & ~PRP_CNTL_CH1EN,
760 pcdev->base_emma + PRP_CNTL);
762 writel(cntl & ~PRP_CNTL_CH2EN,
763 pcdev->base_emma + PRP_CNTL);
765 INIT_LIST_HEAD(&pcdev->capture);
766 INIT_LIST_HEAD(&pcdev->active_bufs);
767 INIT_LIST_HEAD(&pcdev->discard);
769 b = pcdev->discard_buffer;
770 pcdev->discard_buffer = NULL;
772 spin_unlock_irqrestore(&pcdev->lock, flags);
774 dma_free_coherent(ici->v4l2_dev.dev,
775 pcdev->discard_size, b, pcdev->discard_buffer_dma);
778 static struct vb2_ops mx2_videobuf_ops = {
779 .queue_setup = mx2_videobuf_setup,
780 .buf_prepare = mx2_videobuf_prepare,
781 .buf_queue = mx2_videobuf_queue,
782 .start_streaming = mx2_start_streaming,
783 .stop_streaming = mx2_stop_streaming,
786 static int mx2_camera_init_videobuf(struct vb2_queue *q,
787 struct soc_camera_device *icd)
789 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
790 q->io_modes = VB2_MMAP | VB2_USERPTR;
792 q->ops = &mx2_videobuf_ops;
793 q->mem_ops = &vb2_dma_contig_memops;
794 q->buf_struct_size = sizeof(struct mx2_buffer);
795 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
797 return vb2_queue_init(q);
800 #define MX2_BUS_FLAGS (V4L2_MBUS_MASTER | \
801 V4L2_MBUS_VSYNC_ACTIVE_HIGH | \
802 V4L2_MBUS_VSYNC_ACTIVE_LOW | \
803 V4L2_MBUS_HSYNC_ACTIVE_HIGH | \
804 V4L2_MBUS_HSYNC_ACTIVE_LOW | \
805 V4L2_MBUS_PCLK_SAMPLE_RISING | \
806 V4L2_MBUS_PCLK_SAMPLE_FALLING | \
807 V4L2_MBUS_DATA_ACTIVE_HIGH | \
808 V4L2_MBUS_DATA_ACTIVE_LOW)
810 static int mx27_camera_emma_prp_reset(struct mx2_camera_dev *pcdev)
815 cntl = readl(pcdev->base_emma + PRP_CNTL);
816 writel(PRP_CNTL_SWRST, pcdev->base_emma + PRP_CNTL);
817 while (count++ < 100) {
818 if (!(readl(pcdev->base_emma + PRP_CNTL) & PRP_CNTL_SWRST))
827 static int mx2_camera_set_bus_param(struct soc_camera_device *icd)
829 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
830 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
831 struct mx2_camera_dev *pcdev = ici->priv;
832 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
833 unsigned long common_flags;
836 u32 csicr1 = pcdev->csicr1;
838 ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg);
840 common_flags = soc_mbus_config_compatible(&cfg, MX2_BUS_FLAGS);
842 dev_warn(icd->parent,
843 "Flags incompatible: camera 0x%x, host 0x%x\n",
844 cfg.flags, MX2_BUS_FLAGS);
847 } else if (ret != -ENOIOCTLCMD) {
850 common_flags = MX2_BUS_FLAGS;
853 if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) &&
854 (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) {
855 if (pcdev->platform_flags & MX2_CAMERA_HSYNC_HIGH)
856 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW;
858 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH;
861 if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) &&
862 (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) {
863 if (pcdev->platform_flags & MX2_CAMERA_PCLK_SAMPLE_RISING)
864 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING;
866 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING;
869 cfg.flags = common_flags;
870 ret = v4l2_subdev_call(sd, video, s_mbus_config, &cfg);
871 if (ret < 0 && ret != -ENOIOCTLCMD) {
872 dev_dbg(icd->parent, "camera s_mbus_config(0x%lx) returned %d\n",
877 csicr1 = (csicr1 & ~CSICR1_FMT_MASK) | pcdev->emma_prp->cfg.csicr1;
879 if (common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
880 csicr1 |= CSICR1_REDGE;
881 if (common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
882 csicr1 |= CSICR1_SOF_POL;
883 if (common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
884 csicr1 |= CSICR1_HSYNC_POL;
885 if (pcdev->platform_flags & MX2_CAMERA_EXT_VSYNC)
886 csicr1 |= CSICR1_EXT_VSYNC;
887 if (pcdev->platform_flags & MX2_CAMERA_CCIR)
888 csicr1 |= CSICR1_CCIR_EN;
889 if (pcdev->platform_flags & MX2_CAMERA_CCIR_INTERLACE)
890 csicr1 |= CSICR1_CCIR_MODE;
891 if (pcdev->platform_flags & MX2_CAMERA_GATED_CLOCK)
892 csicr1 |= CSICR1_GCLK_MODE;
893 if (pcdev->platform_flags & MX2_CAMERA_INV_DATA)
894 csicr1 |= CSICR1_INV_DATA;
896 pcdev->csicr1 = csicr1;
898 bytesperline = soc_mbus_bytes_per_line(icd->user_width,
899 icd->current_fmt->host_fmt);
900 if (bytesperline < 0)
903 ret = mx27_camera_emma_prp_reset(pcdev);
907 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
912 static int mx2_camera_set_crop(struct soc_camera_device *icd,
913 const struct v4l2_crop *a)
915 struct v4l2_crop a_writable = *a;
916 struct v4l2_rect *rect = &a_writable.c;
917 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
918 struct v4l2_mbus_framefmt mf;
921 soc_camera_limit_side(&rect->left, &rect->width, 0, 2, 4096);
922 soc_camera_limit_side(&rect->top, &rect->height, 0, 2, 4096);
924 ret = v4l2_subdev_call(sd, video, s_crop, a);
928 /* The capture device might have changed its output */
929 ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf);
933 dev_dbg(icd->parent, "Sensor cropped %dx%d\n",
934 mf.width, mf.height);
936 icd->user_width = mf.width;
937 icd->user_height = mf.height;
942 static int mx2_camera_get_formats(struct soc_camera_device *icd,
944 struct soc_camera_format_xlate *xlate)
946 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
947 const struct soc_mbus_pixelfmt *fmt;
948 struct device *dev = icd->parent;
949 enum v4l2_mbus_pixelcode code;
950 int ret, formats = 0;
952 ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, idx, &code);
954 /* no more formats */
957 fmt = soc_mbus_get_fmtdesc(code);
959 dev_err(dev, "Invalid format code #%u: %d\n", idx, code);
963 if (code == V4L2_MBUS_FMT_YUYV8_2X8 ||
964 code == V4L2_MBUS_FMT_UYVY8_2X8) {
968 * CH2 can output YUV420 which is a standard format in
972 soc_mbus_get_fmtdesc(V4L2_MBUS_FMT_YUYV8_1_5X8);
974 dev_dbg(dev, "Providing host format %s for sensor code %d\n",
975 xlate->host_fmt->name, code);
980 if (code == V4L2_MBUS_FMT_UYVY8_2X8) {
984 soc_mbus_get_fmtdesc(V4L2_MBUS_FMT_YUYV8_2X8);
986 dev_dbg(dev, "Providing host format %s for sensor code %d\n",
987 xlate->host_fmt->name, code);
992 /* Generic pass-trough */
995 xlate->host_fmt = fmt;
1002 static int mx2_emmaprp_resize(struct mx2_camera_dev *pcdev,
1003 struct v4l2_mbus_framefmt *mf_in,
1004 struct v4l2_pix_format *pix_out, bool apply)
1010 for (dir = RESIZE_DIR_H; dir <= RESIZE_DIR_V; dir++) {
1011 struct emma_prp_resize tmprsz;
1012 unsigned char *s = tmprsz.s;
1016 if (dir == RESIZE_DIR_H) {
1018 out = pix_out->width;
1021 out = pix_out->height;
1029 /* Calculate ratio */
1033 if (num > RESIZE_NUM_MAX)
1036 if ((num >= 2 * den) && (den == 1) &&
1037 (num < 9) && (!(num & 0x01))) {
1041 /* Average scaling for >= 2:1 ratios */
1042 /* Support can be added for num >=9 and odd values */
1044 tmprsz.algo = RESIZE_ALGO_AVERAGING;
1047 for (i = 0; i < (len / 2); i++)
1051 for (i = 0; i < (len / 2); i++) {
1054 for (j = 0; j < (len / 2); j++)
1061 for (i = (len / 2); i < len; i++)
1062 s[i] = s[len - i - 1];
1064 s[len - 1] |= SZ_COEF;
1066 /* bilinear scaling for < 2:1 ratios */
1067 int v; /* overflow counter */
1068 int coeff, nxt; /* table output */
1069 int in_pos_inc = 2 * den;
1071 int out_pos_inc = 2 * num;
1072 int init_carry = num - den;
1073 int carry = init_carry;
1075 tmprsz.algo = RESIZE_ALGO_BILINEAR;
1076 v = den + in_pos_inc;
1078 coeff = v - out_pos;
1079 out_pos += out_pos_inc;
1080 carry += out_pos_inc;
1081 for (nxt = 0; v < out_pos; nxt++) {
1083 carry -= in_pos_inc;
1086 if (len > RESIZE_NUM_MAX)
1089 coeff = ((coeff << BC_COEF) +
1090 (in_pos_inc >> 1)) / in_pos_inc;
1092 if (coeff >= (SZ_COEF - 1))
1096 s[len] = (unsigned char)coeff;
1099 for (i = 1; i < nxt; i++) {
1100 if (len >= RESIZE_NUM_MAX)
1105 } while (carry != init_carry);
1108 if (dir == RESIZE_DIR_H)
1109 mf_in->width = pix_out->width;
1111 mf_in->height = pix_out->height;
1114 memcpy(&pcdev->resizing[dir], &tmprsz, sizeof(tmprsz));
1119 static int mx2_camera_set_fmt(struct soc_camera_device *icd,
1120 struct v4l2_format *f)
1122 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1123 struct mx2_camera_dev *pcdev = ici->priv;
1124 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1125 const struct soc_camera_format_xlate *xlate;
1126 struct v4l2_pix_format *pix = &f->fmt.pix;
1127 struct v4l2_mbus_framefmt mf;
1130 dev_dbg(icd->parent, "%s: requested params: width = %d, height = %d\n",
1131 __func__, pix->width, pix->height);
1133 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
1135 dev_warn(icd->parent, "Format %x not found\n",
1140 mf.width = pix->width;
1141 mf.height = pix->height;
1142 mf.field = pix->field;
1143 mf.colorspace = pix->colorspace;
1144 mf.code = xlate->code;
1146 ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
1147 if (ret < 0 && ret != -ENOIOCTLCMD)
1150 /* Store width and height returned by the sensor for resizing */
1151 pcdev->s_width = mf.width;
1152 pcdev->s_height = mf.height;
1153 dev_dbg(icd->parent, "%s: sensor params: width = %d, height = %d\n",
1154 __func__, pcdev->s_width, pcdev->s_height);
1156 pcdev->emma_prp = mx27_emma_prp_get_format(xlate->code,
1157 xlate->host_fmt->fourcc);
1159 memset(pcdev->resizing, 0, sizeof(pcdev->resizing));
1160 if ((mf.width != pix->width || mf.height != pix->height) &&
1161 pcdev->emma_prp->cfg.in_fmt == PRP_CNTL_DATA_IN_YUV422) {
1162 if (mx2_emmaprp_resize(pcdev, &mf, pix, true) < 0)
1163 dev_dbg(icd->parent, "%s: can't resize\n", __func__);
1166 if (mf.code != xlate->code)
1169 pix->width = mf.width;
1170 pix->height = mf.height;
1171 pix->field = mf.field;
1172 pix->colorspace = mf.colorspace;
1173 icd->current_fmt = xlate;
1175 dev_dbg(icd->parent, "%s: returned params: width = %d, height = %d\n",
1176 __func__, pix->width, pix->height);
1181 static int mx2_camera_try_fmt(struct soc_camera_device *icd,
1182 struct v4l2_format *f)
1184 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1185 const struct soc_camera_format_xlate *xlate;
1186 struct v4l2_pix_format *pix = &f->fmt.pix;
1187 struct v4l2_mbus_framefmt mf;
1188 __u32 pixfmt = pix->pixelformat;
1189 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1190 struct mx2_camera_dev *pcdev = ici->priv;
1191 struct mx2_fmt_cfg *emma_prp;
1194 dev_dbg(icd->parent, "%s: requested params: width = %d, height = %d\n",
1195 __func__, pix->width, pix->height);
1197 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1198 if (pixfmt && !xlate) {
1199 dev_warn(icd->parent, "Format %x not found\n", pixfmt);
1204 * limit to MX27 hardware capabilities: width must be a multiple of 8 as
1205 * requested by the CSI. (Table 39-2 in the i.MX27 Reference Manual).
1209 /* limit to sensor capabilities */
1210 mf.width = pix->width;
1211 mf.height = pix->height;
1212 mf.field = pix->field;
1213 mf.colorspace = pix->colorspace;
1214 mf.code = xlate->code;
1216 ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf);
1220 dev_dbg(icd->parent, "%s: sensor params: width = %d, height = %d\n",
1221 __func__, pcdev->s_width, pcdev->s_height);
1223 /* If the sensor does not support image size try PrP resizing */
1224 emma_prp = mx27_emma_prp_get_format(xlate->code,
1225 xlate->host_fmt->fourcc);
1227 if ((mf.width != pix->width || mf.height != pix->height) &&
1228 emma_prp->cfg.in_fmt == PRP_CNTL_DATA_IN_YUV422) {
1229 if (mx2_emmaprp_resize(pcdev, &mf, pix, false) < 0)
1230 dev_dbg(icd->parent, "%s: can't resize\n", __func__);
1233 if (mf.field == V4L2_FIELD_ANY)
1234 mf.field = V4L2_FIELD_NONE;
1236 * Driver supports interlaced images provided they have
1237 * both fields so that they can be processed as if they
1240 if (mf.field != V4L2_FIELD_NONE && !V4L2_FIELD_HAS_BOTH(mf.field)) {
1241 dev_err(icd->parent, "Field type %d unsupported.\n",
1246 pix->width = mf.width;
1247 pix->height = mf.height;
1248 pix->field = mf.field;
1249 pix->colorspace = mf.colorspace;
1251 dev_dbg(icd->parent, "%s: returned params: width = %d, height = %d\n",
1252 __func__, pix->width, pix->height);
1257 static int mx2_camera_querycap(struct soc_camera_host *ici,
1258 struct v4l2_capability *cap)
1260 /* cap->name is set by the friendly caller:-> */
1261 strlcpy(cap->card, MX2_CAM_DRIVER_DESCRIPTION, sizeof(cap->card));
1262 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1267 static unsigned int mx2_camera_poll(struct file *file, poll_table *pt)
1269 struct soc_camera_device *icd = file->private_data;
1271 return vb2_poll(&icd->vb2_vidq, file, pt);
1274 static struct soc_camera_host_ops mx2_soc_camera_host_ops = {
1275 .owner = THIS_MODULE,
1276 .add = mx2_camera_add_device,
1277 .remove = mx2_camera_remove_device,
1278 .clock_start = mx2_camera_clock_start,
1279 .clock_stop = mx2_camera_clock_stop,
1280 .set_fmt = mx2_camera_set_fmt,
1281 .set_crop = mx2_camera_set_crop,
1282 .get_formats = mx2_camera_get_formats,
1283 .try_fmt = mx2_camera_try_fmt,
1284 .init_videobuf2 = mx2_camera_init_videobuf,
1285 .poll = mx2_camera_poll,
1286 .querycap = mx2_camera_querycap,
1287 .set_bus_param = mx2_camera_set_bus_param,
1290 static void mx27_camera_frame_done_emma(struct mx2_camera_dev *pcdev,
1291 int bufnum, bool err)
1294 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
1296 struct mx2_buf_internal *ibuf;
1297 struct mx2_buffer *buf;
1298 struct vb2_buffer *vb;
1301 ibuf = list_first_entry(&pcdev->active_bufs, struct mx2_buf_internal,
1304 BUG_ON(ibuf->bufnum != bufnum);
1306 if (ibuf->discard) {
1308 * Discard buffer must not be returned to user space.
1309 * Just return it to the discard queue.
1311 list_move_tail(pcdev->active_bufs.next, &pcdev->discard);
1313 buf = mx2_ibuf_to_buf(ibuf);
1317 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
1318 if (prp->cfg.channel == 1) {
1319 if (readl(pcdev->base_emma + PRP_DEST_RGB1_PTR +
1320 4 * bufnum) != phys) {
1321 dev_err(pcdev->dev, "%lx != %x\n", phys,
1322 readl(pcdev->base_emma +
1323 PRP_DEST_RGB1_PTR + 4 * bufnum));
1326 if (readl(pcdev->base_emma + PRP_DEST_Y_PTR -
1327 0x14 * bufnum) != phys) {
1328 dev_err(pcdev->dev, "%lx != %x\n", phys,
1329 readl(pcdev->base_emma +
1330 PRP_DEST_Y_PTR - 0x14 * bufnum));
1334 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%p %lu\n", __func__, vb,
1335 vb2_plane_vaddr(vb, 0),
1336 vb2_get_plane_payload(vb, 0));
1338 list_del_init(&buf->internal.queue);
1339 v4l2_get_timestamp(&vb->v4l2_buf.timestamp);
1340 vb->v4l2_buf.sequence = pcdev->frame_count;
1342 vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
1344 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
1347 pcdev->frame_count++;
1349 if (list_empty(&pcdev->capture)) {
1350 if (list_empty(&pcdev->discard)) {
1351 dev_warn(pcdev->dev, "%s: trying to access empty discard list\n",
1356 ibuf = list_first_entry(&pcdev->discard,
1357 struct mx2_buf_internal, queue);
1358 ibuf->bufnum = bufnum;
1360 list_move_tail(pcdev->discard.next, &pcdev->active_bufs);
1361 mx27_update_emma_buf(pcdev, pcdev->discard_buffer_dma, bufnum);
1365 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
1368 buf->internal.bufnum = bufnum;
1370 list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
1374 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
1375 mx27_update_emma_buf(pcdev, phys, bufnum);
1378 static irqreturn_t mx27_camera_emma_irq(int irq_emma, void *data)
1380 struct mx2_camera_dev *pcdev = data;
1381 unsigned int status = readl(pcdev->base_emma + PRP_INTRSTATUS);
1382 struct mx2_buf_internal *ibuf;
1384 spin_lock(&pcdev->lock);
1386 if (list_empty(&pcdev->active_bufs)) {
1387 dev_warn(pcdev->dev, "%s: called while active list is empty\n",
1391 spin_unlock(&pcdev->lock);
1396 if (status & (1 << 7)) { /* overflow */
1397 u32 cntl = readl(pcdev->base_emma + PRP_CNTL);
1398 writel(cntl & ~(PRP_CNTL_CH1EN | PRP_CNTL_CH2EN),
1399 pcdev->base_emma + PRP_CNTL);
1400 writel(cntl, pcdev->base_emma + PRP_CNTL);
1402 ibuf = list_first_entry(&pcdev->active_bufs,
1403 struct mx2_buf_internal, queue);
1404 mx27_camera_frame_done_emma(pcdev,
1405 ibuf->bufnum, true);
1407 status &= ~(1 << 7);
1408 } else if (((status & (3 << 5)) == (3 << 5)) ||
1409 ((status & (3 << 3)) == (3 << 3))) {
1411 * Both buffers have triggered, process the one we're expecting
1414 ibuf = list_first_entry(&pcdev->active_bufs,
1415 struct mx2_buf_internal, queue);
1416 mx27_camera_frame_done_emma(pcdev, ibuf->bufnum, false);
1417 status &= ~(1 << (6 - ibuf->bufnum)); /* mark processed */
1418 } else if ((status & (1 << 6)) || (status & (1 << 4))) {
1419 mx27_camera_frame_done_emma(pcdev, 0, false);
1420 } else if ((status & (1 << 5)) || (status & (1 << 3))) {
1421 mx27_camera_frame_done_emma(pcdev, 1, false);
1424 spin_unlock(&pcdev->lock);
1425 writel(status, pcdev->base_emma + PRP_INTRSTATUS);
1430 static int mx27_camera_emma_init(struct platform_device *pdev)
1432 struct mx2_camera_dev *pcdev = platform_get_drvdata(pdev);
1433 struct resource *res_emma;
1437 res_emma = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1438 irq_emma = platform_get_irq(pdev, 1);
1439 if (!res_emma || !irq_emma) {
1440 dev_err(pcdev->dev, "no EMMA resources\n");
1445 pcdev->base_emma = devm_ioremap_resource(pcdev->dev, res_emma);
1446 if (IS_ERR(pcdev->base_emma)) {
1447 err = PTR_ERR(pcdev->base_emma);
1451 err = devm_request_irq(pcdev->dev, irq_emma, mx27_camera_emma_irq, 0,
1452 MX2_CAM_DRV_NAME, pcdev);
1454 dev_err(pcdev->dev, "Camera EMMA interrupt register failed\n");
1458 pcdev->clk_emma_ipg = devm_clk_get(pcdev->dev, "emma-ipg");
1459 if (IS_ERR(pcdev->clk_emma_ipg)) {
1460 err = PTR_ERR(pcdev->clk_emma_ipg);
1464 clk_prepare_enable(pcdev->clk_emma_ipg);
1466 pcdev->clk_emma_ahb = devm_clk_get(pcdev->dev, "emma-ahb");
1467 if (IS_ERR(pcdev->clk_emma_ahb)) {
1468 err = PTR_ERR(pcdev->clk_emma_ahb);
1469 goto exit_clk_emma_ipg;
1472 clk_prepare_enable(pcdev->clk_emma_ahb);
1474 err = mx27_camera_emma_prp_reset(pcdev);
1476 goto exit_clk_emma_ahb;
1481 clk_disable_unprepare(pcdev->clk_emma_ahb);
1483 clk_disable_unprepare(pcdev->clk_emma_ipg);
1488 static int mx2_camera_probe(struct platform_device *pdev)
1490 struct mx2_camera_dev *pcdev;
1491 struct resource *res_csi;
1495 dev_dbg(&pdev->dev, "initialising\n");
1497 res_csi = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1498 irq_csi = platform_get_irq(pdev, 0);
1499 if (res_csi == NULL || irq_csi < 0) {
1500 dev_err(&pdev->dev, "Missing platform resources data\n");
1505 pcdev = devm_kzalloc(&pdev->dev, sizeof(*pcdev), GFP_KERNEL);
1507 dev_err(&pdev->dev, "Could not allocate pcdev\n");
1512 pcdev->clk_csi_ahb = devm_clk_get(&pdev->dev, "ahb");
1513 if (IS_ERR(pcdev->clk_csi_ahb)) {
1514 dev_err(&pdev->dev, "Could not get csi ahb clock\n");
1515 err = PTR_ERR(pcdev->clk_csi_ahb);
1519 pcdev->clk_csi_per = devm_clk_get(&pdev->dev, "per");
1520 if (IS_ERR(pcdev->clk_csi_per)) {
1521 dev_err(&pdev->dev, "Could not get csi per clock\n");
1522 err = PTR_ERR(pcdev->clk_csi_per);
1526 pcdev->pdata = pdev->dev.platform_data;
1530 pcdev->platform_flags = pcdev->pdata->flags;
1532 rate = clk_round_rate(pcdev->clk_csi_per,
1533 pcdev->pdata->clk * 2);
1538 err = clk_set_rate(pcdev->clk_csi_per, rate);
1543 INIT_LIST_HEAD(&pcdev->capture);
1544 INIT_LIST_HEAD(&pcdev->active_bufs);
1545 INIT_LIST_HEAD(&pcdev->discard);
1546 spin_lock_init(&pcdev->lock);
1548 pcdev->base_csi = devm_ioremap_resource(&pdev->dev, res_csi);
1549 if (IS_ERR(pcdev->base_csi)) {
1550 err = PTR_ERR(pcdev->base_csi);
1554 pcdev->dev = &pdev->dev;
1555 platform_set_drvdata(pdev, pcdev);
1557 err = mx27_camera_emma_init(pdev);
1562 * We're done with drvdata here. Clear the pointer so that
1563 * v4l2 core can start using drvdata on its purpose.
1565 platform_set_drvdata(pdev, NULL);
1567 pcdev->soc_host.drv_name = MX2_CAM_DRV_NAME,
1568 pcdev->soc_host.ops = &mx2_soc_camera_host_ops,
1569 pcdev->soc_host.priv = pcdev;
1570 pcdev->soc_host.v4l2_dev.dev = &pdev->dev;
1571 pcdev->soc_host.nr = pdev->id;
1573 pcdev->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
1574 if (IS_ERR(pcdev->alloc_ctx)) {
1575 err = PTR_ERR(pcdev->alloc_ctx);
1578 err = soc_camera_host_register(&pcdev->soc_host);
1580 goto exit_free_emma;
1582 dev_info(&pdev->dev, "MX2 Camera (CSI) driver probed, clock frequency: %ld\n",
1583 clk_get_rate(pcdev->clk_csi_per));
1588 vb2_dma_contig_cleanup_ctx(pcdev->alloc_ctx);
1590 clk_disable_unprepare(pcdev->clk_emma_ipg);
1591 clk_disable_unprepare(pcdev->clk_emma_ahb);
1596 static int mx2_camera_remove(struct platform_device *pdev)
1598 struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
1599 struct mx2_camera_dev *pcdev = container_of(soc_host,
1600 struct mx2_camera_dev, soc_host);
1602 soc_camera_host_unregister(&pcdev->soc_host);
1604 vb2_dma_contig_cleanup_ctx(pcdev->alloc_ctx);
1606 clk_disable_unprepare(pcdev->clk_emma_ipg);
1607 clk_disable_unprepare(pcdev->clk_emma_ahb);
1609 dev_info(&pdev->dev, "MX2 Camera driver unloaded\n");
1614 static struct platform_driver mx2_camera_driver = {
1616 .name = MX2_CAM_DRV_NAME,
1618 .id_table = mx2_camera_devtype,
1619 .remove = mx2_camera_remove,
1622 module_platform_driver_probe(mx2_camera_driver, mx2_camera_probe);
1624 MODULE_DESCRIPTION("i.MX27 SoC Camera Host driver");
1625 MODULE_AUTHOR("Sascha Hauer <sha@pengutronix.de>");
1626 MODULE_LICENSE("GPL");
1627 MODULE_VERSION(MX2_CAM_VERSION);