2 * drivers/media/platform/samsung/mfc5/s5p_mfc_opr_v5.c
4 * Samsung MFC (Multi Function Codec - FIMV) driver
5 * This file contains hw related functions.
7 * Kamil Debski, Copyright (c) 2011 Samsung Electronics
8 * http://www.samsung.com/
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include "s5p_mfc_common.h"
16 #include "s5p_mfc_cmd.h"
17 #include "s5p_mfc_ctrl.h"
18 #include "s5p_mfc_debug.h"
19 #include "s5p_mfc_intr.h"
20 #include "s5p_mfc_pm.h"
21 #include "s5p_mfc_opr.h"
22 #include "s5p_mfc_opr_v5.h"
23 #include <asm/cacheflush.h>
24 #include <linux/delay.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/err.h>
27 #include <linux/firmware.h>
29 #include <linux/jiffies.h>
31 #include <linux/sched.h>
33 #define OFFSETA(x) (((x) - dev->bank1) >> MFC_OFFSET_SHIFT)
34 #define OFFSETB(x) (((x) - dev->bank2) >> MFC_OFFSET_SHIFT)
36 /* Allocate temporary buffers for decoding */
37 static int s5p_mfc_alloc_dec_temp_buffers_v5(struct s5p_mfc_ctx *ctx)
39 struct s5p_mfc_dev *dev = ctx->dev;
40 struct s5p_mfc_buf_size_v5 *buf_size = dev->variant->buf_size->priv;
43 ctx->dsc.size = buf_size->dsc;
44 ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, &ctx->dsc);
46 mfc_err("Failed to allocate temporary buffer\n");
50 BUG_ON(ctx->dsc.dma & ((1 << MFC_BANK1_ALIGN_ORDER) - 1));
51 memset(ctx->dsc.virt, 0, ctx->dsc.size);
57 /* Release temporary buffers for decoding */
58 static void s5p_mfc_release_dec_desc_buffer_v5(struct s5p_mfc_ctx *ctx)
60 s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->dsc);
63 /* Allocate codec buffers */
64 static int s5p_mfc_alloc_codec_buffers_v5(struct s5p_mfc_ctx *ctx)
66 struct s5p_mfc_dev *dev = ctx->dev;
67 unsigned int enc_ref_y_size = 0;
68 unsigned int enc_ref_c_size = 0;
69 unsigned int guard_width, guard_height;
72 if (ctx->type == MFCINST_DECODER) {
73 mfc_debug(2, "Luma size:%d Chroma size:%d MV size:%d\n",
74 ctx->luma_size, ctx->chroma_size, ctx->mv_size);
75 mfc_debug(2, "Totals bufs: %d\n", ctx->total_dpb_count);
76 } else if (ctx->type == MFCINST_ENCODER) {
77 enc_ref_y_size = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN)
78 * ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN);
79 enc_ref_y_size = ALIGN(enc_ref_y_size, S5P_FIMV_NV12MT_SALIGN);
81 if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC) {
82 enc_ref_c_size = ALIGN(ctx->img_width,
83 S5P_FIMV_NV12MT_HALIGN)
84 * ALIGN(ctx->img_height >> 1,
85 S5P_FIMV_NV12MT_VALIGN);
86 enc_ref_c_size = ALIGN(enc_ref_c_size,
87 S5P_FIMV_NV12MT_SALIGN);
89 guard_width = ALIGN(ctx->img_width + 16,
90 S5P_FIMV_NV12MT_HALIGN);
91 guard_height = ALIGN((ctx->img_height >> 1) + 4,
92 S5P_FIMV_NV12MT_VALIGN);
93 enc_ref_c_size = ALIGN(guard_width * guard_height,
94 S5P_FIMV_NV12MT_SALIGN);
96 mfc_debug(2, "recon luma size: %d chroma size: %d\n",
97 enc_ref_y_size, enc_ref_c_size);
101 /* Codecs have different memory requirements */
102 switch (ctx->codec_mode) {
103 case S5P_MFC_CODEC_H264_DEC:
105 ALIGN(S5P_FIMV_DEC_NB_IP_SIZE +
106 S5P_FIMV_DEC_VERT_NB_MV_SIZE,
107 S5P_FIMV_DEC_BUF_ALIGN);
108 ctx->bank2.size = ctx->total_dpb_count * ctx->mv_size;
110 case S5P_MFC_CODEC_MPEG4_DEC:
112 ALIGN(S5P_FIMV_DEC_NB_DCAC_SIZE +
113 S5P_FIMV_DEC_UPNB_MV_SIZE +
114 S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE +
115 S5P_FIMV_DEC_STX_PARSER_SIZE +
116 S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE,
117 S5P_FIMV_DEC_BUF_ALIGN);
120 case S5P_MFC_CODEC_VC1RCV_DEC:
121 case S5P_MFC_CODEC_VC1_DEC:
123 ALIGN(S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE +
124 S5P_FIMV_DEC_UPNB_MV_SIZE +
125 S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE +
126 S5P_FIMV_DEC_NB_DCAC_SIZE +
127 3 * S5P_FIMV_DEC_VC1_BITPLANE_SIZE,
128 S5P_FIMV_DEC_BUF_ALIGN);
131 case S5P_MFC_CODEC_MPEG2_DEC:
135 case S5P_MFC_CODEC_H263_DEC:
137 ALIGN(S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE +
138 S5P_FIMV_DEC_UPNB_MV_SIZE +
139 S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE +
140 S5P_FIMV_DEC_NB_DCAC_SIZE,
141 S5P_FIMV_DEC_BUF_ALIGN);
144 case S5P_MFC_CODEC_H264_ENC:
145 ctx->bank1.size = (enc_ref_y_size * 2) +
146 S5P_FIMV_ENC_UPMV_SIZE +
147 S5P_FIMV_ENC_COLFLG_SIZE +
148 S5P_FIMV_ENC_INTRAMD_SIZE +
149 S5P_FIMV_ENC_NBORINFO_SIZE;
150 ctx->bank2.size = (enc_ref_y_size * 2) +
151 (enc_ref_c_size * 4) +
152 S5P_FIMV_ENC_INTRAPRED_SIZE;
154 case S5P_MFC_CODEC_MPEG4_ENC:
155 ctx->bank1.size = (enc_ref_y_size * 2) +
156 S5P_FIMV_ENC_UPMV_SIZE +
157 S5P_FIMV_ENC_COLFLG_SIZE +
158 S5P_FIMV_ENC_ACDCCOEF_SIZE;
159 ctx->bank2.size = (enc_ref_y_size * 2) +
160 (enc_ref_c_size * 4);
162 case S5P_MFC_CODEC_H263_ENC:
163 ctx->bank1.size = (enc_ref_y_size * 2) +
164 S5P_FIMV_ENC_UPMV_SIZE +
165 S5P_FIMV_ENC_ACDCCOEF_SIZE;
166 ctx->bank2.size = (enc_ref_y_size * 2) +
167 (enc_ref_c_size * 4);
172 /* Allocate only if memory from bank 1 is necessary */
173 if (ctx->bank1.size > 0) {
175 ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, &ctx->bank1);
177 mfc_err("Failed to allocate Bank1 temporary buffer\n");
180 BUG_ON(ctx->bank1.dma & ((1 << MFC_BANK1_ALIGN_ORDER) - 1));
182 /* Allocate only if memory from bank 2 is necessary */
183 if (ctx->bank2.size > 0) {
184 ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_r, &ctx->bank2);
186 mfc_err("Failed to allocate Bank2 temporary buffer\n");
187 s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->bank1);
190 BUG_ON(ctx->bank2.dma & ((1 << MFC_BANK2_ALIGN_ORDER) - 1));
195 /* Release buffers allocated for codec */
196 static void s5p_mfc_release_codec_buffers_v5(struct s5p_mfc_ctx *ctx)
198 s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->bank1);
199 s5p_mfc_release_priv_buf(ctx->dev->mem_dev_r, &ctx->bank2);
202 /* Allocate memory for instance data buffer */
203 static int s5p_mfc_alloc_instance_buffer_v5(struct s5p_mfc_ctx *ctx)
205 struct s5p_mfc_dev *dev = ctx->dev;
206 struct s5p_mfc_buf_size_v5 *buf_size = dev->variant->buf_size->priv;
209 if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
210 ctx->codec_mode == S5P_MFC_CODEC_H264_ENC)
211 ctx->ctx.size = buf_size->h264_ctx;
213 ctx->ctx.size = buf_size->non_h264_ctx;
215 ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, &ctx->ctx);
217 mfc_err("Failed to allocate instance buffer\n");
220 ctx->ctx.ofs = OFFSETA(ctx->ctx.dma);
222 /* Zero content of the allocated memory */
223 memset(ctx->ctx.virt, 0, ctx->ctx.size);
226 /* Initialize shared memory */
227 ctx->shm.size = buf_size->shm;
228 ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, &ctx->shm);
230 mfc_err("Failed to allocate shared memory buffer\n");
234 /* shared memory offset only keeps the offset from base (port a) */
235 ctx->shm.ofs = ctx->shm.dma - dev->bank1;
236 BUG_ON(ctx->shm.ofs & ((1 << MFC_BANK1_ALIGN_ORDER) - 1));
238 memset(ctx->shm.virt, 0, buf_size->shm);
243 /* Release instance buffer */
244 static void s5p_mfc_release_instance_buffer_v5(struct s5p_mfc_ctx *ctx)
246 s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->ctx);
247 s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->shm);
250 static int s5p_mfc_alloc_dev_context_buffer_v5(struct s5p_mfc_dev *dev)
257 static void s5p_mfc_release_dev_context_buffer_v5(struct s5p_mfc_dev *dev)
262 static void s5p_mfc_write_info_v5(struct s5p_mfc_ctx *ctx, unsigned int data,
265 writel(data, (ctx->shm.virt + ofs));
269 static unsigned int s5p_mfc_read_info_v5(struct s5p_mfc_ctx *ctx,
273 return readl(ctx->shm.virt + ofs);
276 static void s5p_mfc_dec_calc_dpb_size_v5(struct s5p_mfc_ctx *ctx)
278 unsigned int guard_width, guard_height;
280 ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN);
281 ctx->buf_height = ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN);
283 "SEQ Done: Movie dimensions %dx%d, buffer dimensions: %dx%d\n",
284 ctx->img_width, ctx->img_height, ctx->buf_width,
287 if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC) {
288 ctx->luma_size = ALIGN(ctx->buf_width * ctx->buf_height,
289 S5P_FIMV_DEC_BUF_ALIGN);
290 ctx->chroma_size = ALIGN(ctx->buf_width *
291 ALIGN((ctx->img_height >> 1),
292 S5P_FIMV_NV12MT_VALIGN),
293 S5P_FIMV_DEC_BUF_ALIGN);
294 ctx->mv_size = ALIGN(ctx->buf_width *
295 ALIGN((ctx->buf_height >> 2),
296 S5P_FIMV_NV12MT_VALIGN),
297 S5P_FIMV_DEC_BUF_ALIGN);
300 ALIGN(ctx->img_width + 24, S5P_FIMV_NV12MT_HALIGN);
302 ALIGN(ctx->img_height + 16, S5P_FIMV_NV12MT_VALIGN);
303 ctx->luma_size = ALIGN(guard_width * guard_height,
304 S5P_FIMV_DEC_BUF_ALIGN);
307 ALIGN(ctx->img_width + 16, S5P_FIMV_NV12MT_HALIGN);
309 ALIGN((ctx->img_height >> 1) + 4,
310 S5P_FIMV_NV12MT_VALIGN);
311 ctx->chroma_size = ALIGN(guard_width * guard_height,
312 S5P_FIMV_DEC_BUF_ALIGN);
318 static void s5p_mfc_enc_calc_src_size_v5(struct s5p_mfc_ctx *ctx)
320 if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M) {
321 ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN);
323 ctx->luma_size = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN)
324 * ALIGN(ctx->img_height, S5P_FIMV_NV12M_LVALIGN);
325 ctx->chroma_size = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN)
326 * ALIGN((ctx->img_height >> 1), S5P_FIMV_NV12M_CVALIGN);
328 ctx->luma_size = ALIGN(ctx->luma_size, S5P_FIMV_NV12M_SALIGN);
330 ALIGN(ctx->chroma_size, S5P_FIMV_NV12M_SALIGN);
331 } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT) {
332 ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN);
334 ctx->luma_size = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN)
335 * ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN);
337 ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN)
338 * ALIGN((ctx->img_height >> 1), S5P_FIMV_NV12MT_VALIGN);
340 ctx->luma_size = ALIGN(ctx->luma_size, S5P_FIMV_NV12MT_SALIGN);
342 ALIGN(ctx->chroma_size, S5P_FIMV_NV12MT_SALIGN);
346 /* Set registers for decoding temporary buffers */
347 static void s5p_mfc_set_dec_desc_buffer(struct s5p_mfc_ctx *ctx)
349 struct s5p_mfc_dev *dev = ctx->dev;
350 struct s5p_mfc_buf_size_v5 *buf_size = dev->variant->buf_size->priv;
352 mfc_write(dev, OFFSETA(ctx->dsc.dma), S5P_FIMV_SI_CH0_DESC_ADR);
353 mfc_write(dev, buf_size->dsc, S5P_FIMV_SI_CH0_DESC_SIZE);
356 /* Set registers for shared buffer */
357 static void s5p_mfc_set_shared_buffer(struct s5p_mfc_ctx *ctx)
359 struct s5p_mfc_dev *dev = ctx->dev;
360 mfc_write(dev, ctx->shm.ofs, S5P_FIMV_SI_CH0_HOST_WR_ADR);
363 /* Set registers for decoding stream buffer */
364 static int s5p_mfc_set_dec_stream_buffer_v5(struct s5p_mfc_ctx *ctx,
365 int buf_addr, unsigned int start_num_byte,
366 unsigned int buf_size)
368 struct s5p_mfc_dev *dev = ctx->dev;
370 mfc_write(dev, OFFSETA(buf_addr), S5P_FIMV_SI_CH0_SB_ST_ADR);
371 mfc_write(dev, ctx->dec_src_buf_size, S5P_FIMV_SI_CH0_CPB_SIZE);
372 mfc_write(dev, buf_size, S5P_FIMV_SI_CH0_SB_FRM_SIZE);
373 s5p_mfc_write_info_v5(ctx, start_num_byte, START_BYTE_NUM);
377 /* Set decoding frame buffer */
378 static int s5p_mfc_set_dec_frame_buffer_v5(struct s5p_mfc_ctx *ctx)
380 unsigned int frame_size, i;
381 unsigned int frame_size_ch, frame_size_mv;
382 struct s5p_mfc_dev *dev = ctx->dev;
384 size_t buf_addr1, buf_addr2;
385 int buf_size1, buf_size2;
387 buf_addr1 = ctx->bank1.dma;
388 buf_size1 = ctx->bank1.size;
389 buf_addr2 = ctx->bank2.dma;
390 buf_size2 = ctx->bank2.size;
391 dpb = mfc_read(dev, S5P_FIMV_SI_CH0_DPB_CONF_CTRL) &
392 ~S5P_FIMV_DPB_COUNT_MASK;
393 mfc_write(dev, ctx->total_dpb_count | dpb,
394 S5P_FIMV_SI_CH0_DPB_CONF_CTRL);
395 s5p_mfc_set_shared_buffer(ctx);
396 switch (ctx->codec_mode) {
397 case S5P_MFC_CODEC_H264_DEC:
398 mfc_write(dev, OFFSETA(buf_addr1),
399 S5P_FIMV_H264_VERT_NB_MV_ADR);
400 buf_addr1 += S5P_FIMV_DEC_VERT_NB_MV_SIZE;
401 buf_size1 -= S5P_FIMV_DEC_VERT_NB_MV_SIZE;
402 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H264_NB_IP_ADR);
403 buf_addr1 += S5P_FIMV_DEC_NB_IP_SIZE;
404 buf_size1 -= S5P_FIMV_DEC_NB_IP_SIZE;
406 case S5P_MFC_CODEC_MPEG4_DEC:
407 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_NB_DCAC_ADR);
408 buf_addr1 += S5P_FIMV_DEC_NB_DCAC_SIZE;
409 buf_size1 -= S5P_FIMV_DEC_NB_DCAC_SIZE;
410 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_UP_NB_MV_ADR);
411 buf_addr1 += S5P_FIMV_DEC_UPNB_MV_SIZE;
412 buf_size1 -= S5P_FIMV_DEC_UPNB_MV_SIZE;
413 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_SA_MV_ADR);
414 buf_addr1 += S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE;
415 buf_size1 -= S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE;
416 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_SP_ADR);
417 buf_addr1 += S5P_FIMV_DEC_STX_PARSER_SIZE;
418 buf_size1 -= S5P_FIMV_DEC_STX_PARSER_SIZE;
419 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_OT_LINE_ADR);
420 buf_addr1 += S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE;
421 buf_size1 -= S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE;
423 case S5P_MFC_CODEC_H263_DEC:
424 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_OT_LINE_ADR);
425 buf_addr1 += S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE;
426 buf_size1 -= S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE;
427 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_UP_NB_MV_ADR);
428 buf_addr1 += S5P_FIMV_DEC_UPNB_MV_SIZE;
429 buf_size1 -= S5P_FIMV_DEC_UPNB_MV_SIZE;
430 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_SA_MV_ADR);
431 buf_addr1 += S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE;
432 buf_size1 -= S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE;
433 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_NB_DCAC_ADR);
434 buf_addr1 += S5P_FIMV_DEC_NB_DCAC_SIZE;
435 buf_size1 -= S5P_FIMV_DEC_NB_DCAC_SIZE;
437 case S5P_MFC_CODEC_VC1_DEC:
438 case S5P_MFC_CODEC_VC1RCV_DEC:
439 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_NB_DCAC_ADR);
440 buf_addr1 += S5P_FIMV_DEC_NB_DCAC_SIZE;
441 buf_size1 -= S5P_FIMV_DEC_NB_DCAC_SIZE;
442 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_OT_LINE_ADR);
443 buf_addr1 += S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE;
444 buf_size1 -= S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE;
445 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_UP_NB_MV_ADR);
446 buf_addr1 += S5P_FIMV_DEC_UPNB_MV_SIZE;
447 buf_size1 -= S5P_FIMV_DEC_UPNB_MV_SIZE;
448 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_SA_MV_ADR);
449 buf_addr1 += S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE;
450 buf_size1 -= S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE;
451 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_BITPLANE3_ADR);
452 buf_addr1 += S5P_FIMV_DEC_VC1_BITPLANE_SIZE;
453 buf_size1 -= S5P_FIMV_DEC_VC1_BITPLANE_SIZE;
454 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_BITPLANE2_ADR);
455 buf_addr1 += S5P_FIMV_DEC_VC1_BITPLANE_SIZE;
456 buf_size1 -= S5P_FIMV_DEC_VC1_BITPLANE_SIZE;
457 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_BITPLANE1_ADR);
458 buf_addr1 += S5P_FIMV_DEC_VC1_BITPLANE_SIZE;
459 buf_size1 -= S5P_FIMV_DEC_VC1_BITPLANE_SIZE;
461 case S5P_MFC_CODEC_MPEG2_DEC:
464 mfc_err("Unknown codec for decoding (%x)\n",
468 frame_size = ctx->luma_size;
469 frame_size_ch = ctx->chroma_size;
470 frame_size_mv = ctx->mv_size;
471 mfc_debug(2, "Frm size: %d ch: %d mv: %d\n", frame_size, frame_size_ch,
473 for (i = 0; i < ctx->total_dpb_count; i++) {
475 mfc_debug(2, "Luma %d: %x\n", i,
476 ctx->dst_bufs[i].cookie.raw.luma);
477 mfc_write(dev, OFFSETB(ctx->dst_bufs[i].cookie.raw.luma),
478 S5P_FIMV_DEC_LUMA_ADR + i * 4);
479 mfc_debug(2, "\tChroma %d: %x\n", i,
480 ctx->dst_bufs[i].cookie.raw.chroma);
481 mfc_write(dev, OFFSETA(ctx->dst_bufs[i].cookie.raw.chroma),
482 S5P_FIMV_DEC_CHROMA_ADR + i * 4);
483 if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC) {
484 mfc_debug(2, "\tBuf2: %x, size: %d\n",
485 buf_addr2, buf_size2);
486 mfc_write(dev, OFFSETB(buf_addr2),
487 S5P_FIMV_H264_MV_ADR + i * 4);
488 buf_addr2 += frame_size_mv;
489 buf_size2 -= frame_size_mv;
492 mfc_debug(2, "Buf1: %u, buf_size1: %d\n", buf_addr1, buf_size1);
493 mfc_debug(2, "Buf 1/2 size after: %d/%d (frames %d)\n",
494 buf_size1, buf_size2, ctx->total_dpb_count);
495 if (buf_size1 < 0 || buf_size2 < 0) {
496 mfc_debug(2, "Not enough memory has been allocated\n");
499 s5p_mfc_write_info_v5(ctx, frame_size, ALLOC_LUMA_DPB_SIZE);
500 s5p_mfc_write_info_v5(ctx, frame_size_ch, ALLOC_CHROMA_DPB_SIZE);
501 if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC)
502 s5p_mfc_write_info_v5(ctx, frame_size_mv, ALLOC_MV_SIZE);
503 mfc_write(dev, ((S5P_FIMV_CH_INIT_BUFS & S5P_FIMV_CH_MASK)
504 << S5P_FIMV_CH_SHIFT) | (ctx->inst_no),
505 S5P_FIMV_SI_CH0_INST_ID);
509 /* Set registers for encoding stream buffer */
510 static int s5p_mfc_set_enc_stream_buffer_v5(struct s5p_mfc_ctx *ctx,
511 unsigned long addr, unsigned int size)
513 struct s5p_mfc_dev *dev = ctx->dev;
515 mfc_write(dev, OFFSETA(addr), S5P_FIMV_ENC_SI_CH0_SB_ADR);
516 mfc_write(dev, size, S5P_FIMV_ENC_SI_CH0_SB_SIZE);
520 static void s5p_mfc_set_enc_frame_buffer_v5(struct s5p_mfc_ctx *ctx,
521 unsigned long y_addr, unsigned long c_addr)
523 struct s5p_mfc_dev *dev = ctx->dev;
525 mfc_write(dev, OFFSETB(y_addr), S5P_FIMV_ENC_SI_CH0_CUR_Y_ADR);
526 mfc_write(dev, OFFSETB(c_addr), S5P_FIMV_ENC_SI_CH0_CUR_C_ADR);
529 static void s5p_mfc_get_enc_frame_buffer_v5(struct s5p_mfc_ctx *ctx,
530 unsigned long *y_addr, unsigned long *c_addr)
532 struct s5p_mfc_dev *dev = ctx->dev;
534 *y_addr = dev->bank2 + (mfc_read(dev, S5P_FIMV_ENCODED_Y_ADDR)
535 << MFC_OFFSET_SHIFT);
536 *c_addr = dev->bank2 + (mfc_read(dev, S5P_FIMV_ENCODED_C_ADDR)
537 << MFC_OFFSET_SHIFT);
540 /* Set encoding ref & codec buffer */
541 static int s5p_mfc_set_enc_ref_buffer_v5(struct s5p_mfc_ctx *ctx)
543 struct s5p_mfc_dev *dev = ctx->dev;
544 size_t buf_addr1, buf_addr2;
545 size_t buf_size1, buf_size2;
546 unsigned int enc_ref_y_size, enc_ref_c_size;
547 unsigned int guard_width, guard_height;
550 buf_addr1 = ctx->bank1.dma;
551 buf_size1 = ctx->bank1.size;
552 buf_addr2 = ctx->bank2.dma;
553 buf_size2 = ctx->bank2.size;
554 enc_ref_y_size = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN)
555 * ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN);
556 enc_ref_y_size = ALIGN(enc_ref_y_size, S5P_FIMV_NV12MT_SALIGN);
557 if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC) {
558 enc_ref_c_size = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN)
559 * ALIGN((ctx->img_height >> 1), S5P_FIMV_NV12MT_VALIGN);
560 enc_ref_c_size = ALIGN(enc_ref_c_size, S5P_FIMV_NV12MT_SALIGN);
562 guard_width = ALIGN(ctx->img_width + 16,
563 S5P_FIMV_NV12MT_HALIGN);
564 guard_height = ALIGN((ctx->img_height >> 1) + 4,
565 S5P_FIMV_NV12MT_VALIGN);
566 enc_ref_c_size = ALIGN(guard_width * guard_height,
567 S5P_FIMV_NV12MT_SALIGN);
569 mfc_debug(2, "buf_size1: %d, buf_size2: %d\n", buf_size1, buf_size2);
570 switch (ctx->codec_mode) {
571 case S5P_MFC_CODEC_H264_ENC:
572 for (i = 0; i < 2; i++) {
573 mfc_write(dev, OFFSETA(buf_addr1),
574 S5P_FIMV_ENC_REF0_LUMA_ADR + (4 * i));
575 buf_addr1 += enc_ref_y_size;
576 buf_size1 -= enc_ref_y_size;
578 mfc_write(dev, OFFSETB(buf_addr2),
579 S5P_FIMV_ENC_REF2_LUMA_ADR + (4 * i));
580 buf_addr2 += enc_ref_y_size;
581 buf_size2 -= enc_ref_y_size;
583 for (i = 0; i < 4; i++) {
584 mfc_write(dev, OFFSETB(buf_addr2),
585 S5P_FIMV_ENC_REF0_CHROMA_ADR + (4 * i));
586 buf_addr2 += enc_ref_c_size;
587 buf_size2 -= enc_ref_c_size;
589 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H264_UP_MV_ADR);
590 buf_addr1 += S5P_FIMV_ENC_UPMV_SIZE;
591 buf_size1 -= S5P_FIMV_ENC_UPMV_SIZE;
592 mfc_write(dev, OFFSETA(buf_addr1),
593 S5P_FIMV_H264_COZERO_FLAG_ADR);
594 buf_addr1 += S5P_FIMV_ENC_COLFLG_SIZE;
595 buf_size1 -= S5P_FIMV_ENC_COLFLG_SIZE;
596 mfc_write(dev, OFFSETA(buf_addr1),
597 S5P_FIMV_H264_UP_INTRA_MD_ADR);
598 buf_addr1 += S5P_FIMV_ENC_INTRAMD_SIZE;
599 buf_size1 -= S5P_FIMV_ENC_INTRAMD_SIZE;
600 mfc_write(dev, OFFSETB(buf_addr2),
601 S5P_FIMV_H264_UP_INTRA_PRED_ADR);
602 buf_addr2 += S5P_FIMV_ENC_INTRAPRED_SIZE;
603 buf_size2 -= S5P_FIMV_ENC_INTRAPRED_SIZE;
604 mfc_write(dev, OFFSETA(buf_addr1),
605 S5P_FIMV_H264_NBOR_INFO_ADR);
606 buf_addr1 += S5P_FIMV_ENC_NBORINFO_SIZE;
607 buf_size1 -= S5P_FIMV_ENC_NBORINFO_SIZE;
608 mfc_debug(2, "buf_size1: %d, buf_size2: %d\n",
609 buf_size1, buf_size2);
611 case S5P_MFC_CODEC_MPEG4_ENC:
612 for (i = 0; i < 2; i++) {
613 mfc_write(dev, OFFSETA(buf_addr1),
614 S5P_FIMV_ENC_REF0_LUMA_ADR + (4 * i));
615 buf_addr1 += enc_ref_y_size;
616 buf_size1 -= enc_ref_y_size;
617 mfc_write(dev, OFFSETB(buf_addr2),
618 S5P_FIMV_ENC_REF2_LUMA_ADR + (4 * i));
619 buf_addr2 += enc_ref_y_size;
620 buf_size2 -= enc_ref_y_size;
622 for (i = 0; i < 4; i++) {
623 mfc_write(dev, OFFSETB(buf_addr2),
624 S5P_FIMV_ENC_REF0_CHROMA_ADR + (4 * i));
625 buf_addr2 += enc_ref_c_size;
626 buf_size2 -= enc_ref_c_size;
628 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_UP_MV_ADR);
629 buf_addr1 += S5P_FIMV_ENC_UPMV_SIZE;
630 buf_size1 -= S5P_FIMV_ENC_UPMV_SIZE;
631 mfc_write(dev, OFFSETA(buf_addr1),
632 S5P_FIMV_MPEG4_COZERO_FLAG_ADR);
633 buf_addr1 += S5P_FIMV_ENC_COLFLG_SIZE;
634 buf_size1 -= S5P_FIMV_ENC_COLFLG_SIZE;
635 mfc_write(dev, OFFSETA(buf_addr1),
636 S5P_FIMV_MPEG4_ACDC_COEF_ADR);
637 buf_addr1 += S5P_FIMV_ENC_ACDCCOEF_SIZE;
638 buf_size1 -= S5P_FIMV_ENC_ACDCCOEF_SIZE;
639 mfc_debug(2, "buf_size1: %d, buf_size2: %d\n",
640 buf_size1, buf_size2);
642 case S5P_MFC_CODEC_H263_ENC:
643 for (i = 0; i < 2; i++) {
644 mfc_write(dev, OFFSETA(buf_addr1),
645 S5P_FIMV_ENC_REF0_LUMA_ADR + (4 * i));
646 buf_addr1 += enc_ref_y_size;
647 buf_size1 -= enc_ref_y_size;
648 mfc_write(dev, OFFSETB(buf_addr2),
649 S5P_FIMV_ENC_REF2_LUMA_ADR + (4 * i));
650 buf_addr2 += enc_ref_y_size;
651 buf_size2 -= enc_ref_y_size;
653 for (i = 0; i < 4; i++) {
654 mfc_write(dev, OFFSETB(buf_addr2),
655 S5P_FIMV_ENC_REF0_CHROMA_ADR + (4 * i));
656 buf_addr2 += enc_ref_c_size;
657 buf_size2 -= enc_ref_c_size;
659 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_UP_MV_ADR);
660 buf_addr1 += S5P_FIMV_ENC_UPMV_SIZE;
661 buf_size1 -= S5P_FIMV_ENC_UPMV_SIZE;
662 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_ACDC_COEF_ADR);
663 buf_addr1 += S5P_FIMV_ENC_ACDCCOEF_SIZE;
664 buf_size1 -= S5P_FIMV_ENC_ACDCCOEF_SIZE;
665 mfc_debug(2, "buf_size1: %d, buf_size2: %d\n",
666 buf_size1, buf_size2);
669 mfc_err("Unknown codec set for encoding: %d\n",
676 static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx)
678 struct s5p_mfc_dev *dev = ctx->dev;
679 struct s5p_mfc_enc_params *p = &ctx->enc_params;
684 mfc_write(dev, ctx->img_width, S5P_FIMV_ENC_HSIZE_PX);
686 mfc_write(dev, ctx->img_height, S5P_FIMV_ENC_VSIZE_PX);
687 /* pictype : enable, IDR period */
688 reg = mfc_read(dev, S5P_FIMV_ENC_PIC_TYPE_CTRL);
692 mfc_write(dev, reg, S5P_FIMV_ENC_PIC_TYPE_CTRL);
693 mfc_write(dev, 0, S5P_FIMV_ENC_B_RECON_WRITE_ON);
694 /* multi-slice control */
695 /* multi-slice MB number or bit size */
696 mfc_write(dev, p->slice_mode, S5P_FIMV_ENC_MSLICE_CTRL);
697 if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB) {
698 mfc_write(dev, p->slice_mb, S5P_FIMV_ENC_MSLICE_MB);
699 } else if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES) {
700 mfc_write(dev, p->slice_bit, S5P_FIMV_ENC_MSLICE_BIT);
702 mfc_write(dev, 0, S5P_FIMV_ENC_MSLICE_MB);
703 mfc_write(dev, 0, S5P_FIMV_ENC_MSLICE_BIT);
705 /* cyclic intra refresh */
706 mfc_write(dev, p->intra_refresh_mb, S5P_FIMV_ENC_CIR_CTRL);
707 /* memory structure cur. frame */
708 if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M)
709 mfc_write(dev, 0, S5P_FIMV_ENC_MAP_FOR_CUR);
710 else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT)
711 mfc_write(dev, 3, S5P_FIMV_ENC_MAP_FOR_CUR);
712 /* padding control & value */
713 reg = mfc_read(dev, S5P_FIMV_ENC_PADDING_CTRL);
718 reg &= ~(0xFF << 16);
719 reg |= (p->pad_cr << 16);
722 reg |= (p->pad_cb << 8);
725 reg |= (p->pad_luma);
727 /** disable & all value clear */
730 mfc_write(dev, reg, S5P_FIMV_ENC_PADDING_CTRL);
731 /* rate control config. */
732 reg = mfc_read(dev, S5P_FIMV_ENC_RC_CONFIG);
733 /** frame-level rate control */
735 reg |= (p->rc_frame << 9);
736 mfc_write(dev, reg, S5P_FIMV_ENC_RC_CONFIG);
739 mfc_write(dev, p->rc_bitrate,
740 S5P_FIMV_ENC_RC_BIT_RATE);
742 mfc_write(dev, 0, S5P_FIMV_ENC_RC_BIT_RATE);
743 /* reaction coefficient */
745 mfc_write(dev, p->rc_reaction_coeff, S5P_FIMV_ENC_RC_RPARA);
746 shm = s5p_mfc_read_info_v5(ctx, EXT_ENC_CONTROL);
747 /* seq header ctrl */
749 shm |= (p->seq_hdr_mode << 3);
750 /* frame skip mode */
752 shm |= (p->frame_skip_mode << 1);
753 s5p_mfc_write_info_v5(ctx, shm, EXT_ENC_CONTROL);
754 /* fixed target bit */
755 s5p_mfc_write_info_v5(ctx, p->fixed_target_bit, RC_CONTROL_CONFIG);
759 static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
761 struct s5p_mfc_dev *dev = ctx->dev;
762 struct s5p_mfc_enc_params *p = &ctx->enc_params;
763 struct s5p_mfc_h264_enc_params *p_264 = &p->codec.h264;
767 s5p_mfc_set_enc_params(ctx);
768 /* pictype : number of B */
769 reg = mfc_read(dev, S5P_FIMV_ENC_PIC_TYPE_CTRL);
770 /* num_b_frame - 0 ~ 2 */
772 reg |= (p->num_b_frame << 16);
773 mfc_write(dev, reg, S5P_FIMV_ENC_PIC_TYPE_CTRL);
774 /* profile & level */
775 reg = mfc_read(dev, S5P_FIMV_ENC_PROFILE);
778 reg |= (p_264->level << 8);
779 /* profile - 0 ~ 2 */
781 reg |= p_264->profile;
782 mfc_write(dev, reg, S5P_FIMV_ENC_PROFILE);
784 mfc_write(dev, p_264->interlace, S5P_FIMV_ENC_PIC_STRUCT);
786 if (p_264->interlace)
787 mfc_write(dev, ctx->img_height >> 1, S5P_FIMV_ENC_VSIZE_PX);
788 /* loopfilter ctrl */
789 mfc_write(dev, p_264->loop_filter_mode, S5P_FIMV_ENC_LF_CTRL);
790 /* loopfilter alpha offset */
791 if (p_264->loop_filter_alpha < 0) {
793 reg |= (0xFF - p_264->loop_filter_alpha) + 1;
796 reg |= (p_264->loop_filter_alpha & 0xF);
798 mfc_write(dev, reg, S5P_FIMV_ENC_ALPHA_OFF);
799 /* loopfilter beta offset */
800 if (p_264->loop_filter_beta < 0) {
802 reg |= (0xFF - p_264->loop_filter_beta) + 1;
805 reg |= (p_264->loop_filter_beta & 0xF);
807 mfc_write(dev, reg, S5P_FIMV_ENC_BETA_OFF);
808 /* entropy coding mode */
809 if (p_264->entropy_mode == V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC)
810 mfc_write(dev, 1, S5P_FIMV_ENC_H264_ENTROPY_MODE);
812 mfc_write(dev, 0, S5P_FIMV_ENC_H264_ENTROPY_MODE);
813 /* number of ref. picture */
814 reg = mfc_read(dev, S5P_FIMV_ENC_H264_NUM_OF_REF);
815 /* num of ref. pictures of P */
817 reg |= (p_264->num_ref_pic_4p << 5);
818 /* max number of ref. pictures */
820 reg |= p_264->max_ref_pic;
821 mfc_write(dev, reg, S5P_FIMV_ENC_H264_NUM_OF_REF);
822 /* 8x8 transform enable */
823 mfc_write(dev, p_264->_8x8_transform, S5P_FIMV_ENC_H264_TRANS_FLAG);
824 /* rate control config. */
825 reg = mfc_read(dev, S5P_FIMV_ENC_RC_CONFIG);
826 /* macroblock level rate control */
828 reg |= (p->rc_mb << 8);
831 reg |= p_264->rc_frame_qp;
832 mfc_write(dev, reg, S5P_FIMV_ENC_RC_CONFIG);
834 if (p->rc_frame && p->rc_framerate_denom)
835 mfc_write(dev, p->rc_framerate_num * 1000
836 / p->rc_framerate_denom, S5P_FIMV_ENC_RC_FRAME_RATE);
838 mfc_write(dev, 0, S5P_FIMV_ENC_RC_FRAME_RATE);
839 /* max & min value of QP */
840 reg = mfc_read(dev, S5P_FIMV_ENC_RC_QBOUND);
843 reg |= (p_264->rc_max_qp << 8);
846 reg |= p_264->rc_min_qp;
847 mfc_write(dev, reg, S5P_FIMV_ENC_RC_QBOUND);
848 /* macroblock adaptive scaling features */
850 reg = mfc_read(dev, S5P_FIMV_ENC_RC_MB_CTRL);
853 reg |= (p_264->rc_mb_dark << 3);
856 reg |= (p_264->rc_mb_smooth << 2);
859 reg |= (p_264->rc_mb_static << 1);
860 /* high activity region */
862 reg |= p_264->rc_mb_activity;
863 mfc_write(dev, reg, S5P_FIMV_ENC_RC_MB_CTRL);
865 if (!p->rc_frame && !p->rc_mb) {
866 shm = s5p_mfc_read_info_v5(ctx, P_B_FRAME_QP);
868 shm |= ((p_264->rc_b_frame_qp & 0x3F) << 6);
869 shm |= (p_264->rc_p_frame_qp & 0x3F);
870 s5p_mfc_write_info_v5(ctx, shm, P_B_FRAME_QP);
872 /* extended encoder ctrl */
873 shm = s5p_mfc_read_info_v5(ctx, EXT_ENC_CONTROL);
876 shm |= (p_264->vui_sar << 1);
877 s5p_mfc_write_info_v5(ctx, shm, EXT_ENC_CONTROL);
878 if (p_264->vui_sar) {
879 /* aspect ration IDC */
880 shm = s5p_mfc_read_info_v5(ctx, SAMPLE_ASPECT_RATIO_IDC);
882 shm |= p_264->vui_sar_idc;
883 s5p_mfc_write_info_v5(ctx, shm, SAMPLE_ASPECT_RATIO_IDC);
884 if (p_264->vui_sar_idc == 0xFF) {
886 shm = s5p_mfc_read_info_v5(ctx, EXTENDED_SAR);
887 shm &= ~(0xFFFFFFFF);
888 shm |= p_264->vui_ext_sar_width << 16;
889 shm |= p_264->vui_ext_sar_height;
890 s5p_mfc_write_info_v5(ctx, shm, EXTENDED_SAR);
893 /* intra picture period for H.264 */
894 shm = s5p_mfc_read_info_v5(ctx, H264_I_PERIOD);
897 shm |= (p_264->open_gop << 16);
899 if (p_264->open_gop) {
901 shm |= p_264->open_gop_size;
903 s5p_mfc_write_info_v5(ctx, shm, H264_I_PERIOD);
904 /* extended encoder ctrl */
905 shm = s5p_mfc_read_info_v5(ctx, EXT_ENC_CONTROL);
906 /* vbv buffer size */
907 if (p->frame_skip_mode ==
908 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
909 shm &= ~(0xFFFF << 16);
910 shm |= (p_264->cpb_size << 16);
912 s5p_mfc_write_info_v5(ctx, shm, EXT_ENC_CONTROL);
916 static int s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx)
918 struct s5p_mfc_dev *dev = ctx->dev;
919 struct s5p_mfc_enc_params *p = &ctx->enc_params;
920 struct s5p_mfc_mpeg4_enc_params *p_mpeg4 = &p->codec.mpeg4;
923 unsigned int framerate;
925 s5p_mfc_set_enc_params(ctx);
926 /* pictype : number of B */
927 reg = mfc_read(dev, S5P_FIMV_ENC_PIC_TYPE_CTRL);
928 /* num_b_frame - 0 ~ 2 */
930 reg |= (p->num_b_frame << 16);
931 mfc_write(dev, reg, S5P_FIMV_ENC_PIC_TYPE_CTRL);
932 /* profile & level */
933 reg = mfc_read(dev, S5P_FIMV_ENC_PROFILE);
936 reg |= (p_mpeg4->level << 8);
937 /* profile - 0 ~ 2 */
939 reg |= p_mpeg4->profile;
940 mfc_write(dev, reg, S5P_FIMV_ENC_PROFILE);
942 mfc_write(dev, p_mpeg4->quarter_pixel, S5P_FIMV_ENC_MPEG4_QUART_PXL);
945 shm = s5p_mfc_read_info_v5(ctx, P_B_FRAME_QP);
947 shm |= ((p_mpeg4->rc_b_frame_qp & 0x3F) << 6);
948 shm |= (p_mpeg4->rc_p_frame_qp & 0x3F);
949 s5p_mfc_write_info_v5(ctx, shm, P_B_FRAME_QP);
953 if (p->rc_framerate_denom > 0) {
954 framerate = p->rc_framerate_num * 1000 /
955 p->rc_framerate_denom;
956 mfc_write(dev, framerate,
957 S5P_FIMV_ENC_RC_FRAME_RATE);
958 shm = s5p_mfc_read_info_v5(ctx, RC_VOP_TIMING);
959 shm &= ~(0xFFFFFFFF);
961 shm |= ((p->rc_framerate_num & 0x7FFF) << 16);
962 shm |= (p->rc_framerate_denom & 0xFFFF);
963 s5p_mfc_write_info_v5(ctx, shm, RC_VOP_TIMING);
966 mfc_write(dev, 0, S5P_FIMV_ENC_RC_FRAME_RATE);
968 /* rate control config. */
969 reg = mfc_read(dev, S5P_FIMV_ENC_RC_CONFIG);
972 reg |= p_mpeg4->rc_frame_qp;
973 mfc_write(dev, reg, S5P_FIMV_ENC_RC_CONFIG);
974 /* max & min value of QP */
975 reg = mfc_read(dev, S5P_FIMV_ENC_RC_QBOUND);
978 reg |= (p_mpeg4->rc_max_qp << 8);
981 reg |= p_mpeg4->rc_min_qp;
982 mfc_write(dev, reg, S5P_FIMV_ENC_RC_QBOUND);
983 /* extended encoder ctrl */
984 shm = s5p_mfc_read_info_v5(ctx, EXT_ENC_CONTROL);
985 /* vbv buffer size */
986 if (p->frame_skip_mode ==
987 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
988 shm &= ~(0xFFFF << 16);
989 shm |= (p->vbv_size << 16);
991 s5p_mfc_write_info_v5(ctx, shm, EXT_ENC_CONTROL);
995 static int s5p_mfc_set_enc_params_h263(struct s5p_mfc_ctx *ctx)
997 struct s5p_mfc_dev *dev = ctx->dev;
998 struct s5p_mfc_enc_params *p = &ctx->enc_params;
999 struct s5p_mfc_mpeg4_enc_params *p_h263 = &p->codec.mpeg4;
1003 s5p_mfc_set_enc_params(ctx);
1006 shm = s5p_mfc_read_info_v5(ctx, P_B_FRAME_QP);
1008 shm |= (p_h263->rc_p_frame_qp & 0x3F);
1009 s5p_mfc_write_info_v5(ctx, shm, P_B_FRAME_QP);
1012 if (p->rc_frame && p->rc_framerate_denom)
1013 mfc_write(dev, p->rc_framerate_num * 1000
1014 / p->rc_framerate_denom, S5P_FIMV_ENC_RC_FRAME_RATE);
1016 mfc_write(dev, 0, S5P_FIMV_ENC_RC_FRAME_RATE);
1017 /* rate control config. */
1018 reg = mfc_read(dev, S5P_FIMV_ENC_RC_CONFIG);
1021 reg |= p_h263->rc_frame_qp;
1022 mfc_write(dev, reg, S5P_FIMV_ENC_RC_CONFIG);
1023 /* max & min value of QP */
1024 reg = mfc_read(dev, S5P_FIMV_ENC_RC_QBOUND);
1026 reg &= ~(0x3F << 8);
1027 reg |= (p_h263->rc_max_qp << 8);
1030 reg |= p_h263->rc_min_qp;
1031 mfc_write(dev, reg, S5P_FIMV_ENC_RC_QBOUND);
1032 /* extended encoder ctrl */
1033 shm = s5p_mfc_read_info_v5(ctx, EXT_ENC_CONTROL);
1034 /* vbv buffer size */
1035 if (p->frame_skip_mode ==
1036 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
1037 shm &= ~(0xFFFF << 16);
1038 shm |= (p->vbv_size << 16);
1040 s5p_mfc_write_info_v5(ctx, shm, EXT_ENC_CONTROL);
1044 /* Initialize decoding */
1045 static int s5p_mfc_init_decode_v5(struct s5p_mfc_ctx *ctx)
1047 struct s5p_mfc_dev *dev = ctx->dev;
1049 s5p_mfc_set_shared_buffer(ctx);
1050 /* Setup loop filter, for decoding this is only valid for MPEG4 */
1051 if (ctx->codec_mode == S5P_MFC_CODEC_MPEG4_DEC)
1052 mfc_write(dev, ctx->loop_filter_mpeg4, S5P_FIMV_ENC_LF_CTRL);
1054 mfc_write(dev, 0, S5P_FIMV_ENC_LF_CTRL);
1055 mfc_write(dev, ((ctx->slice_interface & S5P_FIMV_SLICE_INT_MASK) <<
1056 S5P_FIMV_SLICE_INT_SHIFT) | (ctx->display_delay_enable <<
1057 S5P_FIMV_DDELAY_ENA_SHIFT) | ((ctx->display_delay &
1058 S5P_FIMV_DDELAY_VAL_MASK) << S5P_FIMV_DDELAY_VAL_SHIFT),
1059 S5P_FIMV_SI_CH0_DPB_CONF_CTRL);
1061 ((S5P_FIMV_CH_SEQ_HEADER & S5P_FIMV_CH_MASK) << S5P_FIMV_CH_SHIFT)
1062 | (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID);
1066 static void s5p_mfc_set_flush(struct s5p_mfc_ctx *ctx, int flush)
1068 struct s5p_mfc_dev *dev = ctx->dev;
1072 dpb = mfc_read(dev, S5P_FIMV_SI_CH0_DPB_CONF_CTRL) | (
1073 S5P_FIMV_DPB_FLUSH_MASK << S5P_FIMV_DPB_FLUSH_SHIFT);
1075 dpb = mfc_read(dev, S5P_FIMV_SI_CH0_DPB_CONF_CTRL) &
1076 ~(S5P_FIMV_DPB_FLUSH_MASK << S5P_FIMV_DPB_FLUSH_SHIFT);
1077 mfc_write(dev, dpb, S5P_FIMV_SI_CH0_DPB_CONF_CTRL);
1080 /* Decode a single frame */
1081 static int s5p_mfc_decode_one_frame_v5(struct s5p_mfc_ctx *ctx,
1082 enum s5p_mfc_decode_arg last_frame)
1084 struct s5p_mfc_dev *dev = ctx->dev;
1086 mfc_write(dev, ctx->dec_dst_flag, S5P_FIMV_SI_CH0_RELEASE_BUF);
1087 s5p_mfc_set_shared_buffer(ctx);
1088 s5p_mfc_set_flush(ctx, ctx->dpb_flush_flag);
1089 /* Issue different commands to instance basing on whether it
1090 * is the last frame or not. */
1091 switch (last_frame) {
1093 mfc_write(dev, ((S5P_FIMV_CH_FRAME_START & S5P_FIMV_CH_MASK) <<
1094 S5P_FIMV_CH_SHIFT) | (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID);
1096 case MFC_DEC_LAST_FRAME:
1097 mfc_write(dev, ((S5P_FIMV_CH_LAST_FRAME & S5P_FIMV_CH_MASK) <<
1098 S5P_FIMV_CH_SHIFT) | (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID);
1100 case MFC_DEC_RES_CHANGE:
1101 mfc_write(dev, ((S5P_FIMV_CH_FRAME_START_REALLOC &
1102 S5P_FIMV_CH_MASK) << S5P_FIMV_CH_SHIFT) | (ctx->inst_no),
1103 S5P_FIMV_SI_CH0_INST_ID);
1106 mfc_debug(2, "Decoding a usual frame\n");
1110 static int s5p_mfc_init_encode_v5(struct s5p_mfc_ctx *ctx)
1112 struct s5p_mfc_dev *dev = ctx->dev;
1114 if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC)
1115 s5p_mfc_set_enc_params_h264(ctx);
1116 else if (ctx->codec_mode == S5P_MFC_CODEC_MPEG4_ENC)
1117 s5p_mfc_set_enc_params_mpeg4(ctx);
1118 else if (ctx->codec_mode == S5P_MFC_CODEC_H263_ENC)
1119 s5p_mfc_set_enc_params_h263(ctx);
1121 mfc_err("Unknown codec for encoding (%x)\n",
1125 s5p_mfc_set_shared_buffer(ctx);
1126 mfc_write(dev, ((S5P_FIMV_CH_SEQ_HEADER << 16) & 0x70000) |
1127 (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID);
1131 /* Encode a single frame */
1132 static int s5p_mfc_encode_one_frame_v5(struct s5p_mfc_ctx *ctx)
1134 struct s5p_mfc_dev *dev = ctx->dev;
1136 /* memory structure cur. frame */
1137 if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M)
1138 mfc_write(dev, 0, S5P_FIMV_ENC_MAP_FOR_CUR);
1139 else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT)
1140 mfc_write(dev, 3, S5P_FIMV_ENC_MAP_FOR_CUR);
1141 s5p_mfc_set_shared_buffer(ctx);
1143 if (ctx->state == MFCINST_FINISHING)
1144 cmd = S5P_FIMV_CH_LAST_FRAME;
1146 cmd = S5P_FIMV_CH_FRAME_START;
1147 mfc_write(dev, ((cmd & S5P_FIMV_CH_MASK) << S5P_FIMV_CH_SHIFT)
1148 | (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID);
1153 static int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev)
1155 unsigned long flags;
1159 spin_lock_irqsave(&dev->condlock, flags);
1160 new_ctx = (dev->curr_ctx + 1) % MFC_NUM_CONTEXTS;
1162 while (!test_bit(new_ctx, &dev->ctx_work_bits)) {
1163 new_ctx = (new_ctx + 1) % MFC_NUM_CONTEXTS;
1164 if (++cnt > MFC_NUM_CONTEXTS) {
1165 /* No contexts to run */
1166 spin_unlock_irqrestore(&dev->condlock, flags);
1170 spin_unlock_irqrestore(&dev->condlock, flags);
1174 static void s5p_mfc_run_res_change(struct s5p_mfc_ctx *ctx)
1176 struct s5p_mfc_dev *dev = ctx->dev;
1178 s5p_mfc_set_dec_stream_buffer_v5(ctx, 0, 0, 0);
1179 dev->curr_ctx = ctx->num;
1180 s5p_mfc_clean_ctx_int_flags(ctx);
1181 s5p_mfc_decode_one_frame_v5(ctx, MFC_DEC_RES_CHANGE);
1184 static int s5p_mfc_run_dec_frame(struct s5p_mfc_ctx *ctx, int last_frame)
1186 struct s5p_mfc_dev *dev = ctx->dev;
1187 struct s5p_mfc_buf *temp_vb;
1188 unsigned long flags;
1190 if (ctx->state == MFCINST_FINISHING) {
1191 last_frame = MFC_DEC_LAST_FRAME;
1192 s5p_mfc_set_dec_stream_buffer_v5(ctx, 0, 0, 0);
1193 dev->curr_ctx = ctx->num;
1194 s5p_mfc_clean_ctx_int_flags(ctx);
1195 s5p_mfc_decode_one_frame_v5(ctx, last_frame);
1199 spin_lock_irqsave(&dev->irqlock, flags);
1200 /* Frames are being decoded */
1201 if (list_empty(&ctx->src_queue)) {
1202 mfc_debug(2, "No src buffers\n");
1203 spin_unlock_irqrestore(&dev->irqlock, flags);
1206 /* Get the next source buffer */
1207 temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1208 temp_vb->flags |= MFC_BUF_FLAG_USED;
1209 s5p_mfc_set_dec_stream_buffer_v5(ctx,
1210 vb2_dma_contig_plane_dma_addr(temp_vb->b, 0),
1211 ctx->consumed_stream, temp_vb->b->v4l2_planes[0].bytesused);
1212 spin_unlock_irqrestore(&dev->irqlock, flags);
1213 dev->curr_ctx = ctx->num;
1214 s5p_mfc_clean_ctx_int_flags(ctx);
1215 if (temp_vb->b->v4l2_planes[0].bytesused == 0) {
1216 last_frame = MFC_DEC_LAST_FRAME;
1217 mfc_debug(2, "Setting ctx->state to FINISHING\n");
1218 ctx->state = MFCINST_FINISHING;
1220 s5p_mfc_decode_one_frame_v5(ctx, last_frame);
1224 static int s5p_mfc_run_enc_frame(struct s5p_mfc_ctx *ctx)
1226 struct s5p_mfc_dev *dev = ctx->dev;
1227 unsigned long flags;
1228 struct s5p_mfc_buf *dst_mb;
1229 struct s5p_mfc_buf *src_mb;
1230 unsigned long src_y_addr, src_c_addr, dst_addr;
1231 unsigned int dst_size;
1233 spin_lock_irqsave(&dev->irqlock, flags);
1234 if (list_empty(&ctx->src_queue) && ctx->state != MFCINST_FINISHING) {
1235 mfc_debug(2, "no src buffers\n");
1236 spin_unlock_irqrestore(&dev->irqlock, flags);
1239 if (list_empty(&ctx->dst_queue)) {
1240 mfc_debug(2, "no dst buffers\n");
1241 spin_unlock_irqrestore(&dev->irqlock, flags);
1244 if (list_empty(&ctx->src_queue)) {
1245 /* send null frame */
1246 s5p_mfc_set_enc_frame_buffer_v5(ctx, dev->bank2, dev->bank2);
1249 src_mb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf,
1251 src_mb->flags |= MFC_BUF_FLAG_USED;
1252 if (src_mb->b->v4l2_planes[0].bytesused == 0) {
1253 /* send null frame */
1254 s5p_mfc_set_enc_frame_buffer_v5(ctx, dev->bank2,
1256 ctx->state = MFCINST_FINISHING;
1258 src_y_addr = vb2_dma_contig_plane_dma_addr(src_mb->b,
1260 src_c_addr = vb2_dma_contig_plane_dma_addr(src_mb->b,
1262 s5p_mfc_set_enc_frame_buffer_v5(ctx, src_y_addr,
1264 if (src_mb->flags & MFC_BUF_FLAG_EOS)
1265 ctx->state = MFCINST_FINISHING;
1268 dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);
1269 dst_mb->flags |= MFC_BUF_FLAG_USED;
1270 dst_addr = vb2_dma_contig_plane_dma_addr(dst_mb->b, 0);
1271 dst_size = vb2_plane_size(dst_mb->b, 0);
1272 s5p_mfc_set_enc_stream_buffer_v5(ctx, dst_addr, dst_size);
1273 spin_unlock_irqrestore(&dev->irqlock, flags);
1274 dev->curr_ctx = ctx->num;
1275 s5p_mfc_clean_ctx_int_flags(ctx);
1276 mfc_debug(2, "encoding buffer with index=%d state=%d\n",
1277 src_mb ? src_mb->b->v4l2_buf.index : -1, ctx->state);
1278 s5p_mfc_encode_one_frame_v5(ctx);
1282 static void s5p_mfc_run_init_dec(struct s5p_mfc_ctx *ctx)
1284 struct s5p_mfc_dev *dev = ctx->dev;
1285 unsigned long flags;
1286 struct s5p_mfc_buf *temp_vb;
1288 /* Initializing decoding - parsing header */
1289 spin_lock_irqsave(&dev->irqlock, flags);
1290 mfc_debug(2, "Preparing to init decoding\n");
1291 temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1292 s5p_mfc_set_dec_desc_buffer(ctx);
1293 mfc_debug(2, "Header size: %d\n", temp_vb->b->v4l2_planes[0].bytesused);
1294 s5p_mfc_set_dec_stream_buffer_v5(ctx,
1295 vb2_dma_contig_plane_dma_addr(temp_vb->b, 0),
1296 0, temp_vb->b->v4l2_planes[0].bytesused);
1297 spin_unlock_irqrestore(&dev->irqlock, flags);
1298 dev->curr_ctx = ctx->num;
1299 s5p_mfc_clean_ctx_int_flags(ctx);
1300 s5p_mfc_init_decode_v5(ctx);
1303 static void s5p_mfc_run_init_enc(struct s5p_mfc_ctx *ctx)
1305 struct s5p_mfc_dev *dev = ctx->dev;
1306 unsigned long flags;
1307 struct s5p_mfc_buf *dst_mb;
1308 unsigned long dst_addr;
1309 unsigned int dst_size;
1311 s5p_mfc_set_enc_ref_buffer_v5(ctx);
1312 spin_lock_irqsave(&dev->irqlock, flags);
1313 dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);
1314 dst_addr = vb2_dma_contig_plane_dma_addr(dst_mb->b, 0);
1315 dst_size = vb2_plane_size(dst_mb->b, 0);
1316 s5p_mfc_set_enc_stream_buffer_v5(ctx, dst_addr, dst_size);
1317 spin_unlock_irqrestore(&dev->irqlock, flags);
1318 dev->curr_ctx = ctx->num;
1319 s5p_mfc_clean_ctx_int_flags(ctx);
1320 s5p_mfc_init_encode_v5(ctx);
1323 static int s5p_mfc_run_init_dec_buffers(struct s5p_mfc_ctx *ctx)
1325 struct s5p_mfc_dev *dev = ctx->dev;
1326 unsigned long flags;
1327 struct s5p_mfc_buf *temp_vb;
1331 * Header was parsed now starting processing
1332 * First set the output frame buffers
1334 if (ctx->capture_state != QUEUE_BUFS_MMAPED) {
1335 mfc_err("It seems that not all destionation buffers were "
1336 "mmaped\nMFC requires that all destination are mmaped "
1337 "before starting processing\n");
1340 spin_lock_irqsave(&dev->irqlock, flags);
1341 if (list_empty(&ctx->src_queue)) {
1342 mfc_err("Header has been deallocated in the middle of"
1343 " initialization\n");
1344 spin_unlock_irqrestore(&dev->irqlock, flags);
1347 temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1348 mfc_debug(2, "Header size: %d\n", temp_vb->b->v4l2_planes[0].bytesused);
1349 s5p_mfc_set_dec_stream_buffer_v5(ctx,
1350 vb2_dma_contig_plane_dma_addr(temp_vb->b, 0),
1351 0, temp_vb->b->v4l2_planes[0].bytesused);
1352 spin_unlock_irqrestore(&dev->irqlock, flags);
1353 dev->curr_ctx = ctx->num;
1354 s5p_mfc_clean_ctx_int_flags(ctx);
1355 ret = s5p_mfc_set_dec_frame_buffer_v5(ctx);
1357 mfc_err("Failed to alloc frame mem\n");
1358 ctx->state = MFCINST_ERROR;
1363 /* Try running an operation on hardware */
1364 static void s5p_mfc_try_run_v5(struct s5p_mfc_dev *dev)
1366 struct s5p_mfc_ctx *ctx;
1368 unsigned int ret = 0;
1370 if (test_bit(0, &dev->enter_suspend)) {
1371 mfc_debug(1, "Entering suspend so do not schedule any jobs\n");
1374 /* Check whether hardware is not running */
1375 if (test_and_set_bit(0, &dev->hw_lock) != 0) {
1376 /* This is perfectly ok, the scheduled ctx should wait */
1377 mfc_debug(1, "Couldn't lock HW\n");
1380 /* Choose the context to run */
1381 new_ctx = s5p_mfc_get_new_ctx(dev);
1383 /* No contexts to run */
1384 if (test_and_clear_bit(0, &dev->hw_lock) == 0) {
1385 mfc_err("Failed to unlock hardware\n");
1388 mfc_debug(1, "No ctx is scheduled to be run\n");
1391 ctx = dev->ctx[new_ctx];
1392 /* Got context to run in ctx */
1394 * Last frame has already been sent to MFC.
1395 * Now obtaining frames from MFC buffer
1398 if (ctx->type == MFCINST_DECODER) {
1399 s5p_mfc_set_dec_desc_buffer(ctx);
1400 switch (ctx->state) {
1401 case MFCINST_FINISHING:
1402 s5p_mfc_run_dec_frame(ctx, MFC_DEC_LAST_FRAME);
1404 case MFCINST_RUNNING:
1405 ret = s5p_mfc_run_dec_frame(ctx, MFC_DEC_FRAME);
1408 s5p_mfc_clean_ctx_int_flags(ctx);
1409 ret = s5p_mfc_hw_call(dev->mfc_cmds, open_inst_cmd,
1412 case MFCINST_RETURN_INST:
1413 s5p_mfc_clean_ctx_int_flags(ctx);
1414 ret = s5p_mfc_hw_call(dev->mfc_cmds, close_inst_cmd,
1417 case MFCINST_GOT_INST:
1418 s5p_mfc_run_init_dec(ctx);
1420 case MFCINST_HEAD_PARSED:
1421 ret = s5p_mfc_run_init_dec_buffers(ctx);
1422 mfc_debug(1, "head parsed\n");
1424 case MFCINST_RES_CHANGE_INIT:
1425 s5p_mfc_run_res_change(ctx);
1427 case MFCINST_RES_CHANGE_FLUSH:
1428 s5p_mfc_run_dec_frame(ctx, MFC_DEC_FRAME);
1430 case MFCINST_RES_CHANGE_END:
1431 mfc_debug(2, "Finished remaining frames after resolution change\n");
1432 ctx->capture_state = QUEUE_FREE;
1433 mfc_debug(2, "Will re-init the codec\n");
1434 s5p_mfc_run_init_dec(ctx);
1439 } else if (ctx->type == MFCINST_ENCODER) {
1440 switch (ctx->state) {
1441 case MFCINST_FINISHING:
1442 case MFCINST_RUNNING:
1443 ret = s5p_mfc_run_enc_frame(ctx);
1446 s5p_mfc_clean_ctx_int_flags(ctx);
1447 ret = s5p_mfc_hw_call(dev->mfc_cmds, open_inst_cmd,
1450 case MFCINST_RETURN_INST:
1451 s5p_mfc_clean_ctx_int_flags(ctx);
1452 ret = s5p_mfc_hw_call(dev->mfc_cmds, close_inst_cmd,
1455 case MFCINST_GOT_INST:
1456 s5p_mfc_run_init_enc(ctx);
1462 mfc_err("Invalid context type: %d\n", ctx->type);
1467 /* Free hardware lock */
1468 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
1469 mfc_err("Failed to unlock hardware\n");
1471 /* This is in deed imporant, as no operation has been
1472 * scheduled, reduce the clock count as no one will
1473 * ever do this, because no interrupt related to this try_run
1474 * will ever come from hardware. */
1475 s5p_mfc_clock_off();
1480 static void s5p_mfc_cleanup_queue_v5(struct list_head *lh, struct vb2_queue *vq)
1482 struct s5p_mfc_buf *b;
1485 while (!list_empty(lh)) {
1486 b = list_entry(lh->next, struct s5p_mfc_buf, list);
1487 for (i = 0; i < b->b->num_planes; i++)
1488 vb2_set_plane_payload(b->b, i, 0);
1489 vb2_buffer_done(b->b, VB2_BUF_STATE_ERROR);
1494 static void s5p_mfc_clear_int_flags_v5(struct s5p_mfc_dev *dev)
1496 mfc_write(dev, 0, S5P_FIMV_RISC_HOST_INT);
1497 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD);
1498 mfc_write(dev, 0xffff, S5P_FIMV_SI_RTN_CHID);
1501 static int s5p_mfc_get_dspl_y_adr_v5(struct s5p_mfc_dev *dev)
1503 return mfc_read(dev, S5P_FIMV_SI_DISPLAY_Y_ADR) << MFC_OFFSET_SHIFT;
1506 static int s5p_mfc_get_dec_y_adr_v5(struct s5p_mfc_dev *dev)
1508 return mfc_read(dev, S5P_FIMV_SI_DECODE_Y_ADR) << MFC_OFFSET_SHIFT;
1511 static int s5p_mfc_get_dspl_status_v5(struct s5p_mfc_dev *dev)
1513 return mfc_read(dev, S5P_FIMV_SI_DISPLAY_STATUS);
1516 static int s5p_mfc_get_dec_status_v5(struct s5p_mfc_dev *dev)
1518 return mfc_read(dev, S5P_FIMV_SI_DECODE_STATUS);
1521 static int s5p_mfc_get_dec_frame_type_v5(struct s5p_mfc_dev *dev)
1523 return mfc_read(dev, S5P_FIMV_DECODE_FRAME_TYPE) &
1524 S5P_FIMV_DECODE_FRAME_MASK;
1527 static int s5p_mfc_get_disp_frame_type_v5(struct s5p_mfc_ctx *ctx)
1529 return (s5p_mfc_read_info_v5(ctx, DISP_PIC_FRAME_TYPE) >>
1530 S5P_FIMV_SHARED_DISP_FRAME_TYPE_SHIFT) &
1531 S5P_FIMV_DECODE_FRAME_MASK;
1534 static int s5p_mfc_get_consumed_stream_v5(struct s5p_mfc_dev *dev)
1536 return mfc_read(dev, S5P_FIMV_SI_CONSUMED_BYTES);
1539 static int s5p_mfc_get_int_reason_v5(struct s5p_mfc_dev *dev)
1542 reason = mfc_read(dev, S5P_FIMV_RISC2HOST_CMD) &
1543 S5P_FIMV_RISC2HOST_CMD_MASK;
1545 case S5P_FIMV_R2H_CMD_OPEN_INSTANCE_RET:
1546 reason = S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET;
1548 case S5P_FIMV_R2H_CMD_CLOSE_INSTANCE_RET:
1549 reason = S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET;
1551 case S5P_FIMV_R2H_CMD_SEQ_DONE_RET:
1552 reason = S5P_MFC_R2H_CMD_SEQ_DONE_RET;
1554 case S5P_FIMV_R2H_CMD_FRAME_DONE_RET:
1555 reason = S5P_MFC_R2H_CMD_FRAME_DONE_RET;
1557 case S5P_FIMV_R2H_CMD_SLICE_DONE_RET:
1558 reason = S5P_MFC_R2H_CMD_SLICE_DONE_RET;
1560 case S5P_FIMV_R2H_CMD_SYS_INIT_RET:
1561 reason = S5P_MFC_R2H_CMD_SYS_INIT_RET;
1563 case S5P_FIMV_R2H_CMD_FW_STATUS_RET:
1564 reason = S5P_MFC_R2H_CMD_FW_STATUS_RET;
1566 case S5P_FIMV_R2H_CMD_SLEEP_RET:
1567 reason = S5P_MFC_R2H_CMD_SLEEP_RET;
1569 case S5P_FIMV_R2H_CMD_WAKEUP_RET:
1570 reason = S5P_MFC_R2H_CMD_WAKEUP_RET;
1572 case S5P_FIMV_R2H_CMD_INIT_BUFFERS_RET:
1573 reason = S5P_MFC_R2H_CMD_INIT_BUFFERS_RET;
1575 case S5P_FIMV_R2H_CMD_ENC_COMPLETE_RET:
1576 reason = S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET;
1578 case S5P_FIMV_R2H_CMD_ERR_RET:
1579 reason = S5P_MFC_R2H_CMD_ERR_RET;
1582 reason = S5P_MFC_R2H_CMD_EMPTY;
1587 static int s5p_mfc_get_int_err_v5(struct s5p_mfc_dev *dev)
1589 return mfc_read(dev, S5P_FIMV_RISC2HOST_ARG2);
1592 static int s5p_mfc_err_dec_v5(unsigned int err)
1594 return (err & S5P_FIMV_ERR_DEC_MASK) >> S5P_FIMV_ERR_DEC_SHIFT;
1597 static int s5p_mfc_err_dspl_v5(unsigned int err)
1599 return (err & S5P_FIMV_ERR_DSPL_MASK) >> S5P_FIMV_ERR_DSPL_SHIFT;
1602 static int s5p_mfc_get_img_width_v5(struct s5p_mfc_dev *dev)
1604 return mfc_read(dev, S5P_FIMV_SI_HRESOL);
1607 static int s5p_mfc_get_img_height_v5(struct s5p_mfc_dev *dev)
1609 return mfc_read(dev, S5P_FIMV_SI_VRESOL);
1612 static int s5p_mfc_get_dpb_count_v5(struct s5p_mfc_dev *dev)
1614 return mfc_read(dev, S5P_FIMV_SI_BUF_NUMBER);
1617 static int s5p_mfc_get_mv_count_v5(struct s5p_mfc_dev *dev)
1623 static int s5p_mfc_get_inst_no_v5(struct s5p_mfc_dev *dev)
1625 return mfc_read(dev, S5P_FIMV_RISC2HOST_ARG1);
1628 static int s5p_mfc_get_enc_strm_size_v5(struct s5p_mfc_dev *dev)
1630 return mfc_read(dev, S5P_FIMV_ENC_SI_STRM_SIZE);
1633 static int s5p_mfc_get_enc_slice_type_v5(struct s5p_mfc_dev *dev)
1635 return mfc_read(dev, S5P_FIMV_ENC_SI_SLICE_TYPE);
1638 static int s5p_mfc_get_enc_dpb_count_v5(struct s5p_mfc_dev *dev)
1643 static int s5p_mfc_get_enc_pic_count_v5(struct s5p_mfc_dev *dev)
1645 return mfc_read(dev, S5P_FIMV_ENC_SI_PIC_CNT);
1648 static int s5p_mfc_get_sei_avail_status_v5(struct s5p_mfc_ctx *ctx)
1650 return s5p_mfc_read_info_v5(ctx, FRAME_PACK_SEI_AVAIL);
1653 static int s5p_mfc_get_mvc_num_views_v5(struct s5p_mfc_dev *dev)
1658 static int s5p_mfc_get_mvc_view_id_v5(struct s5p_mfc_dev *dev)
1663 static unsigned int s5p_mfc_get_pic_type_top_v5(struct s5p_mfc_ctx *ctx)
1665 return s5p_mfc_read_info_v5(ctx, PIC_TIME_TOP);
1668 static unsigned int s5p_mfc_get_pic_type_bot_v5(struct s5p_mfc_ctx *ctx)
1670 return s5p_mfc_read_info_v5(ctx, PIC_TIME_BOT);
1673 static unsigned int s5p_mfc_get_crop_info_h_v5(struct s5p_mfc_ctx *ctx)
1675 return s5p_mfc_read_info_v5(ctx, CROP_INFO_H);
1678 static unsigned int s5p_mfc_get_crop_info_v_v5(struct s5p_mfc_ctx *ctx)
1680 return s5p_mfc_read_info_v5(ctx, CROP_INFO_V);
1683 /* Initialize opr function pointers for MFC v5 */
1684 static struct s5p_mfc_hw_ops s5p_mfc_ops_v5 = {
1685 .alloc_dec_temp_buffers = s5p_mfc_alloc_dec_temp_buffers_v5,
1686 .release_dec_desc_buffer = s5p_mfc_release_dec_desc_buffer_v5,
1687 .alloc_codec_buffers = s5p_mfc_alloc_codec_buffers_v5,
1688 .release_codec_buffers = s5p_mfc_release_codec_buffers_v5,
1689 .alloc_instance_buffer = s5p_mfc_alloc_instance_buffer_v5,
1690 .release_instance_buffer = s5p_mfc_release_instance_buffer_v5,
1691 .alloc_dev_context_buffer = s5p_mfc_alloc_dev_context_buffer_v5,
1692 .release_dev_context_buffer = s5p_mfc_release_dev_context_buffer_v5,
1693 .dec_calc_dpb_size = s5p_mfc_dec_calc_dpb_size_v5,
1694 .enc_calc_src_size = s5p_mfc_enc_calc_src_size_v5,
1695 .set_dec_stream_buffer = s5p_mfc_set_dec_stream_buffer_v5,
1696 .set_dec_frame_buffer = s5p_mfc_set_dec_frame_buffer_v5,
1697 .set_enc_stream_buffer = s5p_mfc_set_enc_stream_buffer_v5,
1698 .set_enc_frame_buffer = s5p_mfc_set_enc_frame_buffer_v5,
1699 .get_enc_frame_buffer = s5p_mfc_get_enc_frame_buffer_v5,
1700 .set_enc_ref_buffer = s5p_mfc_set_enc_ref_buffer_v5,
1701 .init_decode = s5p_mfc_init_decode_v5,
1702 .init_encode = s5p_mfc_init_encode_v5,
1703 .encode_one_frame = s5p_mfc_encode_one_frame_v5,
1704 .try_run = s5p_mfc_try_run_v5,
1705 .cleanup_queue = s5p_mfc_cleanup_queue_v5,
1706 .clear_int_flags = s5p_mfc_clear_int_flags_v5,
1707 .write_info = s5p_mfc_write_info_v5,
1708 .read_info = s5p_mfc_read_info_v5,
1709 .get_dspl_y_adr = s5p_mfc_get_dspl_y_adr_v5,
1710 .get_dec_y_adr = s5p_mfc_get_dec_y_adr_v5,
1711 .get_dspl_status = s5p_mfc_get_dspl_status_v5,
1712 .get_dec_status = s5p_mfc_get_dec_status_v5,
1713 .get_dec_frame_type = s5p_mfc_get_dec_frame_type_v5,
1714 .get_disp_frame_type = s5p_mfc_get_disp_frame_type_v5,
1715 .get_consumed_stream = s5p_mfc_get_consumed_stream_v5,
1716 .get_int_reason = s5p_mfc_get_int_reason_v5,
1717 .get_int_err = s5p_mfc_get_int_err_v5,
1718 .err_dec = s5p_mfc_err_dec_v5,
1719 .err_dspl = s5p_mfc_err_dspl_v5,
1720 .get_img_width = s5p_mfc_get_img_width_v5,
1721 .get_img_height = s5p_mfc_get_img_height_v5,
1722 .get_dpb_count = s5p_mfc_get_dpb_count_v5,
1723 .get_mv_count = s5p_mfc_get_mv_count_v5,
1724 .get_inst_no = s5p_mfc_get_inst_no_v5,
1725 .get_enc_strm_size = s5p_mfc_get_enc_strm_size_v5,
1726 .get_enc_slice_type = s5p_mfc_get_enc_slice_type_v5,
1727 .get_enc_dpb_count = s5p_mfc_get_enc_dpb_count_v5,
1728 .get_enc_pic_count = s5p_mfc_get_enc_pic_count_v5,
1729 .get_sei_avail_status = s5p_mfc_get_sei_avail_status_v5,
1730 .get_mvc_num_views = s5p_mfc_get_mvc_num_views_v5,
1731 .get_mvc_view_id = s5p_mfc_get_mvc_view_id_v5,
1732 .get_pic_type_top = s5p_mfc_get_pic_type_top_v5,
1733 .get_pic_type_bot = s5p_mfc_get_pic_type_bot_v5,
1734 .get_crop_info_h = s5p_mfc_get_crop_info_h_v5,
1735 .get_crop_info_v = s5p_mfc_get_crop_info_v_v5,
1738 struct s5p_mfc_hw_ops *s5p_mfc_init_hw_ops_v5(void)
1740 return &s5p_mfc_ops_v5;