1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Author: Jacob Chen <jacob-chen@iotwrt.com>
8 #include <linux/debugfs.h>
9 #include <linux/delay.h>
11 #include <linux/interrupt.h>
12 #include <linux/module.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/reset.h>
16 #include <linux/sched.h>
17 #include <linux/slab.h>
18 #include <linux/timer.h>
20 #include <linux/platform_device.h>
21 #include <media/v4l2-device.h>
22 #include <media/v4l2-event.h>
23 #include <media/v4l2-ioctl.h>
24 #include <media/v4l2-mem2mem.h>
25 #include <media/videobuf2-dma-sg.h>
26 #include <media/videobuf2-v4l2.h>
32 module_param(debug, int, 0644);
34 static void device_run(void *prv)
36 struct rga_ctx *ctx = prv;
37 struct rockchip_rga *rga = ctx->rga;
38 struct vb2_v4l2_buffer *src, *dst;
41 spin_lock_irqsave(&rga->ctrl_lock, flags);
45 src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
46 dst = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
48 rga_buf_map(&src->vb2_buf);
49 rga_buf_map(&dst->vb2_buf);
53 spin_unlock_irqrestore(&rga->ctrl_lock, flags);
56 static irqreturn_t rga_isr(int irq, void *prv)
58 struct rockchip_rga *rga = prv;
61 intr = rga_read(rga, RGA_INT) & 0xf;
63 rga_mod(rga, RGA_INT, intr << 4, 0xf << 4);
66 struct vb2_v4l2_buffer *src, *dst;
67 struct rga_ctx *ctx = rga->curr;
73 src = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
74 dst = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
79 dst->timecode = src->timecode;
80 dst->vb2_buf.timestamp = src->vb2_buf.timestamp;
81 dst->flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
82 dst->flags |= src->flags & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
84 v4l2_m2m_buf_done(src, VB2_BUF_STATE_DONE);
85 v4l2_m2m_buf_done(dst, VB2_BUF_STATE_DONE);
86 v4l2_m2m_job_finish(rga->m2m_dev, ctx->fh.m2m_ctx);
92 static const struct v4l2_m2m_ops rga_m2m_ops = {
93 .device_run = device_run,
97 queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq)
99 struct rga_ctx *ctx = priv;
102 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
103 src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
104 src_vq->drv_priv = ctx;
105 src_vq->ops = &rga_qops;
106 src_vq->mem_ops = &vb2_dma_sg_memops;
107 src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
108 src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
109 src_vq->lock = &ctx->rga->mutex;
110 src_vq->dev = ctx->rga->v4l2_dev.dev;
112 ret = vb2_queue_init(src_vq);
116 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
117 dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
118 dst_vq->drv_priv = ctx;
119 dst_vq->ops = &rga_qops;
120 dst_vq->mem_ops = &vb2_dma_sg_memops;
121 dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
122 dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
123 dst_vq->lock = &ctx->rga->mutex;
124 dst_vq->dev = ctx->rga->v4l2_dev.dev;
126 return vb2_queue_init(dst_vq);
129 static int rga_s_ctrl(struct v4l2_ctrl *ctrl)
131 struct rga_ctx *ctx = container_of(ctrl->handler, struct rga_ctx,
135 spin_lock_irqsave(&ctx->rga->ctrl_lock, flags);
138 ctx->hflip = ctrl->val;
141 ctx->vflip = ctrl->val;
143 case V4L2_CID_ROTATE:
144 ctx->rotate = ctrl->val;
146 case V4L2_CID_BG_COLOR:
147 ctx->fill_color = ctrl->val;
150 spin_unlock_irqrestore(&ctx->rga->ctrl_lock, flags);
154 static const struct v4l2_ctrl_ops rga_ctrl_ops = {
155 .s_ctrl = rga_s_ctrl,
158 static int rga_setup_ctrls(struct rga_ctx *ctx)
160 struct rockchip_rga *rga = ctx->rga;
162 v4l2_ctrl_handler_init(&ctx->ctrl_handler, 4);
164 v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops,
165 V4L2_CID_HFLIP, 0, 1, 1, 0);
167 v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops,
168 V4L2_CID_VFLIP, 0, 1, 1, 0);
170 v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops,
171 V4L2_CID_ROTATE, 0, 270, 90, 0);
173 v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops,
174 V4L2_CID_BG_COLOR, 0, 0xffffffff, 1, 0);
176 if (ctx->ctrl_handler.error) {
177 int err = ctx->ctrl_handler.error;
179 v4l2_err(&rga->v4l2_dev, "%s failed\n", __func__);
180 v4l2_ctrl_handler_free(&ctx->ctrl_handler);
187 static struct rga_fmt formats[] = {
189 .fourcc = V4L2_PIX_FMT_ARGB32,
190 .color_swap = RGA_COLOR_RB_SWAP,
191 .hw_format = RGA_COLOR_FMT_ABGR8888,
198 .fourcc = V4L2_PIX_FMT_XRGB32,
199 .color_swap = RGA_COLOR_RB_SWAP,
200 .hw_format = RGA_COLOR_FMT_XBGR8888,
207 .fourcc = V4L2_PIX_FMT_ABGR32,
208 .color_swap = RGA_COLOR_ALPHA_SWAP,
209 .hw_format = RGA_COLOR_FMT_ABGR8888,
216 .fourcc = V4L2_PIX_FMT_XBGR32,
217 .color_swap = RGA_COLOR_ALPHA_SWAP,
218 .hw_format = RGA_COLOR_FMT_XBGR8888,
225 .fourcc = V4L2_PIX_FMT_RGB24,
226 .color_swap = RGA_COLOR_NONE_SWAP,
227 .hw_format = RGA_COLOR_FMT_RGB888,
234 .fourcc = V4L2_PIX_FMT_BGR24,
235 .color_swap = RGA_COLOR_RB_SWAP,
236 .hw_format = RGA_COLOR_FMT_RGB888,
243 .fourcc = V4L2_PIX_FMT_ARGB444,
244 .color_swap = RGA_COLOR_RB_SWAP,
245 .hw_format = RGA_COLOR_FMT_ABGR4444,
252 .fourcc = V4L2_PIX_FMT_ARGB555,
253 .color_swap = RGA_COLOR_RB_SWAP,
254 .hw_format = RGA_COLOR_FMT_ABGR1555,
261 .fourcc = V4L2_PIX_FMT_RGB565,
262 .color_swap = RGA_COLOR_RB_SWAP,
263 .hw_format = RGA_COLOR_FMT_BGR565,
270 .fourcc = V4L2_PIX_FMT_NV21,
271 .color_swap = RGA_COLOR_UV_SWAP,
272 .hw_format = RGA_COLOR_FMT_YUV420SP,
279 .fourcc = V4L2_PIX_FMT_NV61,
280 .color_swap = RGA_COLOR_UV_SWAP,
281 .hw_format = RGA_COLOR_FMT_YUV422SP,
288 .fourcc = V4L2_PIX_FMT_NV12,
289 .color_swap = RGA_COLOR_NONE_SWAP,
290 .hw_format = RGA_COLOR_FMT_YUV420SP,
297 .fourcc = V4L2_PIX_FMT_NV16,
298 .color_swap = RGA_COLOR_NONE_SWAP,
299 .hw_format = RGA_COLOR_FMT_YUV422SP,
306 .fourcc = V4L2_PIX_FMT_YUV420,
307 .color_swap = RGA_COLOR_NONE_SWAP,
308 .hw_format = RGA_COLOR_FMT_YUV420P,
315 .fourcc = V4L2_PIX_FMT_YUV422P,
316 .color_swap = RGA_COLOR_NONE_SWAP,
317 .hw_format = RGA_COLOR_FMT_YUV422P,
324 .fourcc = V4L2_PIX_FMT_YVU420,
325 .color_swap = RGA_COLOR_UV_SWAP,
326 .hw_format = RGA_COLOR_FMT_YUV420P,
334 #define NUM_FORMATS ARRAY_SIZE(formats)
336 static struct rga_fmt *rga_fmt_find(struct v4l2_format *f)
340 for (i = 0; i < NUM_FORMATS; i++) {
341 if (formats[i].fourcc == f->fmt.pix.pixelformat)
347 static struct rga_frame def_frame = {
348 .width = DEFAULT_WIDTH,
349 .height = DEFAULT_HEIGHT,
350 .colorspace = V4L2_COLORSPACE_DEFAULT,
353 .crop.width = DEFAULT_WIDTH,
354 .crop.height = DEFAULT_HEIGHT,
358 struct rga_frame *rga_get_frame(struct rga_ctx *ctx, enum v4l2_buf_type type)
361 case V4L2_BUF_TYPE_VIDEO_OUTPUT:
363 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
366 return ERR_PTR(-EINVAL);
370 static int rga_open(struct file *file)
372 struct rockchip_rga *rga = video_drvdata(file);
373 struct rga_ctx *ctx = NULL;
376 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
380 /* Set default formats */
382 ctx->out = def_frame;
384 if (mutex_lock_interruptible(&rga->mutex)) {
388 ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(rga->m2m_dev, ctx, &queue_init);
389 if (IS_ERR(ctx->fh.m2m_ctx)) {
390 ret = PTR_ERR(ctx->fh.m2m_ctx);
391 mutex_unlock(&rga->mutex);
395 v4l2_fh_init(&ctx->fh, video_devdata(file));
396 file->private_data = &ctx->fh;
397 v4l2_fh_add(&ctx->fh);
399 rga_setup_ctrls(ctx);
401 /* Write the default values to the ctx struct */
402 v4l2_ctrl_handler_setup(&ctx->ctrl_handler);
404 ctx->fh.ctrl_handler = &ctx->ctrl_handler;
405 mutex_unlock(&rga->mutex);
410 static int rga_release(struct file *file)
412 struct rga_ctx *ctx =
413 container_of(file->private_data, struct rga_ctx, fh);
414 struct rockchip_rga *rga = ctx->rga;
416 mutex_lock(&rga->mutex);
418 v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
420 v4l2_ctrl_handler_free(&ctx->ctrl_handler);
421 v4l2_fh_del(&ctx->fh);
422 v4l2_fh_exit(&ctx->fh);
425 mutex_unlock(&rga->mutex);
430 static const struct v4l2_file_operations rga_fops = {
431 .owner = THIS_MODULE,
433 .release = rga_release,
434 .poll = v4l2_m2m_fop_poll,
435 .unlocked_ioctl = video_ioctl2,
436 .mmap = v4l2_m2m_fop_mmap,
440 vidioc_querycap(struct file *file, void *priv, struct v4l2_capability *cap)
442 strscpy(cap->driver, RGA_NAME, sizeof(cap->driver));
443 strscpy(cap->card, "rockchip-rga", sizeof(cap->card));
444 strscpy(cap->bus_info, "platform:rga", sizeof(cap->bus_info));
449 static int vidioc_enum_fmt(struct file *file, void *prv, struct v4l2_fmtdesc *f)
453 if (f->index >= NUM_FORMATS)
456 fmt = &formats[f->index];
457 f->pixelformat = fmt->fourcc;
462 static int vidioc_g_fmt(struct file *file, void *prv, struct v4l2_format *f)
464 struct rga_ctx *ctx = prv;
465 struct vb2_queue *vq;
466 struct rga_frame *frm;
468 vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
471 frm = rga_get_frame(ctx, f->type);
475 f->fmt.pix.width = frm->width;
476 f->fmt.pix.height = frm->height;
477 f->fmt.pix.field = V4L2_FIELD_NONE;
478 f->fmt.pix.pixelformat = frm->fmt->fourcc;
479 f->fmt.pix.bytesperline = frm->stride;
480 f->fmt.pix.sizeimage = frm->size;
481 f->fmt.pix.colorspace = frm->colorspace;
486 static int vidioc_try_fmt(struct file *file, void *prv, struct v4l2_format *f)
490 fmt = rga_fmt_find(f);
493 f->fmt.pix.pixelformat = fmt->fourcc;
496 f->fmt.pix.field = V4L2_FIELD_NONE;
498 if (f->fmt.pix.width > MAX_WIDTH)
499 f->fmt.pix.width = MAX_WIDTH;
500 if (f->fmt.pix.height > MAX_HEIGHT)
501 f->fmt.pix.height = MAX_HEIGHT;
503 if (f->fmt.pix.width < MIN_WIDTH)
504 f->fmt.pix.width = MIN_WIDTH;
505 if (f->fmt.pix.height < MIN_HEIGHT)
506 f->fmt.pix.height = MIN_HEIGHT;
508 if (fmt->hw_format >= RGA_COLOR_FMT_YUV422SP)
509 f->fmt.pix.bytesperline = f->fmt.pix.width;
511 f->fmt.pix.bytesperline = (f->fmt.pix.width * fmt->depth) >> 3;
513 f->fmt.pix.sizeimage =
514 f->fmt.pix.height * (f->fmt.pix.width * fmt->depth) >> 3;
519 static int vidioc_s_fmt(struct file *file, void *prv, struct v4l2_format *f)
521 struct rga_ctx *ctx = prv;
522 struct rockchip_rga *rga = ctx->rga;
523 struct vb2_queue *vq;
524 struct rga_frame *frm;
528 /* Adjust all values accordingly to the hardware capabilities
531 ret = vidioc_try_fmt(file, prv, f);
534 vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
535 if (vb2_is_busy(vq)) {
536 v4l2_err(&rga->v4l2_dev, "queue (%d) bust\n", f->type);
539 frm = rga_get_frame(ctx, f->type);
542 fmt = rga_fmt_find(f);
545 frm->width = f->fmt.pix.width;
546 frm->height = f->fmt.pix.height;
547 frm->size = f->fmt.pix.sizeimage;
549 frm->stride = f->fmt.pix.bytesperline;
550 frm->colorspace = f->fmt.pix.colorspace;
552 /* Reset crop settings */
555 frm->crop.width = frm->width;
556 frm->crop.height = frm->height;
561 static int vidioc_g_selection(struct file *file, void *prv,
562 struct v4l2_selection *s)
564 struct rga_ctx *ctx = prv;
566 bool use_frame = false;
568 f = rga_get_frame(ctx, s->type);
573 case V4L2_SEL_TGT_COMPOSE_DEFAULT:
574 case V4L2_SEL_TGT_COMPOSE_BOUNDS:
575 if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
578 case V4L2_SEL_TGT_CROP_DEFAULT:
579 case V4L2_SEL_TGT_CROP_BOUNDS:
580 if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
583 case V4L2_SEL_TGT_COMPOSE:
584 if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
588 case V4L2_SEL_TGT_CROP:
589 if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
602 s->r.width = f->width;
603 s->r.height = f->height;
609 static int vidioc_s_selection(struct file *file, void *prv,
610 struct v4l2_selection *s)
612 struct rga_ctx *ctx = prv;
613 struct rockchip_rga *rga = ctx->rga;
617 f = rga_get_frame(ctx, s->type);
622 case V4L2_SEL_TGT_COMPOSE:
624 * COMPOSE target is only valid for capture buffer type, return
625 * error for output buffer type
627 if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
630 case V4L2_SEL_TGT_CROP:
632 * CROP target is only valid for output buffer type, return
633 * error for capture buffer type
635 if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
639 * bound and default crop/compose targets are invalid targets to
646 if (s->r.top < 0 || s->r.left < 0) {
647 v4l2_dbg(debug, 1, &rga->v4l2_dev,
648 "doesn't support negative values for top & left.\n");
652 if (s->r.left + s->r.width > f->width ||
653 s->r.top + s->r.height > f->height ||
654 s->r.width < MIN_WIDTH || s->r.height < MIN_HEIGHT) {
655 v4l2_dbg(debug, 1, &rga->v4l2_dev, "unsupported crop value.\n");
664 static const struct v4l2_ioctl_ops rga_ioctl_ops = {
665 .vidioc_querycap = vidioc_querycap,
667 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt,
668 .vidioc_g_fmt_vid_cap = vidioc_g_fmt,
669 .vidioc_try_fmt_vid_cap = vidioc_try_fmt,
670 .vidioc_s_fmt_vid_cap = vidioc_s_fmt,
672 .vidioc_enum_fmt_vid_out = vidioc_enum_fmt,
673 .vidioc_g_fmt_vid_out = vidioc_g_fmt,
674 .vidioc_try_fmt_vid_out = vidioc_try_fmt,
675 .vidioc_s_fmt_vid_out = vidioc_s_fmt,
677 .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
678 .vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
679 .vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
680 .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
681 .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf,
682 .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs,
683 .vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
685 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
686 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
688 .vidioc_streamon = v4l2_m2m_ioctl_streamon,
689 .vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
691 .vidioc_g_selection = vidioc_g_selection,
692 .vidioc_s_selection = vidioc_s_selection,
695 static const struct video_device rga_videodev = {
696 .name = "rockchip-rga",
698 .ioctl_ops = &rga_ioctl_ops,
700 .release = video_device_release,
701 .vfl_dir = VFL_DIR_M2M,
702 .device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING,
705 static int rga_enable_clocks(struct rockchip_rga *rga)
709 ret = clk_prepare_enable(rga->sclk);
711 dev_err(rga->dev, "Cannot enable rga sclk: %d\n", ret);
715 ret = clk_prepare_enable(rga->aclk);
717 dev_err(rga->dev, "Cannot enable rga aclk: %d\n", ret);
718 goto err_disable_sclk;
721 ret = clk_prepare_enable(rga->hclk);
723 dev_err(rga->dev, "Cannot enable rga hclk: %d\n", ret);
724 goto err_disable_aclk;
730 clk_disable_unprepare(rga->sclk);
732 clk_disable_unprepare(rga->aclk);
737 static void rga_disable_clocks(struct rockchip_rga *rga)
739 clk_disable_unprepare(rga->sclk);
740 clk_disable_unprepare(rga->hclk);
741 clk_disable_unprepare(rga->aclk);
744 static int rga_parse_dt(struct rockchip_rga *rga)
746 struct reset_control *core_rst, *axi_rst, *ahb_rst;
748 core_rst = devm_reset_control_get(rga->dev, "core");
749 if (IS_ERR(core_rst)) {
750 dev_err(rga->dev, "failed to get core reset controller\n");
751 return PTR_ERR(core_rst);
754 axi_rst = devm_reset_control_get(rga->dev, "axi");
755 if (IS_ERR(axi_rst)) {
756 dev_err(rga->dev, "failed to get axi reset controller\n");
757 return PTR_ERR(axi_rst);
760 ahb_rst = devm_reset_control_get(rga->dev, "ahb");
761 if (IS_ERR(ahb_rst)) {
762 dev_err(rga->dev, "failed to get ahb reset controller\n");
763 return PTR_ERR(ahb_rst);
766 reset_control_assert(core_rst);
768 reset_control_deassert(core_rst);
770 reset_control_assert(axi_rst);
772 reset_control_deassert(axi_rst);
774 reset_control_assert(ahb_rst);
776 reset_control_deassert(ahb_rst);
778 rga->sclk = devm_clk_get(rga->dev, "sclk");
779 if (IS_ERR(rga->sclk)) {
780 dev_err(rga->dev, "failed to get sclk clock\n");
781 return PTR_ERR(rga->sclk);
784 rga->aclk = devm_clk_get(rga->dev, "aclk");
785 if (IS_ERR(rga->aclk)) {
786 dev_err(rga->dev, "failed to get aclk clock\n");
787 return PTR_ERR(rga->aclk);
790 rga->hclk = devm_clk_get(rga->dev, "hclk");
791 if (IS_ERR(rga->hclk)) {
792 dev_err(rga->dev, "failed to get hclk clock\n");
793 return PTR_ERR(rga->hclk);
799 static int rga_probe(struct platform_device *pdev)
801 struct rockchip_rga *rga;
802 struct video_device *vfd;
806 if (!pdev->dev.of_node)
809 rga = devm_kzalloc(&pdev->dev, sizeof(*rga), GFP_KERNEL);
813 rga->dev = &pdev->dev;
814 spin_lock_init(&rga->ctrl_lock);
815 mutex_init(&rga->mutex);
817 ret = rga_parse_dt(rga);
819 dev_err(&pdev->dev, "Unable to parse OF data\n");
821 pm_runtime_enable(rga->dev);
823 rga->regs = devm_platform_ioremap_resource(pdev, 0);
824 if (IS_ERR(rga->regs)) {
825 ret = PTR_ERR(rga->regs);
829 irq = platform_get_irq(pdev, 0);
835 ret = devm_request_irq(rga->dev, irq, rga_isr, 0,
836 dev_name(rga->dev), rga);
838 dev_err(rga->dev, "failed to request irq\n");
842 ret = v4l2_device_register(&pdev->dev, &rga->v4l2_dev);
845 vfd = video_device_alloc();
847 v4l2_err(&rga->v4l2_dev, "Failed to allocate video device\n");
852 vfd->lock = &rga->mutex;
853 vfd->v4l2_dev = &rga->v4l2_dev;
855 video_set_drvdata(vfd, rga);
858 platform_set_drvdata(pdev, rga);
859 rga->m2m_dev = v4l2_m2m_init(&rga_m2m_ops);
860 if (IS_ERR(rga->m2m_dev)) {
861 v4l2_err(&rga->v4l2_dev, "Failed to init mem2mem device\n");
862 ret = PTR_ERR(rga->m2m_dev);
866 ret = pm_runtime_resume_and_get(rga->dev);
870 rga->version.major = (rga_read(rga, RGA_VERSION_INFO) >> 24) & 0xFF;
871 rga->version.minor = (rga_read(rga, RGA_VERSION_INFO) >> 20) & 0x0F;
873 v4l2_info(&rga->v4l2_dev, "HW Version: 0x%02x.%02x\n",
874 rga->version.major, rga->version.minor);
876 pm_runtime_put(rga->dev);
878 /* Create CMD buffer */
879 rga->cmdbuf_virt = dma_alloc_attrs(rga->dev, RGA_CMDBUF_SIZE,
880 &rga->cmdbuf_phy, GFP_KERNEL,
881 DMA_ATTR_WRITE_COMBINE);
882 if (!rga->cmdbuf_virt) {
888 (unsigned int *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 3);
889 if (!rga->src_mmu_pages) {
894 (unsigned int *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 3);
895 if (rga->dst_mmu_pages) {
900 def_frame.stride = (def_frame.width * def_frame.fmt->depth) >> 3;
901 def_frame.size = def_frame.stride * def_frame.height;
903 ret = video_register_device(vfd, VFL_TYPE_VIDEO, -1);
905 v4l2_err(&rga->v4l2_dev, "Failed to register video device\n");
909 v4l2_info(&rga->v4l2_dev, "Registered %s as /dev/%s\n",
910 vfd->name, video_device_node_name(vfd));
915 free_pages((unsigned long)rga->dst_mmu_pages, 3);
917 free_pages((unsigned long)rga->src_mmu_pages, 3);
919 dma_free_attrs(rga->dev, RGA_CMDBUF_SIZE, rga->cmdbuf_virt,
920 rga->cmdbuf_phy, DMA_ATTR_WRITE_COMBINE);
922 video_device_release(vfd);
924 v4l2_device_unregister(&rga->v4l2_dev);
926 pm_runtime_disable(rga->dev);
931 static int rga_remove(struct platform_device *pdev)
933 struct rockchip_rga *rga = platform_get_drvdata(pdev);
935 dma_free_attrs(rga->dev, RGA_CMDBUF_SIZE, rga->cmdbuf_virt,
936 rga->cmdbuf_phy, DMA_ATTR_WRITE_COMBINE);
938 free_pages((unsigned long)rga->src_mmu_pages, 3);
939 free_pages((unsigned long)rga->dst_mmu_pages, 3);
941 v4l2_info(&rga->v4l2_dev, "Removing\n");
943 v4l2_m2m_release(rga->m2m_dev);
944 video_unregister_device(rga->vfd);
945 v4l2_device_unregister(&rga->v4l2_dev);
947 pm_runtime_disable(rga->dev);
952 static int __maybe_unused rga_runtime_suspend(struct device *dev)
954 struct rockchip_rga *rga = dev_get_drvdata(dev);
956 rga_disable_clocks(rga);
961 static int __maybe_unused rga_runtime_resume(struct device *dev)
963 struct rockchip_rga *rga = dev_get_drvdata(dev);
965 return rga_enable_clocks(rga);
968 static const struct dev_pm_ops rga_pm = {
969 SET_RUNTIME_PM_OPS(rga_runtime_suspend,
970 rga_runtime_resume, NULL)
973 static const struct of_device_id rockchip_rga_match[] = {
975 .compatible = "rockchip,rk3288-rga",
978 .compatible = "rockchip,rk3399-rga",
983 MODULE_DEVICE_TABLE(of, rockchip_rga_match);
985 static struct platform_driver rga_pdrv = {
987 .remove = rga_remove,
991 .of_match_table = rockchip_rga_match,
995 module_platform_driver(rga_pdrv);
997 MODULE_AUTHOR("Jacob Chen <jacob-chen@iotwrt.com>");
998 MODULE_DESCRIPTION("Rockchip Raster 2d Graphic Acceleration Unit");
999 MODULE_LICENSE("GPL");