1 // SPDX-License-Identifier: GPL-2.0
5 * Qualcomm MSM Camera Subsystem - ISPIF (ISP Interface) Module
7 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
8 * Copyright (C) 2015-2018 Linaro Ltd.
10 #include <linux/clk.h>
11 #include <linux/completion.h>
12 #include <linux/interrupt.h>
13 #include <linux/iopoll.h>
14 #include <linux/kernel.h>
15 #include <linux/mutex.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
18 #include <media/media-entity.h>
19 #include <media/v4l2-device.h>
20 #include <media/v4l2-subdev.h>
22 #include "camss-ispif.h"
25 #define MSM_ISPIF_NAME "msm_ispif"
27 #define ISPIF_RST_CMD_0 0x008
28 #define ISPIF_RST_CMD_0_STROBED_RST_EN (1 << 0)
29 #define ISPIF_RST_CMD_0_MISC_LOGIC_RST (1 << 1)
30 #define ISPIF_RST_CMD_0_SW_REG_RST (1 << 2)
31 #define ISPIF_RST_CMD_0_PIX_INTF_0_CSID_RST (1 << 3)
32 #define ISPIF_RST_CMD_0_PIX_INTF_0_VFE_RST (1 << 4)
33 #define ISPIF_RST_CMD_0_PIX_INTF_1_CSID_RST (1 << 5)
34 #define ISPIF_RST_CMD_0_PIX_INTF_1_VFE_RST (1 << 6)
35 #define ISPIF_RST_CMD_0_RDI_INTF_0_CSID_RST (1 << 7)
36 #define ISPIF_RST_CMD_0_RDI_INTF_0_VFE_RST (1 << 8)
37 #define ISPIF_RST_CMD_0_RDI_INTF_1_CSID_RST (1 << 9)
38 #define ISPIF_RST_CMD_0_RDI_INTF_1_VFE_RST (1 << 10)
39 #define ISPIF_RST_CMD_0_RDI_INTF_2_CSID_RST (1 << 11)
40 #define ISPIF_RST_CMD_0_RDI_INTF_2_VFE_RST (1 << 12)
41 #define ISPIF_RST_CMD_0_PIX_OUTPUT_0_MISR_RST (1 << 16)
42 #define ISPIF_RST_CMD_0_RDI_OUTPUT_0_MISR_RST (1 << 17)
43 #define ISPIF_RST_CMD_0_RDI_OUTPUT_1_MISR_RST (1 << 18)
44 #define ISPIF_RST_CMD_0_RDI_OUTPUT_2_MISR_RST (1 << 19)
45 #define ISPIF_IRQ_GLOBAL_CLEAR_CMD 0x01c
46 #define ISPIF_VFE_m_CTRL_0(m) (0x200 + 0x200 * (m))
47 #define ISPIF_VFE_m_CTRL_0_PIX0_LINE_BUF_EN (1 << 6)
48 #define ISPIF_VFE_m_IRQ_MASK_0(m) (0x208 + 0x200 * (m))
49 #define ISPIF_VFE_m_IRQ_MASK_0_PIX0_ENABLE 0x00001249
50 #define ISPIF_VFE_m_IRQ_MASK_0_PIX0_MASK 0x00001fff
51 #define ISPIF_VFE_m_IRQ_MASK_0_RDI0_ENABLE 0x02492000
52 #define ISPIF_VFE_m_IRQ_MASK_0_RDI0_MASK 0x03ffe000
53 #define ISPIF_VFE_m_IRQ_MASK_1(m) (0x20c + 0x200 * (m))
54 #define ISPIF_VFE_m_IRQ_MASK_1_PIX1_ENABLE 0x00001249
55 #define ISPIF_VFE_m_IRQ_MASK_1_PIX1_MASK 0x00001fff
56 #define ISPIF_VFE_m_IRQ_MASK_1_RDI1_ENABLE 0x02492000
57 #define ISPIF_VFE_m_IRQ_MASK_1_RDI1_MASK 0x03ffe000
58 #define ISPIF_VFE_m_IRQ_MASK_2(m) (0x210 + 0x200 * (m))
59 #define ISPIF_VFE_m_IRQ_MASK_2_RDI2_ENABLE 0x00001249
60 #define ISPIF_VFE_m_IRQ_MASK_2_RDI2_MASK 0x00001fff
61 #define ISPIF_VFE_m_IRQ_STATUS_0(m) (0x21c + 0x200 * (m))
62 #define ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW (1 << 12)
63 #define ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW (1 << 25)
64 #define ISPIF_VFE_m_IRQ_STATUS_1(m) (0x220 + 0x200 * (m))
65 #define ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW (1 << 12)
66 #define ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW (1 << 25)
67 #define ISPIF_VFE_m_IRQ_STATUS_2(m) (0x224 + 0x200 * (m))
68 #define ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW (1 << 12)
69 #define ISPIF_VFE_m_IRQ_CLEAR_0(m) (0x230 + 0x200 * (m))
70 #define ISPIF_VFE_m_IRQ_CLEAR_1(m) (0x234 + 0x200 * (m))
71 #define ISPIF_VFE_m_IRQ_CLEAR_2(m) (0x238 + 0x200 * (m))
72 #define ISPIF_VFE_m_INTF_INPUT_SEL(m) (0x244 + 0x200 * (m))
73 #define ISPIF_VFE_m_INTF_CMD_0(m) (0x248 + 0x200 * (m))
74 #define ISPIF_VFE_m_INTF_CMD_1(m) (0x24c + 0x200 * (m))
75 #define ISPIF_VFE_m_PIX_INTF_n_CID_MASK(m, n) \
76 (0x254 + 0x200 * (m) + 0x4 * (n))
77 #define ISPIF_VFE_m_RDI_INTF_n_CID_MASK(m, n) \
78 (0x264 + 0x200 * (m) + 0x4 * (n))
79 /* PACK_CFG registers are 8x96 only */
80 #define ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(m, n) \
81 (0x270 + 0x200 * (m) + 0x4 * (n))
82 #define ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(m, n) \
83 (0x27c + 0x200 * (m) + 0x4 * (n))
84 #define ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0_CID_c_PLAIN(c) \
85 (1 << ((cid % 8) * 4))
86 #define ISPIF_VFE_m_PIX_INTF_n_STATUS(m, n) \
87 (0x2c0 + 0x200 * (m) + 0x4 * (n))
88 #define ISPIF_VFE_m_RDI_INTF_n_STATUS(m, n) \
89 (0x2d0 + 0x200 * (m) + 0x4 * (n))
91 #define CSI_PIX_CLK_MUX_SEL 0x000
92 #define CSI_RDI_CLK_MUX_SEL 0x008
94 #define ISPIF_TIMEOUT_SLEEP_US 1000
95 #define ISPIF_TIMEOUT_ALL_US 1000000
96 #define ISPIF_RESET_TIMEOUT_MS 500
99 CMD_DISABLE_FRAME_BOUNDARY = 0x0,
100 CMD_ENABLE_FRAME_BOUNDARY = 0x1,
101 CMD_DISABLE_IMMEDIATELY = 0x2,
102 CMD_ALL_DISABLE_IMMEDIATELY = 0xaaaaaaaa,
103 CMD_ALL_NO_CHANGE = 0xffffffff,
106 static const u32 ispif_formats_8x16[] = {
107 MEDIA_BUS_FMT_UYVY8_2X8,
108 MEDIA_BUS_FMT_VYUY8_2X8,
109 MEDIA_BUS_FMT_YUYV8_2X8,
110 MEDIA_BUS_FMT_YVYU8_2X8,
111 MEDIA_BUS_FMT_SBGGR8_1X8,
112 MEDIA_BUS_FMT_SGBRG8_1X8,
113 MEDIA_BUS_FMT_SGRBG8_1X8,
114 MEDIA_BUS_FMT_SRGGB8_1X8,
115 MEDIA_BUS_FMT_SBGGR10_1X10,
116 MEDIA_BUS_FMT_SGBRG10_1X10,
117 MEDIA_BUS_FMT_SGRBG10_1X10,
118 MEDIA_BUS_FMT_SRGGB10_1X10,
119 MEDIA_BUS_FMT_SBGGR12_1X12,
120 MEDIA_BUS_FMT_SGBRG12_1X12,
121 MEDIA_BUS_FMT_SGRBG12_1X12,
122 MEDIA_BUS_FMT_SRGGB12_1X12,
123 MEDIA_BUS_FMT_Y10_1X10,
126 static const u32 ispif_formats_8x96[] = {
127 MEDIA_BUS_FMT_UYVY8_2X8,
128 MEDIA_BUS_FMT_VYUY8_2X8,
129 MEDIA_BUS_FMT_YUYV8_2X8,
130 MEDIA_BUS_FMT_YVYU8_2X8,
131 MEDIA_BUS_FMT_SBGGR8_1X8,
132 MEDIA_BUS_FMT_SGBRG8_1X8,
133 MEDIA_BUS_FMT_SGRBG8_1X8,
134 MEDIA_BUS_FMT_SRGGB8_1X8,
135 MEDIA_BUS_FMT_SBGGR10_1X10,
136 MEDIA_BUS_FMT_SGBRG10_1X10,
137 MEDIA_BUS_FMT_SGRBG10_1X10,
138 MEDIA_BUS_FMT_SRGGB10_1X10,
139 MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE,
140 MEDIA_BUS_FMT_SBGGR12_1X12,
141 MEDIA_BUS_FMT_SGBRG12_1X12,
142 MEDIA_BUS_FMT_SGRBG12_1X12,
143 MEDIA_BUS_FMT_SRGGB12_1X12,
144 MEDIA_BUS_FMT_SBGGR14_1X14,
145 MEDIA_BUS_FMT_SGBRG14_1X14,
146 MEDIA_BUS_FMT_SGRBG14_1X14,
147 MEDIA_BUS_FMT_SRGGB14_1X14,
148 MEDIA_BUS_FMT_Y10_1X10,
149 MEDIA_BUS_FMT_Y10_2X8_PADHI_LE,
153 * ispif_isr_8x96 - ISPIF module interrupt handler for 8x96
154 * @irq: Interrupt line
157 * Return IRQ_HANDLED on success
159 static irqreturn_t ispif_isr_8x96(int irq, void *dev)
161 struct ispif_device *ispif = dev;
162 u32 value0, value1, value2, value3, value4, value5;
164 value0 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_0(0));
165 value1 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_1(0));
166 value2 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_2(0));
167 value3 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_0(1));
168 value4 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_1(1));
169 value5 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_2(1));
171 writel_relaxed(value0, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(0));
172 writel_relaxed(value1, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(0));
173 writel_relaxed(value2, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(0));
174 writel_relaxed(value3, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(1));
175 writel_relaxed(value4, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(1));
176 writel_relaxed(value5, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(1));
178 writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD);
180 if ((value0 >> 27) & 0x1)
181 complete(&ispif->reset_complete);
183 if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW))
184 dev_err_ratelimited(to_device(ispif), "VFE0 pix0 overflow\n");
186 if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW))
187 dev_err_ratelimited(to_device(ispif), "VFE0 rdi0 overflow\n");
189 if (unlikely(value1 & ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW))
190 dev_err_ratelimited(to_device(ispif), "VFE0 pix1 overflow\n");
192 if (unlikely(value1 & ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW))
193 dev_err_ratelimited(to_device(ispif), "VFE0 rdi1 overflow\n");
195 if (unlikely(value2 & ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW))
196 dev_err_ratelimited(to_device(ispif), "VFE0 rdi2 overflow\n");
198 if (unlikely(value3 & ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW))
199 dev_err_ratelimited(to_device(ispif), "VFE1 pix0 overflow\n");
201 if (unlikely(value3 & ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW))
202 dev_err_ratelimited(to_device(ispif), "VFE1 rdi0 overflow\n");
204 if (unlikely(value4 & ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW))
205 dev_err_ratelimited(to_device(ispif), "VFE1 pix1 overflow\n");
207 if (unlikely(value4 & ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW))
208 dev_err_ratelimited(to_device(ispif), "VFE1 rdi1 overflow\n");
210 if (unlikely(value5 & ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW))
211 dev_err_ratelimited(to_device(ispif), "VFE1 rdi2 overflow\n");
217 * ispif_isr_8x16 - ISPIF module interrupt handler for 8x16
218 * @irq: Interrupt line
221 * Return IRQ_HANDLED on success
223 static irqreturn_t ispif_isr_8x16(int irq, void *dev)
225 struct ispif_device *ispif = dev;
226 u32 value0, value1, value2;
228 value0 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_0(0));
229 value1 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_1(0));
230 value2 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_2(0));
232 writel_relaxed(value0, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(0));
233 writel_relaxed(value1, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(0));
234 writel_relaxed(value2, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(0));
236 writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD);
238 if ((value0 >> 27) & 0x1)
239 complete(&ispif->reset_complete);
241 if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW))
242 dev_err_ratelimited(to_device(ispif), "VFE0 pix0 overflow\n");
244 if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW))
245 dev_err_ratelimited(to_device(ispif), "VFE0 rdi0 overflow\n");
247 if (unlikely(value1 & ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW))
248 dev_err_ratelimited(to_device(ispif), "VFE0 pix1 overflow\n");
250 if (unlikely(value1 & ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW))
251 dev_err_ratelimited(to_device(ispif), "VFE0 rdi1 overflow\n");
253 if (unlikely(value2 & ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW))
254 dev_err_ratelimited(to_device(ispif), "VFE0 rdi2 overflow\n");
260 * ispif_reset - Trigger reset on ISPIF module and wait to complete
261 * @ispif: ISPIF device
263 * Return 0 on success or a negative error code otherwise
265 static int ispif_reset(struct ispif_device *ispif)
271 ret = camss_pm_domain_on(to_camss(ispif), PM_DOMAIN_VFE0);
275 ret = camss_pm_domain_on(to_camss(ispif), PM_DOMAIN_VFE1);
279 ret = camss_enable_clocks(ispif->nclocks_for_reset,
280 ispif->clock_for_reset,
285 reinit_completion(&ispif->reset_complete);
287 val = ISPIF_RST_CMD_0_STROBED_RST_EN |
288 ISPIF_RST_CMD_0_MISC_LOGIC_RST |
289 ISPIF_RST_CMD_0_SW_REG_RST |
290 ISPIF_RST_CMD_0_PIX_INTF_0_CSID_RST |
291 ISPIF_RST_CMD_0_PIX_INTF_0_VFE_RST |
292 ISPIF_RST_CMD_0_PIX_INTF_1_CSID_RST |
293 ISPIF_RST_CMD_0_PIX_INTF_1_VFE_RST |
294 ISPIF_RST_CMD_0_RDI_INTF_0_CSID_RST |
295 ISPIF_RST_CMD_0_RDI_INTF_0_VFE_RST |
296 ISPIF_RST_CMD_0_RDI_INTF_1_CSID_RST |
297 ISPIF_RST_CMD_0_RDI_INTF_1_VFE_RST |
298 ISPIF_RST_CMD_0_RDI_INTF_2_CSID_RST |
299 ISPIF_RST_CMD_0_RDI_INTF_2_VFE_RST |
300 ISPIF_RST_CMD_0_PIX_OUTPUT_0_MISR_RST |
301 ISPIF_RST_CMD_0_RDI_OUTPUT_0_MISR_RST |
302 ISPIF_RST_CMD_0_RDI_OUTPUT_1_MISR_RST |
303 ISPIF_RST_CMD_0_RDI_OUTPUT_2_MISR_RST;
305 writel_relaxed(val, ispif->base + ISPIF_RST_CMD_0);
307 time = wait_for_completion_timeout(&ispif->reset_complete,
308 msecs_to_jiffies(ISPIF_RESET_TIMEOUT_MS));
310 dev_err(to_device(ispif), "ISPIF reset timeout\n");
314 camss_disable_clocks(ispif->nclocks_for_reset, ispif->clock_for_reset);
316 camss_pm_domain_off(to_camss(ispif), PM_DOMAIN_VFE0);
317 camss_pm_domain_off(to_camss(ispif), PM_DOMAIN_VFE1);
323 * ispif_set_power - Power on/off ISPIF module
324 * @sd: ISPIF V4L2 subdevice
325 * @on: Requested power state
327 * Return 0 on success or a negative error code otherwise
329 static int ispif_set_power(struct v4l2_subdev *sd, int on)
331 struct ispif_line *line = v4l2_get_subdevdata(sd);
332 struct ispif_device *ispif = line->ispif;
333 struct device *dev = to_device(ispif);
336 mutex_lock(&ispif->power_lock);
339 if (ispif->power_count) {
340 /* Power is already on */
341 ispif->power_count++;
345 ret = pm_runtime_get_sync(dev);
349 ret = camss_enable_clocks(ispif->nclocks, ispif->clock, dev);
351 pm_runtime_put_sync(dev);
355 ret = ispif_reset(ispif);
357 pm_runtime_put_sync(dev);
358 camss_disable_clocks(ispif->nclocks, ispif->clock);
362 ispif->intf_cmd[line->vfe_id].cmd_0 = CMD_ALL_NO_CHANGE;
363 ispif->intf_cmd[line->vfe_id].cmd_1 = CMD_ALL_NO_CHANGE;
365 ispif->power_count++;
367 if (ispif->power_count == 0) {
368 dev_err(dev, "ispif power off on power_count == 0\n");
370 } else if (ispif->power_count == 1) {
371 camss_disable_clocks(ispif->nclocks, ispif->clock);
372 pm_runtime_put_sync(dev);
375 ispif->power_count--;
379 mutex_unlock(&ispif->power_lock);
385 * ispif_select_clk_mux - Select clock for PIX/RDI interface
386 * @ispif: ISPIF device
387 * @intf: VFE interface
388 * @csid: CSID HW module id
389 * @vfe: VFE HW module id
390 * @enable: enable or disable the selected clock
392 static void ispif_select_clk_mux(struct ispif_device *ispif,
393 enum ispif_intf intf, u8 csid,
400 val = readl_relaxed(ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL);
401 val &= ~(0xf << (vfe * 8));
403 val |= (csid << (vfe * 8));
404 writel_relaxed(val, ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL);
408 val = readl_relaxed(ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
409 val &= ~(0xf << (vfe * 12));
411 val |= (csid << (vfe * 12));
412 writel_relaxed(val, ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
416 val = readl_relaxed(ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL);
417 val &= ~(0xf << (4 + (vfe * 8)));
419 val |= (csid << (4 + (vfe * 8)));
420 writel_relaxed(val, ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL);
424 val = readl_relaxed(ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
425 val &= ~(0xf << (4 + (vfe * 12)));
427 val |= (csid << (4 + (vfe * 12)));
428 writel_relaxed(val, ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
432 val = readl_relaxed(ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
433 val &= ~(0xf << (8 + (vfe * 12)));
435 val |= (csid << (8 + (vfe * 12)));
436 writel_relaxed(val, ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
444 * ispif_validate_intf_status - Validate current status of PIX/RDI interface
445 * @ispif: ISPIF device
446 * @intf: VFE interface
447 * @vfe: VFE HW module id
449 * Return 0 when interface is idle or -EBUSY otherwise
451 static int ispif_validate_intf_status(struct ispif_device *ispif,
452 enum ispif_intf intf, u8 vfe)
459 val = readl_relaxed(ispif->base +
460 ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 0));
463 val = readl_relaxed(ispif->base +
464 ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 0));
467 val = readl_relaxed(ispif->base +
468 ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 1));
471 val = readl_relaxed(ispif->base +
472 ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 1));
475 val = readl_relaxed(ispif->base +
476 ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 2));
480 if ((val & 0xf) != 0xf) {
481 dev_err(to_device(ispif), "%s: ispif is busy: 0x%x\n",
490 * ispif_wait_for_stop - Wait for PIX/RDI interface to stop
491 * @ispif: ISPIF device
492 * @intf: VFE interface
493 * @vfe: VFE HW module id
495 * Return 0 on success or a negative error code otherwise
497 static int ispif_wait_for_stop(struct ispif_device *ispif,
498 enum ispif_intf intf, u8 vfe)
506 addr = ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 0);
509 addr = ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 0);
512 addr = ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 1);
515 addr = ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 1);
518 addr = ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 2);
522 ret = readl_poll_timeout(ispif->base + addr,
524 (stop_flag & 0xf) == 0xf,
525 ISPIF_TIMEOUT_SLEEP_US,
526 ISPIF_TIMEOUT_ALL_US);
528 dev_err(to_device(ispif), "%s: ispif stop timeout\n",
535 * ispif_select_csid - Select CSID HW module for input from
536 * @ispif: ISPIF device
537 * @intf: VFE interface
538 * @csid: CSID HW module id
539 * @vfe: VFE HW module id
540 * @enable: enable or disable the selected input
542 static void ispif_select_csid(struct ispif_device *ispif, enum ispif_intf intf,
543 u8 csid, u8 vfe, u8 enable)
547 val = readl_relaxed(ispif->base + ISPIF_VFE_m_INTF_INPUT_SEL(vfe));
550 val &= ~(BIT(1) | BIT(0));
555 val &= ~(BIT(5) | BIT(4));
560 val &= ~(BIT(9) | BIT(8));
565 val &= ~(BIT(13) | BIT(12));
570 val &= ~(BIT(21) | BIT(20));
576 writel(val, ispif->base + ISPIF_VFE_m_INTF_INPUT_SEL(vfe));
580 * ispif_select_cid - Enable/disable desired CID
581 * @ispif: ISPIF device
582 * @intf: VFE interface
583 * @cid: desired CID to enable/disable
584 * @vfe: VFE HW module id
585 * @enable: enable or disable the desired CID
587 static void ispif_select_cid(struct ispif_device *ispif, enum ispif_intf intf,
588 u8 cid, u8 vfe, u8 enable)
590 u32 cid_mask = 1 << cid;
596 addr = ISPIF_VFE_m_PIX_INTF_n_CID_MASK(vfe, 0);
599 addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 0);
602 addr = ISPIF_VFE_m_PIX_INTF_n_CID_MASK(vfe, 1);
605 addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 1);
608 addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 2);
612 val = readl_relaxed(ispif->base + addr);
618 writel(val, ispif->base + addr);
622 * ispif_config_irq - Enable/disable interrupts for PIX/RDI interface
623 * @ispif: ISPIF device
624 * @intf: VFE interface
625 * @vfe: VFE HW module id
626 * @enable: enable or disable
628 static void ispif_config_irq(struct ispif_device *ispif, enum ispif_intf intf,
635 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe));
636 val &= ~ISPIF_VFE_m_IRQ_MASK_0_PIX0_MASK;
638 val |= ISPIF_VFE_m_IRQ_MASK_0_PIX0_ENABLE;
639 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe));
640 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_0_PIX0_ENABLE,
641 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(vfe));
644 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe));
645 val &= ~ISPIF_VFE_m_IRQ_MASK_0_RDI0_MASK;
647 val |= ISPIF_VFE_m_IRQ_MASK_0_RDI0_ENABLE;
648 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe));
649 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_0_RDI0_ENABLE,
650 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(vfe));
653 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe));
654 val &= ~ISPIF_VFE_m_IRQ_MASK_1_PIX1_MASK;
656 val |= ISPIF_VFE_m_IRQ_MASK_1_PIX1_ENABLE;
657 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe));
658 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_1_PIX1_ENABLE,
659 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(vfe));
662 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe));
663 val &= ~ISPIF_VFE_m_IRQ_MASK_1_RDI1_MASK;
665 val |= ISPIF_VFE_m_IRQ_MASK_1_RDI1_ENABLE;
666 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe));
667 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_1_RDI1_ENABLE,
668 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(vfe));
671 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_2(vfe));
672 val &= ~ISPIF_VFE_m_IRQ_MASK_2_RDI2_MASK;
674 val |= ISPIF_VFE_m_IRQ_MASK_2_RDI2_ENABLE;
675 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_2(vfe));
676 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_2_RDI2_ENABLE,
677 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(vfe));
681 writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD);
685 * ispif_config_pack - Config packing for PRDI mode
686 * @ispif: ISPIF device
687 * @code: media bus format code
688 * @intf: VFE interface
689 * @cid: desired CID to handle
690 * @vfe: VFE HW module id
691 * @enable: enable or disable
693 static void ispif_config_pack(struct ispif_device *ispif, u32 code,
694 enum ispif_intf intf, u8 cid, u8 vfe, u8 enable)
698 if (code != MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE &&
699 code != MEDIA_BUS_FMT_Y10_2X8_PADHI_LE)
705 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 0);
707 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 0);
711 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 1);
713 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 1);
717 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 2);
719 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 2);
726 val = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0_CID_c_PLAIN(cid);
730 writel_relaxed(val, ispif->base + addr);
734 * ispif_set_intf_cmd - Set command to enable/disable interface
735 * @ispif: ISPIF device
736 * @cmd: interface command
737 * @intf: VFE interface
738 * @vfe: VFE HW module id
739 * @vc: virtual channel
741 static void ispif_set_intf_cmd(struct ispif_device *ispif, u8 cmd,
742 enum ispif_intf intf, u8 vfe, u8 vc)
747 val = &ispif->intf_cmd[vfe].cmd_1;
748 *val &= ~(0x3 << (vc * 2 + 8));
749 *val |= (cmd << (vc * 2 + 8));
751 writel_relaxed(*val, ispif->base + ISPIF_VFE_m_INTF_CMD_1(vfe));
754 val = &ispif->intf_cmd[vfe].cmd_0;
755 *val &= ~(0x3 << (vc * 2 + intf * 8));
756 *val |= (cmd << (vc * 2 + intf * 8));
758 writel_relaxed(*val, ispif->base + ISPIF_VFE_m_INTF_CMD_0(vfe));
764 * ispif_set_stream - Enable/disable streaming on ISPIF module
765 * @sd: ISPIF V4L2 subdevice
766 * @enable: Requested streaming state
768 * Main configuration of ISPIF module is also done here.
770 * Return 0 on success or a negative error code otherwise
772 static int ispif_set_stream(struct v4l2_subdev *sd, int enable)
774 struct ispif_line *line = v4l2_get_subdevdata(sd);
775 struct ispif_device *ispif = line->ispif;
776 enum ispif_intf intf = line->interface;
777 u8 csid = line->csid_id;
778 u8 vfe = line->vfe_id;
779 u8 vc = 0; /* Virtual Channel 0 */
780 u8 cid = vc * 4; /* id of Virtual Channel and Data Type set */
784 if (!media_entity_remote_pad(&line->pads[MSM_ISPIF_PAD_SINK]))
789 mutex_lock(&ispif->config_lock);
790 ispif_select_clk_mux(ispif, intf, csid, vfe, 1);
792 ret = ispif_validate_intf_status(ispif, intf, vfe);
794 mutex_unlock(&ispif->config_lock);
798 ispif_select_csid(ispif, intf, csid, vfe, 1);
799 ispif_select_cid(ispif, intf, cid, vfe, 1);
800 ispif_config_irq(ispif, intf, vfe, 1);
801 if (to_camss(ispif)->version == CAMSS_8x96)
802 ispif_config_pack(ispif,
803 line->fmt[MSM_ISPIF_PAD_SINK].code,
805 ispif_set_intf_cmd(ispif, CMD_ENABLE_FRAME_BOUNDARY,
808 mutex_lock(&ispif->config_lock);
809 ispif_set_intf_cmd(ispif, CMD_DISABLE_FRAME_BOUNDARY,
811 mutex_unlock(&ispif->config_lock);
813 ret = ispif_wait_for_stop(ispif, intf, vfe);
817 mutex_lock(&ispif->config_lock);
818 if (to_camss(ispif)->version == CAMSS_8x96)
819 ispif_config_pack(ispif,
820 line->fmt[MSM_ISPIF_PAD_SINK].code,
822 ispif_config_irq(ispif, intf, vfe, 0);
823 ispif_select_cid(ispif, intf, cid, vfe, 0);
824 ispif_select_csid(ispif, intf, csid, vfe, 0);
825 ispif_select_clk_mux(ispif, intf, csid, vfe, 0);
828 mutex_unlock(&ispif->config_lock);
834 * __ispif_get_format - Get pointer to format structure
836 * @cfg: V4L2 subdev pad configuration
837 * @pad: pad from which format is requested
838 * @which: TRY or ACTIVE format
840 * Return pointer to TRY or ACTIVE format structure
842 static struct v4l2_mbus_framefmt *
843 __ispif_get_format(struct ispif_line *line,
844 struct v4l2_subdev_pad_config *cfg,
846 enum v4l2_subdev_format_whence which)
848 if (which == V4L2_SUBDEV_FORMAT_TRY)
849 return v4l2_subdev_get_try_format(&line->subdev, cfg, pad);
851 return &line->fmt[pad];
855 * ispif_try_format - Handle try format by pad subdev method
857 * @cfg: V4L2 subdev pad configuration
858 * @pad: pad on which format is requested
859 * @fmt: pointer to v4l2 format structure
860 * @which: wanted subdev format
862 static void ispif_try_format(struct ispif_line *line,
863 struct v4l2_subdev_pad_config *cfg,
865 struct v4l2_mbus_framefmt *fmt,
866 enum v4l2_subdev_format_whence which)
871 case MSM_ISPIF_PAD_SINK:
872 /* Set format on sink pad */
874 for (i = 0; i < line->nformats; i++)
875 if (fmt->code == line->formats[i])
878 /* If not found, use UYVY as default */
879 if (i >= line->nformats)
880 fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
882 fmt->width = clamp_t(u32, fmt->width, 1, 8191);
883 fmt->height = clamp_t(u32, fmt->height, 1, 8191);
885 fmt->field = V4L2_FIELD_NONE;
886 fmt->colorspace = V4L2_COLORSPACE_SRGB;
890 case MSM_ISPIF_PAD_SRC:
891 /* Set and return a format same as sink pad */
893 *fmt = *__ispif_get_format(line, cfg, MSM_ISPIF_PAD_SINK,
899 fmt->colorspace = V4L2_COLORSPACE_SRGB;
903 * ispif_enum_mbus_code - Handle pixel format enumeration
904 * @sd: ISPIF V4L2 subdevice
905 * @cfg: V4L2 subdev pad configuration
906 * @code: pointer to v4l2_subdev_mbus_code_enum structure
907 * return -EINVAL or zero on success
909 static int ispif_enum_mbus_code(struct v4l2_subdev *sd,
910 struct v4l2_subdev_pad_config *cfg,
911 struct v4l2_subdev_mbus_code_enum *code)
913 struct ispif_line *line = v4l2_get_subdevdata(sd);
914 struct v4l2_mbus_framefmt *format;
916 if (code->pad == MSM_ISPIF_PAD_SINK) {
917 if (code->index >= line->nformats)
920 code->code = line->formats[code->index];
925 format = __ispif_get_format(line, cfg, MSM_ISPIF_PAD_SINK,
928 code->code = format->code;
935 * ispif_enum_frame_size - Handle frame size enumeration
936 * @sd: ISPIF V4L2 subdevice
937 * @cfg: V4L2 subdev pad configuration
938 * @fse: pointer to v4l2_subdev_frame_size_enum structure
939 * return -EINVAL or zero on success
941 static int ispif_enum_frame_size(struct v4l2_subdev *sd,
942 struct v4l2_subdev_pad_config *cfg,
943 struct v4l2_subdev_frame_size_enum *fse)
945 struct ispif_line *line = v4l2_get_subdevdata(sd);
946 struct v4l2_mbus_framefmt format;
951 format.code = fse->code;
954 ispif_try_format(line, cfg, fse->pad, &format, fse->which);
955 fse->min_width = format.width;
956 fse->min_height = format.height;
958 if (format.code != fse->code)
961 format.code = fse->code;
964 ispif_try_format(line, cfg, fse->pad, &format, fse->which);
965 fse->max_width = format.width;
966 fse->max_height = format.height;
972 * ispif_get_format - Handle get format by pads subdev method
973 * @sd: ISPIF V4L2 subdevice
974 * @cfg: V4L2 subdev pad configuration
975 * @fmt: pointer to v4l2 subdev format structure
977 * Return -EINVAL or zero on success
979 static int ispif_get_format(struct v4l2_subdev *sd,
980 struct v4l2_subdev_pad_config *cfg,
981 struct v4l2_subdev_format *fmt)
983 struct ispif_line *line = v4l2_get_subdevdata(sd);
984 struct v4l2_mbus_framefmt *format;
986 format = __ispif_get_format(line, cfg, fmt->pad, fmt->which);
990 fmt->format = *format;
996 * ispif_set_format - Handle set format by pads subdev method
997 * @sd: ISPIF V4L2 subdevice
998 * @cfg: V4L2 subdev pad configuration
999 * @fmt: pointer to v4l2 subdev format structure
1001 * Return -EINVAL or zero on success
1003 static int ispif_set_format(struct v4l2_subdev *sd,
1004 struct v4l2_subdev_pad_config *cfg,
1005 struct v4l2_subdev_format *fmt)
1007 struct ispif_line *line = v4l2_get_subdevdata(sd);
1008 struct v4l2_mbus_framefmt *format;
1010 format = __ispif_get_format(line, cfg, fmt->pad, fmt->which);
1014 ispif_try_format(line, cfg, fmt->pad, &fmt->format, fmt->which);
1015 *format = fmt->format;
1017 /* Propagate the format from sink to source */
1018 if (fmt->pad == MSM_ISPIF_PAD_SINK) {
1019 format = __ispif_get_format(line, cfg, MSM_ISPIF_PAD_SRC,
1022 *format = fmt->format;
1023 ispif_try_format(line, cfg, MSM_ISPIF_PAD_SRC, format,
1031 * ispif_init_formats - Initialize formats on all pads
1032 * @sd: ISPIF V4L2 subdevice
1033 * @fh: V4L2 subdev file handle
1035 * Initialize all pad formats with default values.
1037 * Return 0 on success or a negative error code otherwise
1039 static int ispif_init_formats(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1041 struct v4l2_subdev_format format = {
1042 .pad = MSM_ISPIF_PAD_SINK,
1043 .which = fh ? V4L2_SUBDEV_FORMAT_TRY :
1044 V4L2_SUBDEV_FORMAT_ACTIVE,
1046 .code = MEDIA_BUS_FMT_UYVY8_2X8,
1052 return ispif_set_format(sd, fh ? fh->pad : NULL, &format);
1056 * msm_ispif_subdev_init - Initialize ISPIF device structure and resources
1057 * @ispif: ISPIF device
1058 * @res: ISPIF module resources table
1060 * Return 0 on success or a negative error code otherwise
1062 int msm_ispif_subdev_init(struct ispif_device *ispif,
1063 const struct resources_ispif *res)
1065 struct device *dev = to_device(ispif);
1066 struct platform_device *pdev = to_platform_device(dev);
1071 /* Number of ISPIF lines - same as number of CSID hardware modules */
1072 if (to_camss(ispif)->version == CAMSS_8x16)
1073 ispif->line_num = 2;
1074 else if (to_camss(ispif)->version == CAMSS_8x96)
1075 ispif->line_num = 4;
1079 ispif->line = kcalloc(ispif->line_num, sizeof(*ispif->line),
1084 for (i = 0; i < ispif->line_num; i++) {
1085 ispif->line[i].ispif = ispif;
1086 ispif->line[i].id = i;
1088 if (to_camss(ispif)->version == CAMSS_8x16) {
1089 ispif->line[i].formats = ispif_formats_8x16;
1090 ispif->line[i].nformats =
1091 ARRAY_SIZE(ispif_formats_8x16);
1092 } else if (to_camss(ispif)->version == CAMSS_8x96) {
1093 ispif->line[i].formats = ispif_formats_8x96;
1094 ispif->line[i].nformats =
1095 ARRAY_SIZE(ispif_formats_8x96);
1103 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, res->reg[0]);
1104 ispif->base = devm_ioremap_resource(dev, r);
1105 if (IS_ERR(ispif->base)) {
1106 dev_err(dev, "could not map memory\n");
1107 return PTR_ERR(ispif->base);
1110 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, res->reg[1]);
1111 ispif->base_clk_mux = devm_ioremap_resource(dev, r);
1112 if (IS_ERR(ispif->base_clk_mux)) {
1113 dev_err(dev, "could not map memory\n");
1114 return PTR_ERR(ispif->base_clk_mux);
1119 r = platform_get_resource_byname(pdev, IORESOURCE_IRQ, res->interrupt);
1122 dev_err(dev, "missing IRQ\n");
1126 ispif->irq = r->start;
1127 snprintf(ispif->irq_name, sizeof(ispif->irq_name), "%s_%s",
1128 dev_name(dev), MSM_ISPIF_NAME);
1129 if (to_camss(ispif)->version == CAMSS_8x16)
1130 ret = devm_request_irq(dev, ispif->irq, ispif_isr_8x16,
1131 IRQF_TRIGGER_RISING, ispif->irq_name, ispif);
1132 else if (to_camss(ispif)->version == CAMSS_8x96)
1133 ret = devm_request_irq(dev, ispif->irq, ispif_isr_8x96,
1134 IRQF_TRIGGER_RISING, ispif->irq_name, ispif);
1138 dev_err(dev, "request_irq failed: %d\n", ret);
1145 while (res->clock[ispif->nclocks])
1148 ispif->clock = devm_kcalloc(dev,
1149 ispif->nclocks, sizeof(*ispif->clock),
1154 for (i = 0; i < ispif->nclocks; i++) {
1155 struct camss_clock *clock = &ispif->clock[i];
1157 clock->clk = devm_clk_get(dev, res->clock[i]);
1158 if (IS_ERR(clock->clk))
1159 return PTR_ERR(clock->clk);
1165 ispif->nclocks_for_reset = 0;
1166 while (res->clock_for_reset[ispif->nclocks_for_reset])
1167 ispif->nclocks_for_reset++;
1169 ispif->clock_for_reset = devm_kcalloc(dev,
1170 ispif->nclocks_for_reset,
1171 sizeof(*ispif->clock_for_reset),
1173 if (!ispif->clock_for_reset)
1176 for (i = 0; i < ispif->nclocks_for_reset; i++) {
1177 struct camss_clock *clock = &ispif->clock_for_reset[i];
1179 clock->clk = devm_clk_get(dev, res->clock_for_reset[i]);
1180 if (IS_ERR(clock->clk))
1181 return PTR_ERR(clock->clk);
1187 mutex_init(&ispif->power_lock);
1188 ispif->power_count = 0;
1190 mutex_init(&ispif->config_lock);
1192 init_completion(&ispif->reset_complete);
1198 * ispif_get_intf - Get ISPIF interface to use by VFE line id
1199 * @line_id: VFE line id that the ISPIF line is connected to
1201 * Return ISPIF interface to use
1203 static enum ispif_intf ispif_get_intf(enum vfe_line_id line_id)
1206 case (VFE_LINE_RDI0):
1208 case (VFE_LINE_RDI1):
1210 case (VFE_LINE_RDI2):
1212 case (VFE_LINE_PIX):
1220 * ispif_link_setup - Setup ISPIF connections
1221 * @entity: Pointer to media entity structure
1222 * @local: Pointer to local pad
1223 * @remote: Pointer to remote pad
1224 * @flags: Link flags
1226 * Return 0 on success
1228 static int ispif_link_setup(struct media_entity *entity,
1229 const struct media_pad *local,
1230 const struct media_pad *remote, u32 flags)
1232 if (flags & MEDIA_LNK_FL_ENABLED) {
1233 if (media_entity_remote_pad(local))
1236 if (local->flags & MEDIA_PAD_FL_SINK) {
1237 struct v4l2_subdev *sd;
1238 struct ispif_line *line;
1240 sd = media_entity_to_v4l2_subdev(entity);
1241 line = v4l2_get_subdevdata(sd);
1243 msm_csid_get_csid_id(remote->entity, &line->csid_id);
1244 } else { /* MEDIA_PAD_FL_SOURCE */
1245 struct v4l2_subdev *sd;
1246 struct ispif_line *line;
1247 enum vfe_line_id id;
1249 sd = media_entity_to_v4l2_subdev(entity);
1250 line = v4l2_get_subdevdata(sd);
1252 msm_vfe_get_vfe_id(remote->entity, &line->vfe_id);
1253 msm_vfe_get_vfe_line_id(remote->entity, &id);
1254 line->interface = ispif_get_intf(id);
1261 static const struct v4l2_subdev_core_ops ispif_core_ops = {
1262 .s_power = ispif_set_power,
1265 static const struct v4l2_subdev_video_ops ispif_video_ops = {
1266 .s_stream = ispif_set_stream,
1269 static const struct v4l2_subdev_pad_ops ispif_pad_ops = {
1270 .enum_mbus_code = ispif_enum_mbus_code,
1271 .enum_frame_size = ispif_enum_frame_size,
1272 .get_fmt = ispif_get_format,
1273 .set_fmt = ispif_set_format,
1276 static const struct v4l2_subdev_ops ispif_v4l2_ops = {
1277 .core = &ispif_core_ops,
1278 .video = &ispif_video_ops,
1279 .pad = &ispif_pad_ops,
1282 static const struct v4l2_subdev_internal_ops ispif_v4l2_internal_ops = {
1283 .open = ispif_init_formats,
1286 static const struct media_entity_operations ispif_media_ops = {
1287 .link_setup = ispif_link_setup,
1288 .link_validate = v4l2_subdev_link_validate,
1292 * msm_ispif_register_entities - Register subdev node for ISPIF module
1293 * @ispif: ISPIF device
1294 * @v4l2_dev: V4L2 device
1296 * Return 0 on success or a negative error code otherwise
1298 int msm_ispif_register_entities(struct ispif_device *ispif,
1299 struct v4l2_device *v4l2_dev)
1301 struct device *dev = to_device(ispif);
1305 for (i = 0; i < ispif->line_num; i++) {
1306 struct v4l2_subdev *sd = &ispif->line[i].subdev;
1307 struct media_pad *pads = ispif->line[i].pads;
1309 v4l2_subdev_init(sd, &ispif_v4l2_ops);
1310 sd->internal_ops = &ispif_v4l2_internal_ops;
1311 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1312 snprintf(sd->name, ARRAY_SIZE(sd->name), "%s%d",
1314 v4l2_set_subdevdata(sd, &ispif->line[i]);
1316 ret = ispif_init_formats(sd, NULL);
1318 dev_err(dev, "Failed to init format: %d\n", ret);
1322 pads[MSM_ISPIF_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
1323 pads[MSM_ISPIF_PAD_SRC].flags = MEDIA_PAD_FL_SOURCE;
1325 sd->entity.function = MEDIA_ENT_F_IO_V4L;
1326 sd->entity.ops = &ispif_media_ops;
1327 ret = media_entity_pads_init(&sd->entity, MSM_ISPIF_PADS_NUM,
1330 dev_err(dev, "Failed to init media entity: %d\n", ret);
1334 ret = v4l2_device_register_subdev(v4l2_dev, sd);
1336 dev_err(dev, "Failed to register subdev: %d\n", ret);
1337 media_entity_cleanup(&sd->entity);
1345 for (i--; i >= 0; i--) {
1346 struct v4l2_subdev *sd = &ispif->line[i].subdev;
1348 v4l2_device_unregister_subdev(sd);
1349 media_entity_cleanup(&sd->entity);
1356 * msm_ispif_unregister_entities - Unregister ISPIF module subdev node
1357 * @ispif: ISPIF device
1359 void msm_ispif_unregister_entities(struct ispif_device *ispif)
1363 mutex_destroy(&ispif->power_lock);
1364 mutex_destroy(&ispif->config_lock);
1366 for (i = 0; i < ispif->line_num; i++) {
1367 struct v4l2_subdev *sd = &ispif->line[i].subdev;
1369 v4l2_device_unregister_subdev(sd);
1370 media_entity_cleanup(&sd->entity);