drivers/media/i2c/ov6650.c

   1 /*
   2  * V4L2 subdevice driver for OmniVision OV6650 Camera Sensor
   3  *
   4  * Copyright (C) 2010 Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
   5  *
   6  * Based on OmniVision OV96xx Camera Driver
   7  * Copyright (C) 2009 Marek Vasut <marek.vasut@gmail.com>
   8  *
   9  * Based on ov772x camera driver:
  10  * Copyright (C) 2008 Renesas Solutions Corp.
  11  * Kuninori Morimoto <morimoto.kuninori@renesas.com>
  12  *
  13  * Based on ov7670 and soc_camera_platform driver,
  14  * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
  15  * Copyright (C) 2008 Magnus Damm
  16  * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
  17  *
  18  * Hardware specific bits initially based on former work by Matt Callow
  19  * drivers/media/video/omap/sensor_ov6650.c
  20  * Copyright (C) 2006 Matt Callow
  21  *
  22  * This program is free software; you can redistribute it and/or modify
  23  * it under the terms of the GNU General Public License version 2 as
  24  * published by the Free Software Foundation.
  25  */
  26
  27 #include <linux/bitops.h>
  28 #include <linux/delay.h>
  29 #include <linux/i2c.h>
  30 #include <linux/slab.h>
  31 #include <linux/v4l2-mediabus.h>
  32 #include <linux/module.h>
  33
  34 #include <media/v4l2-clk.h>
  35 #include <media/v4l2-ctrls.h>
  36 #include <media/v4l2-device.h>
  37
  38 /* Register definitions */
  39 #define REG_GAIN                0x00    /* range 00 - 3F */
  40 #define REG_BLUE                0x01
  41 #define REG_RED                 0x02
  42 #define REG_SAT                 0x03    /* [7:4] saturation [0:3] reserved */
  43 #define REG_HUE                 0x04    /* [7:6] rsrvd [5] hue en [4:0] hue */
  44
  45 #define REG_BRT                 0x06
  46
  47 #define REG_PIDH                0x0a
  48 #define REG_PIDL                0x0b
  49
  50 #define REG_AECH                0x10
  51 #define REG_CLKRC               0x11    /* Data Format and Internal Clock */
  52                                         /* [7:6] Input system clock (MHz)*/
  53                                         /*   00=8, 01=12, 10=16, 11=24 */
  54                                         /* [5:0]: Internal Clock Pre-Scaler */
  55 #define REG_COMA                0x12    /* [7] Reset */
  56 #define REG_COMB                0x13
  57 #define REG_COMC                0x14
  58 #define REG_COMD                0x15
  59 #define REG_COML                0x16
  60 #define REG_HSTRT               0x17
  61 #define REG_HSTOP               0x18
  62 #define REG_VSTRT               0x19
  63 #define REG_VSTOP               0x1a
  64 #define REG_PSHFT               0x1b
  65 #define REG_MIDH                0x1c
  66 #define REG_MIDL                0x1d
  67 #define REG_HSYNS               0x1e
  68 #define REG_HSYNE               0x1f
  69 #define REG_COME                0x20
  70 #define REG_YOFF                0x21
  71 #define REG_UOFF                0x22
  72 #define REG_VOFF                0x23
  73 #define REG_AEW                 0x24
  74 #define REG_AEB                 0x25
  75 #define REG_COMF                0x26
  76 #define REG_COMG                0x27
  77 #define REG_COMH                0x28
  78 #define REG_COMI                0x29
  79
  80 #define REG_FRARL               0x2b
  81 #define REG_COMJ                0x2c
  82 #define REG_COMK                0x2d
  83 #define REG_AVGY                0x2e
  84 #define REG_REF0                0x2f
  85 #define REG_REF1                0x30
  86 #define REG_REF2                0x31
  87 #define REG_FRAJH               0x32
  88 #define REG_FRAJL               0x33
  89 #define REG_FACT                0x34
  90 #define REG_L1AEC               0x35
  91 #define REG_AVGU                0x36
  92 #define REG_AVGV                0x37
  93
  94 #define REG_SPCB                0x60
  95 #define REG_SPCC                0x61
  96 #define REG_GAM1                0x62
  97 #define REG_GAM2                0x63
  98 #define REG_GAM3                0x64
  99 #define REG_SPCD                0x65
 100
 101 #define REG_SPCE                0x68
 102 #define REG_ADCL                0x69
 103
 104 #define REG_RMCO                0x6c
 105 #define REG_GMCO                0x6d
 106 #define REG_BMCO                0x6e
 107
 108
 109 /* Register bits, values, etc. */
 110 #define OV6650_PIDH             0x66    /* high byte of product ID number */
 111 #define OV6650_PIDL             0x50    /* low byte of product ID number */
 112 #define OV6650_MIDH             0x7F    /* high byte of mfg ID */
 113 #define OV6650_MIDL             0xA2    /* low byte of mfg ID */
 114
 115 #define DEF_GAIN                0x00
 116 #define DEF_BLUE                0x80
 117 #define DEF_RED                 0x80
 118
 119 #define SAT_SHIFT               4
 120 #define SAT_MASK                (0xf << SAT_SHIFT)
 121 #define SET_SAT(x)              (((x) << SAT_SHIFT) & SAT_MASK)
 122
 123 #define HUE_EN                  BIT(5)
 124 #define HUE_MASK                0x1f
 125 #define DEF_HUE                 0x10
 126 #define SET_HUE(x)              (HUE_EN | ((x) & HUE_MASK))
 127
 128 #define DEF_AECH                0x4D
 129
 130 #define CLKRC_6MHz              0x00
 131 #define CLKRC_12MHz             0x40
 132 #define CLKRC_16MHz             0x80
 133 #define CLKRC_24MHz             0xc0
 134 #define CLKRC_DIV_MASK          0x3f
 135 #define GET_CLKRC_DIV(x)        (((x) & CLKRC_DIV_MASK) + 1)
 136
 137 #define COMA_RESET              BIT(7)
 138 #define COMA_QCIF               BIT(5)
 139 #define COMA_RAW_RGB            BIT(4)
 140 #define COMA_RGB                BIT(3)
 141 #define COMA_BW                 BIT(2)
 142 #define COMA_WORD_SWAP          BIT(1)
 143 #define COMA_BYTE_SWAP          BIT(0)
 144 #define DEF_COMA                0x00
 145
 146 #define COMB_FLIP_V             BIT(7)
 147 #define COMB_FLIP_H             BIT(5)
 148 #define COMB_BAND_FILTER        BIT(4)
 149 #define COMB_AWB                BIT(2)
 150 #define COMB_AGC                BIT(1)
 151 #define COMB_AEC                BIT(0)
 152 #define DEF_COMB                0x5f
 153
 154 #define COML_ONE_CHANNEL        BIT(7)
 155
 156 #define DEF_HSTRT               0x24
 157 #define DEF_HSTOP               0xd4
 158 #define DEF_VSTRT               0x04
 159 #define DEF_VSTOP               0x94
 160
 161 #define COMF_HREF_LOW           BIT(4)
 162
 163 #define COMJ_PCLK_RISING        BIT(4)
 164 #define COMJ_VSYNC_HIGH         BIT(0)
 165
 166 /* supported resolutions */
 167 #define W_QCIF                  (DEF_HSTOP - DEF_HSTRT)
 168 #define W_CIF                   (W_QCIF << 1)
 169 #define H_QCIF                  (DEF_VSTOP - DEF_VSTRT)
 170 #define H_CIF                   (H_QCIF << 1)
 171
 172 #define FRAME_RATE_MAX          30
 173
 174
 175 struct ov6650_reg {
 176         u8      reg;
 177         u8      val;
 178 };
 179
 180 struct ov6650 {
 181         struct v4l2_subdev      subdev;
 182         struct v4l2_ctrl_handler hdl;
 183         struct {
 184                 /* exposure/autoexposure cluster */
 185                 struct v4l2_ctrl *autoexposure;
 186                 struct v4l2_ctrl *exposure;
 187         };
 188         struct {
 189                 /* gain/autogain cluster */
 190                 struct v4l2_ctrl *autogain;
 191                 struct v4l2_ctrl *gain;
 192         };
 193         struct {
 194                 /* blue/red/autowhitebalance cluster */
 195                 struct v4l2_ctrl *autowb;
 196                 struct v4l2_ctrl *blue;
 197                 struct v4l2_ctrl *red;
 198         };
 199         struct v4l2_clk         *clk;
 200         bool                    half_scale;     /* scale down output by 2 */
 201         struct v4l2_rect        rect;           /* sensor cropping window */
 202         unsigned long           pclk_limit;     /* from host */
 203         unsigned long           pclk_max;       /* from resolution and format */
 204         struct v4l2_fract       tpf;            /* as requested with s_frame_interval */
 205         u32 code;
 206         enum v4l2_colorspace    colorspace;
 207 };
 208
 209
 210 static u32 ov6650_codes[] = {
 211         MEDIA_BUS_FMT_YUYV8_2X8,
 212         MEDIA_BUS_FMT_UYVY8_2X8,
 213         MEDIA_BUS_FMT_YVYU8_2X8,
 214         MEDIA_BUS_FMT_VYUY8_2X8,
 215         MEDIA_BUS_FMT_SBGGR8_1X8,
 216         MEDIA_BUS_FMT_Y8_1X8,
 217 };
 218
 219 /* read a register */
 220 static int ov6650_reg_read(struct i2c_client *client, u8 reg, u8 *val)
 221 {
 222         int ret;
 223         u8 data = reg;
 224         struct i2c_msg msg = {
 225                 .addr   = client->addr,
 226                 .flags  = 0,
 227                 .len    = 1,
 228                 .buf    = &data,
 229         };
 230
 231         ret = i2c_transfer(client->adapter, &msg, 1);
 232         if (ret < 0)
 233                 goto err;
 234
 235         msg.flags = I2C_M_RD;
 236         ret = i2c_transfer(client->adapter, &msg, 1);
 237         if (ret < 0)
 238                 goto err;
 239
 240         *val = data;
 241         return 0;
 242
 243 err:
 244         dev_err(&client->dev, "Failed reading register 0x%02x!\n", reg);
 245         return ret;
 246 }
 247
 248 /* write a register */
 249 static int ov6650_reg_write(struct i2c_client *client, u8 reg, u8 val)
 250 {
 251         int ret;
 252         unsigned char data[2] = { reg, val };
 253         struct i2c_msg msg = {
 254                 .addr   = client->addr,
 255                 .flags  = 0,
 256                 .len    = 2,
 257                 .buf    = data,
 258         };
 259
 260         ret = i2c_transfer(client->adapter, &msg, 1);
 261         udelay(100);
 262
 263         if (ret < 0) {
 264                 dev_err(&client->dev, "Failed writing register 0x%02x!\n", reg);
 265                 return ret;
 266         }
 267         return 0;
 268 }
 269
 270
 271 /* Read a register, alter its bits, write it back */
 272 static int ov6650_reg_rmw(struct i2c_client *client, u8 reg, u8 set, u8 mask)
 273 {
 274         u8 val;
 275         int ret;
 276
 277         ret = ov6650_reg_read(client, reg, &val);
 278         if (ret) {
 279                 dev_err(&client->dev,
 280                         "[Read]-Modify-Write of register 0x%02x failed!\n",
 281                         reg);
 282                 return ret;
 283         }
 284
 285         val &= ~mask;
 286         val |= set;
 287
 288         ret = ov6650_reg_write(client, reg, val);
 289         if (ret)
 290                 dev_err(&client->dev,
 291                         "Read-Modify-[Write] of register 0x%02x failed!\n",
 292                         reg);
 293
 294         return ret;
 295 }
 296
 297 static struct ov6650 *to_ov6650(const struct i2c_client *client)
 298 {
 299         return container_of(i2c_get_clientdata(client), struct ov6650, subdev);
 300 }
 301
 302 /* Start/Stop streaming from the device */
 303 static int ov6650_s_stream(struct v4l2_subdev *sd, int enable)
 304 {
 305         return 0;
 306 }
 307
 308 /* Get status of additional camera capabilities */
 309 static int ov6550_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
 310 {
 311         struct ov6650 *priv = container_of(ctrl->handler, struct ov6650, hdl);
 312         struct v4l2_subdev *sd = &priv->subdev;
 313         struct i2c_client *client = v4l2_get_subdevdata(sd);
 314         uint8_t reg, reg2;
 315         int ret;
 316
 317         switch (ctrl->id) {
 318         case V4L2_CID_AUTOGAIN:
 319                 ret = ov6650_reg_read(client, REG_GAIN, &reg);
 320                 if (!ret)
 321                         priv->gain->val = reg;
 322                 return ret;
 323         case V4L2_CID_AUTO_WHITE_BALANCE:
 324                 ret = ov6650_reg_read(client, REG_BLUE, &reg);
 325                 if (!ret)
 326                         ret = ov6650_reg_read(client, REG_RED, &reg2);
 327                 if (!ret) {
 328                         priv->blue->val = reg;
 329                         priv->red->val = reg2;
 330                 }
 331                 return ret;
 332         case V4L2_CID_EXPOSURE_AUTO:
 333                 ret = ov6650_reg_read(client, REG_AECH, &reg);
 334                 if (!ret)
 335                         priv->exposure->val = reg;
 336                 return ret;
 337         }
 338         return -EINVAL;
 339 }
 340
 341 /* Set status of additional camera capabilities */
 342 static int ov6550_s_ctrl(struct v4l2_ctrl *ctrl)
 343 {
 344         struct ov6650 *priv = container_of(ctrl->handler, struct ov6650, hdl);
 345         struct v4l2_subdev *sd = &priv->subdev;
 346         struct i2c_client *client = v4l2_get_subdevdata(sd);
 347         int ret;
 348
 349         switch (ctrl->id) {
 350         case V4L2_CID_AUTOGAIN:
 351                 ret = ov6650_reg_rmw(client, REG_COMB,
 352                                 ctrl->val ? COMB_AGC : 0, COMB_AGC);
 353                 if (!ret && !ctrl->val)
 354                         ret = ov6650_reg_write(client, REG_GAIN, priv->gain->val);
 355                 return ret;
 356         case V4L2_CID_AUTO_WHITE_BALANCE:
 357                 ret = ov6650_reg_rmw(client, REG_COMB,
 358                                 ctrl->val ? COMB_AWB : 0, COMB_AWB);
 359                 if (!ret && !ctrl->val) {
 360                         ret = ov6650_reg_write(client, REG_BLUE, priv->blue->val);
 361                         if (!ret)
 362                                 ret = ov6650_reg_write(client, REG_RED,
 363                                                         priv->red->val);
 364                 }
 365                 return ret;
 366         case V4L2_CID_SATURATION:
 367                 return ov6650_reg_rmw(client, REG_SAT, SET_SAT(ctrl->val),
 368                                 SAT_MASK);
 369         case V4L2_CID_HUE:
 370                 return ov6650_reg_rmw(client, REG_HUE, SET_HUE(ctrl->val),
 371                                 HUE_MASK);
 372         case V4L2_CID_BRIGHTNESS:
 373                 return ov6650_reg_write(client, REG_BRT, ctrl->val);
 374         case V4L2_CID_EXPOSURE_AUTO:
 375                 ret = ov6650_reg_rmw(client, REG_COMB, ctrl->val ==
 376                                 V4L2_EXPOSURE_AUTO ? COMB_AEC : 0, COMB_AEC);
 377                 if (!ret && ctrl->val == V4L2_EXPOSURE_MANUAL)
 378                         ret = ov6650_reg_write(client, REG_AECH,
 379                                                 priv->exposure->val);
 380                 return ret;
 381         case V4L2_CID_GAMMA:
 382                 return ov6650_reg_write(client, REG_GAM1, ctrl->val);
 383         case V4L2_CID_VFLIP:
 384                 return ov6650_reg_rmw(client, REG_COMB,
 385                                 ctrl->val ? COMB_FLIP_V : 0, COMB_FLIP_V);
 386         case V4L2_CID_HFLIP:
 387                 return ov6650_reg_rmw(client, REG_COMB,
 388                                 ctrl->val ? COMB_FLIP_H : 0, COMB_FLIP_H);
 389         }
 390
 391         return -EINVAL;
 392 }
 393
 394 #ifdef CONFIG_VIDEO_ADV_DEBUG
 395 static int ov6650_get_register(struct v4l2_subdev *sd,
 396                                 struct v4l2_dbg_register *reg)
 397 {
 398         struct i2c_client *client = v4l2_get_subdevdata(sd);
 399         int ret;
 400         u8 val;
 401
 402         if (reg->reg & ~0xff)
 403                 return -EINVAL;
 404
 405         reg->size = 1;
 406
 407         ret = ov6650_reg_read(client, reg->reg, &val);
 408         if (!ret)
 409                 reg->val = (__u64)val;
 410
 411         return ret;
 412 }
 413
 414 static int ov6650_set_register(struct v4l2_subdev *sd,
 415                                 const struct v4l2_dbg_register *reg)
 416 {
 417         struct i2c_client *client = v4l2_get_subdevdata(sd);
 418
 419         if (reg->reg & ~0xff || reg->val & ~0xff)
 420                 return -EINVAL;
 421
 422         return ov6650_reg_write(client, reg->reg, reg->val);
 423 }
 424 #endif
 425
 426 static int ov6650_s_power(struct v4l2_subdev *sd, int on)
 427 {
 428         struct i2c_client *client = v4l2_get_subdevdata(sd);
 429         struct ov6650 *priv = to_ov6650(client);
 430         int ret = 0;
 431
 432         if (on)
 433                 ret = v4l2_clk_enable(priv->clk);
 434         else
 435                 v4l2_clk_disable(priv->clk);
 436
 437         return ret;
 438 }
 439
 440 static int ov6650_get_selection(struct v4l2_subdev *sd,
 441                 struct v4l2_subdev_pad_config *cfg,
 442                 struct v4l2_subdev_selection *sel)
 443 {
 444         struct i2c_client *client = v4l2_get_subdevdata(sd);
 445         struct ov6650 *priv = to_ov6650(client);
 446
 447         if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
 448                 return -EINVAL;
 449
 450         switch (sel->target) {
 451         case V4L2_SEL_TGT_CROP_BOUNDS:
 452                 sel->r.left = DEF_HSTRT << 1;
 453                 sel->r.top = DEF_VSTRT << 1;
 454                 sel->r.width = W_CIF;
 455                 sel->r.height = H_CIF;
 456                 return 0;
 457         case V4L2_SEL_TGT_CROP:
 458                 sel->r = priv->rect;
 459                 return 0;
 460         default:
 461                 return -EINVAL;
 462         }
 463 }
 464
 465 static int ov6650_set_selection(struct v4l2_subdev *sd,
 466                 struct v4l2_subdev_pad_config *cfg,
 467                 struct v4l2_subdev_selection *sel)
 468 {
 469         struct i2c_client *client = v4l2_get_subdevdata(sd);
 470         struct ov6650 *priv = to_ov6650(client);
 471         struct v4l2_rect rect = sel->r;
 472         int ret;
 473
 474         if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE ||
 475             sel->target != V4L2_SEL_TGT_CROP)
 476                 return -EINVAL;
 477
 478         v4l_bound_align_image(&rect.width, 2, W_CIF, 1,
 479                               &rect.height, 2, H_CIF, 1, 0);
 480         v4l_bound_align_image(&rect.left, DEF_HSTRT << 1,
 481                               (DEF_HSTRT << 1) + W_CIF - (__s32)rect.width, 1,
 482                               &rect.top, DEF_VSTRT << 1,
 483                               (DEF_VSTRT << 1) + H_CIF - (__s32)rect.height, 1,
 484                               0);
 485
 486         ret = ov6650_reg_write(client, REG_HSTRT, rect.left >> 1);
 487         if (!ret) {
 488                 priv->rect.left = rect.left;
 489                 ret = ov6650_reg_write(client, REG_HSTOP,
 490                                 (rect.left + rect.width) >> 1);
 491         }
 492         if (!ret) {
 493                 priv->rect.width = rect.width;
 494                 ret = ov6650_reg_write(client, REG_VSTRT, rect.top >> 1);
 495         }
 496         if (!ret) {
 497                 priv->rect.top = rect.top;
 498                 ret = ov6650_reg_write(client, REG_VSTOP,
 499                                 (rect.top + rect.height) >> 1);
 500         }
 501         if (!ret)
 502                 priv->rect.height = rect.height;
 503
 504         return ret;
 505 }
 506
 507 static int ov6650_get_fmt(struct v4l2_subdev *sd,
 508                 struct v4l2_subdev_pad_config *cfg,
 509                 struct v4l2_subdev_format *format)
 510 {
 511         struct v4l2_mbus_framefmt *mf = &format->format;
 512         struct i2c_client *client = v4l2_get_subdevdata(sd);
 513         struct ov6650 *priv = to_ov6650(client);
 514
 515         if (format->pad)
 516                 return -EINVAL;
 517
 518         mf->width       = priv->rect.width >> priv->half_scale;
 519         mf->height      = priv->rect.height >> priv->half_scale;
 520         mf->code        = priv->code;
 521         mf->colorspace  = priv->colorspace;
 522         mf->field       = V4L2_FIELD_NONE;
 523
 524         return 0;
 525 }
 526
 527 static bool is_unscaled_ok(int width, int height, struct v4l2_rect *rect)
 528 {
 529         return width > rect->width >> 1 || height > rect->height >> 1;
 530 }
 531
 532 static u8 to_clkrc(struct v4l2_fract *timeperframe,
 533                 unsigned long pclk_limit, unsigned long pclk_max)
 534 {
 535         unsigned long pclk;
 536
 537         if (timeperframe->numerator && timeperframe->denominator)
 538                 pclk = pclk_max * timeperframe->denominator /
 539                                 (FRAME_RATE_MAX * timeperframe->numerator);
 540         else
 541                 pclk = pclk_max;
 542
 543         if (pclk_limit && pclk_limit < pclk)
 544                 pclk = pclk_limit;
 545
 546         return (pclk_max - 1) / pclk;
 547 }
 548
 549 /* set the format we will capture in */
 550 static int ov6650_s_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *mf)
 551 {
 552         struct i2c_client *client = v4l2_get_subdevdata(sd);
 553         struct ov6650 *priv = to_ov6650(client);
 554         bool half_scale = !is_unscaled_ok(mf->width, mf->height, &priv->rect);
 555         struct v4l2_subdev_selection sel = {
 556                 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
 557                 .target = V4L2_SEL_TGT_CROP,
 558                 .r.left = priv->rect.left + (priv->rect.width >> 1) -
 559                         (mf->width >> (1 - half_scale)),
 560                 .r.top = priv->rect.top + (priv->rect.height >> 1) -
 561                         (mf->height >> (1 - half_scale)),
 562                 .r.width = mf->width << half_scale,
 563                 .r.height = mf->height << half_scale,
 564         };
 565         u32 code = mf->code;
 566         unsigned long mclk, pclk;
 567         u8 coma_set = 0, coma_mask = 0, coml_set, coml_mask, clkrc;
 568         int ret;
 569
 570         /* select color matrix configuration for given color encoding */
 571         switch (code) {
 572         case MEDIA_BUS_FMT_Y8_1X8:
 573                 dev_dbg(&client->dev, "pixel format GREY8_1X8\n");
 574                 coma_mask |= COMA_RGB | COMA_WORD_SWAP | COMA_BYTE_SWAP;
 575                 coma_set |= COMA_BW;
 576                 break;
 577         case MEDIA_BUS_FMT_YUYV8_2X8:
 578                 dev_dbg(&client->dev, "pixel format YUYV8_2X8_LE\n");
 579                 coma_mask |= COMA_RGB | COMA_BW | COMA_BYTE_SWAP;
 580                 coma_set |= COMA_WORD_SWAP;
 581                 break;
 582         case MEDIA_BUS_FMT_YVYU8_2X8:
 583                 dev_dbg(&client->dev, "pixel format YVYU8_2X8_LE (untested)\n");
 584                 coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP |
 585                                 COMA_BYTE_SWAP;
 586                 break;
 587         case MEDIA_BUS_FMT_UYVY8_2X8:
 588                 dev_dbg(&client->dev, "pixel format YUYV8_2X8_BE\n");
 589                 if (half_scale) {
 590                         coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP;
 591                         coma_set |= COMA_BYTE_SWAP;
 592                 } else {
 593                         coma_mask |= COMA_RGB | COMA_BW;
 594                         coma_set |= COMA_BYTE_SWAP | COMA_WORD_SWAP;
 595                 }
 596                 break;
 597         case MEDIA_BUS_FMT_VYUY8_2X8:
 598                 dev_dbg(&client->dev, "pixel format YVYU8_2X8_BE (untested)\n");
 599                 if (half_scale) {
 600                         coma_mask |= COMA_RGB | COMA_BW;
 601                         coma_set |= COMA_BYTE_SWAP | COMA_WORD_SWAP;
 602                 } else {
 603                         coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP;
 604                         coma_set |= COMA_BYTE_SWAP;
 605                 }
 606                 break;
 607         case MEDIA_BUS_FMT_SBGGR8_1X8:
 608                 dev_dbg(&client->dev, "pixel format SBGGR8_1X8 (untested)\n");
 609                 coma_mask |= COMA_BW | COMA_BYTE_SWAP | COMA_WORD_SWAP;
 610                 coma_set |= COMA_RAW_RGB | COMA_RGB;
 611                 break;
 612         default:
 613                 dev_err(&client->dev, "Pixel format not handled: 0x%x\n", code);
 614                 return -EINVAL;
 615         }
 616         priv->code = code;
 617
 618         if (code == MEDIA_BUS_FMT_Y8_1X8 ||
 619                         code == MEDIA_BUS_FMT_SBGGR8_1X8) {
 620                 coml_mask = COML_ONE_CHANNEL;
 621                 coml_set = 0;
 622                 priv->pclk_max = 4000000;
 623         } else {
 624                 coml_mask = 0;
 625                 coml_set = COML_ONE_CHANNEL;
 626                 priv->pclk_max = 8000000;
 627         }
 628
 629         if (code == MEDIA_BUS_FMT_SBGGR8_1X8)
 630                 priv->colorspace = V4L2_COLORSPACE_SRGB;
 631         else if (code != 0)
 632                 priv->colorspace = V4L2_COLORSPACE_JPEG;
 633
 634         if (half_scale) {
 635                 dev_dbg(&client->dev, "max resolution: QCIF\n");
 636                 coma_set |= COMA_QCIF;
 637                 priv->pclk_max /= 2;
 638         } else {
 639                 dev_dbg(&client->dev, "max resolution: CIF\n");
 640                 coma_mask |= COMA_QCIF;
 641         }
 642         priv->half_scale = half_scale;
 643
 644         clkrc = CLKRC_12MHz;
 645         mclk = 12000000;
 646         priv->pclk_limit = 1334000;
 647         dev_dbg(&client->dev, "using 12MHz input clock\n");
 648
 649         clkrc |= to_clkrc(&priv->tpf, priv->pclk_limit, priv->pclk_max);
 650
 651         pclk = priv->pclk_max / GET_CLKRC_DIV(clkrc);
 652         dev_dbg(&client->dev, "pixel clock divider: %ld.%ld\n",
 653                         mclk / pclk, 10 * mclk % pclk / pclk);
 654
 655         ret = ov6650_set_selection(sd, NULL, &sel);
 656         if (!ret)
 657                 ret = ov6650_reg_rmw(client, REG_COMA, coma_set, coma_mask);
 658         if (!ret)
 659                 ret = ov6650_reg_write(client, REG_CLKRC, clkrc);
 660         if (!ret)
 661                 ret = ov6650_reg_rmw(client, REG_COML, coml_set, coml_mask);
 662
 663         if (!ret) {
 664                 mf->colorspace  = priv->colorspace;
 665                 mf->width = priv->rect.width >> half_scale;
 666                 mf->height = priv->rect.height >> half_scale;
 667         }
 668         return ret;
 669 }
 670
 671 static int ov6650_set_fmt(struct v4l2_subdev *sd,
 672                 struct v4l2_subdev_pad_config *cfg,
 673                 struct v4l2_subdev_format *format)
 674 {
 675         struct v4l2_mbus_framefmt *mf = &format->format;
 676         struct i2c_client *client = v4l2_get_subdevdata(sd);
 677         struct ov6650 *priv = to_ov6650(client);
 678
 679         if (format->pad)
 680                 return -EINVAL;
 681
 682         if (is_unscaled_ok(mf->width, mf->height, &priv->rect))
 683                 v4l_bound_align_image(&mf->width, 2, W_CIF, 1,
 684                                 &mf->height, 2, H_CIF, 1, 0);
 685
 686         mf->field = V4L2_FIELD_NONE;
 687
 688         switch (mf->code) {
 689         case MEDIA_BUS_FMT_Y10_1X10:
 690                 mf->code = MEDIA_BUS_FMT_Y8_1X8;
 691                 /* fall through */
 692         case MEDIA_BUS_FMT_Y8_1X8:
 693         case MEDIA_BUS_FMT_YVYU8_2X8:
 694         case MEDIA_BUS_FMT_YUYV8_2X8:
 695         case MEDIA_BUS_FMT_VYUY8_2X8:
 696         case MEDIA_BUS_FMT_UYVY8_2X8:
 697                 mf->colorspace = V4L2_COLORSPACE_JPEG;
 698                 break;
 699         default:
 700                 mf->code = MEDIA_BUS_FMT_SBGGR8_1X8;
 701                 /* fall through */
 702         case MEDIA_BUS_FMT_SBGGR8_1X8:
 703                 mf->colorspace = V4L2_COLORSPACE_SRGB;
 704                 break;
 705         }
 706
 707         if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
 708                 return ov6650_s_fmt(sd, mf);
 709         cfg->try_fmt = *mf;
 710
 711         return 0;
 712 }
 713
 714 static int ov6650_enum_mbus_code(struct v4l2_subdev *sd,
 715                 struct v4l2_subdev_pad_config *cfg,
 716                 struct v4l2_subdev_mbus_code_enum *code)
 717 {
 718         if (code->pad || code->index >= ARRAY_SIZE(ov6650_codes))
 719                 return -EINVAL;
 720
 721         code->code = ov6650_codes[code->index];
 722         return 0;
 723 }
 724
 725 static int ov6650_g_frame_interval(struct v4l2_subdev *sd,
 726                                    struct v4l2_subdev_frame_interval *ival)
 727 {
 728         struct i2c_client *client = v4l2_get_subdevdata(sd);
 729         struct ov6650 *priv = to_ov6650(client);
 730
 731         ival->interval.numerator = GET_CLKRC_DIV(to_clkrc(&priv->tpf,
 732                         priv->pclk_limit, priv->pclk_max));
 733         ival->interval.denominator = FRAME_RATE_MAX;
 734
 735         dev_dbg(&client->dev, "Frame interval: %u/%u s\n",
 736                 ival->interval.numerator, ival->interval.denominator);
 737
 738         return 0;
 739 }
 740
 741 static int ov6650_s_frame_interval(struct v4l2_subdev *sd,
 742                                    struct v4l2_subdev_frame_interval *ival)
 743 {
 744         struct i2c_client *client = v4l2_get_subdevdata(sd);
 745         struct ov6650 *priv = to_ov6650(client);
 746         struct v4l2_fract *tpf = &ival->interval;
 747         int div, ret;
 748         u8 clkrc;
 749
 750         if (tpf->numerator == 0 || tpf->denominator == 0)
 751                 div = 1;  /* Reset to full rate */
 752         else
 753                 div = (tpf->numerator * FRAME_RATE_MAX) / tpf->denominator;
 754
 755         if (div == 0)
 756                 div = 1;
 757         else if (div > GET_CLKRC_DIV(CLKRC_DIV_MASK))
 758                 div = GET_CLKRC_DIV(CLKRC_DIV_MASK);
 759
 760         /*
 761          * Keep result to be used as tpf limit
 762          * for subsequent clock divider calculations
 763          */
 764         priv->tpf.numerator = div;
 765         priv->tpf.denominator = FRAME_RATE_MAX;
 766
 767         clkrc = to_clkrc(&priv->tpf, priv->pclk_limit, priv->pclk_max);
 768
 769         ret = ov6650_reg_rmw(client, REG_CLKRC, clkrc, CLKRC_DIV_MASK);
 770         if (!ret) {
 771                 tpf->numerator = GET_CLKRC_DIV(clkrc);
 772                 tpf->denominator = FRAME_RATE_MAX;
 773         }
 774
 775         return ret;
 776 }
 777
 778 /* Soft reset the camera. This has nothing to do with the RESET pin! */
 779 static int ov6650_reset(struct i2c_client *client)
 780 {
 781         int ret;
 782
 783         dev_dbg(&client->dev, "reset\n");
 784
 785         ret = ov6650_reg_rmw(client, REG_COMA, COMA_RESET, 0);
 786         if (ret)
 787                 dev_err(&client->dev,
 788                         "An error occurred while entering soft reset!\n");
 789
 790         return ret;
 791 }
 792
 793 /* program default register values */
 794 static int ov6650_prog_dflt(struct i2c_client *client)
 795 {
 796         int ret;
 797
 798         dev_dbg(&client->dev, "initializing\n");
 799
 800         ret = ov6650_reg_write(client, REG_COMA, 0);    /* ~COMA_RESET */
 801         if (!ret)
 802                 ret = ov6650_reg_rmw(client, REG_COMB, 0, COMB_BAND_FILTER);
 803
 804         return ret;
 805 }
 806
 807 static int ov6650_video_probe(struct v4l2_subdev *sd)
 808 {
 809         struct i2c_client *client = v4l2_get_subdevdata(sd);
 810         struct ov6650 *priv = to_ov6650(client);
 811         u8              pidh, pidl, midh, midl;
 812         int             ret;
 813
 814         priv->clk = v4l2_clk_get(&client->dev, NULL);
 815         if (IS_ERR(priv->clk)) {
 816                 ret = PTR_ERR(priv->clk);
 817                 dev_err(&client->dev, "v4l2_clk request err: %d\n", ret);
 818                 return ret;
 819         }
 820
 821         ret = ov6650_s_power(sd, 1);
 822         if (ret < 0)
 823                 goto eclkput;
 824
 825         msleep(20);
 826
 827         /*
 828          * check and show product ID and manufacturer ID
 829          */
 830         ret = ov6650_reg_read(client, REG_PIDH, &pidh);
 831         if (!ret)
 832                 ret = ov6650_reg_read(client, REG_PIDL, &pidl);
 833         if (!ret)
 834                 ret = ov6650_reg_read(client, REG_MIDH, &midh);
 835         if (!ret)
 836                 ret = ov6650_reg_read(client, REG_MIDL, &midl);
 837
 838         if (ret)
 839                 goto done;
 840
 841         if ((pidh != OV6650_PIDH) || (pidl != OV6650_PIDL)) {
 842                 dev_err(&client->dev, "Product ID error 0x%02x:0x%02x\n",
 843                                 pidh, pidl);
 844                 ret = -ENODEV;
 845                 goto done;
 846         }
 847
 848         dev_info(&client->dev,
 849                 "ov6650 Product ID 0x%02x:0x%02x Manufacturer ID 0x%02x:0x%02x\n",
 850                 pidh, pidl, midh, midl);
 851
 852         ret = ov6650_reset(client);
 853         if (!ret)
 854                 ret = ov6650_prog_dflt(client);
 855         if (!ret)
 856                 ret = v4l2_ctrl_handler_setup(&priv->hdl);
 857
 858 done:
 859         ov6650_s_power(sd, 0);
 860         if (!ret)
 861                 return 0;
 862 eclkput:
 863         v4l2_clk_put(priv->clk);
 864
 865         return ret;
 866 }
 867
 868 static const struct v4l2_ctrl_ops ov6550_ctrl_ops = {
 869         .g_volatile_ctrl = ov6550_g_volatile_ctrl,
 870         .s_ctrl = ov6550_s_ctrl,
 871 };
 872
 873 static const struct v4l2_subdev_core_ops ov6650_core_ops = {
 874 #ifdef CONFIG_VIDEO_ADV_DEBUG
 875         .g_register             = ov6650_get_register,
 876         .s_register             = ov6650_set_register,
 877 #endif
 878         .s_power                = ov6650_s_power,
 879 };
 880
 881 /* Request bus settings on camera side */
 882 static int ov6650_g_mbus_config(struct v4l2_subdev *sd,
 883                                 struct v4l2_mbus_config *cfg)
 884 {
 885
 886         cfg->flags = V4L2_MBUS_MASTER |
 887                 V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_PCLK_SAMPLE_FALLING |
 888                 V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_LOW |
 889                 V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_LOW |
 890                 V4L2_MBUS_DATA_ACTIVE_HIGH;
 891         cfg->type = V4L2_MBUS_PARALLEL;
 892
 893         return 0;
 894 }
 895
 896 /* Alter bus settings on camera side */
 897 static int ov6650_s_mbus_config(struct v4l2_subdev *sd,
 898                                 const struct v4l2_mbus_config *cfg)
 899 {
 900         struct i2c_client *client = v4l2_get_subdevdata(sd);
 901         int ret;
 902
 903         if (cfg->flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
 904                 ret = ov6650_reg_rmw(client, REG_COMJ, COMJ_PCLK_RISING, 0);
 905         else
 906                 ret = ov6650_reg_rmw(client, REG_COMJ, 0, COMJ_PCLK_RISING);
 907         if (ret)
 908                 return ret;
 909
 910         if (cfg->flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
 911                 ret = ov6650_reg_rmw(client, REG_COMF, COMF_HREF_LOW, 0);
 912         else
 913                 ret = ov6650_reg_rmw(client, REG_COMF, 0, COMF_HREF_LOW);
 914         if (ret)
 915                 return ret;
 916
 917         if (cfg->flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
 918                 ret = ov6650_reg_rmw(client, REG_COMJ, COMJ_VSYNC_HIGH, 0);
 919         else
 920                 ret = ov6650_reg_rmw(client, REG_COMJ, 0, COMJ_VSYNC_HIGH);
 921
 922         return ret;
 923 }
 924
 925 static const struct v4l2_subdev_video_ops ov6650_video_ops = {
 926         .s_stream       = ov6650_s_stream,
 927         .g_frame_interval = ov6650_g_frame_interval,
 928         .s_frame_interval = ov6650_s_frame_interval,
 929         .g_mbus_config  = ov6650_g_mbus_config,
 930         .s_mbus_config  = ov6650_s_mbus_config,
 931 };
 932
 933 static const struct v4l2_subdev_pad_ops ov6650_pad_ops = {
 934         .enum_mbus_code = ov6650_enum_mbus_code,
 935         .get_selection  = ov6650_get_selection,
 936         .set_selection  = ov6650_set_selection,
 937         .get_fmt        = ov6650_get_fmt,
 938         .set_fmt        = ov6650_set_fmt,
 939 };
 940
 941 static const struct v4l2_subdev_ops ov6650_subdev_ops = {
 942         .core   = &ov6650_core_ops,
 943         .video  = &ov6650_video_ops,
 944         .pad    = &ov6650_pad_ops,
 945 };
 946
 947 static const struct v4l2_subdev_internal_ops ov6650_internal_ops = {
 948         .registered = ov6650_video_probe,
 949 };
 950
 951 /*
 952  * i2c_driver function
 953  */
 954 static int ov6650_probe(struct i2c_client *client,
 955                         const struct i2c_device_id *did)
 956 {
 957         struct ov6650 *priv;
 958         int ret;
 959
 960         priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
 961         if (!priv)
 962                 return -ENOMEM;
 963
 964         v4l2_i2c_subdev_init(&priv->subdev, client, &ov6650_subdev_ops);
 965         v4l2_ctrl_handler_init(&priv->hdl, 13);
 966         v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
 967                         V4L2_CID_VFLIP, 0, 1, 1, 0);
 968         v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
 969                         V4L2_CID_HFLIP, 0, 1, 1, 0);
 970         priv->autogain = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
 971                         V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
 972         priv->gain = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
 973                         V4L2_CID_GAIN, 0, 0x3f, 1, DEF_GAIN);
 974         priv->autowb = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
 975                         V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
 976         priv->blue = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
 977                         V4L2_CID_BLUE_BALANCE, 0, 0xff, 1, DEF_BLUE);
 978         priv->red = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
 979                         V4L2_CID_RED_BALANCE, 0, 0xff, 1, DEF_RED);
 980         v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
 981                         V4L2_CID_SATURATION, 0, 0xf, 1, 0x8);
 982         v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
 983                         V4L2_CID_HUE, 0, HUE_MASK, 1, DEF_HUE);
 984         v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
 985                         V4L2_CID_BRIGHTNESS, 0, 0xff, 1, 0x80);
 986         priv->autoexposure = v4l2_ctrl_new_std_menu(&priv->hdl,
 987                         &ov6550_ctrl_ops, V4L2_CID_EXPOSURE_AUTO,
 988                         V4L2_EXPOSURE_MANUAL, 0, V4L2_EXPOSURE_AUTO);
 989         priv->exposure = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
 990                         V4L2_CID_EXPOSURE, 0, 0xff, 1, DEF_AECH);
 991         v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
 992                         V4L2_CID_GAMMA, 0, 0xff, 1, 0x12);
 993
 994         priv->subdev.ctrl_handler = &priv->hdl;
 995         if (priv->hdl.error)
 996                 return priv->hdl.error;
 997
 998         v4l2_ctrl_auto_cluster(2, &priv->autogain, 0, true);
 999         v4l2_ctrl_auto_cluster(3, &priv->autowb, 0, true);
1000         v4l2_ctrl_auto_cluster(2, &priv->autoexposure,
1001                                 V4L2_EXPOSURE_MANUAL, true);
1002
1003         priv->rect.left   = DEF_HSTRT << 1;
1004         priv->rect.top    = DEF_VSTRT << 1;
1005         priv->rect.width  = W_CIF;
1006         priv->rect.height = H_CIF;
1007         priv->half_scale  = false;
1008         priv->code        = MEDIA_BUS_FMT_YUYV8_2X8;
1009         priv->colorspace  = V4L2_COLORSPACE_JPEG;
1010
1011         priv->subdev.internal_ops = &ov6650_internal_ops;
1012         priv->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1013
1014         ret = v4l2_async_register_subdev(&priv->subdev);
1015         if (ret)
1016                 v4l2_ctrl_handler_free(&priv->hdl);
1017
1018         return ret;
1019 }
1020
1021 static int ov6650_remove(struct i2c_client *client)
1022 {
1023         struct ov6650 *priv = to_ov6650(client);
1024
1025         v4l2_clk_put(priv->clk);
1026         v4l2_async_unregister_subdev(&priv->subdev);
1027         v4l2_ctrl_handler_free(&priv->hdl);
1028         return 0;
1029 }
1030
1031 static const struct i2c_device_id ov6650_id[] = {
1032         { "ov6650", 0 },
1033         { }
1034 };
1035 MODULE_DEVICE_TABLE(i2c, ov6650_id);
1036
1037 static struct i2c_driver ov6650_i2c_driver = {
1038         .driver = {
1039                 .name = "ov6650",
1040         },
1041         .probe    = ov6650_probe,
1042         .remove   = ov6650_remove,
1043         .id_table = ov6650_id,
1044 };
1045
1046 module_i2c_driver(ov6650_i2c_driver);
1047
1048 MODULE_DESCRIPTION("SoC Camera driver for OmniVision OV6650");
1049 MODULE_AUTHOR("Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>");
1050 MODULE_LICENSE("GPL v2");