2 * Driver for the Conexant CX2584x Audio/Video decoder chip and related cores
4 * Integrated Consumer Infrared Controller
6 * Copyright (C) 2010 Andy Walls <awalls@md.metrocast.net>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/slab.h>
20 #include <linux/kfifo.h>
21 #include <linux/module.h>
22 #include <media/drv-intf/cx25840.h>
23 #include <media/rc-core.h>
25 #include "cx25840-core.h"
27 static unsigned int ir_debug;
28 module_param(ir_debug, int, 0644);
29 MODULE_PARM_DESC(ir_debug, "enable integrated IR debug messages");
31 #define CX25840_IR_REG_BASE 0x200
33 #define CX25840_IR_CNTRL_REG 0x200
34 #define CNTRL_WIN_3_3 0x00000000
35 #define CNTRL_WIN_4_3 0x00000001
36 #define CNTRL_WIN_3_4 0x00000002
37 #define CNTRL_WIN_4_4 0x00000003
38 #define CNTRL_WIN 0x00000003
39 #define CNTRL_EDG_NONE 0x00000000
40 #define CNTRL_EDG_FALL 0x00000004
41 #define CNTRL_EDG_RISE 0x00000008
42 #define CNTRL_EDG_BOTH 0x0000000C
43 #define CNTRL_EDG 0x0000000C
44 #define CNTRL_DMD 0x00000010
45 #define CNTRL_MOD 0x00000020
46 #define CNTRL_RFE 0x00000040
47 #define CNTRL_TFE 0x00000080
48 #define CNTRL_RXE 0x00000100
49 #define CNTRL_TXE 0x00000200
50 #define CNTRL_RIC 0x00000400
51 #define CNTRL_TIC 0x00000800
52 #define CNTRL_CPL 0x00001000
53 #define CNTRL_LBM 0x00002000
54 #define CNTRL_R 0x00004000
56 #define CX25840_IR_TXCLK_REG 0x204
57 #define TXCLK_TCD 0x0000FFFF
59 #define CX25840_IR_RXCLK_REG 0x208
60 #define RXCLK_RCD 0x0000FFFF
62 #define CX25840_IR_CDUTY_REG 0x20C
63 #define CDUTY_CDC 0x0000000F
65 #define CX25840_IR_STATS_REG 0x210
66 #define STATS_RTO 0x00000001
67 #define STATS_ROR 0x00000002
68 #define STATS_RBY 0x00000004
69 #define STATS_TBY 0x00000008
70 #define STATS_RSR 0x00000010
71 #define STATS_TSR 0x00000020
73 #define CX25840_IR_IRQEN_REG 0x214
74 #define IRQEN_RTE 0x00000001
75 #define IRQEN_ROE 0x00000002
76 #define IRQEN_RSE 0x00000010
77 #define IRQEN_TSE 0x00000020
78 #define IRQEN_MSK 0x00000033
80 #define CX25840_IR_FILTR_REG 0x218
81 #define FILTR_LPF 0x0000FFFF
83 #define CX25840_IR_FIFO_REG 0x23C
84 #define FIFO_RXTX 0x0000FFFF
85 #define FIFO_RXTX_LVL 0x00010000
86 #define FIFO_RXTX_RTO 0x0001FFFF
87 #define FIFO_RX_NDV 0x00020000
88 #define FIFO_RX_DEPTH 8
89 #define FIFO_TX_DEPTH 8
91 #define CX25840_VIDCLK_FREQ 108000000 /* 108 MHz, BT.656 */
92 #define CX25840_IR_REFCLK_FREQ (CX25840_VIDCLK_FREQ / 2)
95 * We use this union internally for convenience, but callers to tx_write
96 * and rx_read will be expecting records of type struct ir_raw_event.
97 * Always ensure the size of this union is dictated by struct ir_raw_event.
99 union cx25840_ir_fifo_rec {
101 struct ir_raw_event ir_core_data;
104 #define CX25840_IR_RX_KFIFO_SIZE (256 * sizeof(union cx25840_ir_fifo_rec))
105 #define CX25840_IR_TX_KFIFO_SIZE (256 * sizeof(union cx25840_ir_fifo_rec))
107 struct cx25840_ir_state {
108 struct i2c_client *c;
110 struct v4l2_subdev_ir_parameters rx_params;
111 struct mutex rx_params_lock; /* protects Rx parameter settings cache */
112 atomic_t rxclk_divider;
115 struct kfifo rx_kfifo;
116 spinlock_t rx_kfifo_lock; /* protect Rx data kfifo */
118 struct v4l2_subdev_ir_parameters tx_params;
119 struct mutex tx_params_lock; /* protects Tx parameter settings cache */
120 atomic_t txclk_divider;
123 static inline struct cx25840_ir_state *to_ir_state(struct v4l2_subdev *sd)
125 struct cx25840_state *state = to_state(sd);
126 return state ? state->ir_state : NULL;
131 * Rx and Tx Clock Divider register computations
133 * Note the largest clock divider value of 0xffff corresponds to:
134 * (0xffff + 1) * 1000 / 108/2 MHz = 1,213,629.629... ns
135 * which fits in 21 bits, so we'll use unsigned int for time arguments.
137 static inline u16 count_to_clock_divider(unsigned int d)
139 if (d > RXCLK_RCD + 1)
148 static inline u16 ns_to_clock_divider(unsigned int ns)
150 return count_to_clock_divider(
151 DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ / 1000000 * ns, 1000));
154 static inline unsigned int clock_divider_to_ns(unsigned int divider)
156 /* Period of the Rx or Tx clock in ns */
157 return DIV_ROUND_CLOSEST((divider + 1) * 1000,
158 CX25840_IR_REFCLK_FREQ / 1000000);
161 static inline u16 carrier_freq_to_clock_divider(unsigned int freq)
163 return count_to_clock_divider(
164 DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, freq * 16));
167 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider)
169 return DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, (divider + 1) * 16);
172 static inline u16 freq_to_clock_divider(unsigned int freq,
173 unsigned int rollovers)
175 return count_to_clock_divider(
176 DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, freq * rollovers));
179 static inline unsigned int clock_divider_to_freq(unsigned int divider,
180 unsigned int rollovers)
182 return DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ,
183 (divider + 1) * rollovers);
187 * Low Pass Filter register calculations
189 * Note the largest count value of 0xffff corresponds to:
190 * 0xffff * 1000 / 108/2 MHz = 1,213,611.11... ns
191 * which fits in 21 bits, so we'll use unsigned int for time arguments.
193 static inline u16 count_to_lpf_count(unsigned int d)
202 static inline u16 ns_to_lpf_count(unsigned int ns)
204 return count_to_lpf_count(
205 DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ / 1000000 * ns, 1000));
208 static inline unsigned int lpf_count_to_ns(unsigned int count)
210 /* Duration of the Low Pass Filter rejection window in ns */
211 return DIV_ROUND_CLOSEST(count * 1000,
212 CX25840_IR_REFCLK_FREQ / 1000000);
215 static inline unsigned int lpf_count_to_us(unsigned int count)
217 /* Duration of the Low Pass Filter rejection window in us */
218 return DIV_ROUND_CLOSEST(count, CX25840_IR_REFCLK_FREQ / 1000000);
222 * FIFO register pulse width count computations
224 static u32 clock_divider_to_resolution(u16 divider)
227 * Resolution is the duration of 1 tick of the readable portion of
228 * of the pulse width counter as read from the FIFO. The two lsb's are
229 * not readable, hence the << 2. This function returns ns.
231 return DIV_ROUND_CLOSEST((1 << 2) * ((u32) divider + 1) * 1000,
232 CX25840_IR_REFCLK_FREQ / 1000000);
235 static u64 pulse_width_count_to_ns(u16 count, u16 divider)
241 * The 2 lsb's of the pulse width timer count are not readable, hence
242 * the (count << 2) | 0x3
244 n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */
245 rem = do_div(n, CX25840_IR_REFCLK_FREQ / 1000000); /* / MHz => ns */
246 if (rem >= CX25840_IR_REFCLK_FREQ / 1000000 / 2)
252 /* Keep as we will need this for Transmit functionality */
253 static u16 ns_to_pulse_width_count(u32 ns, u16 divider)
260 * The 2 lsb's of the pulse width timer count are not accessible, hence
263 n = ((u64) ns) * CX25840_IR_REFCLK_FREQ / 1000000; /* millicycles */
264 d = (1 << 2) * ((u32) divider + 1) * 1000; /* millicycles/count */
277 static unsigned int pulse_width_count_to_us(u16 count, u16 divider)
283 * The 2 lsb's of the pulse width timer count are not readable, hence
284 * the (count << 2) | 0x3
286 n = (((u64) count << 2) | 0x3) * (divider + 1); /* cycles */
287 rem = do_div(n, CX25840_IR_REFCLK_FREQ / 1000000); /* / MHz => us */
288 if (rem >= CX25840_IR_REFCLK_FREQ / 1000000 / 2)
290 return (unsigned int) n;
294 * Pulse Clocks computations: Combined Pulse Width Count & Rx Clock Counts
296 * The total pulse clock count is an 18 bit pulse width timer count as the most
297 * significant part and (up to) 16 bit clock divider count as a modulus.
298 * When the Rx clock divider ticks down to 0, it increments the 18 bit pulse
299 * width timer count's least significant bit.
301 static u64 ns_to_pulse_clocks(u32 ns)
305 clocks = CX25840_IR_REFCLK_FREQ / 1000000 * (u64) ns; /* millicycles */
306 rem = do_div(clocks, 1000); /* /1000 = cycles */
312 static u16 pulse_clocks_to_clock_divider(u64 count)
314 do_div(count, (FIFO_RXTX << 2) | 0x3);
316 /* net result needs to be rounded down and decremented by 1 */
317 if (count > RXCLK_RCD + 1)
327 * IR Control Register helpers
329 enum tx_fifo_watermark {
330 TX_FIFO_HALF_EMPTY = 0,
331 TX_FIFO_EMPTY = CNTRL_TIC,
334 enum rx_fifo_watermark {
335 RX_FIFO_HALF_FULL = 0,
336 RX_FIFO_NOT_EMPTY = CNTRL_RIC,
339 static inline void control_tx_irq_watermark(struct i2c_client *c,
340 enum tx_fifo_watermark level)
342 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_TIC, level);
345 static inline void control_rx_irq_watermark(struct i2c_client *c,
346 enum rx_fifo_watermark level)
348 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_RIC, level);
351 static inline void control_tx_enable(struct i2c_client *c, bool enable)
353 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~(CNTRL_TXE | CNTRL_TFE),
354 enable ? (CNTRL_TXE | CNTRL_TFE) : 0);
357 static inline void control_rx_enable(struct i2c_client *c, bool enable)
359 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~(CNTRL_RXE | CNTRL_RFE),
360 enable ? (CNTRL_RXE | CNTRL_RFE) : 0);
363 static inline void control_tx_modulation_enable(struct i2c_client *c,
366 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_MOD,
367 enable ? CNTRL_MOD : 0);
370 static inline void control_rx_demodulation_enable(struct i2c_client *c,
373 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_DMD,
374 enable ? CNTRL_DMD : 0);
377 static inline void control_rx_s_edge_detection(struct i2c_client *c,
380 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_EDG_BOTH,
381 edge_types & CNTRL_EDG_BOTH);
384 static void control_rx_s_carrier_window(struct i2c_client *c,
385 unsigned int carrier,
386 unsigned int *carrier_range_low,
387 unsigned int *carrier_range_high)
390 unsigned int c16 = carrier * 16;
392 if (*carrier_range_low < DIV_ROUND_CLOSEST(c16, 16 + 3)) {
394 *carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 4);
397 *carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 3);
400 if (*carrier_range_high > DIV_ROUND_CLOSEST(c16, 16 - 3)) {
402 *carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 4);
405 *carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 3);
407 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_WIN, v);
410 static inline void control_tx_polarity_invert(struct i2c_client *c,
413 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_CPL,
414 invert ? CNTRL_CPL : 0);
418 * IR Rx & Tx Clock Register helpers
420 static unsigned int txclk_tx_s_carrier(struct i2c_client *c,
424 *divider = carrier_freq_to_clock_divider(freq);
425 cx25840_write4(c, CX25840_IR_TXCLK_REG, *divider);
426 return clock_divider_to_carrier_freq(*divider);
429 static unsigned int rxclk_rx_s_carrier(struct i2c_client *c,
433 *divider = carrier_freq_to_clock_divider(freq);
434 cx25840_write4(c, CX25840_IR_RXCLK_REG, *divider);
435 return clock_divider_to_carrier_freq(*divider);
438 static u32 txclk_tx_s_max_pulse_width(struct i2c_client *c, u32 ns,
443 if (ns > IR_MAX_DURATION)
444 ns = IR_MAX_DURATION;
445 pulse_clocks = ns_to_pulse_clocks(ns);
446 *divider = pulse_clocks_to_clock_divider(pulse_clocks);
447 cx25840_write4(c, CX25840_IR_TXCLK_REG, *divider);
448 return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
451 static u32 rxclk_rx_s_max_pulse_width(struct i2c_client *c, u32 ns,
456 if (ns > IR_MAX_DURATION)
457 ns = IR_MAX_DURATION;
458 pulse_clocks = ns_to_pulse_clocks(ns);
459 *divider = pulse_clocks_to_clock_divider(pulse_clocks);
460 cx25840_write4(c, CX25840_IR_RXCLK_REG, *divider);
461 return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
465 * IR Tx Carrier Duty Cycle register helpers
467 static unsigned int cduty_tx_s_duty_cycle(struct i2c_client *c,
468 unsigned int duty_cycle)
471 n = DIV_ROUND_CLOSEST(duty_cycle * 100, 625); /* 16ths of 100% */
476 cx25840_write4(c, CX25840_IR_CDUTY_REG, n);
477 return DIV_ROUND_CLOSEST((n + 1) * 100, 16);
481 * IR Filter Register helpers
483 static u32 filter_rx_s_min_width(struct i2c_client *c, u32 min_width_ns)
485 u32 count = ns_to_lpf_count(min_width_ns);
486 cx25840_write4(c, CX25840_IR_FILTR_REG, count);
487 return lpf_count_to_ns(count);
491 * IR IRQ Enable Register helpers
493 static inline void irqenable_rx(struct v4l2_subdev *sd, u32 mask)
495 struct cx25840_state *state = to_state(sd);
497 if (is_cx23885(state) || is_cx23887(state))
499 mask &= (IRQEN_RTE | IRQEN_ROE | IRQEN_RSE);
500 cx25840_and_or4(state->c, CX25840_IR_IRQEN_REG,
501 ~(IRQEN_RTE | IRQEN_ROE | IRQEN_RSE), mask);
504 static inline void irqenable_tx(struct v4l2_subdev *sd, u32 mask)
506 struct cx25840_state *state = to_state(sd);
508 if (is_cx23885(state) || is_cx23887(state))
511 cx25840_and_or4(state->c, CX25840_IR_IRQEN_REG, ~IRQEN_TSE, mask);
515 * V4L2 Subdevice IR Ops
517 int cx25840_ir_irq_handler(struct v4l2_subdev *sd, u32 status, bool *handled)
519 struct cx25840_state *state = to_state(sd);
520 struct cx25840_ir_state *ir_state = to_ir_state(sd);
521 struct i2c_client *c = NULL;
524 union cx25840_ir_fifo_rec rx_data[FIFO_RX_DEPTH];
525 unsigned int i, j, k;
527 int tsr, rsr, rto, ror, tse, rse, rte, roe, kror;
528 u32 cntrl, irqen, stats;
531 if (ir_state == NULL)
536 /* Only support the IR controller for the CX2388[57] AV Core for now */
537 if (!(is_cx23885(state) || is_cx23887(state)))
540 cntrl = cx25840_read4(c, CX25840_IR_CNTRL_REG);
541 irqen = cx25840_read4(c, CX25840_IR_IRQEN_REG);
542 if (is_cx23885(state) || is_cx23887(state))
544 stats = cx25840_read4(c, CX25840_IR_STATS_REG);
546 tsr = stats & STATS_TSR; /* Tx FIFO Service Request */
547 rsr = stats & STATS_RSR; /* Rx FIFO Service Request */
548 rto = stats & STATS_RTO; /* Rx Pulse Width Timer Time Out */
549 ror = stats & STATS_ROR; /* Rx FIFO Over Run */
551 tse = irqen & IRQEN_TSE; /* Tx FIFO Service Request IRQ Enable */
552 rse = irqen & IRQEN_RSE; /* Rx FIFO Service Reuqest IRQ Enable */
553 rte = irqen & IRQEN_RTE; /* Rx Pulse Width Timer Time Out IRQ Enable */
554 roe = irqen & IRQEN_ROE; /* Rx FIFO Over Run IRQ Enable */
556 v4l2_dbg(2, ir_debug, sd, "IR IRQ Status: %s %s %s %s %s %s\n",
557 tsr ? "tsr" : " ", rsr ? "rsr" : " ",
558 rto ? "rto" : " ", ror ? "ror" : " ",
559 stats & STATS_TBY ? "tby" : " ",
560 stats & STATS_RBY ? "rby" : " ");
562 v4l2_dbg(2, ir_debug, sd, "IR IRQ Enables: %s %s %s %s\n",
563 tse ? "tse" : " ", rse ? "rse" : " ",
564 rte ? "rte" : " ", roe ? "roe" : " ");
567 * Transmitter interrupt service
572 * Check the watermark threshold setting
573 * Pull FIFO_TX_DEPTH or FIFO_TX_DEPTH/2 entries from tx_kfifo
574 * Push the data to the hardware FIFO.
575 * If there was nothing more to send in the tx_kfifo, disable
576 * the TSR IRQ and notify the v4l2_device.
577 * If there was something in the tx_kfifo, check the tx_kfifo
578 * level and notify the v4l2_device, if it is low.
580 /* For now, inhibit TSR interrupt until Tx is implemented */
582 events = V4L2_SUBDEV_IR_TX_FIFO_SERVICE_REQ;
583 v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_TX_NOTIFY, &events);
588 * Receiver interrupt service
591 if ((rse && rsr) || (rte && rto)) {
593 * Receive data on RSR to clear the STATS_RSR.
594 * Receive data on RTO, since we may not have yet hit the RSR
595 * watermark when we receive the RTO.
597 for (i = 0, v = FIFO_RX_NDV;
598 (v & FIFO_RX_NDV) && !kror; i = 0) {
600 (v & FIFO_RX_NDV) && j < FIFO_RX_DEPTH; j++) {
601 v = cx25840_read4(c, CX25840_IR_FIFO_REG);
602 rx_data[i].hw_fifo_data = v & ~FIFO_RX_NDV;
607 j = i * sizeof(union cx25840_ir_fifo_rec);
608 k = kfifo_in_locked(&ir_state->rx_kfifo,
609 (unsigned char *) rx_data, j,
610 &ir_state->rx_kfifo_lock);
612 kror++; /* rx_kfifo over run */
620 events |= V4L2_SUBDEV_IR_RX_SW_FIFO_OVERRUN;
621 v4l2_err(sd, "IR receiver software FIFO overrun\n");
625 * The RX FIFO Enable (CNTRL_RFE) must be toggled to clear
626 * the Rx FIFO Over Run status (STATS_ROR)
629 events |= V4L2_SUBDEV_IR_RX_HW_FIFO_OVERRUN;
630 v4l2_err(sd, "IR receiver hardware FIFO overrun\n");
634 * The IR Receiver Enable (CNTRL_RXE) must be toggled to clear
635 * the Rx Pulse Width Timer Time Out (STATS_RTO)
638 events |= V4L2_SUBDEV_IR_RX_END_OF_RX_DETECTED;
641 /* Clear STATS_ROR & STATS_RTO as needed by reseting hardware */
642 cx25840_write4(c, CX25840_IR_CNTRL_REG, cntrl & ~v);
643 cx25840_write4(c, CX25840_IR_CNTRL_REG, cntrl);
646 spin_lock_irqsave(&ir_state->rx_kfifo_lock, flags);
647 if (kfifo_len(&ir_state->rx_kfifo) >= CX25840_IR_RX_KFIFO_SIZE / 2)
648 events |= V4L2_SUBDEV_IR_RX_FIFO_SERVICE_REQ;
649 spin_unlock_irqrestore(&ir_state->rx_kfifo_lock, flags);
652 v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_RX_NOTIFY, &events);
657 static int cx25840_ir_rx_read(struct v4l2_subdev *sd, u8 *buf, size_t count,
660 struct cx25840_ir_state *ir_state = to_ir_state(sd);
664 union cx25840_ir_fifo_rec *p;
667 if (ir_state == NULL)
670 invert = (bool) atomic_read(&ir_state->rx_invert);
671 divider = (u16) atomic_read(&ir_state->rxclk_divider);
673 n = count / sizeof(union cx25840_ir_fifo_rec)
674 * sizeof(union cx25840_ir_fifo_rec);
680 n = kfifo_out_locked(&ir_state->rx_kfifo, buf, n,
681 &ir_state->rx_kfifo_lock);
683 n /= sizeof(union cx25840_ir_fifo_rec);
684 *num = n * sizeof(union cx25840_ir_fifo_rec);
686 for (p = (union cx25840_ir_fifo_rec *) buf, i = 0; i < n; p++, i++) {
688 if ((p->hw_fifo_data & FIFO_RXTX_RTO) == FIFO_RXTX_RTO) {
689 /* Assume RTO was because of no IR light input */
693 u = (p->hw_fifo_data & FIFO_RXTX_LVL) ? 1 : 0;
699 v = (unsigned) pulse_width_count_to_ns(
700 (u16) (p->hw_fifo_data & FIFO_RXTX), divider);
701 if (v > IR_MAX_DURATION)
704 p->ir_core_data = (struct ir_raw_event)
705 { .pulse = u, .duration = v, .timeout = w };
707 v4l2_dbg(2, ir_debug, sd, "rx read: %10u ns %s %s\n",
708 v, u ? "mark" : "space", w ? "(timed out)" : "");
710 v4l2_dbg(2, ir_debug, sd, "rx read: end of rx\n");
715 static int cx25840_ir_rx_g_parameters(struct v4l2_subdev *sd,
716 struct v4l2_subdev_ir_parameters *p)
718 struct cx25840_ir_state *ir_state = to_ir_state(sd);
720 if (ir_state == NULL)
723 mutex_lock(&ir_state->rx_params_lock);
724 memcpy(p, &ir_state->rx_params,
725 sizeof(struct v4l2_subdev_ir_parameters));
726 mutex_unlock(&ir_state->rx_params_lock);
730 static int cx25840_ir_rx_shutdown(struct v4l2_subdev *sd)
732 struct cx25840_ir_state *ir_state = to_ir_state(sd);
733 struct i2c_client *c;
735 if (ir_state == NULL)
739 mutex_lock(&ir_state->rx_params_lock);
741 /* Disable or slow down all IR Rx circuits and counters */
743 control_rx_enable(c, false);
744 control_rx_demodulation_enable(c, false);
745 control_rx_s_edge_detection(c, CNTRL_EDG_NONE);
746 filter_rx_s_min_width(c, 0);
747 cx25840_write4(c, CX25840_IR_RXCLK_REG, RXCLK_RCD);
749 ir_state->rx_params.shutdown = true;
751 mutex_unlock(&ir_state->rx_params_lock);
755 static int cx25840_ir_rx_s_parameters(struct v4l2_subdev *sd,
756 struct v4l2_subdev_ir_parameters *p)
758 struct cx25840_ir_state *ir_state = to_ir_state(sd);
759 struct i2c_client *c;
760 struct v4l2_subdev_ir_parameters *o;
763 if (ir_state == NULL)
767 return cx25840_ir_rx_shutdown(sd);
769 if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH)
773 o = &ir_state->rx_params;
775 mutex_lock(&ir_state->rx_params_lock);
777 o->shutdown = p->shutdown;
779 p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH;
782 p->bytes_per_data_element = sizeof(union cx25840_ir_fifo_rec);
783 o->bytes_per_data_element = p->bytes_per_data_element;
785 /* Before we tweak the hardware, we have to disable the receiver */
787 control_rx_enable(c, false);
789 control_rx_demodulation_enable(c, p->modulation);
790 o->modulation = p->modulation;
793 p->carrier_freq = rxclk_rx_s_carrier(c, p->carrier_freq,
796 o->carrier_freq = p->carrier_freq;
799 o->duty_cycle = p->duty_cycle;
801 control_rx_s_carrier_window(c, p->carrier_freq,
802 &p->carrier_range_lower,
803 &p->carrier_range_upper);
804 o->carrier_range_lower = p->carrier_range_lower;
805 o->carrier_range_upper = p->carrier_range_upper;
808 (u32) pulse_width_count_to_ns(FIFO_RXTX, rxclk_divider);
811 rxclk_rx_s_max_pulse_width(c, p->max_pulse_width,
814 o->max_pulse_width = p->max_pulse_width;
815 atomic_set(&ir_state->rxclk_divider, rxclk_divider);
817 p->noise_filter_min_width =
818 filter_rx_s_min_width(c, p->noise_filter_min_width);
819 o->noise_filter_min_width = p->noise_filter_min_width;
821 p->resolution = clock_divider_to_resolution(rxclk_divider);
822 o->resolution = p->resolution;
824 /* FIXME - make this dependent on resolution for better performance */
825 control_rx_irq_watermark(c, RX_FIFO_HALF_FULL);
827 control_rx_s_edge_detection(c, CNTRL_EDG_BOTH);
829 o->invert_level = p->invert_level;
830 atomic_set(&ir_state->rx_invert, p->invert_level);
832 o->interrupt_enable = p->interrupt_enable;
833 o->enable = p->enable;
837 spin_lock_irqsave(&ir_state->rx_kfifo_lock, flags);
838 kfifo_reset(&ir_state->rx_kfifo);
839 spin_unlock_irqrestore(&ir_state->rx_kfifo_lock, flags);
840 if (p->interrupt_enable)
841 irqenable_rx(sd, IRQEN_RSE | IRQEN_RTE | IRQEN_ROE);
842 control_rx_enable(c, p->enable);
845 mutex_unlock(&ir_state->rx_params_lock);
850 static int cx25840_ir_tx_write(struct v4l2_subdev *sd, u8 *buf, size_t count,
853 struct cx25840_ir_state *ir_state = to_ir_state(sd);
855 if (ir_state == NULL)
860 * FIXME - the code below is an incomplete and untested sketch of what
861 * may need to be done. The critical part is to get 4 (or 8) pulses
862 * from the tx_kfifo, or converted from ns to the proper units from the
863 * input, and push them off to the hardware Tx FIFO right away, if the
864 * HW TX fifo needs service. The rest can be pushed to the tx_kfifo in
865 * a less critical timeframe. Also watch out for overruning the
866 * tx_kfifo - don't let it happen and let the caller know not all his
867 * pulses were written.
869 u32 *ns_pulse = (u32 *) buf;
871 u32 fifo_pulse[FIFO_TX_DEPTH];
874 /* Compute how much we can fit in the tx kfifo */
875 n = CX25840_IR_TX_KFIFO_SIZE - kfifo_len(ir_state->tx_kfifo);
876 n = min(n, (unsigned int) count);
879 /* FIXME - turn on Tx Fifo service interrupt
880 * check hardware fifo level, and other stuff
882 for (i = 0; i < n; ) {
883 for (j = 0; j < FIFO_TX_DEPTH / 2 && i < n; j++) {
884 mark = ns_pulse[i] & LEVEL_MASK;
885 fifo_pulse[j] = ns_to_pulse_width_count(
888 ir_state->txclk_divider);
890 fifo_pulse[j] &= FIFO_RXTX_LVL;
893 kfifo_put(ir_state->tx_kfifo, (u8 *) fifo_pulse,
896 *num = n * sizeof(u32);
898 /* For now enable the Tx FIFO Service interrupt & pretend we did work */
899 irqenable_tx(sd, IRQEN_TSE);
905 static int cx25840_ir_tx_g_parameters(struct v4l2_subdev *sd,
906 struct v4l2_subdev_ir_parameters *p)
908 struct cx25840_ir_state *ir_state = to_ir_state(sd);
910 if (ir_state == NULL)
913 mutex_lock(&ir_state->tx_params_lock);
914 memcpy(p, &ir_state->tx_params,
915 sizeof(struct v4l2_subdev_ir_parameters));
916 mutex_unlock(&ir_state->tx_params_lock);
920 static int cx25840_ir_tx_shutdown(struct v4l2_subdev *sd)
922 struct cx25840_ir_state *ir_state = to_ir_state(sd);
923 struct i2c_client *c;
925 if (ir_state == NULL)
929 mutex_lock(&ir_state->tx_params_lock);
931 /* Disable or slow down all IR Tx circuits and counters */
933 control_tx_enable(c, false);
934 control_tx_modulation_enable(c, false);
935 cx25840_write4(c, CX25840_IR_TXCLK_REG, TXCLK_TCD);
937 ir_state->tx_params.shutdown = true;
939 mutex_unlock(&ir_state->tx_params_lock);
943 static int cx25840_ir_tx_s_parameters(struct v4l2_subdev *sd,
944 struct v4l2_subdev_ir_parameters *p)
946 struct cx25840_ir_state *ir_state = to_ir_state(sd);
947 struct i2c_client *c;
948 struct v4l2_subdev_ir_parameters *o;
951 if (ir_state == NULL)
955 return cx25840_ir_tx_shutdown(sd);
957 if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH)
961 o = &ir_state->tx_params;
962 mutex_lock(&ir_state->tx_params_lock);
964 o->shutdown = p->shutdown;
966 p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH;
969 p->bytes_per_data_element = sizeof(union cx25840_ir_fifo_rec);
970 o->bytes_per_data_element = p->bytes_per_data_element;
972 /* Before we tweak the hardware, we have to disable the transmitter */
974 control_tx_enable(c, false);
976 control_tx_modulation_enable(c, p->modulation);
977 o->modulation = p->modulation;
980 p->carrier_freq = txclk_tx_s_carrier(c, p->carrier_freq,
982 o->carrier_freq = p->carrier_freq;
984 p->duty_cycle = cduty_tx_s_duty_cycle(c, p->duty_cycle);
985 o->duty_cycle = p->duty_cycle;
988 (u32) pulse_width_count_to_ns(FIFO_RXTX, txclk_divider);
991 txclk_tx_s_max_pulse_width(c, p->max_pulse_width,
994 o->max_pulse_width = p->max_pulse_width;
995 atomic_set(&ir_state->txclk_divider, txclk_divider);
997 p->resolution = clock_divider_to_resolution(txclk_divider);
998 o->resolution = p->resolution;
1000 /* FIXME - make this dependent on resolution for better performance */
1001 control_tx_irq_watermark(c, TX_FIFO_HALF_EMPTY);
1003 control_tx_polarity_invert(c, p->invert_carrier_sense);
1004 o->invert_carrier_sense = p->invert_carrier_sense;
1007 * FIXME: we don't have hardware help for IO pin level inversion
1008 * here like we have on the CX23888.
1009 * Act on this with some mix of logical inversion of data levels,
1010 * carrier polarity, and carrier duty cycle.
1012 o->invert_level = p->invert_level;
1014 o->interrupt_enable = p->interrupt_enable;
1015 o->enable = p->enable;
1017 /* reset tx_fifo here */
1018 if (p->interrupt_enable)
1019 irqenable_tx(sd, IRQEN_TSE);
1020 control_tx_enable(c, p->enable);
1023 mutex_unlock(&ir_state->tx_params_lock);
1029 * V4L2 Subdevice Core Ops support
1031 int cx25840_ir_log_status(struct v4l2_subdev *sd)
1033 struct cx25840_state *state = to_state(sd);
1034 struct i2c_client *c = state->c;
1037 u32 cntrl, txclk, rxclk, cduty, stats, irqen, filtr;
1039 /* The CX23888 chip doesn't have an IR controller on the A/V core */
1040 if (is_cx23888(state))
1043 cntrl = cx25840_read4(c, CX25840_IR_CNTRL_REG);
1044 txclk = cx25840_read4(c, CX25840_IR_TXCLK_REG) & TXCLK_TCD;
1045 rxclk = cx25840_read4(c, CX25840_IR_RXCLK_REG) & RXCLK_RCD;
1046 cduty = cx25840_read4(c, CX25840_IR_CDUTY_REG) & CDUTY_CDC;
1047 stats = cx25840_read4(c, CX25840_IR_STATS_REG);
1048 irqen = cx25840_read4(c, CX25840_IR_IRQEN_REG);
1049 if (is_cx23885(state) || is_cx23887(state))
1051 filtr = cx25840_read4(c, CX25840_IR_FILTR_REG) & FILTR_LPF;
1053 v4l2_info(sd, "IR Receiver:\n");
1054 v4l2_info(sd, "\tEnabled: %s\n",
1055 cntrl & CNTRL_RXE ? "yes" : "no");
1056 v4l2_info(sd, "\tDemodulation from a carrier: %s\n",
1057 cntrl & CNTRL_DMD ? "enabled" : "disabled");
1058 v4l2_info(sd, "\tFIFO: %s\n",
1059 cntrl & CNTRL_RFE ? "enabled" : "disabled");
1060 switch (cntrl & CNTRL_EDG) {
1061 case CNTRL_EDG_NONE:
1064 case CNTRL_EDG_FALL:
1067 case CNTRL_EDG_RISE:
1070 case CNTRL_EDG_BOTH:
1071 s = "rising & falling edges";
1077 v4l2_info(sd, "\tPulse timers' start/stop trigger: %s\n", s);
1078 v4l2_info(sd, "\tFIFO data on pulse timer overflow: %s\n",
1079 cntrl & CNTRL_R ? "not loaded" : "overflow marker");
1080 v4l2_info(sd, "\tFIFO interrupt watermark: %s\n",
1081 cntrl & CNTRL_RIC ? "not empty" : "half full or greater");
1082 v4l2_info(sd, "\tLoopback mode: %s\n",
1083 cntrl & CNTRL_LBM ? "loopback active" : "normal receive");
1084 if (cntrl & CNTRL_DMD) {
1085 v4l2_info(sd, "\tExpected carrier (16 clocks): %u Hz\n",
1086 clock_divider_to_carrier_freq(rxclk));
1087 switch (cntrl & CNTRL_WIN) {
1109 v4l2_info(sd, "\tNext carrier edge window: 16 clocks -%1d/+%1d, %u to %u Hz\n",
1111 clock_divider_to_freq(rxclk, 16 + j),
1112 clock_divider_to_freq(rxclk, 16 - i));
1114 v4l2_info(sd, "\tMax measurable pulse width: %u us, %llu ns\n",
1115 pulse_width_count_to_us(FIFO_RXTX, rxclk),
1116 pulse_width_count_to_ns(FIFO_RXTX, rxclk));
1117 v4l2_info(sd, "\tLow pass filter: %s\n",
1118 filtr ? "enabled" : "disabled");
1120 v4l2_info(sd, "\tMin acceptable pulse width (LPF): %u us, %u ns\n",
1121 lpf_count_to_us(filtr),
1122 lpf_count_to_ns(filtr));
1123 v4l2_info(sd, "\tPulse width timer timed-out: %s\n",
1124 stats & STATS_RTO ? "yes" : "no");
1125 v4l2_info(sd, "\tPulse width timer time-out intr: %s\n",
1126 irqen & IRQEN_RTE ? "enabled" : "disabled");
1127 v4l2_info(sd, "\tFIFO overrun: %s\n",
1128 stats & STATS_ROR ? "yes" : "no");
1129 v4l2_info(sd, "\tFIFO overrun interrupt: %s\n",
1130 irqen & IRQEN_ROE ? "enabled" : "disabled");
1131 v4l2_info(sd, "\tBusy: %s\n",
1132 stats & STATS_RBY ? "yes" : "no");
1133 v4l2_info(sd, "\tFIFO service requested: %s\n",
1134 stats & STATS_RSR ? "yes" : "no");
1135 v4l2_info(sd, "\tFIFO service request interrupt: %s\n",
1136 irqen & IRQEN_RSE ? "enabled" : "disabled");
1138 v4l2_info(sd, "IR Transmitter:\n");
1139 v4l2_info(sd, "\tEnabled: %s\n",
1140 cntrl & CNTRL_TXE ? "yes" : "no");
1141 v4l2_info(sd, "\tModulation onto a carrier: %s\n",
1142 cntrl & CNTRL_MOD ? "enabled" : "disabled");
1143 v4l2_info(sd, "\tFIFO: %s\n",
1144 cntrl & CNTRL_TFE ? "enabled" : "disabled");
1145 v4l2_info(sd, "\tFIFO interrupt watermark: %s\n",
1146 cntrl & CNTRL_TIC ? "not empty" : "half full or less");
1147 v4l2_info(sd, "\tCarrier polarity: %s\n",
1148 cntrl & CNTRL_CPL ? "space:burst mark:noburst"
1149 : "space:noburst mark:burst");
1150 if (cntrl & CNTRL_MOD) {
1151 v4l2_info(sd, "\tCarrier (16 clocks): %u Hz\n",
1152 clock_divider_to_carrier_freq(txclk));
1153 v4l2_info(sd, "\tCarrier duty cycle: %2u/16\n",
1156 v4l2_info(sd, "\tMax pulse width: %u us, %llu ns\n",
1157 pulse_width_count_to_us(FIFO_RXTX, txclk),
1158 pulse_width_count_to_ns(FIFO_RXTX, txclk));
1159 v4l2_info(sd, "\tBusy: %s\n",
1160 stats & STATS_TBY ? "yes" : "no");
1161 v4l2_info(sd, "\tFIFO service requested: %s\n",
1162 stats & STATS_TSR ? "yes" : "no");
1163 v4l2_info(sd, "\tFIFO service request interrupt: %s\n",
1164 irqen & IRQEN_TSE ? "enabled" : "disabled");
1170 const struct v4l2_subdev_ir_ops cx25840_ir_ops = {
1171 .rx_read = cx25840_ir_rx_read,
1172 .rx_g_parameters = cx25840_ir_rx_g_parameters,
1173 .rx_s_parameters = cx25840_ir_rx_s_parameters,
1175 .tx_write = cx25840_ir_tx_write,
1176 .tx_g_parameters = cx25840_ir_tx_g_parameters,
1177 .tx_s_parameters = cx25840_ir_tx_s_parameters,
1181 static const struct v4l2_subdev_ir_parameters default_rx_params = {
1182 .bytes_per_data_element = sizeof(union cx25840_ir_fifo_rec),
1183 .mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH,
1186 .interrupt_enable = false,
1190 .carrier_freq = 36000, /* 36 kHz - RC-5, and RC-6 carrier */
1192 /* RC-5: 666,667 ns = 1/36 kHz * 32 cycles * 1 mark * 0.75 */
1193 /* RC-6: 333,333 ns = 1/36 kHz * 16 cycles * 1 mark * 0.75 */
1194 .noise_filter_min_width = 333333, /* ns */
1195 .carrier_range_lower = 35000,
1196 .carrier_range_upper = 37000,
1197 .invert_level = false,
1200 static const struct v4l2_subdev_ir_parameters default_tx_params = {
1201 .bytes_per_data_element = sizeof(union cx25840_ir_fifo_rec),
1202 .mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH,
1205 .interrupt_enable = false,
1209 .carrier_freq = 36000, /* 36 kHz - RC-5 carrier */
1210 .duty_cycle = 25, /* 25 % - RC-5 carrier */
1211 .invert_level = false,
1212 .invert_carrier_sense = false,
1215 int cx25840_ir_probe(struct v4l2_subdev *sd)
1217 struct cx25840_state *state = to_state(sd);
1218 struct cx25840_ir_state *ir_state;
1219 struct v4l2_subdev_ir_parameters default_params;
1221 /* Only init the IR controller for the CX2388[57] AV Core for now */
1222 if (!(is_cx23885(state) || is_cx23887(state)))
1225 ir_state = devm_kzalloc(&state->c->dev, sizeof(*ir_state), GFP_KERNEL);
1226 if (ir_state == NULL)
1229 spin_lock_init(&ir_state->rx_kfifo_lock);
1230 if (kfifo_alloc(&ir_state->rx_kfifo,
1231 CX25840_IR_RX_KFIFO_SIZE, GFP_KERNEL))
1234 ir_state->c = state->c;
1235 state->ir_state = ir_state;
1237 /* Ensure no interrupts arrive yet */
1238 if (is_cx23885(state) || is_cx23887(state))
1239 cx25840_write4(ir_state->c, CX25840_IR_IRQEN_REG, IRQEN_MSK);
1241 cx25840_write4(ir_state->c, CX25840_IR_IRQEN_REG, 0);
1243 mutex_init(&ir_state->rx_params_lock);
1244 default_params = default_rx_params;
1245 v4l2_subdev_call(sd, ir, rx_s_parameters, &default_params);
1247 mutex_init(&ir_state->tx_params_lock);
1248 default_params = default_tx_params;
1249 v4l2_subdev_call(sd, ir, tx_s_parameters, &default_params);
1254 int cx25840_ir_remove(struct v4l2_subdev *sd)
1256 struct cx25840_state *state = to_state(sd);
1257 struct cx25840_ir_state *ir_state = to_ir_state(sd);
1259 if (ir_state == NULL)
1262 cx25840_ir_rx_shutdown(sd);
1263 cx25840_ir_tx_shutdown(sd);
1265 kfifo_free(&ir_state->rx_kfifo);
1266 state->ir_state = NULL;