1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Driver for ST STV0367 DVB-T & DVB-C demodulator IC.
7 * Copyright (C) ST Microelectronics.
8 * Copyright (C) 2010,2011 NetUP Inc.
9 * Copyright (C) 2010,2011 Igor M. Liplianin <liplianin@netup.ru>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/string.h>
15 #include <linux/slab.h>
16 #include <linux/i2c.h>
18 #include <linux/int_log.h>
21 #include "stv0367_defs.h"
22 #include "stv0367_regs.h"
23 #include "stv0367_priv.h"
25 /* Max transfer size done by I2C transfer functions */
26 #define MAX_XFER_SIZE 64
29 module_param_named(debug, stvdebug, int, 0644);
32 module_param_named(i2c_debug, i2cdebug, int, 0644);
34 #define dprintk(args...) \
37 printk(KERN_DEBUG args); \
41 enum active_demod_state { demod_none, demod_ter, demod_cab };
43 struct stv0367cab_state {
44 enum stv0367_cab_signal_type state;
50 int locked; /* channel found */
51 u32 freq_khz; /* found frequency (in kHz) */
52 u32 symbol_rate; /* found symbol rate (in Bds) */
53 enum fe_spectral_inversion spect_inv; /* Spectrum Inversion */
54 u32 qamfec_status_reg; /* status reg to poll for FEC Lock */
57 struct stv0367ter_state {
59 enum stv0367_ter_signal_type state;
60 enum stv0367_ter_if_iq_mode if_iq_mode;
61 enum stv0367_ter_mode mode;/* mode 2K or 8K */
62 enum fe_guard_interval guard;
63 enum stv0367_ter_hierarchy hierarchy;
65 enum fe_spectral_inversion sense; /* current search spectrum */
66 u8 force; /* force mode/guard */
67 u8 bw; /* channel width 6, 7 or 8 in MHz */
68 u8 pBW; /* channel width used during previous lock */
72 s8 echo_pos; /* echo position */
78 struct stv0367_state {
79 struct dvb_frontend fe;
80 struct i2c_adapter *i2c;
82 const struct stv0367_config *config;
85 struct stv0367cab_state *cab_state;
87 struct stv0367ter_state *ter_state;
88 /* flags for operation control */
91 u8 reinit_on_setfrontend;
93 enum active_demod_state activedemod;
96 #define RF_LOOKUP_TABLE_SIZE 31
97 #define RF_LOOKUP_TABLE2_SIZE 16
98 /* RF Level (for RF AGC->AGC1) Lookup Table, depends on the board and tuner.*/
99 static const s32 stv0367cab_RF_LookUp1[RF_LOOKUP_TABLE_SIZE][RF_LOOKUP_TABLE_SIZE] = {
101 48, 50, 51, 53, 54, 56, 57, 58, 60, 61, 62, 63,
102 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,
103 76, 77, 78, 80, 83, 85, 88,
105 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
106 34, 35, 36, 37, 38, 39, 41, 42, 43, 44, 46, 47,
107 49, 50, 52, 53, 54, 55, 56,
110 /* RF Level (for IF AGC->AGC2) Lookup Table, depends on the board and tuner.*/
111 static const s32 stv0367cab_RF_LookUp2[RF_LOOKUP_TABLE2_SIZE][RF_LOOKUP_TABLE2_SIZE] = {
113 28, 29, 31, 32, 34, 35, 36, 37,
114 38, 39, 40, 41, 42, 43, 44, 45,
116 57, 58, 59, 60, 61, 62, 63, 64,
117 65, 66, 67, 68, 69, 70, 71, 72,
122 int stv0367_writeregs(struct stv0367_state *state, u16 reg, u8 *data, int len)
124 u8 buf[MAX_XFER_SIZE];
125 struct i2c_msg msg = {
126 .addr = state->config->demod_address,
133 if (2 + len > sizeof(buf)) {
135 "%s: i2c wr reg=%04x: len=%d is too big!\n",
136 KBUILD_MODNAME, reg, len);
143 memcpy(buf + 2, data, len);
146 printk(KERN_DEBUG "%s: [%02x] %02x: %02x\n", __func__,
147 state->config->demod_address, reg, buf[2]);
149 ret = i2c_transfer(state->i2c, &msg, 1);
151 printk(KERN_ERR "%s: i2c write error! ([%02x] %02x: %02x)\n",
152 __func__, state->config->demod_address, reg, buf[2]);
154 return (ret != 1) ? -EREMOTEIO : 0;
157 static int stv0367_writereg(struct stv0367_state *state, u16 reg, u8 data)
159 u8 tmp = data; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
161 return stv0367_writeregs(state, reg, &tmp, 1);
164 static u8 stv0367_readreg(struct stv0367_state *state, u16 reg)
168 struct i2c_msg msg[] = {
170 .addr = state->config->demod_address,
175 .addr = state->config->demod_address,
186 ret = i2c_transfer(state->i2c, msg, 2);
188 printk(KERN_ERR "%s: i2c read error ([%02x] %02x: %02x)\n",
189 __func__, state->config->demod_address, reg, b1[0]);
192 printk(KERN_DEBUG "%s: [%02x] %02x: %02x\n", __func__,
193 state->config->demod_address, reg, b1[0]);
198 static void extract_mask_pos(u32 label, u8 *mask, u8 *pos)
200 u8 position = 0, i = 0;
202 (*mask) = label & 0xff;
204 while ((position == 0) && (i < 8)) {
205 position = ((*mask) >> i) & 0x01;
212 static void stv0367_writebits(struct stv0367_state *state, u32 label, u8 val)
216 reg = stv0367_readreg(state, (label >> 16) & 0xffff);
217 extract_mask_pos(label, &mask, &pos);
219 val = mask & (val << pos);
221 reg = (reg & (~mask)) | val;
222 stv0367_writereg(state, (label >> 16) & 0xffff, reg);
226 static void stv0367_setbits(u8 *reg, u32 label, u8 val)
230 extract_mask_pos(label, &mask, &pos);
232 val = mask & (val << pos);
234 (*reg) = ((*reg) & (~mask)) | val;
237 static u8 stv0367_readbits(struct stv0367_state *state, u32 label)
242 extract_mask_pos(label, &mask, &pos);
244 val = stv0367_readreg(state, label >> 16);
245 val = (val & mask) >> pos;
250 #if 0 /* Currently, unused */
251 static u8 stv0367_getbits(u8 reg, u32 label)
255 extract_mask_pos(label, &mask, &pos);
257 return (reg & mask) >> pos;
261 static void stv0367_write_table(struct stv0367_state *state,
262 const struct st_register *deftab)
269 stv0367_writereg(state, deftab[i].addr, deftab[i].value);
274 static void stv0367_pll_setup(struct stv0367_state *state,
275 u32 icspeed, u32 xtal)
277 /* note on regs: R367TER_* and R367CAB_* defines each point to
278 * 0xf0d8, so just use R367TER_ for both cases
282 case STV0367_ICSPEED_58000:
286 dprintk("STV0367 SetCLKgen for 58MHz IC and 27Mhz crystal\n");
287 /* PLLMDIV: 27, PLLNDIV: 232 */
288 stv0367_writereg(state, R367TER_PLLMDIV, 0x1b);
289 stv0367_writereg(state, R367TER_PLLNDIV, 0xe8);
294 case STV0367_ICSPEED_53125:
296 /* set internal freq to 53.125MHz */
298 stv0367_writereg(state, R367TER_PLLMDIV, 0x2);
299 stv0367_writereg(state, R367TER_PLLNDIV, 0x1b);
302 stv0367_writereg(state, R367TER_PLLMDIV, 0xa);
303 stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
307 dprintk("FE_STV0367TER_SetCLKgen for 27Mhz\n");
308 stv0367_writereg(state, R367TER_PLLMDIV, 0x1);
309 stv0367_writereg(state, R367TER_PLLNDIV, 0x8);
312 stv0367_writereg(state, R367TER_PLLMDIV, 0xc);
313 stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
318 stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
321 static int stv0367_get_if_khz(struct stv0367_state *state, u32 *ifkhz)
323 if (state->auto_if_khz && state->fe.ops.tuner_ops.get_if_frequency) {
324 state->fe.ops.tuner_ops.get_if_frequency(&state->fe, ifkhz);
325 *ifkhz = *ifkhz / 1000; /* hz -> khz */
327 *ifkhz = state->config->if_khz;
332 static int stv0367ter_gate_ctrl(struct dvb_frontend *fe, int enable)
334 struct stv0367_state *state = fe->demodulator_priv;
335 u8 tmp = stv0367_readreg(state, R367TER_I2CRPT);
337 dprintk("%s:\n", __func__);
340 stv0367_setbits(&tmp, F367TER_STOP_ENABLE, 0);
341 stv0367_setbits(&tmp, F367TER_I2CT_ON, 1);
343 stv0367_setbits(&tmp, F367TER_STOP_ENABLE, 1);
344 stv0367_setbits(&tmp, F367TER_I2CT_ON, 0);
347 stv0367_writereg(state, R367TER_I2CRPT, tmp);
352 static u32 stv0367_get_tuner_freq(struct dvb_frontend *fe)
354 struct dvb_frontend_ops *frontend_ops = &fe->ops;
355 struct dvb_tuner_ops *tuner_ops = &frontend_ops->tuner_ops;
359 dprintk("%s:\n", __func__);
361 if (tuner_ops->get_frequency) {
362 err = tuner_ops->get_frequency(fe, &freq);
364 printk(KERN_ERR "%s: Invalid parameter\n", __func__);
368 dprintk("%s: frequency=%d\n", __func__, freq);
376 static u16 CellsCoeffs_8MHz_367cofdm[3][6][5] = {
378 {0x10EF, 0xE205, 0x10EF, 0xCE49, 0x6DA7}, /* CELL 1 COEFFS 27M*/
379 {0x2151, 0xc557, 0x2151, 0xc705, 0x6f93}, /* CELL 2 COEFFS */
380 {0x2503, 0xc000, 0x2503, 0xc375, 0x7194}, /* CELL 3 COEFFS */
381 {0x20E9, 0xca94, 0x20e9, 0xc153, 0x7194}, /* CELL 4 COEFFS */
382 {0x06EF, 0xF852, 0x06EF, 0xC057, 0x7207}, /* CELL 5 COEFFS */
383 {0x0000, 0x0ECC, 0x0ECC, 0x0000, 0x3647} /* CELL 6 COEFFS */
385 {0x10A0, 0xE2AF, 0x10A1, 0xCE76, 0x6D6D}, /* CELL 1 COEFFS 25M*/
386 {0x20DC, 0xC676, 0x20D9, 0xC80A, 0x6F29},
387 {0x2532, 0xC000, 0x251D, 0xC391, 0x706F},
388 {0x1F7A, 0xCD2B, 0x2032, 0xC15E, 0x711F},
389 {0x0698, 0xFA5E, 0x0568, 0xC059, 0x7193},
390 {0x0000, 0x0918, 0x149C, 0x0000, 0x3642} /* CELL 6 COEFFS */
392 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
393 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
394 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
395 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
396 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
397 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
401 static u16 CellsCoeffs_7MHz_367cofdm[3][6][5] = {
403 {0x12CA, 0xDDAF, 0x12CA, 0xCCEB, 0x6FB1}, /* CELL 1 COEFFS 27M*/
404 {0x2329, 0xC000, 0x2329, 0xC6B0, 0x725F}, /* CELL 2 COEFFS */
405 {0x2394, 0xC000, 0x2394, 0xC2C7, 0x7410}, /* CELL 3 COEFFS */
406 {0x251C, 0xC000, 0x251C, 0xC103, 0x74D9}, /* CELL 4 COEFFS */
407 {0x0804, 0xF546, 0x0804, 0xC040, 0x7544}, /* CELL 5 COEFFS */
408 {0x0000, 0x0CD9, 0x0CD9, 0x0000, 0x370A} /* CELL 6 COEFFS */
410 {0x1285, 0xDE47, 0x1285, 0xCD17, 0x6F76}, /*25M*/
411 {0x234C, 0xC000, 0x2348, 0xC6DA, 0x7206},
412 {0x23B4, 0xC000, 0x23AC, 0xC2DB, 0x73B3},
413 {0x253D, 0xC000, 0x25B6, 0xC10B, 0x747F},
414 {0x0721, 0xF79C, 0x065F, 0xC041, 0x74EB},
415 {0x0000, 0x08FA, 0x1162, 0x0000, 0x36FF}
417 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
418 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
419 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
420 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
421 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
422 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
426 static u16 CellsCoeffs_6MHz_367cofdm[3][6][5] = {
428 {0x1699, 0xD5B8, 0x1699, 0xCBC3, 0x713B}, /* CELL 1 COEFFS 27M*/
429 {0x2245, 0xC000, 0x2245, 0xC568, 0x74D5}, /* CELL 2 COEFFS */
430 {0x227F, 0xC000, 0x227F, 0xC1FC, 0x76C6}, /* CELL 3 COEFFS */
431 {0x235E, 0xC000, 0x235E, 0xC0A7, 0x778A}, /* CELL 4 COEFFS */
432 {0x0ECB, 0xEA0B, 0x0ECB, 0xC027, 0x77DD}, /* CELL 5 COEFFS */
433 {0x0000, 0x0B68, 0x0B68, 0x0000, 0xC89A}, /* CELL 6 COEFFS */
435 {0x1655, 0xD64E, 0x1658, 0xCBEF, 0x70FE}, /*25M*/
436 {0x225E, 0xC000, 0x2256, 0xC589, 0x7489},
437 {0x2293, 0xC000, 0x2295, 0xC209, 0x767E},
438 {0x2377, 0xC000, 0x23AA, 0xC0AB, 0x7746},
439 {0x0DC7, 0xEBC8, 0x0D07, 0xC027, 0x7799},
440 {0x0000, 0x0888, 0x0E9C, 0x0000, 0x3757}
443 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}, /* 30M */
444 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
445 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
446 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
447 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000},
448 {0x0000, 0x0000, 0x0000, 0x0000, 0x0000}
452 static u32 stv0367ter_get_mclk(struct stv0367_state *state, u32 ExtClk_Hz)
454 u32 mclk_Hz = 0; /* master clock frequency (Hz) */
457 dprintk("%s:\n", __func__);
459 if (stv0367_readbits(state, F367TER_BYPASS_PLLXN) == 0) {
460 n = (u32)stv0367_readbits(state, F367TER_PLL_NDIV);
464 m = (u32)stv0367_readbits(state, F367TER_PLL_MDIV);
468 p = (u32)stv0367_readbits(state, F367TER_PLL_PDIV);
472 mclk_Hz = ((ExtClk_Hz / 2) * n) / (m * (1 << p));
474 dprintk("N=%d M=%d P=%d mclk_Hz=%d ExtClk_Hz=%d\n",
475 n, m, p, mclk_Hz, ExtClk_Hz);
479 dprintk("%s: mclk_Hz=%d\n", __func__, mclk_Hz);
484 static int stv0367ter_filt_coeff_init(struct stv0367_state *state,
485 u16 CellsCoeffs[3][6][5], u32 DemodXtal)
489 dprintk("%s:\n", __func__);
491 freq = stv0367ter_get_mclk(state, DemodXtal);
493 if (freq == 53125000)
494 k = 1; /* equivalent to Xtal 25M on 362*/
495 else if (freq == 54000000)
496 k = 0; /* equivalent to Xtal 27M on 362*/
497 else if (freq == 52500000)
498 k = 2; /* equivalent to Xtal 30M on 362*/
502 for (i = 1; i <= 6; i++) {
503 stv0367_writebits(state, F367TER_IIR_CELL_NB, i - 1);
505 for (j = 1; j <= 5; j++) {
506 stv0367_writereg(state,
507 (R367TER_IIRCX_COEFF1_MSB + 2 * (j - 1)),
508 MSB(CellsCoeffs[k][i-1][j-1]));
509 stv0367_writereg(state,
510 (R367TER_IIRCX_COEFF1_LSB + 2 * (j - 1)),
511 LSB(CellsCoeffs[k][i-1][j-1]));
519 static void stv0367ter_agc_iir_lock_detect_set(struct stv0367_state *state)
521 dprintk("%s:\n", __func__);
523 stv0367_writebits(state, F367TER_LOCK_DETECT_LSB, 0x00);
526 stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x00);
527 stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06);
528 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04);
531 stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x01);
532 stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06);
533 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04);
536 stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x02);
537 stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01);
538 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00);
541 stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x03);
542 stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01);
543 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00);
547 static int stv0367_iir_filt_init(struct stv0367_state *state, u8 Bandwidth,
550 dprintk("%s:\n", __func__);
552 stv0367_writebits(state, F367TER_NRST_IIR, 0);
556 if (!stv0367ter_filt_coeff_init(state,
557 CellsCoeffs_6MHz_367cofdm,
562 if (!stv0367ter_filt_coeff_init(state,
563 CellsCoeffs_7MHz_367cofdm,
568 if (!stv0367ter_filt_coeff_init(state,
569 CellsCoeffs_8MHz_367cofdm,
577 stv0367_writebits(state, F367TER_NRST_IIR, 1);
582 static void stv0367ter_agc_iir_rst(struct stv0367_state *state)
587 dprintk("%s:\n", __func__);
589 com_n = stv0367_readbits(state, F367TER_COM_N);
591 stv0367_writebits(state, F367TER_COM_N, 0x07);
593 stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x00);
594 stv0367_writebits(state, F367TER_COM_AGC_ON, 0x00);
596 stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x01);
597 stv0367_writebits(state, F367TER_COM_AGC_ON, 0x01);
599 stv0367_writebits(state, F367TER_COM_N, com_n);
603 static int stv0367ter_duration(s32 mode, int tempo1, int tempo2, int tempo3)
608 local_tempo = tempo1;
611 local_tempo = tempo2;
615 local_tempo = tempo3;
621 /* msleep(local_tempo); */
626 stv0367_ter_signal_type stv0367ter_check_syr(struct stv0367_state *state)
629 unsigned short int SYR_var;
632 dprintk("%s:\n", __func__);
634 SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK);
636 while ((!SYR_var) && (wd > 0)) {
637 usleep_range(2000, 3000);
639 SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK);
643 SYRStatus = FE_TER_NOSYMBOL;
645 SYRStatus = FE_TER_SYMBOLOK;
647 dprintk("stv0367ter_check_syr SYRStatus %s\n",
648 SYR_var == 0 ? "No Symbol" : "OK");
654 stv0367_ter_signal_type stv0367ter_check_cpamp(struct stv0367_state *state,
658 s32 CPAMPvalue = 0, CPAMPStatus, CPAMPMin;
661 dprintk("%s:\n", __func__);
677 CPAMPMin = 0xffff; /*drives to NOCPAMP */
681 dprintk("%s: CPAMPMin=%d wd=%d\n", __func__, CPAMPMin, wd);
683 CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT);
684 while ((CPAMPvalue < CPAMPMin) && (wd > 0)) {
685 usleep_range(1000, 2000);
687 CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT);
688 /*dprintk("CPAMPvalue= %d at wd=%d\n",CPAMPvalue,wd); */
690 dprintk("******last CPAMPvalue= %d at wd=%d\n", CPAMPvalue, wd);
691 if (CPAMPvalue < CPAMPMin) {
692 CPAMPStatus = FE_TER_NOCPAMP;
693 dprintk("%s: CPAMP failed\n", __func__);
695 dprintk("%s: CPAMP OK !\n", __func__);
696 CPAMPStatus = FE_TER_CPAMPOK;
702 static enum stv0367_ter_signal_type
703 stv0367ter_lock_algo(struct stv0367_state *state)
705 enum stv0367_ter_signal_type ret_flag;
707 u8 try, u_var1 = 0, u_var2 = 0, u_var3 = 0, u_var4 = 0, mode, guard;
710 dprintk("%s:\n", __func__);
717 ret_flag = FE_TER_LOCKOK;
719 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
721 if (state->config->if_iq_mode != 0)
722 stv0367_writebits(state, F367TER_COM_N, 0x07);
724 stv0367_writebits(state, F367TER_GUARD, 3);/* suggest 2k 1/4 */
725 stv0367_writebits(state, F367TER_MODE, 0);
726 stv0367_writebits(state, F367TER_SYR_TR_DIS, 0);
727 usleep_range(5000, 10000);
729 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
732 if (stv0367ter_check_syr(state) == FE_TER_NOSYMBOL)
733 return FE_TER_NOSYMBOL;
735 if chip locked on wrong mode first try,
736 it must lock correctly second try */
737 mode = stv0367_readbits(state, F367TER_SYR_MODE);
738 if (stv0367ter_check_cpamp(state, mode) ==
741 ret_flag = FE_TER_NOCPAMP;
747 } while ((try < 10) && (ret_flag != FE_TER_LOCKOK));
749 tmp = stv0367_readreg(state, R367TER_SYR_STAT);
750 tmp2 = stv0367_readreg(state, R367TER_STATUS);
751 dprintk("state=%p\n", state);
752 dprintk("LOCK OK! mode=%d SYR_STAT=0x%x R367TER_STATUS=0x%x\n",
755 tmp = stv0367_readreg(state, R367TER_PRVIT);
756 tmp2 = stv0367_readreg(state, R367TER_I2CRPT);
757 dprintk("PRVIT=0x%x I2CRPT=0x%x\n", tmp, tmp2);
759 tmp = stv0367_readreg(state, R367TER_GAIN_SRC1);
760 dprintk("GAIN_SRC1=0x%x\n", tmp);
762 if ((mode != 0) && (mode != 1) && (mode != 2))
765 /*guard=stv0367_readbits(state,F367TER_SYR_GUARD); */
767 /*suppress EPQ auto for SYR_GARD 1/16 or 1/32
768 and set channel predictor in automatic */
774 stv0367_writebits(state, F367TER_AUTO_LE_EN, 0);
775 stv0367_writereg(state, R367TER_CHC_CTL, 0x01);
779 stv0367_writebits(state, F367TER_AUTO_LE_EN, 1);
780 stv0367_writereg(state, R367TER_CHC_CTL, 0x11);
788 /*reset fec an reedsolo FOR 367 only*/
789 stv0367_writebits(state, F367TER_RST_SFEC, 1);
790 stv0367_writebits(state, F367TER_RST_REEDSOLO, 1);
791 usleep_range(1000, 2000);
792 stv0367_writebits(state, F367TER_RST_SFEC, 0);
793 stv0367_writebits(state, F367TER_RST_REEDSOLO, 0);
795 u_var1 = stv0367_readbits(state, F367TER_LK);
796 u_var2 = stv0367_readbits(state, F367TER_PRF);
797 u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK);
798 /* u_var4=stv0367_readbits(state,F367TER_TSFIFO_LINEOK); */
800 wd = stv0367ter_duration(mode, 125, 500, 250);
801 tempo = stv0367ter_duration(mode, 4, 16, 8);
803 /*while ( ((!u_var1)||(!u_var2)||(!u_var3)||(!u_var4)) && (wd>=0)) */
804 while (((!u_var1) || (!u_var2) || (!u_var3)) && (wd >= 0)) {
805 usleep_range(1000 * tempo, 1000 * (tempo + 1));
807 u_var1 = stv0367_readbits(state, F367TER_LK);
808 u_var2 = stv0367_readbits(state, F367TER_PRF);
809 u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK);
810 /*u_var4=stv0367_readbits(state, F367TER_TSFIFO_LINEOK); */
814 return FE_TER_NOLOCK;
818 return FE_TER_NOPRFOUND;
823 guard = stv0367_readbits(state, F367TER_SYR_GUARD);
824 stv0367_writereg(state, R367TER_CHC_CTL, 0x11);
828 stv0367_writebits(state, F367TER_AUTO_LE_EN, 0);
829 /*stv0367_writereg(state,R367TER_CHC_CTL, 0x1);*/
830 stv0367_writebits(state, F367TER_SYR_FILTER, 0);
834 stv0367_writebits(state, F367TER_AUTO_LE_EN, 1);
835 /*stv0367_writereg(state,R367TER_CHC_CTL, 0x11);*/
836 stv0367_writebits(state, F367TER_SYR_FILTER, 1);
843 /* apply Sfec workaround if 8K 64QAM CR!=1/2*/
844 if ((stv0367_readbits(state, F367TER_TPS_CONST) == 2) &&
846 (stv0367_readbits(state, F367TER_TPS_HPCODE) != 0)) {
847 stv0367_writereg(state, R367TER_SFDLYSETH, 0xc0);
848 stv0367_writereg(state, R367TER_SFDLYSETM, 0x60);
849 stv0367_writereg(state, R367TER_SFDLYSETL, 0x0);
851 stv0367_writereg(state, R367TER_SFDLYSETH, 0x0);
853 wd = stv0367ter_duration(mode, 125, 500, 250);
854 u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK);
856 while ((!u_var4) && (wd >= 0)) {
857 usleep_range(1000 * tempo, 1000 * (tempo + 1));
859 u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK);
863 return FE_TER_NOLOCK;
865 /* for 367 leave COM_N at 0x7 for IQ_mode*/
866 /*if(ter_state->if_iq_mode!=FE_TER_NORMAL_IF_TUNER) {
868 while ((stv0367_readbits(state,F367TER_COM_USEGAINTRK)!=1) &&
869 (stv0367_readbits(state,F367TER_COM_AGCLOCK)!=1)&&(tempo<100)) {
870 ChipWaitOrAbort(state,1);
874 stv0367_writebits(state,F367TER_COM_N,0x17);
877 stv0367_writebits(state, F367TER_SYR_TR_DIS, 1);
879 dprintk("FE_TER_LOCKOK !!!\n");
881 return FE_TER_LOCKOK;
885 static void stv0367ter_set_ts_mode(struct stv0367_state *state,
886 enum stv0367_ts_mode PathTS)
889 dprintk("%s:\n", __func__);
894 stv0367_writebits(state, F367TER_TS_DIS, 0);
897 /*for removing warning :default we can assume in parallel mode*/
898 case STV0367_PARALLEL_PUNCT_CLOCK:
899 stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 0);
900 stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 0);
902 case STV0367_SERIAL_PUNCT_CLOCK:
903 stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 1);
904 stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 1);
909 static void stv0367ter_set_clk_pol(struct stv0367_state *state,
910 enum stv0367_clk_pol clock)
913 dprintk("%s:\n", __func__);
919 case STV0367_RISINGEDGE_CLOCK:
920 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 1);
922 case STV0367_FALLINGEDGE_CLOCK:
923 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0);
925 /*case FE_TER_CLOCK_POLARITY_DEFAULT:*/
927 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0);
933 static void stv0367ter_core_sw(struct stv0367_state *state)
936 dprintk("%s:\n", __func__);
938 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
939 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
943 static int stv0367ter_standby(struct dvb_frontend *fe, u8 standby_on)
945 struct stv0367_state *state = fe->demodulator_priv;
947 dprintk("%s:\n", __func__);
950 stv0367_writebits(state, F367TER_STDBY, 1);
951 stv0367_writebits(state, F367TER_STDBY_FEC, 1);
952 stv0367_writebits(state, F367TER_STDBY_CORE, 1);
954 stv0367_writebits(state, F367TER_STDBY, 0);
955 stv0367_writebits(state, F367TER_STDBY_FEC, 0);
956 stv0367_writebits(state, F367TER_STDBY_CORE, 0);
962 static int stv0367ter_sleep(struct dvb_frontend *fe)
964 return stv0367ter_standby(fe, 1);
967 static int stv0367ter_init(struct dvb_frontend *fe)
969 struct stv0367_state *state = fe->demodulator_priv;
970 struct stv0367ter_state *ter_state = state->ter_state;
972 dprintk("%s:\n", __func__);
976 stv0367_write_table(state,
977 stv0367_deftabs[state->deftabs][STV0367_TAB_TER]);
979 stv0367_pll_setup(state, STV0367_ICSPEED_53125, state->config->xtal);
981 stv0367_writereg(state, R367TER_I2CRPT, 0xa0);
982 stv0367_writereg(state, R367TER_ANACTRL, 0x00);
984 /*Set TS1 and TS2 to serial or parallel mode */
985 stv0367ter_set_ts_mode(state, state->config->ts_mode);
986 stv0367ter_set_clk_pol(state, state->config->clk_pol);
988 state->chip_id = stv0367_readreg(state, R367TER_ID);
989 ter_state->first_lock = 0;
990 ter_state->unlock_counter = 2;
995 static int stv0367ter_algo(struct dvb_frontend *fe)
997 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
998 struct stv0367_state *state = fe->demodulator_priv;
999 struct stv0367ter_state *ter_state = state->ter_state;
1000 int offset = 0, tempo = 0;
1002 u8 /*constell,*/ counter;
1004 s32 timing_offset = 0;
1005 u32 trl_nomrate = 0, InternalFreq = 0, temp = 0, ifkhz = 0;
1007 dprintk("%s:\n", __func__);
1009 stv0367_get_if_khz(state, &ifkhz);
1011 ter_state->frequency = p->frequency;
1012 ter_state->force = FE_TER_FORCENONE
1013 + stv0367_readbits(state, F367TER_FORCE) * 2;
1014 ter_state->if_iq_mode = state->config->if_iq_mode;
1015 switch (state->config->if_iq_mode) {
1016 case FE_TER_NORMAL_IF_TUNER: /* Normal IF mode */
1017 dprintk("ALGO: FE_TER_NORMAL_IF_TUNER selected\n");
1018 stv0367_writebits(state, F367TER_TUNER_BB, 0);
1019 stv0367_writebits(state, F367TER_LONGPATH_IF, 0);
1020 stv0367_writebits(state, F367TER_DEMUX_SWAP, 0);
1022 case FE_TER_LONGPATH_IF_TUNER: /* Long IF mode */
1023 dprintk("ALGO: FE_TER_LONGPATH_IF_TUNER selected\n");
1024 stv0367_writebits(state, F367TER_TUNER_BB, 0);
1025 stv0367_writebits(state, F367TER_LONGPATH_IF, 1);
1026 stv0367_writebits(state, F367TER_DEMUX_SWAP, 1);
1028 case FE_TER_IQ_TUNER: /* IQ mode */
1029 dprintk("ALGO: FE_TER_IQ_TUNER selected\n");
1030 stv0367_writebits(state, F367TER_TUNER_BB, 1);
1031 stv0367_writebits(state, F367TER_PPM_INVSEL, 0);
1034 printk(KERN_ERR "ALGO: wrong TUNER type selected\n");
1038 usleep_range(5000, 7000);
1040 switch (p->inversion) {
1041 case INVERSION_AUTO:
1043 dprintk("%s: inversion AUTO\n", __func__);
1044 if (ter_state->if_iq_mode == FE_TER_IQ_TUNER)
1045 stv0367_writebits(state, F367TER_IQ_INVERT,
1048 stv0367_writebits(state, F367TER_INV_SPECTR,
1054 if (ter_state->if_iq_mode == FE_TER_IQ_TUNER)
1055 stv0367_writebits(state, F367TER_IQ_INVERT,
1058 stv0367_writebits(state, F367TER_INV_SPECTR,
1064 if ((ter_state->if_iq_mode != FE_TER_NORMAL_IF_TUNER) &&
1065 (ter_state->pBW != ter_state->bw)) {
1066 stv0367ter_agc_iir_lock_detect_set(state);
1068 /*set fine agc target to 180 for LPIF or IQ mode*/
1069 /* set Q_AGCTarget */
1070 stv0367_writebits(state, F367TER_SEL_IQNTAR, 1);
1071 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB);
1072 /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */
1074 /* set Q_AGCTarget */
1075 stv0367_writebits(state, F367TER_SEL_IQNTAR, 0);
1076 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB);
1077 /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */
1079 if (!stv0367_iir_filt_init(state, ter_state->bw,
1080 state->config->xtal))
1082 /*set IIR filter once for 6,7 or 8MHz BW*/
1083 ter_state->pBW = ter_state->bw;
1085 stv0367ter_agc_iir_rst(state);
1088 if (ter_state->hierarchy == FE_TER_HIER_LOW_PRIO)
1089 stv0367_writebits(state, F367TER_BDI_LPSEL, 0x01);
1091 stv0367_writebits(state, F367TER_BDI_LPSEL, 0x00);
1093 InternalFreq = stv0367ter_get_mclk(state, state->config->xtal) / 1000;
1095 ((((ter_state->bw * 64 * (1 << 15) * 100)
1096 / (InternalFreq)) * 10) / 7);
1098 stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB, temp % 2);
1100 stv0367_writebits(state, F367TER_TRL_NOMRATE_HI, temp / 256);
1101 stv0367_writebits(state, F367TER_TRL_NOMRATE_LO, temp % 256);
1103 temp = stv0367_readbits(state, F367TER_TRL_NOMRATE_HI) * 512 +
1104 stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2 +
1105 stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB);
1106 temp = (int)(((1 << 17) * ter_state->bw * 1000) / (7 * (InternalFreq)));
1107 stv0367_writebits(state, F367TER_GAIN_SRC_HI, temp / 256);
1108 stv0367_writebits(state, F367TER_GAIN_SRC_LO, temp % 256);
1109 temp = stv0367_readbits(state, F367TER_GAIN_SRC_HI) * 256 +
1110 stv0367_readbits(state, F367TER_GAIN_SRC_LO);
1113 ((InternalFreq - ifkhz) * (1 << 16) / (InternalFreq));
1115 dprintk("DEROT temp=0x%x\n", temp);
1116 stv0367_writebits(state, F367TER_INC_DEROT_HI, temp / 256);
1117 stv0367_writebits(state, F367TER_INC_DEROT_LO, temp % 256);
1119 ter_state->echo_pos = 0;
1120 ter_state->ucblocks = 0; /* liplianin */
1121 ter_state->pBER = 0; /* liplianin */
1122 stv0367_writebits(state, F367TER_LONG_ECHO, ter_state->echo_pos);
1124 if (stv0367ter_lock_algo(state) != FE_TER_LOCKOK)
1127 ter_state->state = FE_TER_LOCKOK;
1129 ter_state->mode = stv0367_readbits(state, F367TER_SYR_MODE);
1130 ter_state->guard = stv0367_readbits(state, F367TER_SYR_GUARD);
1132 ter_state->first_lock = 1; /* we know sense now :) */
1134 ter_state->agc_val =
1135 (stv0367_readbits(state, F367TER_AGC1_VAL_LO) << 16) +
1136 (stv0367_readbits(state, F367TER_AGC1_VAL_HI) << 24) +
1137 stv0367_readbits(state, F367TER_AGC2_VAL_LO) +
1138 (stv0367_readbits(state, F367TER_AGC2_VAL_HI) << 8);
1140 /* Carrier offset calculation */
1141 stv0367_writebits(state, F367TER_FREEZE, 1);
1142 offset = (stv0367_readbits(state, F367TER_CRL_FOFFSET_VHI) << 16) ;
1143 offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_HI) << 8);
1144 offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_LO));
1145 stv0367_writebits(state, F367TER_FREEZE, 0);
1146 if (offset > 8388607)
1149 offset = offset * 2 / 16384;
1151 if (ter_state->mode == FE_TER_MODE_2K)
1152 offset = (offset * 4464) / 1000;/*** 1 FFT BIN=4.464khz***/
1153 else if (ter_state->mode == FE_TER_MODE_4K)
1154 offset = (offset * 223) / 100;/*** 1 FFT BIN=2.23khz***/
1155 else if (ter_state->mode == FE_TER_MODE_8K)
1156 offset = (offset * 111) / 100;/*** 1 FFT BIN=1.1khz***/
1158 if (stv0367_readbits(state, F367TER_PPM_INVSEL) == 1) {
1159 if ((stv0367_readbits(state, F367TER_INV_SPECTR) ==
1160 (stv0367_readbits(state,
1161 F367TER_STATUS_INV_SPECRUM) == 1)))
1162 offset = offset * -1;
1165 if (ter_state->bw == 6)
1166 offset = (offset * 6) / 8;
1167 else if (ter_state->bw == 7)
1168 offset = (offset * 7) / 8;
1170 ter_state->frequency += offset;
1172 tempo = 10; /* exit even if timing_offset stays null */
1173 while ((timing_offset == 0) && (tempo > 0)) {
1174 usleep_range(10000, 20000); /*was 20ms */
1175 /* fine tuning of timing offset if required */
1176 timing_offset = stv0367_readbits(state, F367TER_TRL_TOFFSET_LO)
1177 + 256 * stv0367_readbits(state,
1178 F367TER_TRL_TOFFSET_HI);
1179 if (timing_offset >= 32768)
1180 timing_offset -= 65536;
1181 trl_nomrate = (512 * stv0367_readbits(state,
1182 F367TER_TRL_NOMRATE_HI)
1183 + stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2
1184 + stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB));
1186 timing_offset = ((signed)(1000000 / trl_nomrate) *
1187 timing_offset) / 2048;
1191 if (timing_offset <= 0) {
1192 timing_offset = (timing_offset - 11) / 22;
1195 timing_offset = (timing_offset + 11) / 22;
1199 for (counter = 0; counter < abs(timing_offset); counter++) {
1200 trl_nomrate += step;
1201 stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB,
1203 stv0367_writebits(state, F367TER_TRL_NOMRATE_LO,
1205 usleep_range(1000, 2000);
1208 usleep_range(5000, 6000);
1209 /* unlocks could happen in case of trl centring big step,
1210 then a core off/on restarts demod */
1211 u_var = stv0367_readbits(state, F367TER_LK);
1214 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
1216 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
1222 static int stv0367ter_set_frontend(struct dvb_frontend *fe)
1224 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1225 struct stv0367_state *state = fe->demodulator_priv;
1226 struct stv0367ter_state *ter_state = state->ter_state;
1229 s8 num_trials, index;
1230 u8 SenseTrials[] = { INVERSION_ON, INVERSION_OFF };
1232 if (state->reinit_on_setfrontend)
1233 stv0367ter_init(fe);
1235 if (fe->ops.tuner_ops.set_params) {
1236 if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl)
1237 fe->ops.i2c_gate_ctrl(fe, 1);
1238 fe->ops.tuner_ops.set_params(fe);
1239 if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl)
1240 fe->ops.i2c_gate_ctrl(fe, 0);
1243 switch (p->transmission_mode) {
1245 case TRANSMISSION_MODE_AUTO:
1246 case TRANSMISSION_MODE_2K:
1247 ter_state->mode = FE_TER_MODE_2K;
1249 /* case TRANSMISSION_MODE_4K:
1250 pLook.mode = FE_TER_MODE_4K;
1252 case TRANSMISSION_MODE_8K:
1253 ter_state->mode = FE_TER_MODE_8K;
1257 switch (p->guard_interval) {
1259 case GUARD_INTERVAL_1_32:
1260 case GUARD_INTERVAL_1_16:
1261 case GUARD_INTERVAL_1_8:
1262 case GUARD_INTERVAL_1_4:
1263 ter_state->guard = p->guard_interval;
1265 case GUARD_INTERVAL_AUTO:
1266 ter_state->guard = GUARD_INTERVAL_1_32;
1270 switch (p->bandwidth_hz) {
1272 ter_state->bw = FE_TER_CHAN_BW_6M;
1275 ter_state->bw = FE_TER_CHAN_BW_7M;
1279 ter_state->bw = FE_TER_CHAN_BW_8M;
1282 ter_state->hierarchy = FE_TER_HIER_NONE;
1284 switch (p->inversion) {
1291 if (ter_state->first_lock)
1296 ter_state->state = FE_TER_NOLOCK;
1299 while (((index) < num_trials) && (ter_state->state != FE_TER_LOCKOK)) {
1300 if (!ter_state->first_lock) {
1301 if (p->inversion == INVERSION_AUTO)
1302 ter_state->sense = SenseTrials[index];
1305 stv0367ter_algo(fe);
1307 if ((ter_state->state == FE_TER_LOCKOK) &&
1308 (p->inversion == INVERSION_AUTO) &&
1310 /* invert spectrum sense */
1311 SenseTrials[index] = SenseTrials[0];
1312 SenseTrials[(index + 1) % 2] = (SenseTrials[1] + 1) % 2;
1321 static int stv0367ter_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1323 struct stv0367_state *state = fe->demodulator_priv;
1324 struct stv0367ter_state *ter_state = state->ter_state;
1327 /*wait for counting completion*/
1328 if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0) {
1330 ((u32)stv0367_readbits(state, F367TER_ERR_CNT1)
1332 + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI)
1334 + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO));
1335 ter_state->ucblocks = errs;
1338 (*ucblocks) = ter_state->ucblocks;
1343 static int stv0367ter_get_frontend(struct dvb_frontend *fe,
1344 struct dtv_frontend_properties *p)
1346 struct stv0367_state *state = fe->demodulator_priv;
1347 struct stv0367ter_state *ter_state = state->ter_state;
1348 enum stv0367_ter_mode mode;
1349 int constell = 0,/* snr = 0,*/ Data = 0;
1351 p->frequency = stv0367_get_tuner_freq(fe);
1352 if ((int)p->frequency < 0)
1353 p->frequency = -p->frequency;
1355 constell = stv0367_readbits(state, F367TER_TPS_CONST);
1357 p->modulation = QPSK;
1358 else if (constell == 1)
1359 p->modulation = QAM_16;
1361 p->modulation = QAM_64;
1363 p->inversion = stv0367_readbits(state, F367TER_INV_SPECTR);
1365 /* Get the Hierarchical mode */
1366 Data = stv0367_readbits(state, F367TER_TPS_HIERMODE);
1370 p->hierarchy = HIERARCHY_NONE;
1373 p->hierarchy = HIERARCHY_1;
1376 p->hierarchy = HIERARCHY_2;
1379 p->hierarchy = HIERARCHY_4;
1382 p->hierarchy = HIERARCHY_AUTO;
1386 /* Get the FEC Rate */
1387 if (ter_state->hierarchy == FE_TER_HIER_LOW_PRIO)
1388 Data = stv0367_readbits(state, F367TER_TPS_LPCODE);
1390 Data = stv0367_readbits(state, F367TER_TPS_HPCODE);
1394 p->code_rate_HP = FEC_1_2;
1397 p->code_rate_HP = FEC_2_3;
1400 p->code_rate_HP = FEC_3_4;
1403 p->code_rate_HP = FEC_5_6;
1406 p->code_rate_HP = FEC_7_8;
1409 p->code_rate_HP = FEC_AUTO;
1413 mode = stv0367_readbits(state, F367TER_SYR_MODE);
1416 case FE_TER_MODE_2K:
1417 p->transmission_mode = TRANSMISSION_MODE_2K;
1419 /* case FE_TER_MODE_4K:
1420 p->transmission_mode = TRANSMISSION_MODE_4K;
1422 case FE_TER_MODE_8K:
1423 p->transmission_mode = TRANSMISSION_MODE_8K;
1426 p->transmission_mode = TRANSMISSION_MODE_AUTO;
1429 p->guard_interval = stv0367_readbits(state, F367TER_SYR_GUARD);
1434 static u32 stv0367ter_snr_readreg(struct dvb_frontend *fe)
1436 struct stv0367_state *state = fe->demodulator_priv;
1439 u8 cut = stv0367_readbits(state, F367TER_IDENTIFICATIONREG);
1442 usleep_range(2000, 3000);
1443 if (cut == 0x50) /*cut 1.0 cut 1.1*/
1444 snru32 += stv0367_readbits(state, F367TER_CHCSNR) / 4;
1446 snru32 += 125 * stv0367_readbits(state, F367TER_CHCSNR);
1450 snru32 /= 10;/*average on 10 values*/
1455 static int stv0367ter_read_snr(struct dvb_frontend *fe, u16 *snr)
1457 u32 snrval = stv0367ter_snr_readreg(fe);
1459 *snr = snrval / 1000;
1465 static int stv0367ter_status(struct dvb_frontend *fe)
1468 struct stv0367_state *state = fe->demodulator_priv;
1469 struct stv0367ter_state *ter_state = state->ter_state;
1472 locked = (stv0367_readbits(state, F367TER_LK));
1474 ter_state->unlock_counter += 1;
1476 ter_state->unlock_counter = 0;
1478 if (ter_state->unlock_counter > 2) {
1479 if (!stv0367_readbits(state, F367TER_TPS_LOCK) ||
1480 (!stv0367_readbits(state, F367TER_LK))) {
1481 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
1482 usleep_range(2000, 3000);
1483 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
1485 locked = (stv0367_readbits(state, F367TER_TPS_LOCK)) &&
1486 (stv0367_readbits(state, F367TER_LK));
1494 static int stv0367ter_read_status(struct dvb_frontend *fe,
1495 enum fe_status *status)
1497 struct stv0367_state *state = fe->demodulator_priv;
1499 dprintk("%s:\n", __func__);
1503 if (stv0367_readbits(state, F367TER_LK)) {
1504 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI
1505 | FE_HAS_SYNC | FE_HAS_LOCK;
1506 dprintk("%s: stv0367 has locked\n", __func__);
1512 static int stv0367ter_read_ber(struct dvb_frontend *fe, u32 *ber)
1514 struct stv0367_state *state = fe->demodulator_priv;
1515 struct stv0367ter_state *ter_state = state->ter_state;
1516 u32 Errors = 0, tber = 0, temporary = 0;
1517 int abc = 0, def = 0;
1520 /*wait for counting completion*/
1521 if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0)
1522 Errors = ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT)
1524 + ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT_HI)
1526 + ((u32)stv0367_readbits(state,
1527 F367TER_SFEC_ERR_CNT_LO));
1528 /*measurement not completed, load previous value*/
1530 tber = ter_state->pBER;
1534 abc = stv0367_readbits(state, F367TER_SFEC_ERR_SOURCE);
1535 def = stv0367_readbits(state, F367TER_SFEC_NUM_EVENT);
1539 } else if (abc == 0x7) {
1541 temporary = (Errors * 1000000000) / (8 * (1 << 14));
1542 } else if (Errors <= 42) {
1543 temporary = (Errors * 100000000) / (8 * (1 << 14));
1544 temporary = temporary * 10;
1545 } else if (Errors <= 429) {
1546 temporary = (Errors * 10000000) / (8 * (1 << 14));
1547 temporary = temporary * 100;
1548 } else if (Errors <= 4294) {
1549 temporary = (Errors * 1000000) / (8 * (1 << 14));
1550 temporary = temporary * 1000;
1551 } else if (Errors <= 42949) {
1552 temporary = (Errors * 100000) / (8 * (1 << 14));
1553 temporary = temporary * 10000;
1554 } else if (Errors <= 429496) {
1555 temporary = (Errors * 10000) / (8 * (1 << 14));
1556 temporary = temporary * 100000;
1557 } else { /*if (Errors<4294967) 2^22 max error*/
1558 temporary = (Errors * 1000) / (8 * (1 << 14));
1559 temporary = temporary * 100000; /* still to *10 */
1564 /*tber=Errors/(8*(1 <<14));*/
1567 /*tber=Errors/(8*(1 <<16));*/
1568 tber = temporary / 4;
1570 /*tber=Errors/(8*(1 <<18));*/
1571 tber = temporary / 16;
1573 /*tber=Errors/(8*(1 <<20));*/
1574 tber = temporary / 64;
1576 /*tber=Errors/(8*(1 <<22));*/
1577 tber = temporary / 256;
1579 /* should not pass here*/
1582 if ((Errors < 4294967) && (Errors > 429496))
1587 /* save actual value */
1588 ter_state->pBER = tber;
1595 static u32 stv0367ter_get_per(struct stv0367_state *state)
1597 struct stv0367ter_state *ter_state = state->ter_state;
1598 u32 Errors = 0, Per = 0, temporary = 0;
1599 int abc = 0, def = 0, cpt = 0;
1601 while (((stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 1) &&
1602 (cpt < 400)) || ((Errors == 0) && (cpt < 400))) {
1603 usleep_range(1000, 2000);
1604 Errors = ((u32)stv0367_readbits(state, F367TER_ERR_CNT1)
1606 + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI)
1608 + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO));
1611 abc = stv0367_readbits(state, F367TER_ERR_SRC1);
1612 def = stv0367_readbits(state, F367TER_NUM_EVT1);
1616 else if (abc == 0x9) {
1618 temporary = (Errors * 1000000000) / (8 * (1 << 8));
1619 } else if (Errors <= 42) {
1620 temporary = (Errors * 100000000) / (8 * (1 << 8));
1621 temporary = temporary * 10;
1622 } else if (Errors <= 429) {
1623 temporary = (Errors * 10000000) / (8 * (1 << 8));
1624 temporary = temporary * 100;
1625 } else if (Errors <= 4294) {
1626 temporary = (Errors * 1000000) / (8 * (1 << 8));
1627 temporary = temporary * 1000;
1628 } else if (Errors <= 42949) {
1629 temporary = (Errors * 100000) / (8 * (1 << 8));
1630 temporary = temporary * 10000;
1631 } else { /*if(Errors<=429496) 2^16 errors max*/
1632 temporary = (Errors * 10000) / (8 * (1 << 8));
1633 temporary = temporary * 100000;
1638 /*Per=Errors/(1 << 8);*/
1641 /*Per=Errors/(1 << 10);*/
1642 Per = temporary / 4;
1644 /*Per=Errors/(1 << 12);*/
1645 Per = temporary / 16;
1647 /*Per=Errors/(1 << 14);*/
1648 Per = temporary / 64;
1650 /*Per=Errors/(1 << 16);*/
1651 Per = temporary / 256;
1656 /* save actual value */
1657 ter_state->pPER = Per;
1662 static int stv0367_get_tune_settings(struct dvb_frontend *fe,
1663 struct dvb_frontend_tune_settings
1666 fe_tune_settings->min_delay_ms = 1000;
1667 fe_tune_settings->step_size = 0;
1668 fe_tune_settings->max_drift = 0;
1673 static void stv0367_release(struct dvb_frontend *fe)
1675 struct stv0367_state *state = fe->demodulator_priv;
1677 kfree(state->ter_state);
1678 kfree(state->cab_state);
1682 static const struct dvb_frontend_ops stv0367ter_ops = {
1683 .delsys = { SYS_DVBT },
1685 .name = "ST STV0367 DVB-T",
1686 .frequency_min_hz = 47 * MHz,
1687 .frequency_max_hz = 862 * MHz,
1688 .frequency_stepsize_hz = 15625,
1689 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
1690 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
1692 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
1693 FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_QAM_AUTO |
1694 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER |
1695 FE_CAN_INVERSION_AUTO |
1698 .release = stv0367_release,
1699 .init = stv0367ter_init,
1700 .sleep = stv0367ter_sleep,
1701 .i2c_gate_ctrl = stv0367ter_gate_ctrl,
1702 .set_frontend = stv0367ter_set_frontend,
1703 .get_frontend = stv0367ter_get_frontend,
1704 .get_tune_settings = stv0367_get_tune_settings,
1705 .read_status = stv0367ter_read_status,
1706 .read_ber = stv0367ter_read_ber,/* too slow */
1707 /* .read_signal_strength = stv0367_read_signal_strength,*/
1708 .read_snr = stv0367ter_read_snr,
1709 .read_ucblocks = stv0367ter_read_ucblocks,
1712 struct dvb_frontend *stv0367ter_attach(const struct stv0367_config *config,
1713 struct i2c_adapter *i2c)
1715 struct stv0367_state *state = NULL;
1716 struct stv0367ter_state *ter_state = NULL;
1718 /* allocate memory for the internal state */
1719 state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
1722 ter_state = kzalloc(sizeof(struct stv0367ter_state), GFP_KERNEL);
1723 if (ter_state == NULL)
1726 /* setup the state */
1728 state->config = config;
1729 state->ter_state = ter_state;
1730 state->fe.ops = stv0367ter_ops;
1731 state->fe.demodulator_priv = state;
1732 state->chip_id = stv0367_readreg(state, 0xf000);
1734 /* demod operation options */
1735 state->use_i2c_gatectrl = 1;
1736 state->deftabs = STV0367_DEFTAB_GENERIC;
1737 state->reinit_on_setfrontend = 1;
1738 state->auto_if_khz = 0;
1740 dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
1742 /* check if the demod is there */
1743 if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
1753 EXPORT_SYMBOL(stv0367ter_attach);
1755 static int stv0367cab_gate_ctrl(struct dvb_frontend *fe, int enable)
1757 struct stv0367_state *state = fe->demodulator_priv;
1759 dprintk("%s:\n", __func__);
1761 stv0367_writebits(state, F367CAB_I2CT_ON, (enable > 0) ? 1 : 0);
1766 static u32 stv0367cab_get_mclk(struct dvb_frontend *fe, u32 ExtClk_Hz)
1768 struct stv0367_state *state = fe->demodulator_priv;
1769 u32 mclk_Hz = 0;/* master clock frequency (Hz) */
1773 if (stv0367_readbits(state, F367CAB_BYPASS_PLLXN) == 0) {
1774 N = (u32)stv0367_readbits(state, F367CAB_PLL_NDIV);
1778 M = (u32)stv0367_readbits(state, F367CAB_PLL_MDIV);
1782 P = (u32)stv0367_readbits(state, F367CAB_PLL_PDIV);
1787 mclk_Hz = ((ExtClk_Hz / 2) * N) / (M * (1 << P));
1788 dprintk("stv0367cab_get_mclk BYPASS_PLLXN mclk_Hz=%d\n",
1791 mclk_Hz = ExtClk_Hz;
1793 dprintk("stv0367cab_get_mclk final mclk_Hz=%d\n", mclk_Hz);
1798 static u32 stv0367cab_get_adc_freq(struct dvb_frontend *fe, u32 ExtClk_Hz)
1800 return stv0367cab_get_mclk(fe, ExtClk_Hz);
1803 static enum stv0367cab_mod stv0367cab_SetQamSize(struct stv0367_state *state,
1805 enum stv0367cab_mod QAMSize)
1808 stv0367_writebits(state, F367CAB_QAM_MODE, QAMSize);
1810 /* Set Registers settings specific to the QAM size */
1812 case FE_CAB_MOD_QAM4:
1813 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1815 case FE_CAB_MOD_QAM16:
1816 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x64);
1817 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1818 stv0367_writereg(state, R367CAB_FSM_STATE, 0x90);
1819 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1820 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
1821 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95);
1822 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
1823 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x8a);
1825 case FE_CAB_MOD_QAM32:
1826 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1827 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x6e);
1828 stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0);
1829 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1830 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xb7);
1831 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x9d);
1832 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f);
1833 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
1835 case FE_CAB_MOD_QAM64:
1836 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x82);
1837 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a);
1838 if (SymbolRate > 4500000) {
1839 stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0);
1840 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1841 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa5);
1842 } else if (SymbolRate > 2500000) {
1843 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
1844 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1845 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6);
1847 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
1848 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1);
1849 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
1851 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95);
1852 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
1853 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x99);
1855 case FE_CAB_MOD_QAM128:
1856 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1857 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x76);
1858 stv0367_writereg(state, R367CAB_FSM_STATE, 0x90);
1859 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xb1);
1860 if (SymbolRate > 4500000)
1861 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
1862 else if (SymbolRate > 2500000)
1863 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6);
1865 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0x97);
1867 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x8e);
1868 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f);
1869 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
1871 case FE_CAB_MOD_QAM256:
1872 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x94);
1873 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a);
1874 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
1875 if (SymbolRate > 4500000)
1876 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1877 else if (SymbolRate > 2500000)
1878 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1880 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1);
1882 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
1883 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x85);
1884 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
1885 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
1887 case FE_CAB_MOD_QAM512:
1888 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1890 case FE_CAB_MOD_QAM1024:
1891 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1900 static u32 stv0367cab_set_derot_freq(struct stv0367_state *state,
1901 u32 adc_hz, s32 derot_hz)
1906 adc_khz = adc_hz / 1000;
1908 dprintk("%s: adc_hz=%d derot_hz=%d\n", __func__, adc_hz, derot_hz);
1911 if (derot_hz < 1000000)
1912 derot_hz = adc_hz / 4; /* ZIF operation */
1913 if (derot_hz > adc_hz)
1914 derot_hz = derot_hz - adc_hz;
1915 sampled_if = (u32)derot_hz / 1000;
1916 sampled_if *= 32768;
1917 sampled_if /= adc_khz;
1921 if (sampled_if > 8388607)
1922 sampled_if = 8388607;
1924 dprintk("%s: sampled_if=0x%x\n", __func__, sampled_if);
1926 stv0367_writereg(state, R367CAB_MIX_NCO_LL, sampled_if);
1927 stv0367_writereg(state, R367CAB_MIX_NCO_HL, (sampled_if >> 8));
1928 stv0367_writebits(state, F367CAB_MIX_NCO_INC_HH, (sampled_if >> 16));
1933 static u32 stv0367cab_get_derot_freq(struct stv0367_state *state, u32 adc_hz)
1937 sampled_if = stv0367_readbits(state, F367CAB_MIX_NCO_INC_LL) +
1938 (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HL) << 8) +
1939 (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HH) << 16);
1942 sampled_if *= (adc_hz / 1000);
1944 sampled_if /= 32768;
1949 static u32 stv0367cab_set_srate(struct stv0367_state *state, u32 adc_hz,
1950 u32 mclk_hz, u32 SymbolRate,
1951 enum stv0367cab_mod QAMSize)
1953 u32 QamSizeCorr = 0;
1954 u32 u32_tmp = 0, u32_tmp1 = 0;
1957 dprintk("%s:\n", __func__);
1959 /* Set Correction factor of SRC gain */
1961 case FE_CAB_MOD_QAM4:
1964 case FE_CAB_MOD_QAM16:
1967 case FE_CAB_MOD_QAM32:
1970 case FE_CAB_MOD_QAM64:
1973 case FE_CAB_MOD_QAM128:
1976 case FE_CAB_MOD_QAM256:
1979 case FE_CAB_MOD_QAM512:
1982 case FE_CAB_MOD_QAM1024:
1989 /* Transfer ratio calculation */
1991 u32_tmp = 256 * SymbolRate;
1992 u32_tmp = u32_tmp / adc_hz;
1994 stv0367_writereg(state, R367CAB_EQU_CRL_TFR, (u8)u32_tmp);
1996 /* Symbol rate and SRC gain calculation */
1997 adp_khz = (mclk_hz >> 1) / 1000;/* TRL works at half the system clock */
1999 u32_tmp = SymbolRate;
2000 u32_tmp1 = SymbolRate;
2002 if (u32_tmp < 2097152) { /* 2097152 = 2^21 */
2003 /* Symbol rate calculation */
2004 u32_tmp *= 2048; /* 2048 = 2^11 */
2005 u32_tmp = u32_tmp / adp_khz;
2006 u32_tmp = u32_tmp * 16384; /* 16384 = 2^14 */
2007 u32_tmp /= 125 ; /* 125 = 1000/2^3 */
2008 u32_tmp = u32_tmp * 8; /* 8 = 2^3 */
2010 /* SRC Gain Calculation */
2011 u32_tmp1 *= 2048; /* *2*2^10 */
2012 u32_tmp1 /= 439; /* *2/878 */
2013 u32_tmp1 *= 256; /* *2^8 */
2014 u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2015 u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2016 u32_tmp1 = u32_tmp1 / 10000000;
2018 } else if (u32_tmp < 4194304) { /* 4194304 = 2**22 */
2019 /* Symbol rate calculation */
2020 u32_tmp *= 1024 ; /* 1024 = 2**10 */
2021 u32_tmp = u32_tmp / adp_khz;
2022 u32_tmp = u32_tmp * 16384; /* 16384 = 2**14 */
2023 u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2024 u32_tmp = u32_tmp * 16; /* 16 = 2**4 */
2026 /* SRC Gain Calculation */
2027 u32_tmp1 *= 1024; /* *2*2^9 */
2028 u32_tmp1 /= 439; /* *2/878 */
2029 u32_tmp1 *= 256; /* *2^8 */
2030 u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz)*/
2031 u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2032 u32_tmp1 = u32_tmp1 / 5000000;
2033 } else if (u32_tmp < 8388607) { /* 8388607 = 2**23 */
2034 /* Symbol rate calculation */
2035 u32_tmp *= 512 ; /* 512 = 2**9 */
2036 u32_tmp = u32_tmp / adp_khz;
2037 u32_tmp = u32_tmp * 16384; /* 16384 = 2**14 */
2038 u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2039 u32_tmp = u32_tmp * 32; /* 32 = 2**5 */
2041 /* SRC Gain Calculation */
2042 u32_tmp1 *= 512; /* *2*2^8 */
2043 u32_tmp1 /= 439; /* *2/878 */
2044 u32_tmp1 *= 256; /* *2^8 */
2045 u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2046 u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2047 u32_tmp1 = u32_tmp1 / 2500000;
2049 /* Symbol rate calculation */
2050 u32_tmp *= 256 ; /* 256 = 2**8 */
2051 u32_tmp = u32_tmp / adp_khz;
2052 u32_tmp = u32_tmp * 16384; /* 16384 = 2**13 */
2053 u32_tmp /= 125 ; /* 125 = 1000/2**3 */
2054 u32_tmp = u32_tmp * 64; /* 64 = 2**6 */
2056 /* SRC Gain Calculation */
2057 u32_tmp1 *= 256; /* 2*2^7 */
2058 u32_tmp1 /= 439; /* *2/878 */
2059 u32_tmp1 *= 256; /* *2^8 */
2060 u32_tmp1 = u32_tmp1 / adp_khz; /* /(AdpClk in kHz) */
2061 u32_tmp1 *= QamSizeCorr * 9; /* *1000*corr factor */
2062 u32_tmp1 = u32_tmp1 / 1250000;
2066 /* Filters' coefficients are calculated and written
2067 into registers only if the filters are enabled */
2068 if (stv0367_readbits(state, F367CAB_ADJ_EN)) {
2069 stv0367cab_SetIirAdjacentcoefficient(state, mclk_hz,
2071 /* AllPass filter must be enabled
2072 when the adjacents filter is used */
2073 stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 1);
2074 stv0367cab_SetAllPasscoefficient(state, mclk_hz, SymbolRate);
2076 /* AllPass filter must be disabled
2077 when the adjacents filter is not used */
2079 stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0);
2081 stv0367_writereg(state, R367CAB_SRC_NCO_LL, u32_tmp);
2082 stv0367_writereg(state, R367CAB_SRC_NCO_LH, (u32_tmp >> 8));
2083 stv0367_writereg(state, R367CAB_SRC_NCO_HL, (u32_tmp >> 16));
2084 stv0367_writereg(state, R367CAB_SRC_NCO_HH, (u32_tmp >> 24));
2086 stv0367_writereg(state, R367CAB_IQDEM_GAIN_SRC_L, u32_tmp1 & 0x00ff);
2087 stv0367_writebits(state, F367CAB_GAIN_SRC_HI, (u32_tmp1 >> 8) & 0x00ff);
2092 static u32 stv0367cab_GetSymbolRate(struct stv0367_state *state, u32 mclk_hz)
2097 regsym = stv0367_readreg(state, R367CAB_SRC_NCO_LL) +
2098 (stv0367_readreg(state, R367CAB_SRC_NCO_LH) << 8) +
2099 (stv0367_readreg(state, R367CAB_SRC_NCO_HL) << 16) +
2100 (stv0367_readreg(state, R367CAB_SRC_NCO_HH) << 24);
2102 adp_khz = (mclk_hz >> 1) / 1000;/* TRL works at half the system clock */
2104 if (regsym < 134217728) { /* 134217728L = 2**27*/
2105 regsym = regsym * 32; /* 32 = 2**5 */
2106 regsym = regsym / 32768; /* 32768L = 2**15 */
2107 regsym = adp_khz * regsym; /* AdpClk in kHz */
2108 regsym = regsym / 128; /* 128 = 2**7 */
2109 regsym *= 125 ; /* 125 = 1000/2**3 */
2110 regsym /= 2048 ; /* 2048 = 2**11 */
2111 } else if (regsym < 268435456) { /* 268435456L = 2**28 */
2112 regsym = regsym * 16; /* 16 = 2**4 */
2113 regsym = regsym / 32768; /* 32768L = 2**15 */
2114 regsym = adp_khz * regsym; /* AdpClk in kHz */
2115 regsym = regsym / 128; /* 128 = 2**7 */
2116 regsym *= 125 ; /* 125 = 1000/2**3*/
2117 regsym /= 1024 ; /* 256 = 2**10*/
2118 } else if (regsym < 536870912) { /* 536870912L = 2**29*/
2119 regsym = regsym * 8; /* 8 = 2**3 */
2120 regsym = regsym / 32768; /* 32768L = 2**15 */
2121 regsym = adp_khz * regsym; /* AdpClk in kHz */
2122 regsym = regsym / 128; /* 128 = 2**7 */
2123 regsym *= 125 ; /* 125 = 1000/2**3 */
2124 regsym /= 512 ; /* 128 = 2**9 */
2126 regsym = regsym * 4; /* 4 = 2**2 */
2127 regsym = regsym / 32768; /* 32768L = 2**15 */
2128 regsym = adp_khz * regsym; /* AdpClk in kHz */
2129 regsym = regsym / 128; /* 128 = 2**7 */
2130 regsym *= 125 ; /* 125 = 1000/2**3 */
2131 regsym /= 256 ; /* 64 = 2**8 */
2137 static u32 stv0367cab_fsm_status(struct stv0367_state *state)
2139 return stv0367_readbits(state, F367CAB_FSM_STATUS);
2142 static u32 stv0367cab_qamfec_lock(struct stv0367_state *state)
2144 return stv0367_readbits(state,
2145 (state->cab_state->qamfec_status_reg ?
2146 state->cab_state->qamfec_status_reg :
2147 F367CAB_QAMFEC_LOCK));
2151 enum stv0367_cab_signal_type stv0367cab_fsm_signaltype(u32 qam_fsm_status)
2153 enum stv0367_cab_signal_type signaltype = FE_CAB_NOAGC;
2155 switch (qam_fsm_status) {
2157 signaltype = FE_CAB_NOAGC;
2160 signaltype = FE_CAB_NOTIMING;
2163 signaltype = FE_CAB_TIMINGOK;
2166 signaltype = FE_CAB_NOCARRIER;
2169 signaltype = FE_CAB_CARRIEROK;
2172 signaltype = FE_CAB_NOBLIND;
2175 signaltype = FE_CAB_BLINDOK;
2178 signaltype = FE_CAB_NODEMOD;
2181 signaltype = FE_CAB_DEMODOK;
2184 signaltype = FE_CAB_DEMODOK;
2187 signaltype = FE_CAB_NODEMOD;
2190 signaltype = FE_CAB_NOBLIND;
2193 signaltype = FE_CAB_NOSIGNAL;
2202 static int stv0367cab_read_status(struct dvb_frontend *fe,
2203 enum fe_status *status)
2205 struct stv0367_state *state = fe->demodulator_priv;
2207 dprintk("%s:\n", __func__);
2211 /* update cab_state->state from QAM_FSM_STATUS */
2212 state->cab_state->state = stv0367cab_fsm_signaltype(
2213 stv0367cab_fsm_status(state));
2215 if (stv0367cab_qamfec_lock(state)) {
2216 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI
2217 | FE_HAS_SYNC | FE_HAS_LOCK;
2218 dprintk("%s: stv0367 has locked\n", __func__);
2220 if (state->cab_state->state > FE_CAB_NOSIGNAL)
2221 *status |= FE_HAS_SIGNAL;
2223 if (state->cab_state->state > FE_CAB_NOCARRIER)
2224 *status |= FE_HAS_CARRIER;
2226 if (state->cab_state->state >= FE_CAB_DEMODOK)
2227 *status |= FE_HAS_VITERBI;
2229 if (state->cab_state->state >= FE_CAB_DATAOK)
2230 *status |= FE_HAS_SYNC;
2236 static int stv0367cab_standby(struct dvb_frontend *fe, u8 standby_on)
2238 struct stv0367_state *state = fe->demodulator_priv;
2240 dprintk("%s:\n", __func__);
2243 stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x03);
2244 stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x01);
2245 stv0367_writebits(state, F367CAB_STDBY, 1);
2246 stv0367_writebits(state, F367CAB_STDBY_CORE, 1);
2247 stv0367_writebits(state, F367CAB_EN_BUFFER_I, 0);
2248 stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 0);
2249 stv0367_writebits(state, F367CAB_POFFQ, 1);
2250 stv0367_writebits(state, F367CAB_POFFI, 1);
2252 stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x00);
2253 stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x00);
2254 stv0367_writebits(state, F367CAB_STDBY, 0);
2255 stv0367_writebits(state, F367CAB_STDBY_CORE, 0);
2256 stv0367_writebits(state, F367CAB_EN_BUFFER_I, 1);
2257 stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 1);
2258 stv0367_writebits(state, F367CAB_POFFQ, 0);
2259 stv0367_writebits(state, F367CAB_POFFI, 0);
2265 static int stv0367cab_sleep(struct dvb_frontend *fe)
2267 return stv0367cab_standby(fe, 1);
2270 static int stv0367cab_init(struct dvb_frontend *fe)
2272 struct stv0367_state *state = fe->demodulator_priv;
2273 struct stv0367cab_state *cab_state = state->cab_state;
2275 dprintk("%s:\n", __func__);
2277 stv0367_write_table(state,
2278 stv0367_deftabs[state->deftabs][STV0367_TAB_CAB]);
2280 switch (state->config->ts_mode) {
2281 case STV0367_DVBCI_CLOCK:
2282 dprintk("Setting TSMode = STV0367_DVBCI_CLOCK\n");
2283 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x03);
2285 case STV0367_SERIAL_PUNCT_CLOCK:
2286 case STV0367_SERIAL_CONT_CLOCK:
2287 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x01);
2289 case STV0367_PARALLEL_PUNCT_CLOCK:
2290 case STV0367_OUTPUTMODE_DEFAULT:
2291 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x00);
2295 switch (state->config->clk_pol) {
2296 case STV0367_RISINGEDGE_CLOCK:
2297 stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x00);
2299 case STV0367_FALLINGEDGE_CLOCK:
2300 case STV0367_CLOCKPOLARITY_DEFAULT:
2301 stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x01);
2305 stv0367_writebits(state, F367CAB_SYNC_STRIP, 0x00);
2307 stv0367_writebits(state, F367CAB_CT_NBST, 0x01);
2309 stv0367_writebits(state, F367CAB_TS_SWAP, 0x01);
2311 stv0367_writebits(state, F367CAB_FIFO_BYPASS, 0x00);
2313 stv0367_writereg(state, R367CAB_ANACTRL, 0x00);/*PLL enabled and used */
2315 cab_state->mclk = stv0367cab_get_mclk(fe, state->config->xtal);
2316 cab_state->adc_clk = stv0367cab_get_adc_freq(fe, state->config->xtal);
2321 enum stv0367_cab_signal_type stv0367cab_algo(struct stv0367_state *state,
2322 struct dtv_frontend_properties *p)
2324 struct stv0367cab_state *cab_state = state->cab_state;
2325 enum stv0367_cab_signal_type signalType = FE_CAB_NOAGC;
2326 u32 QAMFEC_Lock, QAM_Lock, u32_tmp, ifkhz,
2327 LockTime, TRLTimeOut, AGCTimeOut, CRLSymbols,
2328 CRLTimeOut, EQLTimeOut, DemodTimeOut, FECTimeOut;
2332 dprintk("%s:\n", __func__);
2334 stv0367_get_if_khz(state, &ifkhz);
2336 /* Timeouts calculation */
2337 /* A max lock time of 25 ms is allowed for delayed AGC */
2339 /* 100000 symbols needed by the TRL as a maximum value */
2340 TRLTimeOut = 100000000 / p->symbol_rate;
2341 /* CRLSymbols is the needed number of symbols to achieve a lock
2342 within [-4%, +4%] of the symbol rate.
2343 CRL timeout is calculated
2344 for a lock within [-search_range, +search_range].
2345 EQL timeout can be changed depending on
2346 the micro-reflections we want to handle.
2347 A characterization must be performed
2348 with these echoes to get new timeout values.
2350 switch (p->modulation) {
2352 CRLSymbols = 150000;
2356 CRLSymbols = 250000;
2360 CRLSymbols = 200000;
2364 CRLSymbols = 250000;
2368 CRLSymbols = 250000;
2372 CRLSymbols = 200000;
2377 if (pIntParams->search_range < 0) {
2378 CRLTimeOut = (25 * CRLSymbols *
2379 (-pIntParams->search_range / 1000)) /
2380 (pIntParams->symbol_rate / 1000);
2383 CRLTimeOut = (25 * CRLSymbols * (cab_state->search_range / 1000)) /
2384 (p->symbol_rate / 1000);
2386 CRLTimeOut = (1000 * CRLTimeOut) / p->symbol_rate;
2387 /* Timeouts below 50ms are coerced */
2388 if (CRLTimeOut < 50)
2390 /* A maximum of 100 TS packets is needed to get FEC lock even in case
2391 the spectrum inversion needs to be changed.
2392 This is equal to 20 ms in case of the lowest symbol rate of 0.87Msps
2395 DemodTimeOut = AGCTimeOut + TRLTimeOut + CRLTimeOut + EQLTimeOut;
2397 dprintk("%s: DemodTimeOut=%d\n", __func__, DemodTimeOut);
2399 /* Reset the TRL to ensure nothing starts until the
2400 AGC is stable which ensures a better lock time
2402 stv0367_writereg(state, R367CAB_CTRL_1, 0x04);
2403 /* Set AGC accumulation time to minimum and lock threshold to maximum
2404 in order to speed up the AGC lock */
2405 TrackAGCAccum = stv0367_readbits(state, F367CAB_AGC_ACCUMRSTSEL);
2406 stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, 0x0);
2407 /* Modulus Mapper is disabled */
2408 stv0367_writebits(state, F367CAB_MODULUSMAP_EN, 0);
2409 /* Disable the sweep function */
2410 stv0367_writebits(state, F367CAB_SWEEP_EN, 0);
2411 /* The sweep function is never used, Sweep rate must be set to 0 */
2412 /* Set the derotator frequency in Hz */
2413 stv0367cab_set_derot_freq(state, cab_state->adc_clk,
2414 (1000 * (s32)ifkhz + cab_state->derot_offset));
2415 /* Disable the Allpass Filter when the symbol rate is out of range */
2416 if ((p->symbol_rate > 10800000) | (p->symbol_rate < 1800000)) {
2417 stv0367_writebits(state, F367CAB_ADJ_EN, 0);
2418 stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0);
2421 /* Check if the tuner is locked */
2422 tuner_lock = stv0367cab_tuner_get_status(fe);
2423 if (tuner_lock == 0)
2424 return FE_367CAB_NOTUNER;
2426 /* Release the TRL to start demodulator acquisition */
2427 /* Wait for QAM lock */
2429 stv0367_writereg(state, R367CAB_CTRL_1, 0x00);
2431 QAM_Lock = stv0367cab_fsm_status(state);
2432 if ((LockTime >= (DemodTimeOut - EQLTimeOut)) &&
2435 * We don't wait longer, the frequency/phase offset
2438 LockTime = DemodTimeOut;
2439 else if ((LockTime >= (AGCTimeOut + TRLTimeOut)) &&
2442 * We don't wait longer, either there is no signal or
2443 * it is not the right symbol rate or it is an analog
2447 LockTime = DemodTimeOut;
2448 u32_tmp = stv0367_readbits(state,
2449 F367CAB_AGC_PWR_WORD_LO) +
2450 (stv0367_readbits(state,
2451 F367CAB_AGC_PWR_WORD_ME) << 8) +
2452 (stv0367_readbits(state,
2453 F367CAB_AGC_PWR_WORD_HI) << 16);
2454 if (u32_tmp >= 131072)
2455 u32_tmp = 262144 - u32_tmp;
2456 u32_tmp = u32_tmp / (1 << (11 - stv0367_readbits(state,
2457 F367CAB_AGC_IF_BWSEL)));
2459 if (u32_tmp < stv0367_readbits(state,
2460 F367CAB_AGC_PWRREF_LO) +
2461 256 * stv0367_readbits(state,
2462 F367CAB_AGC_PWRREF_HI) - 10)
2465 usleep_range(10000, 20000);
2468 dprintk("QAM_Lock=0x%x LockTime=%d\n", QAM_Lock, LockTime);
2469 tmp = stv0367_readreg(state, R367CAB_IT_STATUS1);
2471 dprintk("R367CAB_IT_STATUS1=0x%x\n", tmp);
2473 } while (((QAM_Lock != 0x0c) && (QAM_Lock != 0x0b)) &&
2474 (LockTime < DemodTimeOut));
2476 dprintk("QAM_Lock=0x%x\n", QAM_Lock);
2478 tmp = stv0367_readreg(state, R367CAB_IT_STATUS1);
2479 dprintk("R367CAB_IT_STATUS1=0x%x\n", tmp);
2480 tmp = stv0367_readreg(state, R367CAB_IT_STATUS2);
2481 dprintk("R367CAB_IT_STATUS2=0x%x\n", tmp);
2483 tmp = stv0367cab_get_derot_freq(state, cab_state->adc_clk);
2484 dprintk("stv0367cab_get_derot_freq=0x%x\n", tmp);
2486 if ((QAM_Lock == 0x0c) || (QAM_Lock == 0x0b)) {
2487 /* Wait for FEC lock */
2490 usleep_range(5000, 7000);
2492 QAMFEC_Lock = stv0367cab_qamfec_lock(state);
2493 } while (!QAMFEC_Lock && (LockTime < FECTimeOut));
2498 signalType = FE_CAB_DATAOK;
2499 cab_state->spect_inv = stv0367_readbits(state,
2502 /* not clear for me */
2504 if (ifkhz > cab_state->adc_clk / 1000) {
2505 cab_state->freq_khz =
2506 FE_Cab_TunerGetFrequency(pIntParams->hTuner)
2507 - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
2508 - cab_state->adc_clk / 1000 + ifkhz;
2510 cab_state->freq_khz =
2511 FE_Cab_TunerGetFrequency(pIntParams->hTuner)
2512 - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
2516 cab_state->freq_khz =
2517 FE_Cab_TunerGetFrequency(pIntParams->hTuner) +
2518 stv0367cab_get_derot_freq(state,
2519 cab_state->adc_clk) -
2520 cab_state->adc_clk / 4000;
2523 cab_state->symbol_rate = stv0367cab_GetSymbolRate(state,
2525 cab_state->locked = 1;
2527 /* stv0367_setbits(state, F367CAB_AGC_ACCUMRSTSEL,7);*/
2529 signalType = stv0367cab_fsm_signaltype(QAM_Lock);
2531 /* Set the AGC control values to tracking values */
2532 stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, TrackAGCAccum);
2536 static int stv0367cab_set_frontend(struct dvb_frontend *fe)
2538 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2539 struct stv0367_state *state = fe->demodulator_priv;
2540 struct stv0367cab_state *cab_state = state->cab_state;
2541 enum stv0367cab_mod QAMSize = 0;
2543 dprintk("%s: freq = %d, srate = %d\n", __func__,
2544 p->frequency, p->symbol_rate);
2546 cab_state->derot_offset = 0;
2548 switch (p->modulation) {
2550 QAMSize = FE_CAB_MOD_QAM16;
2553 QAMSize = FE_CAB_MOD_QAM32;
2556 QAMSize = FE_CAB_MOD_QAM64;
2559 QAMSize = FE_CAB_MOD_QAM128;
2562 QAMSize = FE_CAB_MOD_QAM256;
2568 if (state->reinit_on_setfrontend)
2569 stv0367cab_init(fe);
2571 /* Tuner Frequency Setting */
2572 if (fe->ops.tuner_ops.set_params) {
2573 if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl)
2574 fe->ops.i2c_gate_ctrl(fe, 1);
2575 fe->ops.tuner_ops.set_params(fe);
2576 if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl)
2577 fe->ops.i2c_gate_ctrl(fe, 0);
2580 stv0367cab_SetQamSize(
2585 stv0367cab_set_srate(state,
2590 /* Search algorithm launch, [-1.1*RangeOffset, +1.1*RangeOffset] scan */
2591 cab_state->state = stv0367cab_algo(state, p);
2595 static int stv0367cab_get_frontend(struct dvb_frontend *fe,
2596 struct dtv_frontend_properties *p)
2598 struct stv0367_state *state = fe->demodulator_priv;
2599 struct stv0367cab_state *cab_state = state->cab_state;
2602 enum stv0367cab_mod QAMSize;
2604 dprintk("%s:\n", __func__);
2606 stv0367_get_if_khz(state, &ifkhz);
2607 p->symbol_rate = stv0367cab_GetSymbolRate(state, cab_state->mclk);
2609 QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE);
2611 case FE_CAB_MOD_QAM16:
2612 p->modulation = QAM_16;
2614 case FE_CAB_MOD_QAM32:
2615 p->modulation = QAM_32;
2617 case FE_CAB_MOD_QAM64:
2618 p->modulation = QAM_64;
2620 case FE_CAB_MOD_QAM128:
2621 p->modulation = QAM_128;
2623 case FE_CAB_MOD_QAM256:
2624 p->modulation = QAM_256;
2630 p->frequency = stv0367_get_tuner_freq(fe);
2632 dprintk("%s: tuner frequency = %d\n", __func__, p->frequency);
2636 (stv0367cab_get_derot_freq(state, cab_state->adc_clk) -
2637 cab_state->adc_clk / 4000);
2641 if (ifkhz > cab_state->adc_clk / 1000)
2642 p->frequency += (ifkhz
2643 - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
2644 - cab_state->adc_clk / 1000);
2646 p->frequency += (ifkhz
2647 - stv0367cab_get_derot_freq(state, cab_state->adc_clk));
2653 void stv0367cab_GetErrorCount(state, enum stv0367cab_mod QAMSize,
2654 u32 symbol_rate, FE_367qam_Monitor *Monitor_results)
2656 stv0367cab_OptimiseNByteAndGetBER(state, QAMSize, symbol_rate, Monitor_results);
2657 stv0367cab_GetPacketsCount(state, Monitor_results);
2662 static int stv0367cab_read_ber(struct dvb_frontend *fe, u32 *ber)
2664 struct stv0367_state *state = fe->demodulator_priv;
2669 static s32 stv0367cab_get_rf_lvl(struct stv0367_state *state)
2672 s32 RfAgcPwm = 0, IfAgcPwm = 0;
2675 stv0367_writebits(state, F367CAB_STDBY_ADCGP, 0x0);
2678 (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_LO) & 0x03) +
2679 (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_HI) << 2);
2680 RfAgcPwm = 100 * RfAgcPwm / 1023;
2683 stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_LO) +
2684 (stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_HI) << 8);
2685 if (IfAgcPwm >= 2048)
2690 IfAgcPwm = 100 * IfAgcPwm / 4095;
2692 /* For DTT75467 on NIM */
2693 if (RfAgcPwm < 90 && IfAgcPwm < 28) {
2694 for (i = 0; i < RF_LOOKUP_TABLE_SIZE; i++) {
2695 if (RfAgcPwm <= stv0367cab_RF_LookUp1[0][i]) {
2696 rfLevel = (-1) * stv0367cab_RF_LookUp1[1][i];
2700 if (i == RF_LOOKUP_TABLE_SIZE)
2702 } else { /*if IF AGC>10*/
2703 for (i = 0; i < RF_LOOKUP_TABLE2_SIZE; i++) {
2704 if (IfAgcPwm <= stv0367cab_RF_LookUp2[0][i]) {
2705 rfLevel = (-1) * stv0367cab_RF_LookUp2[1][i];
2709 if (i == RF_LOOKUP_TABLE2_SIZE)
2715 static int stv0367cab_read_strength(struct dvb_frontend *fe, u16 *strength)
2717 struct stv0367_state *state = fe->demodulator_priv;
2719 s32 signal = stv0367cab_get_rf_lvl(state);
2721 dprintk("%s: signal=%d dBm\n", __func__, signal);
2726 *strength = (22 + signal) * (-1311);
2728 dprintk("%s: strength=%d\n", __func__, (*strength));
2733 static int stv0367cab_snr_power(struct dvb_frontend *fe)
2735 struct stv0367_state *state = fe->demodulator_priv;
2736 enum stv0367cab_mod QAMSize;
2738 QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE);
2740 case FE_CAB_MOD_QAM4:
2742 case FE_CAB_MOD_QAM16:
2744 case FE_CAB_MOD_QAM32:
2746 case FE_CAB_MOD_QAM64:
2748 case FE_CAB_MOD_QAM128:
2750 case FE_CAB_MOD_QAM256:
2752 case FE_CAB_MOD_QAM1024:
2761 static int stv0367cab_snr_readreg(struct dvb_frontend *fe, int avgdiv)
2763 struct stv0367_state *state = fe->demodulator_priv;
2767 for (i = 0; i < 10; i++) {
2768 regval += (stv0367_readbits(state, F367CAB_SNR_LO)
2769 + 256 * stv0367_readbits(state, F367CAB_SNR_HI));
2778 static int stv0367cab_read_snr(struct dvb_frontend *fe, u16 *snr)
2780 struct stv0367_state *state = fe->demodulator_priv;
2781 u32 noisepercentage;
2782 u32 regval = 0, temp = 0;
2785 power = stv0367cab_snr_power(fe);
2786 regval = stv0367cab_snr_readreg(fe, 1);
2790 * (1 << (3 + stv0367_readbits(state, F367CAB_SNR_PER)));
2794 /* table values, not needed to calculate logarithms */
2796 noisepercentage = 100;
2797 else if (temp >= 3981)
2798 noisepercentage = 93;
2799 else if (temp >= 3162)
2800 noisepercentage = 86;
2801 else if (temp >= 2512)
2802 noisepercentage = 79;
2803 else if (temp >= 1995)
2804 noisepercentage = 72;
2805 else if (temp >= 1585)
2806 noisepercentage = 65;
2807 else if (temp >= 1259)
2808 noisepercentage = 58;
2809 else if (temp >= 1000)
2810 noisepercentage = 50;
2811 else if (temp >= 794)
2812 noisepercentage = 43;
2813 else if (temp >= 501)
2814 noisepercentage = 36;
2815 else if (temp >= 316)
2816 noisepercentage = 29;
2817 else if (temp >= 200)
2818 noisepercentage = 22;
2819 else if (temp >= 158)
2820 noisepercentage = 14;
2821 else if (temp >= 126)
2822 noisepercentage = 7;
2824 noisepercentage = 0;
2826 dprintk("%s: noisepercentage=%d\n", __func__, noisepercentage);
2828 *snr = (noisepercentage * 65535) / 100;
2833 static int stv0367cab_read_ucblcks(struct dvb_frontend *fe, u32 *ucblocks)
2835 struct stv0367_state *state = fe->demodulator_priv;
2836 int corrected, tscount;
2838 *ucblocks = (stv0367_readreg(state, R367CAB_RS_COUNTER_5) << 8)
2839 | stv0367_readreg(state, R367CAB_RS_COUNTER_4);
2840 corrected = (stv0367_readreg(state, R367CAB_RS_COUNTER_3) << 8)
2841 | stv0367_readreg(state, R367CAB_RS_COUNTER_2);
2842 tscount = (stv0367_readreg(state, R367CAB_RS_COUNTER_2) << 8)
2843 | stv0367_readreg(state, R367CAB_RS_COUNTER_1);
2845 dprintk("%s: uncorrected blocks=%d corrected blocks=%d tscount=%d\n",
2846 __func__, *ucblocks, corrected, tscount);
2851 static const struct dvb_frontend_ops stv0367cab_ops = {
2852 .delsys = { SYS_DVBC_ANNEX_A },
2854 .name = "ST STV0367 DVB-C",
2855 .frequency_min_hz = 47 * MHz,
2856 .frequency_max_hz = 862 * MHz,
2857 .frequency_stepsize_hz = 62500,
2858 .symbol_rate_min = 870000,
2859 .symbol_rate_max = 11700000,
2860 .caps = 0x400 |/* FE_CAN_QAM_4 */
2861 FE_CAN_QAM_16 | FE_CAN_QAM_32 |
2862 FE_CAN_QAM_64 | FE_CAN_QAM_128 |
2863 FE_CAN_QAM_256 | FE_CAN_FEC_AUTO
2865 .release = stv0367_release,
2866 .init = stv0367cab_init,
2867 .sleep = stv0367cab_sleep,
2868 .i2c_gate_ctrl = stv0367cab_gate_ctrl,
2869 .set_frontend = stv0367cab_set_frontend,
2870 .get_frontend = stv0367cab_get_frontend,
2871 .read_status = stv0367cab_read_status,
2872 /* .read_ber = stv0367cab_read_ber, */
2873 .read_signal_strength = stv0367cab_read_strength,
2874 .read_snr = stv0367cab_read_snr,
2875 .read_ucblocks = stv0367cab_read_ucblcks,
2876 .get_tune_settings = stv0367_get_tune_settings,
2879 struct dvb_frontend *stv0367cab_attach(const struct stv0367_config *config,
2880 struct i2c_adapter *i2c)
2882 struct stv0367_state *state = NULL;
2883 struct stv0367cab_state *cab_state = NULL;
2885 /* allocate memory for the internal state */
2886 state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
2889 cab_state = kzalloc(sizeof(struct stv0367cab_state), GFP_KERNEL);
2890 if (cab_state == NULL)
2893 /* setup the state */
2895 state->config = config;
2896 cab_state->search_range = 280000;
2897 cab_state->qamfec_status_reg = F367CAB_QAMFEC_LOCK;
2898 state->cab_state = cab_state;
2899 state->fe.ops = stv0367cab_ops;
2900 state->fe.demodulator_priv = state;
2901 state->chip_id = stv0367_readreg(state, 0xf000);
2903 /* demod operation options */
2904 state->use_i2c_gatectrl = 1;
2905 state->deftabs = STV0367_DEFTAB_GENERIC;
2906 state->reinit_on_setfrontend = 1;
2907 state->auto_if_khz = 0;
2909 dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
2911 /* check if the demod is there */
2912 if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
2922 EXPORT_SYMBOL(stv0367cab_attach);
2925 * Functions for operation on Digital Devices hardware
2928 static void stv0367ddb_setup_ter(struct stv0367_state *state)
2930 stv0367_writereg(state, R367TER_DEBUG_LT4, 0x00);
2931 stv0367_writereg(state, R367TER_DEBUG_LT5, 0x00);
2932 stv0367_writereg(state, R367TER_DEBUG_LT6, 0x00); /* R367CAB_CTRL_1 */
2933 stv0367_writereg(state, R367TER_DEBUG_LT7, 0x00); /* R367CAB_CTRL_2 */
2934 stv0367_writereg(state, R367TER_DEBUG_LT8, 0x00);
2935 stv0367_writereg(state, R367TER_DEBUG_LT9, 0x00);
2938 /* Buffer Q disabled, I Enabled, unsigned ADC */
2939 stv0367_writereg(state, R367TER_ANADIGCTRL, 0x89);
2940 stv0367_writereg(state, R367TER_DUAL_AD12, 0x04); /* ADCQ disabled */
2943 /* PLL bypassed and disabled */
2944 stv0367_writereg(state, R367TER_ANACTRL, 0x0D);
2945 stv0367_writereg(state, R367TER_TOPCTRL, 0x00); /* Set OFDM */
2947 /* IC runs at 54 MHz with a 27 MHz crystal */
2948 stv0367_pll_setup(state, STV0367_ICSPEED_53125, state->config->xtal);
2951 /* PLL enabled and used */
2952 stv0367_writereg(state, R367TER_ANACTRL, 0x00);
2954 state->activedemod = demod_ter;
2957 static void stv0367ddb_setup_cab(struct stv0367_state *state)
2959 stv0367_writereg(state, R367TER_DEBUG_LT4, 0x00);
2960 stv0367_writereg(state, R367TER_DEBUG_LT5, 0x01);
2961 stv0367_writereg(state, R367TER_DEBUG_LT6, 0x06); /* R367CAB_CTRL_1 */
2962 stv0367_writereg(state, R367TER_DEBUG_LT7, 0x03); /* R367CAB_CTRL_2 */
2963 stv0367_writereg(state, R367TER_DEBUG_LT8, 0x00);
2964 stv0367_writereg(state, R367TER_DEBUG_LT9, 0x00);
2967 /* Buffer Q disabled, I Enabled, signed ADC */
2968 stv0367_writereg(state, R367TER_ANADIGCTRL, 0x8B);
2970 stv0367_writereg(state, R367TER_DUAL_AD12, 0x04);
2973 /* PLL bypassed and disabled */
2974 stv0367_writereg(state, R367TER_ANACTRL, 0x0D);
2976 stv0367_writereg(state, R367TER_TOPCTRL, 0x10);
2978 /* IC runs at 58 MHz with a 27 MHz crystal */
2979 stv0367_pll_setup(state, STV0367_ICSPEED_58000, state->config->xtal);
2982 /* PLL enabled and used */
2983 stv0367_writereg(state, R367TER_ANACTRL, 0x00);
2985 state->cab_state->mclk = stv0367cab_get_mclk(&state->fe,
2986 state->config->xtal);
2987 state->cab_state->adc_clk = stv0367cab_get_adc_freq(&state->fe,
2988 state->config->xtal);
2990 state->activedemod = demod_cab;
2993 static int stv0367ddb_set_frontend(struct dvb_frontend *fe)
2995 struct stv0367_state *state = fe->demodulator_priv;
2997 switch (fe->dtv_property_cache.delivery_system) {
2999 if (state->activedemod != demod_ter)
3000 stv0367ddb_setup_ter(state);
3002 return stv0367ter_set_frontend(fe);
3003 case SYS_DVBC_ANNEX_A:
3004 if (state->activedemod != demod_cab)
3005 stv0367ddb_setup_cab(state);
3007 /* protect against division error oopses */
3008 if (fe->dtv_property_cache.symbol_rate == 0) {
3009 printk(KERN_ERR "Invalid symbol rate\n");
3013 return stv0367cab_set_frontend(fe);
3021 static void stv0367ddb_read_signal_strength(struct dvb_frontend *fe)
3023 struct stv0367_state *state = fe->demodulator_priv;
3024 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3027 switch (state->activedemod) {
3029 signalstrength = stv0367cab_get_rf_lvl(state) * 1000;
3032 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3036 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
3037 p->strength.stat[0].uvalue = signalstrength;
3040 static void stv0367ddb_read_snr(struct dvb_frontend *fe)
3042 struct stv0367_state *state = fe->demodulator_priv;
3043 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3045 u32 regval, tmpval, snrval = 0;
3047 switch (state->activedemod) {
3049 snrval = stv0367ter_snr_readreg(fe);
3052 cab_pwr = stv0367cab_snr_power(fe);
3053 regval = stv0367cab_snr_readreg(fe, 0);
3055 /* prevent division by zero */
3061 tmpval = (cab_pwr * 320) / regval;
3062 snrval = ((tmpval != 0) ? (intlog2(tmpval) / 5581) : 0);
3065 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3069 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
3070 p->cnr.stat[0].uvalue = snrval;
3073 static void stv0367ddb_read_ucblocks(struct dvb_frontend *fe)
3075 struct stv0367_state *state = fe->demodulator_priv;
3076 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3079 switch (state->activedemod) {
3081 stv0367ter_read_ucblocks(fe, &ucblocks);
3084 stv0367cab_read_ucblcks(fe, &ucblocks);
3087 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3091 p->block_error.stat[0].scale = FE_SCALE_COUNTER;
3092 p->block_error.stat[0].uvalue = ucblocks;
3095 static int stv0367ddb_read_status(struct dvb_frontend *fe,
3096 enum fe_status *status)
3098 struct stv0367_state *state = fe->demodulator_priv;
3099 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3102 switch (state->activedemod) {
3104 ret = stv0367ter_read_status(fe, status);
3107 ret = stv0367cab_read_status(fe, status);
3113 /* stop and report on *_read_status failure */
3117 stv0367ddb_read_signal_strength(fe);
3119 /* read carrier/noise when a carrier is detected */
3120 if (*status & FE_HAS_CARRIER)
3121 stv0367ddb_read_snr(fe);
3123 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3125 /* read uncorrected blocks on FE_HAS_LOCK */
3126 if (*status & FE_HAS_LOCK)
3127 stv0367ddb_read_ucblocks(fe);
3129 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3134 static int stv0367ddb_get_frontend(struct dvb_frontend *fe,
3135 struct dtv_frontend_properties *p)
3137 struct stv0367_state *state = fe->demodulator_priv;
3139 switch (state->activedemod) {
3141 return stv0367ter_get_frontend(fe, p);
3143 return stv0367cab_get_frontend(fe, p);
3151 static int stv0367ddb_sleep(struct dvb_frontend *fe)
3153 struct stv0367_state *state = fe->demodulator_priv;
3155 switch (state->activedemod) {
3157 state->activedemod = demod_none;
3158 return stv0367ter_sleep(fe);
3160 state->activedemod = demod_none;
3161 return stv0367cab_sleep(fe);
3169 static int stv0367ddb_init(struct stv0367_state *state)
3171 struct stv0367ter_state *ter_state = state->ter_state;
3172 struct dtv_frontend_properties *p = &state->fe.dtv_property_cache;
3174 stv0367_writereg(state, R367TER_TOPCTRL, 0x10);
3176 if (stv0367_deftabs[state->deftabs][STV0367_TAB_BASE])
3177 stv0367_write_table(state,
3178 stv0367_deftabs[state->deftabs][STV0367_TAB_BASE]);
3180 stv0367_write_table(state,
3181 stv0367_deftabs[state->deftabs][STV0367_TAB_CAB]);
3183 stv0367_writereg(state, R367TER_TOPCTRL, 0x00);
3184 stv0367_write_table(state,
3185 stv0367_deftabs[state->deftabs][STV0367_TAB_TER]);
3187 stv0367_writereg(state, R367TER_GAIN_SRC1, 0x2A);
3188 stv0367_writereg(state, R367TER_GAIN_SRC2, 0xD6);
3189 stv0367_writereg(state, R367TER_INC_DEROT1, 0x55);
3190 stv0367_writereg(state, R367TER_INC_DEROT2, 0x55);
3191 stv0367_writereg(state, R367TER_TRL_CTL, 0x14);
3192 stv0367_writereg(state, R367TER_TRL_NOMRATE1, 0xAE);
3193 stv0367_writereg(state, R367TER_TRL_NOMRATE2, 0x56);
3194 stv0367_writereg(state, R367TER_FEPATH_CFG, 0x0);
3198 stv0367_writereg(state, R367TER_TSCFGH, 0x70);
3199 stv0367_writereg(state, R367TER_TSCFGM, 0xC0);
3200 stv0367_writereg(state, R367TER_TSCFGL, 0x20);
3201 stv0367_writereg(state, R367TER_TSSPEED, 0x40); /* Fixed at 54 MHz */
3203 stv0367_writereg(state, R367TER_TSCFGH, 0x71);
3204 stv0367_writereg(state, R367TER_TSCFGH, 0x70);
3206 stv0367_writereg(state, R367TER_TOPCTRL, 0x10);
3208 /* Also needed for QAM */
3209 stv0367_writereg(state, R367TER_AGC12C, 0x01); /* AGC Pin setup */
3211 stv0367_writereg(state, R367TER_AGCCTRL1, 0x8A);
3213 /* QAM TS setup, note exact format also depends on descrambler */
3215 /* Inverted Clock, Swap, serial */
3216 stv0367_writereg(state, R367CAB_OUTFORMAT_0, 0x85);
3218 /* Clock setup (PLL bypassed and disabled) */
3219 stv0367_writereg(state, R367TER_ANACTRL, 0x0D);
3221 /* IC runs at 58 MHz with a 27 MHz crystal */
3222 stv0367_pll_setup(state, STV0367_ICSPEED_58000, state->config->xtal);
3225 /* Buffer Q disabled, I Enabled, signed ADC */
3226 stv0367_writereg(state, R367TER_ANADIGCTRL, 0x8b);
3227 stv0367_writereg(state, R367TER_DUAL_AD12, 0x04); /* ADCQ disabled */
3229 /* Improves the C/N lock limit */
3230 stv0367_writereg(state, R367CAB_FSM_SNR2_HTH, 0x23);
3231 /* ZIF/IF Automatic mode */
3232 stv0367_writereg(state, R367CAB_IQ_QAM, 0x01);
3233 /* Improving burst noise performances */
3234 stv0367_writereg(state, R367CAB_EQU_FFE_LEAKAGE, 0x83);
3235 /* Improving ACI performances */
3236 stv0367_writereg(state, R367CAB_IQDEM_ADJ_EN, 0x05);
3238 /* PLL enabled and used */
3239 stv0367_writereg(state, R367TER_ANACTRL, 0x00);
3241 stv0367_writereg(state, R367TER_I2CRPT, (0x08 | ((5 & 0x07) << 4)));
3243 ter_state->pBER = 0;
3244 ter_state->first_lock = 0;
3245 ter_state->unlock_counter = 2;
3247 p->strength.len = 1;
3248 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3250 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3251 p->block_error.len = 1;
3252 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3257 static const struct dvb_frontend_ops stv0367ddb_ops = {
3258 .delsys = { SYS_DVBC_ANNEX_A, SYS_DVBT },
3260 .name = "ST STV0367 DDB DVB-C/T",
3261 .frequency_min_hz = 47 * MHz,
3262 .frequency_max_hz = 865 * MHz,
3263 .frequency_stepsize_hz = 166667,
3264 .symbol_rate_min = 870000,
3265 .symbol_rate_max = 11700000,
3267 0x400 |/* FE_CAN_QAM_4 */
3268 FE_CAN_QAM_16 | FE_CAN_QAM_32 |
3269 FE_CAN_QAM_64 | FE_CAN_QAM_128 |
3272 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
3273 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
3274 FE_CAN_QPSK | FE_CAN_TRANSMISSION_MODE_AUTO |
3275 FE_CAN_RECOVER | FE_CAN_INVERSION_AUTO |
3278 .release = stv0367_release,
3279 .sleep = stv0367ddb_sleep,
3280 .i2c_gate_ctrl = stv0367cab_gate_ctrl, /* valid for TER and CAB */
3281 .set_frontend = stv0367ddb_set_frontend,
3282 .get_frontend = stv0367ddb_get_frontend,
3283 .get_tune_settings = stv0367_get_tune_settings,
3284 .read_status = stv0367ddb_read_status,
3287 struct dvb_frontend *stv0367ddb_attach(const struct stv0367_config *config,
3288 struct i2c_adapter *i2c)
3290 struct stv0367_state *state = NULL;
3291 struct stv0367ter_state *ter_state = NULL;
3292 struct stv0367cab_state *cab_state = NULL;
3294 /* allocate memory for the internal state */
3295 state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
3298 ter_state = kzalloc(sizeof(struct stv0367ter_state), GFP_KERNEL);
3299 if (ter_state == NULL)
3301 cab_state = kzalloc(sizeof(struct stv0367cab_state), GFP_KERNEL);
3302 if (cab_state == NULL)
3305 /* setup the state */
3307 state->config = config;
3308 state->ter_state = ter_state;
3309 cab_state->search_range = 280000;
3310 cab_state->qamfec_status_reg = F367CAB_DESCR_SYNCSTATE;
3311 state->cab_state = cab_state;
3312 state->fe.ops = stv0367ddb_ops;
3313 state->fe.demodulator_priv = state;
3314 state->chip_id = stv0367_readreg(state, R367TER_ID);
3316 /* demod operation options */
3317 state->use_i2c_gatectrl = 0;
3318 state->deftabs = STV0367_DEFTAB_DDB;
3319 state->reinit_on_setfrontend = 0;
3320 state->auto_if_khz = 1;
3321 state->activedemod = demod_none;
3323 dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
3325 /* check if the demod is there */
3326 if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
3329 dev_info(&i2c->dev, "Found %s with ChipID %02X at adr %02X\n",
3330 state->fe.ops.info.name, state->chip_id,
3331 config->demod_address);
3333 stv0367ddb_init(state);
3343 EXPORT_SYMBOL(stv0367ddb_attach);
3345 MODULE_PARM_DESC(debug, "Set debug");
3346 MODULE_PARM_DESC(i2c_debug, "Set i2c debug");
3348 MODULE_AUTHOR("Igor M. Liplianin");
3349 MODULE_DESCRIPTION("ST STV0367 DVB-C/T demodulator driver");
3350 MODULE_LICENSE("GPL");