2 * Driver for Silicon Labs Si2161 DVB-T and Si2165 DVB-C/-T Demodulator
4 * Copyright (C) 2013-2017 Matthias Schwarzott <zzam@gentoo.org>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 * http://www.silabs.com/Support%20Documents/TechnicalDocs/Si2165-short.pdf
20 #include <linux/delay.h>
21 #include <linux/errno.h>
22 #include <linux/init.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/string.h>
26 #include <linux/slab.h>
27 #include <linux/firmware.h>
28 #include <linux/regmap.h>
30 #include <media/dvb_frontend.h>
31 #include <media/dvb_math.h>
32 #include "si2165_priv.h"
36 * Hauppauge WinTV-HVR-930C-HD B130 / PCTV QuatroStick 521e 1113xx
39 * Hauppauge WinTV-HVR-930C-HD B131 / PCTV QuatroStick 522e 1114xx
40 * uses 24 MHz clock provided by tuner
44 struct i2c_client *client;
46 struct regmap *regmap;
48 struct dvb_frontend fe;
50 struct si2165_config config;
55 /* calculated by xtal and div settings */
68 static int si2165_write(struct si2165_state *state, const u16 reg,
69 const u8 *src, const int count)
73 dev_dbg(&state->client->dev, "i2c write: reg: 0x%04x, data: %*ph\n",
76 ret = regmap_bulk_write(state->regmap, reg, src, count);
79 dev_err(&state->client->dev, "%s: ret == %d\n", __func__, ret);
84 static int si2165_read(struct si2165_state *state,
85 const u16 reg, u8 *val, const int count)
87 int ret = regmap_bulk_read(state->regmap, reg, val, count);
90 dev_err(&state->client->dev, "%s: error (addr %02x reg %04x error (ret == %i)\n",
91 __func__, state->config.i2c_addr, reg, ret);
95 dev_dbg(&state->client->dev, "i2c read: reg: 0x%04x, data: %*ph\n",
101 static int si2165_readreg8(struct si2165_state *state,
102 const u16 reg, u8 *val)
104 unsigned int val_tmp;
105 int ret = regmap_read(state->regmap, reg, &val_tmp);
107 dev_dbg(&state->client->dev, "reg read: R(0x%04x)=0x%02x\n", reg, *val);
111 static int si2165_readreg16(struct si2165_state *state,
112 const u16 reg, u16 *val)
116 int ret = si2165_read(state, reg, buf, 2);
117 *val = buf[0] | buf[1] << 8;
118 dev_dbg(&state->client->dev, "reg read: R(0x%04x)=0x%04x\n", reg, *val);
122 static int si2165_readreg24(struct si2165_state *state,
123 const u16 reg, u32 *val)
127 int ret = si2165_read(state, reg, buf, 3);
128 *val = buf[0] | buf[1] << 8 | buf[2] << 16;
129 dev_dbg(&state->client->dev, "reg read: R(0x%04x)=0x%06x\n", reg, *val);
133 static int si2165_writereg8(struct si2165_state *state, const u16 reg, u8 val)
135 return regmap_write(state->regmap, reg, val);
138 static int si2165_writereg16(struct si2165_state *state, const u16 reg, u16 val)
140 u8 buf[2] = { val & 0xff, (val >> 8) & 0xff };
142 return si2165_write(state, reg, buf, 2);
145 static int si2165_writereg24(struct si2165_state *state, const u16 reg, u32 val)
147 u8 buf[3] = { val & 0xff, (val >> 8) & 0xff, (val >> 16) & 0xff };
149 return si2165_write(state, reg, buf, 3);
152 static int si2165_writereg32(struct si2165_state *state, const u16 reg, u32 val)
160 return si2165_write(state, reg, buf, 4);
163 static int si2165_writereg_mask8(struct si2165_state *state, const u16 reg,
168 int ret = si2165_readreg8(state, reg, &tmp);
177 return si2165_writereg8(state, reg, val);
180 #define REG16(reg, val) \
181 { (reg), (val) & 0xff }, \
182 { (reg) + 1, (val) >> 8 & 0xff }
183 struct si2165_reg_value_pair {
188 static int si2165_write_reg_list(struct si2165_state *state,
189 const struct si2165_reg_value_pair *regs,
195 for (i = 0; i < count; i++) {
196 ret = si2165_writereg8(state, regs[i].reg, regs[i].val);
203 static int si2165_get_tune_settings(struct dvb_frontend *fe,
204 struct dvb_frontend_tune_settings *s)
206 s->min_delay_ms = 1000;
210 static int si2165_init_pll(struct si2165_state *state)
212 u32 ref_freq_hz = state->config.ref_freq_hz;
213 u8 divr = 1; /* 1..7 */
214 u8 divp = 1; /* only 1 or 4 */
215 u8 divn = 56; /* 1..63 */
221 * hardcoded values can be deleted if calculation is verified
222 * or it yields the same values as the windows driver
224 switch (ref_freq_hz) {
234 /* ref_freq / divr must be between 4 and 16 MHz */
235 if (ref_freq_hz > 16000000u)
239 * now select divn and divp such that
240 * fvco is in 1624..1824 MHz
242 if (1624000000u * divr > ref_freq_hz * 2u * 63u)
245 /* is this already correct regarding rounding? */
246 divn = 1624000000u * divr / (ref_freq_hz * 2u * divp);
250 /* adc_clk and sys_clk depend on xtal and pll settings */
251 state->fvco_hz = ref_freq_hz / divr
253 state->adc_clk = state->fvco_hz / (divm * 4u);
254 state->sys_clk = state->fvco_hz / (divl * 2u);
256 /* write all 4 pll registers 0x00a0..0x00a3 at once */
259 buf[2] = (divn & 0x3f) | ((divp == 1) ? 0x40 : 0x00) | 0x80;
261 return si2165_write(state, REG_PLL_DIVL, buf, 4);
264 static int si2165_adjust_pll_divl(struct si2165_state *state, u8 divl)
266 state->sys_clk = state->fvco_hz / (divl * 2u);
267 return si2165_writereg8(state, REG_PLL_DIVL, divl);
270 static u32 si2165_get_fe_clk(struct si2165_state *state)
272 /* assume Oversampling mode Ovr4 is used */
273 return state->adc_clk;
276 static int si2165_wait_init_done(struct si2165_state *state)
282 for (i = 0; i < 3; ++i) {
283 ret = si2165_readreg8(state, REG_INIT_DONE, &val);
288 usleep_range(1000, 50000);
290 dev_err(&state->client->dev, "init_done was not set\n");
294 static int si2165_upload_firmware_block(struct si2165_state *state,
295 const u8 *data, u32 len, u32 *poffset,
299 u8 buf_ctrl[4] = { 0x00, 0x00, 0x00, 0xc0 };
302 u32 offset = poffset ? *poffset : 0;
309 dev_dbg(&state->client->dev,
310 "fw load: %s: called with len=0x%x offset=0x%x blockcount=0x%x\n",
311 __func__, len, offset, block_count);
312 while (offset + 12 <= len && cur_block < block_count) {
313 dev_dbg(&state->client->dev,
314 "fw load: %s: in while len=0x%x offset=0x%x cur_block=0x%x blockcount=0x%x\n",
315 __func__, len, offset, cur_block, block_count);
316 wordcount = data[offset];
317 if (wordcount < 1 || data[offset + 1] ||
318 data[offset + 2] || data[offset + 3]) {
319 dev_warn(&state->client->dev,
320 "bad fw data[0..3] = %*ph\n",
325 if (offset + 8 + wordcount * 4 > len) {
326 dev_warn(&state->client->dev,
327 "len is too small for block len=%d, wordcount=%d\n",
332 buf_ctrl[0] = wordcount - 1;
334 ret = si2165_write(state, REG_DCOM_CONTROL_BYTE, buf_ctrl, 4);
337 ret = si2165_write(state, REG_DCOM_ADDR, data + offset + 4, 4);
343 while (wordcount > 0) {
344 ret = si2165_write(state, REG_DCOM_DATA,
354 dev_dbg(&state->client->dev,
355 "fw load: %s: after while len=0x%x offset=0x%x cur_block=0x%x blockcount=0x%x\n",
356 __func__, len, offset, cur_block, block_count);
361 dev_dbg(&state->client->dev,
362 "fw load: %s: returned offset=0x%x\n",
370 static int si2165_upload_firmware(struct si2165_state *state)
377 const struct firmware *fw = NULL;
386 switch (state->chip_revcode) {
387 case 0x03: /* revision D */
388 fw_file = SI2165_FIRMWARE_REV_D;
391 dev_info(&state->client->dev, "no firmware file for revision=%d\n",
392 state->chip_revcode);
396 /* request the firmware, this will block and timeout */
397 ret = request_firmware(&fw, fw_file, &state->client->dev);
399 dev_warn(&state->client->dev, "firmware file '%s' not found\n",
407 dev_info(&state->client->dev, "downloading firmware from file '%s' size=%d\n",
411 dev_warn(&state->client->dev, "firmware size is not multiple of 4\n");
416 /* check header (8 bytes) */
418 dev_warn(&state->client->dev, "firmware header is missing\n");
423 if (data[0] != 1 || data[1] != 0) {
424 dev_warn(&state->client->dev, "firmware file version is wrong\n");
429 patch_version = data[2];
430 block_count = data[4];
431 crc_expected = data[7] << 8 | data[6];
433 /* start uploading fw */
434 /* boot/wdog status */
435 ret = si2165_writereg8(state, REG_WDOG_AND_BOOT, 0x00);
439 ret = si2165_writereg8(state, REG_RST_ALL, 0x00);
442 /* boot/wdog status */
443 ret = si2165_readreg8(state, REG_WDOG_AND_BOOT, val);
447 /* enable reset on error */
448 ret = si2165_readreg8(state, REG_EN_RST_ERROR, val);
451 ret = si2165_readreg8(state, REG_EN_RST_ERROR, val);
454 ret = si2165_writereg8(state, REG_EN_RST_ERROR, 0x02);
458 /* start right after the header */
461 dev_info(&state->client->dev, "%s: extracted patch_version=0x%02x, block_count=0x%02x, crc_expected=0x%04x\n",
462 __func__, patch_version, block_count, crc_expected);
464 ret = si2165_upload_firmware_block(state, data, len, &offset, 1);
468 ret = si2165_writereg8(state, REG_PATCH_VERSION, patch_version);
473 ret = si2165_writereg8(state, REG_RST_CRC, 0x01);
477 ret = si2165_upload_firmware_block(state, data, len,
478 &offset, block_count);
480 dev_err(&state->client->dev,
481 "firmware could not be uploaded\n");
486 ret = si2165_readreg16(state, REG_CRC, &val16);
490 if (val16 != crc_expected) {
491 dev_err(&state->client->dev,
492 "firmware crc mismatch %04x != %04x\n",
493 val16, crc_expected);
498 ret = si2165_upload_firmware_block(state, data, len, &offset, 5);
503 dev_err(&state->client->dev,
504 "firmware len mismatch %04x != %04x\n",
510 /* reset watchdog error register */
511 ret = si2165_writereg_mask8(state, REG_WDOG_AND_BOOT, 0x02, 0x02);
515 /* enable reset on error */
516 ret = si2165_writereg_mask8(state, REG_EN_RST_ERROR, 0x01, 0x01);
520 dev_info(&state->client->dev, "fw load finished\n");
523 state->firmware_loaded = true;
526 release_firmware(fw);
533 static int si2165_init(struct dvb_frontend *fe)
536 struct si2165_state *state = fe->demodulator_priv;
537 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
539 u8 patch_version = 0x00;
541 dev_dbg(&state->client->dev, "%s: called\n", __func__);
544 ret = si2165_writereg8(state, REG_CHIP_MODE, state->config.chip_mode);
547 /* dsp_clock_enable */
548 ret = si2165_writereg8(state, REG_DSP_CLOCK, 0x01);
551 /* verify chip_mode */
552 ret = si2165_readreg8(state, REG_CHIP_MODE, &val);
555 if (val != state->config.chip_mode) {
556 dev_err(&state->client->dev, "could not set chip_mode\n");
561 ret = si2165_writereg8(state, REG_AGC_IF_TRI, 0x00);
564 ret = si2165_writereg8(state, REG_AGC_IF_SLR, 0x01);
567 ret = si2165_writereg8(state, REG_AGC2_OUTPUT, 0x00);
570 ret = si2165_writereg8(state, REG_AGC2_CLKDIV, 0x07);
574 ret = si2165_writereg8(state, REG_RSSI_PAD_CTRL, 0x00);
577 ret = si2165_writereg8(state, REG_RSSI_ENABLE, 0x00);
581 ret = si2165_init_pll(state);
585 /* enable chip_init */
586 ret = si2165_writereg8(state, REG_CHIP_INIT, 0x01);
590 ret = si2165_writereg8(state, REG_START_INIT, 0x01);
593 ret = si2165_wait_init_done(state);
597 /* disable chip_init */
598 ret = si2165_writereg8(state, REG_CHIP_INIT, 0x00);
602 /* ber_pkt - default 65535 */
603 ret = si2165_writereg16(state, REG_BER_PKT,
604 STATISTICS_PERIOD_PKT_COUNT);
608 ret = si2165_readreg8(state, REG_PATCH_VERSION, &patch_version);
612 ret = si2165_writereg8(state, REG_AUTO_RESET, 0x00);
617 ret = si2165_writereg32(state, REG_ADDR_JUMP, 0xf4000000);
620 /* boot/wdog status */
621 ret = si2165_readreg8(state, REG_WDOG_AND_BOOT, &val);
625 if (patch_version == 0x00) {
626 ret = si2165_upload_firmware(state);
631 /* ts output config */
632 ret = si2165_writereg8(state, REG_TS_DATA_MODE, 0x20);
635 ret = si2165_writereg16(state, REG_TS_TRI, 0x00fe);
638 ret = si2165_writereg24(state, REG_TS_SLR, 0x555555);
641 ret = si2165_writereg8(state, REG_TS_CLK_MODE, 0x01);
644 ret = si2165_writereg8(state, REG_TS_PARALLEL_MODE, 0x00);
648 c = &state->fe.dtv_property_cache;
650 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
651 c->post_bit_error.len = 1;
652 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
653 c->post_bit_count.len = 1;
654 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
661 static int si2165_sleep(struct dvb_frontend *fe)
664 struct si2165_state *state = fe->demodulator_priv;
666 /* dsp clock disable */
667 ret = si2165_writereg8(state, REG_DSP_CLOCK, 0x00);
671 ret = si2165_writereg8(state, REG_CHIP_MODE, SI2165_MODE_OFF);
677 static int si2165_read_status(struct dvb_frontend *fe, enum fe_status *status)
682 struct si2165_state *state = fe->demodulator_priv;
683 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
684 u32 delsys = c->delivery_system;
690 /* check fast signal type */
691 ret = si2165_readreg8(state, REG_CHECK_SIGNAL, &u8tmp);
694 switch (u8tmp & 0x3) {
695 case 0: /* searching */
696 case 1: /* nothing */
698 case 2: /* digital signal */
699 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER;
703 case SYS_DVBC_ANNEX_A:
704 /* check packet sync lock */
705 ret = si2165_readreg8(state, REG_PS_LOCK, &u8tmp);
709 *status |= FE_HAS_SIGNAL;
710 *status |= FE_HAS_CARRIER;
711 *status |= FE_HAS_VITERBI;
712 *status |= FE_HAS_SYNC;
718 ret = si2165_readreg8(state, REG_FEC_LOCK, &u8tmp);
722 *status |= FE_HAS_SIGNAL;
723 *status |= FE_HAS_CARRIER;
724 *status |= FE_HAS_VITERBI;
725 *status |= FE_HAS_SYNC;
726 *status |= FE_HAS_LOCK;
730 if (delsys == SYS_DVBC_ANNEX_A && *status & FE_HAS_VITERBI) {
731 ret = si2165_readreg24(state, REG_C_N, &u32tmp);
737 * 1000 * 10 * log10(2^24 / regval) =
738 * 1000 * 10 * (log10(2^24) - log10(regval)) =
739 * 1000 * 10 * (intlog10(2^24) - intlog10(regval)) / 2^24
741 * intlog10(x) = log10(x) * 2^24
742 * intlog10(2^24) = log10(2^24) * 2^24 = 121210686
744 u32tmp = (1000 * 10 * (121210686 - (u64)intlog10(u32tmp)))
746 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
747 c->cnr.stat[0].svalue = u32tmp;
749 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
752 if (*status & FE_HAS_VITERBI) {
753 if (c->post_bit_error.stat[0].scale == FE_SCALE_NOT_AVAILABLE) {
754 /* start new sampling period to get rid of old data*/
755 ret = si2165_writereg8(state, REG_BER_RST, 0x01);
759 /* set scale to enter read code on next call */
760 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
761 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
762 c->post_bit_error.stat[0].uvalue = 0;
763 c->post_bit_count.stat[0].uvalue = 0;
766 * reset DVBv3 value to deliver a good result
772 ret = si2165_readreg8(state, REG_BER_AVAIL, &u8tmp);
779 ret = si2165_readreg24(state, REG_BER_BIT,
784 c->post_bit_error.stat[0].uvalue +=
786 c->post_bit_count.stat[0].uvalue +=
787 STATISTICS_PERIOD_BIT_COUNT;
789 /* start new sampling period */
790 ret = si2165_writereg8(state,
795 dev_dbg(&state->client->dev,
796 "post_bit_error=%u post_bit_count=%u\n",
797 biterrcnt, STATISTICS_PERIOD_BIT_COUNT);
801 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
802 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
808 static int si2165_read_snr(struct dvb_frontend *fe, u16 *snr)
810 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
812 if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL)
813 *snr = div_s64(c->cnr.stat[0].svalue, 100);
819 static int si2165_read_ber(struct dvb_frontend *fe, u32 *ber)
821 struct si2165_state *state = fe->demodulator_priv;
822 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
824 if (c->post_bit_error.stat[0].scale != FE_SCALE_COUNTER) {
829 *ber = c->post_bit_error.stat[0].uvalue - state->ber_prev;
830 state->ber_prev = c->post_bit_error.stat[0].uvalue;
835 static int si2165_set_oversamp(struct si2165_state *state, u32 dvb_rate)
843 oversamp = si2165_get_fe_clk(state);
845 do_div(oversamp, dvb_rate);
846 reg_value = oversamp & 0x3fffffff;
848 dev_dbg(&state->client->dev, "Write oversamp=%#x\n", reg_value);
849 return si2165_writereg32(state, REG_OVERSAMP, reg_value);
852 static int si2165_set_if_freq_shift(struct si2165_state *state)
854 struct dvb_frontend *fe = &state->fe;
857 u32 fe_clk = si2165_get_fe_clk(state);
860 if (!fe->ops.tuner_ops.get_if_frequency) {
861 dev_err(&state->client->dev,
862 "Error: get_if_frequency() not defined at tuner. Can't work without it!\n");
869 fe->ops.tuner_ops.get_if_frequency(fe, &IF);
871 if_freq_shift <<= 29;
873 do_div(if_freq_shift, fe_clk);
874 reg_value = (s32)if_freq_shift;
876 if (state->config.inversion)
877 reg_value = -reg_value;
879 reg_value = reg_value & 0x1fffffff;
881 /* if_freq_shift, usbdump contained 0x023ee08f; */
882 return si2165_writereg32(state, REG_IF_FREQ_SHIFT, reg_value);
885 static const struct si2165_reg_value_pair dvbt_regs[] = {
886 /* standard = DVB-T */
887 { REG_DVB_STANDARD, 0x01 },
888 /* impulsive_noise_remover */
889 { REG_IMPULSIVE_NOISE_REM, 0x01 },
890 { REG_AUTO_RESET, 0x00 },
892 { REG_AGC2_MIN, 0x41 },
893 { REG_AGC2_KACQ, 0x0e },
894 { REG_AGC2_KLOC, 0x10 },
896 { REG_AGC_UNFREEZE_THR, 0x03 },
897 { REG_AGC_CRESTF_DBX8, 0x78 },
899 { REG_AAF_CRESTF_DBX8, 0x78 },
900 { REG_ACI_CRESTF_DBX8, 0x68 },
901 /* freq_sync_range */
902 REG16(REG_FREQ_SYNC_RANGE, 0x0064),
904 { REG_GP_REG0_MSB, 0x00 }
907 static int si2165_set_frontend_dvbt(struct dvb_frontend *fe)
910 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
911 struct si2165_state *state = fe->demodulator_priv;
914 u32 bw_hz = p->bandwidth_hz;
916 dev_dbg(&state->client->dev, "%s: called\n", __func__);
918 if (!state->has_dvbt)
921 /* no bandwidth auto-detection */
925 dvb_rate = bw_hz * 8 / 7;
926 bw10k = bw_hz / 10000;
928 ret = si2165_adjust_pll_divl(state, 12);
932 /* bandwidth in 10KHz steps */
933 ret = si2165_writereg16(state, REG_T_BANDWIDTH, bw10k);
936 ret = si2165_set_oversamp(state, dvb_rate);
940 ret = si2165_write_reg_list(state, dvbt_regs, ARRAY_SIZE(dvbt_regs));
947 static const struct si2165_reg_value_pair dvbc_regs[] = {
948 /* standard = DVB-C */
949 { REG_DVB_STANDARD, 0x05 },
952 { REG_AGC2_MIN, 0x50 },
953 { REG_AGC2_KACQ, 0x0e },
954 { REG_AGC2_KLOC, 0x10 },
956 { REG_AGC_UNFREEZE_THR, 0x03 },
957 { REG_AGC_CRESTF_DBX8, 0x68 },
959 { REG_AAF_CRESTF_DBX8, 0x68 },
960 { REG_ACI_CRESTF_DBX8, 0x50 },
962 { REG_EQ_AUTO_CONTROL, 0x0d },
964 { REG_KP_LOCK, 0x05 },
965 { REG_CENTRAL_TAP, 0x09 },
966 REG16(REG_UNKNOWN_350, 0x3e80),
968 { REG_AUTO_RESET, 0x01 },
969 REG16(REG_UNKNOWN_24C, 0x0000),
970 REG16(REG_UNKNOWN_27C, 0x0000),
971 { REG_SWEEP_STEP, 0x03 },
972 { REG_AGC_IF_TRI, 0x00 },
975 static int si2165_set_frontend_dvbc(struct dvb_frontend *fe)
977 struct si2165_state *state = fe->demodulator_priv;
979 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
980 const u32 dvb_rate = p->symbol_rate;
983 if (!state->has_dvbc)
989 ret = si2165_adjust_pll_divl(state, 14);
994 ret = si2165_set_oversamp(state, dvb_rate);
998 switch (p->modulation) {
1019 ret = si2165_writereg8(state, REG_REQ_CONSTELLATION, u8tmp);
1023 ret = si2165_writereg32(state, REG_LOCK_TIMEOUT, 0x007a1200);
1027 ret = si2165_write_reg_list(state, dvbc_regs, ARRAY_SIZE(dvbc_regs));
1034 static const struct si2165_reg_value_pair adc_rewrite[] = {
1035 { REG_ADC_RI1, 0x46 },
1036 { REG_ADC_RI3, 0x00 },
1037 { REG_ADC_RI5, 0x0a },
1038 { REG_ADC_RI6, 0xff },
1039 { REG_ADC_RI8, 0x70 }
1042 static int si2165_set_frontend(struct dvb_frontend *fe)
1044 struct si2165_state *state = fe->demodulator_priv;
1045 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1046 u32 delsys = p->delivery_system;
1050 /* initial setting of if freq shift */
1051 ret = si2165_set_if_freq_shift(state);
1057 ret = si2165_set_frontend_dvbt(fe);
1061 case SYS_DVBC_ANNEX_A:
1062 ret = si2165_set_frontend_dvbc(fe);
1071 ret = si2165_writereg32(state, REG_ADDR_JUMP, 0xf4000000);
1075 if (fe->ops.tuner_ops.set_params)
1076 fe->ops.tuner_ops.set_params(fe);
1078 /* recalc if_freq_shift if IF might has changed */
1079 ret = si2165_set_if_freq_shift(state);
1083 /* boot/wdog status */
1084 ret = si2165_readreg8(state, REG_WDOG_AND_BOOT, val);
1087 ret = si2165_writereg8(state, REG_WDOG_AND_BOOT, 0x00);
1092 ret = si2165_writereg8(state, REG_RST_ALL, 0x00);
1096 ret = si2165_writereg32(state, REG_GP_REG0_LSB, 0x00000000);
1100 /* write adc values after each reset*/
1101 ret = si2165_write_reg_list(state, adc_rewrite,
1102 ARRAY_SIZE(adc_rewrite));
1107 ret = si2165_writereg8(state, REG_START_SYNCHRO, 0x01);
1110 /* boot/wdog status */
1111 ret = si2165_readreg8(state, REG_WDOG_AND_BOOT, val);
1118 static const struct dvb_frontend_ops si2165_ops = {
1120 .name = "Silicon Labs ",
1122 .symbol_rate_min = 1000000,
1123 .symbol_rate_max = 7200000,
1125 .frequency_stepsize_hz = 166667,
1126 .caps = FE_CAN_FEC_1_2 |
1138 FE_CAN_GUARD_INTERVAL_AUTO |
1139 FE_CAN_HIERARCHY_AUTO |
1141 FE_CAN_TRANSMISSION_MODE_AUTO |
1145 .get_tune_settings = si2165_get_tune_settings,
1147 .init = si2165_init,
1148 .sleep = si2165_sleep,
1150 .set_frontend = si2165_set_frontend,
1151 .read_status = si2165_read_status,
1152 .read_snr = si2165_read_snr,
1153 .read_ber = si2165_read_ber,
1156 static int si2165_probe(struct i2c_client *client,
1157 const struct i2c_device_id *id)
1159 struct si2165_state *state = NULL;
1160 struct si2165_platform_data *pdata = client->dev.platform_data;
1165 const char *chip_name;
1166 static const struct regmap_config regmap_config = {
1169 .max_register = 0x08ff,
1172 /* allocate memory for the internal state */
1173 state = kzalloc(sizeof(*state), GFP_KERNEL);
1180 state->regmap = devm_regmap_init_i2c(client, ®map_config);
1181 if (IS_ERR(state->regmap)) {
1182 ret = PTR_ERR(state->regmap);
1186 /* setup the state */
1187 state->client = client;
1188 state->config.i2c_addr = client->addr;
1189 state->config.chip_mode = pdata->chip_mode;
1190 state->config.ref_freq_hz = pdata->ref_freq_hz;
1191 state->config.inversion = pdata->inversion;
1193 if (state->config.ref_freq_hz < 4000000 ||
1194 state->config.ref_freq_hz > 27000000) {
1195 dev_err(&state->client->dev, "ref_freq of %d Hz not supported by this driver\n",
1196 state->config.ref_freq_hz);
1201 /* create dvb_frontend */
1202 memcpy(&state->fe.ops, &si2165_ops,
1203 sizeof(struct dvb_frontend_ops));
1204 state->fe.ops.release = NULL;
1205 state->fe.demodulator_priv = state;
1206 i2c_set_clientdata(client, state);
1209 ret = si2165_writereg8(state, REG_CHIP_MODE, state->config.chip_mode);
1213 ret = si2165_readreg8(state, REG_CHIP_MODE, &val);
1216 if (val != state->config.chip_mode)
1219 ret = si2165_readreg8(state, REG_CHIP_REVCODE, &state->chip_revcode);
1223 ret = si2165_readreg8(state, REV_CHIP_TYPE, &state->chip_type);
1228 ret = si2165_writereg8(state, REG_CHIP_MODE, SI2165_MODE_OFF);
1232 if (state->chip_revcode < 26)
1233 rev_char = 'A' + state->chip_revcode;
1237 switch (state->chip_type) {
1239 chip_name = "Si2161";
1240 state->has_dvbt = true;
1243 chip_name = "Si2165";
1244 state->has_dvbt = true;
1245 state->has_dvbc = true;
1248 dev_err(&state->client->dev, "Unsupported Silicon Labs chip (type %d, rev %d)\n",
1249 state->chip_type, state->chip_revcode);
1253 dev_info(&state->client->dev,
1254 "Detected Silicon Labs %s-%c (type %d, rev %d)\n",
1255 chip_name, rev_char, state->chip_type,
1256 state->chip_revcode);
1258 strlcat(state->fe.ops.info.name, chip_name,
1259 sizeof(state->fe.ops.info.name));
1262 if (state->has_dvbt) {
1263 state->fe.ops.delsys[n++] = SYS_DVBT;
1264 strlcat(state->fe.ops.info.name, " DVB-T",
1265 sizeof(state->fe.ops.info.name));
1267 if (state->has_dvbc) {
1268 state->fe.ops.delsys[n++] = SYS_DVBC_ANNEX_A;
1269 strlcat(state->fe.ops.info.name, " DVB-C",
1270 sizeof(state->fe.ops.info.name));
1273 /* return fe pointer */
1274 *pdata->fe = &state->fe;
1282 dev_dbg(&client->dev, "failed=%d\n", ret);
1286 static int si2165_remove(struct i2c_client *client)
1288 struct si2165_state *state = i2c_get_clientdata(client);
1290 dev_dbg(&client->dev, "\n");
1296 static const struct i2c_device_id si2165_id_table[] = {
1300 MODULE_DEVICE_TABLE(i2c, si2165_id_table);
1302 static struct i2c_driver si2165_driver = {
1304 .owner = THIS_MODULE,
1307 .probe = si2165_probe,
1308 .remove = si2165_remove,
1309 .id_table = si2165_id_table,
1312 module_i2c_driver(si2165_driver);
1314 MODULE_DESCRIPTION("Silicon Labs Si2165 DVB-C/-T Demodulator driver");
1315 MODULE_AUTHOR("Matthias Schwarzott <zzam@gentoo.org>");
1316 MODULE_LICENSE("GPL");
1317 MODULE_FIRMWARE(SI2165_FIRMWARE_REV_D);